CN215342615U - Full super junction MOSFET device structure - Google Patents
Full super junction MOSFET device structure Download PDFInfo
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- CN215342615U CN215342615U CN202121358425.1U CN202121358425U CN215342615U CN 215342615 U CN215342615 U CN 215342615U CN 202121358425 U CN202121358425 U CN 202121358425U CN 215342615 U CN215342615 U CN 215342615U
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Abstract
The utility model discloses a full super junction MOSFET device structure, which comprises an MOSFET device structure body, wherein the MOSFET device structure body is divided into a terminal area and a cell area, the terminal area and the cell area respectively mainly comprise an N epitaxial silicon substrate, a first epitaxial layer and a second epitaxial layer which are sequentially arranged from bottom to top, and the thickness of the second epitaxial layer is greater than that of the first epitaxial layer; p columns and N columns are arranged in the second epitaxial layers of the terminal region and the cell region in a staggered mode, the depth of the P columns in the cell region is smaller than the thickness of the second epitaxial layer, the depth of the P columns in the terminal region is larger than the thickness of the second epitaxial layer, and the P columns are arranged in the first epitaxial layer in an extending mode; the upper surface of the second epitaxial layer in the terminal area is provided with a P-type area and an oxide layer, the upper surface of the second epitaxial layer in the cell area is provided with a body area, a grid electrode and a source electrode, and one side of the N epitaxial silicon substrate, which deviates from the first epitaxial layer, is provided with a drain electrode.
Description
Technical Field
The utility model relates to the field of super junction MOSFET device design and process manufacturing, in particular to a full super junction MOSFET device structure.
Background
The basic structure of the super junction MOSFET device is composed of P columns and N columns which are alternately arranged. When the device is in a blocking state, the P column and the N column in the super junction structure are completely depleted, and under the modulation of the transverse electric field of the drift region, the longitudinal electric field of the device tends to be uniformly distributed. Theoretically, the voltage endurance capability of the super junction structure only depends on the thickness of the drift region and is independent of the doping concentration, so that the super junction structure breaks through the silicon limit of the traditional power device with the on-resistance limited by the breakdown voltage, and the Ron-VB relation is changed from 2.5 power to 1.32 power. Therefore, the super junction MOSFET device has a lower on-resistance and a faster switching speed, so that the super junction MOSFET device has been widely used in the fields of solar energy, wind power generation, servers and communication power systems, medical and industrial control, power switches and the like, and is a key device for application in the high-power electronic industry.
In addition, the terminal and the cell region of the conventional super junction power device adopt the P column and the N column with the same length, and the P column and the N column are mutually depleted to bear high voltage, but the breakdown voltage of the super junction device is very sensitive to charge imbalance, and the process deviations of the width, the distance, the concentration and the like of the P column and the N column in the terminal region easily cause the peak value of an electric field to be remarkably increased to damage the device. Therefore, the conventional super junction power device also has the problem of unstable breakdown voltage.
Disclosure of Invention
The present invention is directed to provide a full super junction MOSFET device structure having a stable breakdown voltage and a breakdown occurring in a cell region, and a method for manufacturing the same.
The utility model aims to provide a full-super-junction MOSFET device structure, which comprises an MOSFET device structure body, wherein the MOSFET device structure body is divided into a terminal area and a cell area, the terminal area and the cell area respectively mainly comprise an N epitaxial silicon substrate, a first epitaxial layer and a second epitaxial layer which are sequentially arranged from bottom to top, and the thickness of the second epitaxial layer is greater than that of the first epitaxial layer; p columns and N columns are arranged in the second epitaxial layers of the terminal region and the cell region in a staggered mode, the depth of the P columns in the cell region is smaller than the thickness of the second epitaxial layer, the depth of the P columns in the terminal region is larger than the thickness of the second epitaxial layer, and the P columns are arranged in the first epitaxial layer in an extending mode; the upper surface of the second epitaxial layer in the terminal area is provided with a P-type area and an oxide layer, the upper surface of the second epitaxial layer in the cell area is provided with a body area, a grid electrode and a source electrode, and one side of the N epitaxial silicon substrate, which deviates from the first epitaxial layer, is provided with a drain electrode.
Further, the P-pillar in the termination region extends to a depth within the first epitaxial layer that is no greater than half the thickness of the first epitaxial layer.
A manufacturing method of the full super junction MOSFET device structure mainly comprises the following steps:
1) growing a first epitaxial layer on the selected N epitaxial silicon substrate;
2) defining a window in a terminal area of the device by using a first mask, etching a groove, then carrying out P epitaxial filling, and forming a P column in the terminal area of the device;
3) growing a second epitaxial layer, simultaneously performing deep trench etching on the cell region and the terminal region of the device by using a second mask, then performing P-type epitaxial filling, and simultaneously forming a P column and an N column in the cell region and the terminal region, wherein the P column of the terminal region is connected with the P column in the step 2) so that the length of the P column of the terminal region is greater than that of the P column of the cell region;
4) defining and injecting a lightly doped P-type region on the surface of the terminal region by using a third mask to form a terminal structure on the surface;
5) generating an oxide layer with a thickness of one layer on the silicon surface by means of thermal oxidation or oxide layer deposition, and photoetching and etching the active region by using a fourth mask;
6) growing a gate oxide layer in a thermal oxidation mode, wherein the specific thickness of the gate oxide layer is determined by the breakdown voltage and the application voltage of a device;
7) depositing polycrystalline silicon, photoetching gate polycrystalline silicon by using a fifth mask, and etching the polycrystalline silicon to form a gate of the device;
8) carrying out P-type implantation and annealing to form a body region of the device;
9) carrying out source region photoetching by using a sixth mask, injecting N-type impurities and annealing to form a heavily-doped N-type source region;
10) depositing a dielectric layer, and then defining and etching a grid electrode contact hole and a source electrode contact hole by using a seventh mask;
11) sputtering top metal, and photoetching and etching the top metal by using an eighth mask to form a source electrode and a grid electrode of the device; depositing an oxide layer as a passivation layer, and photoetching and etching the passivation layer by using a ninth mask to finish the manufacturing of the top layer structure;
12) and thinning the back of the silicon wafer to a specific thickness, and depositing back metal by a sputtering or evaporation method to form the drain electrode of the device.
Further, the thickness of the first epitaxial layer grown in the step 1) is 3 um-10 um, the specific thickness is the optimal value according to the breakdown voltage requirement of the device, the resistivity of the first epitaxial layer can be the same as or different from that of the second epitaxial layer, and the specific resistivity is determined by the breakdown voltage requirement of the device.
The utility model has the beneficial technical effects that: according to the utility model, the P column N column with the length longer than that of the cell region is formed in the terminal region through device and process manufacturing design, so that the basic breakdown voltage of the terminal region is improved, the breakdown voltage of the terminal region can be higher than that of the cell region, the device has stable breakdown voltage, breakdown occurs in the cell region, and the avalanche tolerance of the device is increased.
Drawings
Fig. 1 is a schematic diagram of a first structure of a full super junction MOSFET device structure according to the present invention;
fig. 2 is a schematic diagram of a second structure of the fully super junction MOSFET device structure according to the present invention;
FIG. 3 is a flowchart of an embodiment of a process for fabricating a super junction MOSFET structure of the present invention;
fig. 4 is a flowchart of an embodiment of a super junction MOSFET structure manufacturing process of the present invention.
Detailed Description
In order to make those skilled in the art more clearly understand the objects, technical solutions and advantages of the present invention, taking an N-type super junction MOSFET as an example, a manufacturing process takes a deep trench etching and P epitaxial filling process to form a P-pillar and N-pillar as an example, and the present invention will be further explained with reference to the accompanying drawings and embodiments.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "left", "right", "inside", "outside", "lateral", "vertical", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description of the present invention, and do not indicate or imply that the device or element referred to must have a specific orientation, and thus, should not be construed as limiting the present invention.
As shown in fig. 1 to 4, the full-super-junction MOSFET device structure according to the present invention includes a MOSFET device structure body, the MOSFET device structure body is divided into a terminal region and a cell region, the terminal region and the cell region both mainly include an N epitaxial silicon substrate 1, a first epitaxial layer 2 and a second epitaxial layer 3, which are sequentially arranged from bottom to top, and the thickness of the second epitaxial layer 3 is greater than that of the first epitaxial layer 2; p columns 4 and N columns 5 are arranged in the second epitaxial layers 3 of the terminal region and the cell region in a staggered mode, the depth of the P columns 4 in the cell region is smaller than the thickness of the second epitaxial layers 3, the depth of the P columns 4 in the terminal region is larger than the thickness of the second epitaxial layers 3, and the P columns are arranged in the first epitaxial layers 2 in an extending mode; the upper surface of the second epitaxial layer 3 in the terminal area is provided with a P-type area and an oxidation layer 6, the upper surface of the second epitaxial layer 3 in the cell area is provided with a body area 7, a grid 8 and a source electrode 9, and one side of the N epitaxial silicon substrate 1 deviating from the first epitaxial layer 2 is provided with a drain electrode 10. The P-pillars 4 in the termination region extend into the first epitaxial layer 2 to a depth of no more than half the thickness of the first epitaxial layer 2.
A manufacturing method of the full super junction MOSFET device structure is characterized in that a P column and an N column which are longer than a cell region are formed in a terminal region, so that the breakdown voltage of the terminal of the device is higher than that of the cell region, and a stable breakdown voltage can be obtained. The method mainly comprises the following steps:
1) growing a first epitaxial layer 2 on a selected N epitaxial silicon substrate 1; the thickness of the first epitaxial layer 2 of growing is 3um ~10um, and the specific thickness is according to the device breakdown voltage needs and takes the optimum value, and the resistivity of first epitaxial layer 2 can be the same with the resistivity of second epitaxial layer 3 or can be different, and specific resistivity is decided by the breakdown voltage needs of device.
2) Defining a window in a terminal area of the device by using a first mask, etching a groove, then carrying out P epitaxial filling, and forming a P column 4 in the terminal area of the device;
3) growing a second epitaxial layer 3, simultaneously performing deep trench etching on a cell region and a terminal region of the device by using a second mask, then performing P-type epitaxial filling, and simultaneously forming a P column 4 and an N column 5 in the cell region and the terminal region, wherein the P column of the terminal region is connected with the P column in the step 2) so that the length of the P column 4 of the terminal region is greater than that of the P column 4 of the cell region;
4) defining and injecting a lightly doped P-type region on the surface of the terminal region by using a third mask to form a terminal structure on the surface;
5) generating an oxide layer 6 with a thickness of one layer on the silicon surface by means of thermal oxidation or oxide layer deposition, and photoetching and etching the active region by using a fourth mask;
6) growing a gate oxide layer in a thermal oxidation mode, wherein the specific thickness of the gate oxide layer is determined by the breakdown voltage and the application voltage of a device;
7) depositing polycrystalline silicon, photoetching gate polycrystalline silicon by using a fifth mask, and etching the polycrystalline silicon to form a gate of the device;
8) performing a P-type implant and anneal to form the body region 7 of the device;
9) carrying out source region photoetching by using a sixth mask, injecting N-type impurities and annealing to form a heavily-doped N-type source region;
10) depositing a dielectric layer, and then defining and etching a grid electrode contact hole and a source electrode contact hole by using a seventh mask;
11) sputtering top metal, and photoetching and etching the top metal by using an eighth mask to form a source electrode 9 and a grid electrode 8 of the device; depositing an oxide layer as a passivation layer, and photoetching and etching the passivation layer by using a ninth mask to finish the manufacturing of the top layer structure;
12) the back of the silicon chip is thinned to a specific thickness, and back metal is deposited by a sputtering or evaporation method to form the drain electrode 10 of the device.
Referring to fig. 3, for the process of forming the P column by multiple times of epitaxy and multiple injection, an epitaxial layer 1 grows on a selected epitaxial silicon substrate, the resistivity of the epitaxial layer can be the same as or different from that of a subsequent epitaxial layer, the thickness of the epitaxial layer is about 3-10 um according to the breakdown voltage required by a device, and then the P column is formed by photoetching injection on the terminal area of the device by using the mask plate.
Referring to FIG. 4, for a process of forming a P column by deep trench etching and filling P type epitaxy, an epitaxial layer 1 grows on a selected epitaxial silicon substrate, the resistivity of the epitaxial layer can be the same as or different from that of a subsequent epitaxial layer, the thickness of the epitaxial layer is about 3-10 um according to the breakdown voltage required by a device, and the mask is used for photoetching a terminal region of the device and etching the trench and filling the P epitaxy in the terminal region to form the P column.
According to the utility model, the P column N column with the length longer than that of the cell region is formed in the terminal region through device and process manufacturing design, so that the basic breakdown voltage of the terminal region is improved, the breakdown voltage of the terminal region can be higher than that of the cell region, the device has stable breakdown voltage, breakdown occurs in the cell region, and the avalanche tolerance of the device is increased. In addition, the utility model is not only suitable for the process preparation method for forming the P column N column by multiple times of epitaxy and multiple times of injection, but also suitable for the process preparation method for forming the P column N column by deep trench etching epitaxy filling.
The specific embodiments described herein are merely illustrative of the principles and utilities of the present invention and are not intended to limit the utility model. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (2)
1. The utility model provides a full super junction MOSFET device structure, includes MOSFET device structure body, its characterized in that: the MOSFET device structure body is divided into a terminal area and a cell area, the terminal area and the cell area respectively mainly comprise an N epitaxial silicon substrate, a first epitaxial layer and a second epitaxial layer which are sequentially arranged from bottom to top, and the thickness of the second epitaxial layer is larger than that of the first epitaxial layer; p columns and N columns are arranged in the second epitaxial layers of the terminal region and the cell region in a staggered mode, the depth of the P columns in the cell region is smaller than the thickness of the second epitaxial layer, the depth of the P columns in the terminal region is larger than the thickness of the second epitaxial layer, and the P columns are arranged in the first epitaxial layer in an extending mode; the upper surface of the second epitaxial layer in the terminal area is provided with a P-type area and an oxide layer, the upper surface of the second epitaxial layer in the cell area is provided with a body area, a grid electrode and a source electrode, and one side of the N epitaxial silicon substrate, which deviates from the first epitaxial layer, is provided with a drain electrode.
2. The fully superjunction MOSFET device structure of claim 1, wherein: the P column in the terminal region extends to a depth within the first epitaxial layer that is no greater than half the thickness of the first epitaxial layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202121358425.1U CN215342615U (en) | 2021-06-18 | 2021-06-18 | Full super junction MOSFET device structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202121358425.1U CN215342615U (en) | 2021-06-18 | 2021-06-18 | Full super junction MOSFET device structure |
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| CN215342615U true CN215342615U (en) | 2021-12-28 |
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| CN202121358425.1U Active CN215342615U (en) | 2021-06-18 | 2021-06-18 | Full super junction MOSFET device structure |
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