CN115148820A - SiC trench MOSFET device and manufacturing method thereof - Google Patents
SiC trench MOSFET device and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000005855 radiation Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention discloses a SiC groove MOSFET device and a manufacturing method thereof.A second conductive type column region is formed, so that a peak electric field of a gate oxide layer is reduced, the gate oxide layer is protected, and meanwhile, a super junction structure formed by the column region and an epitaxial layer is utilized, the resistance of a drift region of the device is obviously reduced on the premise of ensuring that the breakdown characteristic of the device is not degraded, so that the forward conduction characteristic of the device is effectively improved.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a SiC trench MOSFET device and a manufacturing method thereof.
Background
The development of power electronic systems puts higher demands on the performance of semiconductor devices, particularly in terms of high temperature, high frequency, radiation resistance, high voltage, and the like. The traditional silicon material device manufacturing process is mature, but the application of the silicon device in an extreme working environment is limited by the performance of the material. The typical representative of the third generation wide bandgap semiconductor material is SiC, which has the characteristics of stable physical and chemical properties, a larger bandgap, a higher thermal conductivity, a higher breakdown voltage, a higher electron saturation drift velocity, a stronger radiation resistance, and the like, and thus, siC becomes one of the most important semiconductor materials for manufacturing high power devices capable of adapting to extreme environments.
A conventional planar gate type SiC MOSFET device has a parasitic junction field effect transistor structure, so that the on-resistance of the device is increased. The SiC trench MOSFET device not only improves the mobility of the channel, but also eliminates JFET effect by forming the channel on the side wall of the trench, so that the on-resistance of the device is greatly reduced, the cell size is reduced, and the power density is increased. However, the main problem of the SiC trench MOSFET device is that the gate oxide layer at the corner of the trench needs to bear a large electric field strength, which affects the reliability of the device. The traditional solution is to form a P-shield region at the bottom of the trench to protect the gate oxide layer, but the forward current channel is narrowed, and the on-resistance of the device is increased.
Disclosure of Invention
The technical problem to be solved is as follows: aiming at the technical problems, the invention provides the SiC trench MOSFET device and the manufacturing method thereof, which can effectively solve the defects that the gate oxide layer at the corner of the trench of the SiC trench MOSFET device bears larger electric field intensity and the reliability of the device is reduced.
The technical scheme is as follows: a SiC trench MOSFET device comprising
Drain electrode an electrode;
a first conductive type substrate on an upper surface of the drain electrode;
the first conductive type epitaxial layer is positioned on the upper surface of the first conductive type substrate;
the second conduction type well region is positioned on the upper surface of the first conduction type epitaxial layer;
the first conduction type source region is positioned on the upper surface of the preset region of the second conduction type well region;
a heavily doped region of the second conductivity type, the upper surface of the rest area of the second conductive type well region;
the grid groove is positioned in the first conduction type epitaxial layer, the second conduction type well region and the first conduction type source region;
the gate dielectric layer is positioned on the surface of the gate groove;
the gate electrode is positioned in the gate dielectric layer;
a source electrode positioned on the upper surface of the first conductive type source region part and the upper surface of the second conductive type heavily doped region;
the second conductive type column region is positioned in the first conductive type epitaxial layer below the second conductive type well region and the gate groove;
and the isolation dielectric layer is positioned on the upper surface of the residual part of the first conduction type source region and the upper surface of the gate dielectric layer.
Preferably, there is at least one gate trench.
Preferably, two or more gate trenches are arranged in a continuous or discontinuous manner.
Preferably, the second conductivity type pillar region has a depth to width ratio greater than 2:1.
a method of fabricating a SiC trench MOSFET device, comprising the steps of:
s1, forming a first conductive type epitaxial layer on a first conductive type substrate through epitaxial growth;
s2, removing the first conduction type epitaxial layer in the region where the second conduction type column region is located through deep groove etching;
s3, forming a second conductive type column region through an epitaxial backfill process or a multi-injection-epitaxial process;
s4, forming a well region epitaxial layer through secondary epitaxy, and forming a second conduction type well region, a second conduction type heavily doped region and a first conduction type source region through a photoetching process and an ion implantation process;
s5, forming a gate groove from the first conduction type source region to the first conduction type epitaxial layer through etching;
s6, removing the etching mask layer, and performing passivation treatment and high-temperature annealing on the gate trench;
s7, depositing a gate dielectric layer in the gate trench, and performing high-temperature annealing treatment;
s8, growing a gate electrode material in the gate dielectric layer through a chemical vapor deposition process to form a gate electrode;
and S9, depositing and forming an isolation dielectric layer on the upper surface of the first conduction type source region part and the upper surface of the grid dielectric layer to form a source electrode window, forming source electrode ohmic contact through the source electrode window, forming drain electrode ohmic contact on the lower surface of the first conduction type substrate, forming a source electrode on the upper surface of the source electrode ohmic contact layer, and forming a drain electrode on the lower surface of the drain electrode ohmic contact layer.
Preferably, in step S5, the depth of the gate trench is greater than the thickness of the well region epitaxial layer, and the second conductive type pillar region below the gate trench is connected to the bottom of the gate trench.
Preferably, the difference between the width of the second conductive type column region and the width of the gate trench is not more than 1 mu m.
Has the advantages that: according to the invention, by forming the second conductive type column region, the peak electric field of the gate oxide layer is reduced, the gate oxide layer is protected, and meanwhile, the resistance of the drift region of the device is obviously reduced by utilizing the super junction structure formed by the column region and the epitaxial layer on the premise of ensuring that the breakdown characteristic of the device is not degraded, so that the forward conduction characteristic of the device is effectively improved.
Drawings
Fig. 1 is a schematic structural view of a SiC trench MOSFET device of embodiment 1;
fig. 2 is a schematic structural view of a SiC trench MOSFET device of embodiment 2;
fig. 3 is a schematic structural view of a SiC trench MOSFET device of embodiment 3;
fig. 4-12 are schematic flow charts of the preparation of the SiC trench MOSFET device of example 1;
number in the figure: 1. a drain electrode; 2. a first conductive type substrate; 3. a first conductivity type epitaxial layer; 4. a second conductive type column region; 5. a gate dielectric layer; 6. a second conductivity type well region; 7. a gate electrode; 8. a second conductive type heavily doped region; 9. a first conductive type source region; 10. a source electrode; 11. and an isolation dielectric layer 12, a second conductivity type modulation region.
Detailed Description
The invention is described in detail below with reference to the following figures and specific examples:
example 1
As shown in fig. 1, a SiC trenchA MOSFET device comprising a drain electrode 1; a first conductive type substrate 2 on an upper surface of the drain electrode 1; a first conductive type epitaxial layer 3 on the upper surface of the first conductive type substrate 2, wherein the doping concentration of the first conductive type epitaxial layer 3 is 1 × 10 16 cm -3 ~2×10 17 cm -3 (ii) a A second conductivity type well region 6 located on the upper surface of the first conductivity type epitaxial layer 3; a first conductivity type source region 9 located on an upper surface of a predetermined region of the second conductivity type well region 6; a second conductivity type heavily doped region 8 located on the upper surface of the rest region of the second conductivity type well region 6; at least one grid groove is arranged in the first conductive type epitaxial layer 3, the second conductive type well region 6 and the first conductive type source region 9, two or more grid grooves are arranged in a continuous or discontinuous mode, the depth of each grid groove is 0.7 to 1.5 mu m, the width of each grid groove is 0.8 to 1.4 mu m, and the depth of each grid groove is larger than the thickness of the well region epitaxial layer; the gate dielectric layer 5 is positioned on the surface of the gate groove; the gate electrode 7 is positioned in the gate dielectric layer 5, and the gate electrode 7 is made of metal or doped polysilicon; a source electrode 10 located on a portion of an upper surface of the first conductive type source region 9 and an upper surface of the second conductive type heavily doped region 8; a second conductive type column region 4 in the first conductive type epitaxial layer 3 under the second conductive type well region 6 and the gate trench, the second conductive type column region 4 having a doping concentration of 1 × 10 16 cm -3 ~5×10 17 cm -3 The ratio of the depth to the width of the second conductivity type pillar region 4 is greater than 2:1, the width of the second conductive type column region 4 is less than that of the gate trench, and the difference between the widths is not more than 1 μm; and the isolation dielectric layer 11 is positioned on the upper surface of the rest part of the first conduction type source region 9 and the upper surface of the gate dielectric layer 5, and the isolation dielectric layer 11 is silicon dioxide, nitride or a compound of different nitrides.
A method of fabricating a SiC trench MOSFET device, comprising the steps of:
s1. As shown in fig. 4 to 5, a first conductivity type epitaxial layer 3 is formed on a first conductivity type substrate 2 by epitaxial growth;
s2, as shown in FIG. 6, growing an etching mask layer on the surface of the first conduction type epitaxial layer 3 through chemical vapor deposition, then performing graphical processing on the etching mask layer through a photoetching process, performing inductive coupling plasma etching on the first conduction type epitaxial layer 3 by using the graphical etching mask layer, and removing the first conduction type epitaxial layer 3 in the area where the second conduction type column area 4 is located;
s3, as shown in the figure 7, removing the etching mask layer, and forming a second conductive type column region 4 through an epitaxial backfill process or a multi-injection-epitaxial process;
s4, as shown in the figures 8-9, a well region epitaxial layer is formed through secondary epitaxy, and a second conduction type well region 6, a second conduction type heavily doped region 8 and a first conduction type source region 9 are formed through a photoetching process and an ion implantation process;
s5, as shown in the figure 10, a graphical etching mask layer is formed on the surface of the well region epitaxial layer, and inductively coupled plasma etching is carried out from the first conduction type source region 9 to the first conduction type epitaxial layer 3 to form a gate groove;
s6, removing the etching mask layer, and performing passivation treatment and high-temperature annealing on the gate trench;
s7, as shown in the figure 11, forming a silicon dioxide layer on the surface of the groove through thermal oxidation and chemical vapor deposition processes to be used as a gate dielectric layer 5, and carrying out high-temperature annealing treatment;
s8, as shown in the figure 12, growing polycrystalline silicon in the gate dielectric layer 5 through a chemical vapor deposition process, injecting the polycrystalline silicon, and etching the polycrystalline silicon to remove the polycrystalline silicon outside the groove area to form a gate electrode 7;
and S9, as shown in figure 1, depositing an isolation dielectric layer 11 on the upper surface of the part of the first conductive type source region 9 and the upper surface of the gate dielectric layer 5 to form a source electrode window, forming a source electrode ohmic contact through the source electrode window, forming a drain electrode ohmic contact on the lower surface of the first conductive type substrate 2, forming a source electrode 10 on the upper surface of the source electrode ohmic contact layer, and forming a drain electrode 1 on the lower surface of the drain electrode ohmic contact layer.
In the step S5, the depth of the gate groove is larger than the thickness of the well region epitaxial layer, and the second conductive type column region below the gate groove is connected with the bottom of the gate groove.
The difference between the width of the second conductive type column region and the width of the grid groove is not more than 1 mu m.
Example 2
A SiC trench MOSFET device, as shown in fig. 2, is substantially the same as embodiment 1 except that a second conductivity type modulation region 12 is formed between the second conductivity type well region 6 and the second conductivity type column region 4 by ion implantation so that the second conductivity type column region 4 is short-circuited to the source and can assist in modulating the gate oxide electric field.
Example 3
A SiC trench MOSFET device, as shown in fig. 3, is substantially the same as embodiment 1, except that the bottom thickness of the gate dielectric layer 5 is not less than 300 nm, the sidewall thickness is 40 to 60 nm, and the bottom thickness is significantly greater than the sidewall thickness, so that the thickened SiC trench MOSFET device can improve the capacitance characteristics of the device.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (7)
1. A SiC trench MOSFET device, characterized by: comprises that
A drain electrode (1);
a first conductivity type substrate (2) on an upper surface of the drain electrode (1);
a first conductivity type epitaxial layer (3) on the upper surface of the first conductivity type substrate (2);
a second conductivity type well region (6) located on the upper surface of the first conductivity type epitaxial layer (3);
the first conduction type source region (9) is positioned on the upper surface of a preset region of the second conduction type well region (6);
a second conductive type heavily doped region (8) which is positioned on the upper surface of the rest region of the second conductive type well region (6);
the grid groove is positioned in the first conduction type epitaxial layer (3), the second conduction type well region (6) and the first conduction type source region (9);
the gate dielectric layer (5) is positioned on the surface of the gate groove;
the gate electrode (7) is positioned inside the gate dielectric layer (5);
a source electrode (10) positioned on the upper surface of the part of the first conduction type source region (9) and the upper surface of the second conduction type heavily doped region (8);
a second conductivity type column region (4) located in the first conductivity type epitaxial layer (3) under the second conductivity type well region (6) and the gate trench;
and the isolation dielectric layer (11) is positioned on the upper surface of the rest part of the first conduction type source region (9) and the upper surface of the gate dielectric layer (5).
2. The SiC trench MOSFET device of claim 1, wherein: at least one gate trench is provided.
3. The SiC trench MOSFET device of claim 2, wherein: two or more gate trenches are arranged in a continuous or discontinuous manner.
4. The SiC trench MOSFET device of claim 1, wherein: the ratio of the depth to the width of the second conductivity type pillar region (4) is greater than 2:1.
5. a method of manufacturing a SiC trench MOSFET device according to claim 1, comprising the steps of:
s1, forming a first conduction type epitaxial layer (3) on a first conduction type substrate (2) through epitaxial growth;
s2, removing the first conduction type epitaxial layer (3) in the region where the second conduction type column region (4) is located through deep groove etching;
s3, forming a second conductive type column region (4) through an epitaxial backfill process or a multiple injection-epitaxial process;
s4, forming a well region epitaxial layer through secondary epitaxy, and forming a second conduction type well region (6), a second conduction type heavily doped region (8) and a first conduction type source region (9) through a photoetching process and an ion implantation process;
s5, forming a gate groove from the first conduction type source region (9) to the first conduction type epitaxial layer (3) through etching;
s6, removing the etching mask layer, and performing passivation treatment and high-temperature annealing on the gate trench;
s7, depositing a gate dielectric layer (5) in the gate trench, and performing high-temperature annealing treatment;
s8, growing a gate electrode material in the gate dielectric layer (5) through a chemical vapor deposition process to form a gate electrode (7);
and S9, depositing and forming an isolation dielectric layer (11) on the upper surface of the part of the first conduction type source region (9) and the upper surface of the gate dielectric layer (5) to form a source electrode window, forming a source electrode ohmic contact through the source electrode window, forming a drain electrode ohmic contact on the lower surface of the first conduction type substrate (2), forming a source electrode (10) on the upper surface of the source electrode ohmic contact layer, and forming a drain electrode (1) on the lower surface of the drain electrode ohmic contact layer.
6. The method of manufacturing a SiC trench MOSFET device as recited in claim 5, wherein: in the step S5, the depth of the gate groove is larger than the thickness of the well region epitaxial layer, and the second conductive type column region (4) below the gate groove is connected with the bottom of the gate groove.
7. The method of manufacturing a SiC trench MOSFET device as recited in claim 5, wherein: the difference between the width of the second conductive type column region (4) and the width of the grid groove is not more than 1 mu m.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116230774A (en) * | 2023-05-04 | 2023-06-06 | 南京第三代半导体技术创新中心有限公司 | Asymmetric silicon carbide trench gate MOSFET and manufacturing method thereof |
| CN117219674A (en) * | 2023-11-07 | 2023-12-12 | 深圳天狼芯半导体有限公司 | Super-junction-like groove type MOSFET device and preparation method thereof |
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2022
- 2022-07-04 CN CN202210787120.5A patent/CN115148820A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116230774A (en) * | 2023-05-04 | 2023-06-06 | 南京第三代半导体技术创新中心有限公司 | Asymmetric silicon carbide trench gate MOSFET and manufacturing method thereof |
| CN117219674A (en) * | 2023-11-07 | 2023-12-12 | 深圳天狼芯半导体有限公司 | Super-junction-like groove type MOSFET device and preparation method thereof |
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