CN209804661U - MOSFET device with silicon carbide double-side deep L-shaped base region structure - Google Patents
MOSFET device with silicon carbide double-side deep L-shaped base region structure Download PDFInfo
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- CN209804661U CN209804661U CN201920792089.8U CN201920792089U CN209804661U CN 209804661 U CN209804661 U CN 209804661U CN 201920792089 U CN201920792089 U CN 201920792089U CN 209804661 U CN209804661 U CN 209804661U
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Abstract
The utility model relates to a two MOSFET devices of dark L shape base region structure of side of carborundum, this MOSFET device includes: an epitaxial layer; the base region is positioned on two sides of the epitaxial layer; the drift layer is positioned on the lower surfaces of the epitaxial layer and the base region; the substrate layer is positioned on the lower surface of the drift layer; the drain electrode is positioned on the lower surface of the substrate layer; the first source region is positioned on the upper surface of the preset region of the base region; the second source region is positioned on the upper surface of the rest region of the base region; the source electrode is positioned on the upper surfaces of the first source region and the second source region; the gate dielectric layer is positioned on the upper surface of the epitaxial layer and is connected with the base region; the polycrystalline silicon layer is positioned on the inner surface of the gate dielectric layer; and the grid is positioned on the upper surface of the polycrystalline silicon layer. The utility model discloses a MOSFET device through the structure that changes the P type base region, under the condition that does not increase device cellular area, has reduced the electric field gathering at groove grid turning, has improved the breakdown voltage of device.
Description
Technical Field
The utility model belongs to the technical field of the microelectronics, concretely relates to two side MOSFET devices of dark L shape base region structure of carborundum.
background
the wide band gap semiconductor material silicon carbide has excellent physical and chemical characteristics of larger forbidden band width, higher critical breakdown electric field, high thermal conductivity, high electron saturation drift velocity and the like, and is suitable for manufacturing high-temperature, high-voltage, high-power and anti-radiation semiconductor devices. In the field of power electronics, power MOSFET devices have been widely used, and have the characteristics of simple gate drive, short switching time, and the like.
in a traditional groove gate structure MOSFET, an electric field at the corner of a gate dielectric layer is concentrated to cause breakdown of the gate dielectric layer, so that the device is broken down under the condition of being lower than the rated breakdown voltage, and the forward blocking characteristic of the device is seriously influenced.
SUMMERY OF THE UTILITY MODEL
In order to solve the above-mentioned problem that exists among the prior art, the utility model provides a two side deep L shape base region of carborundum device of region structure. The to-be-solved technical problem of the utility model is realized through following technical scheme:
an embodiment of the utility model provides a MOSFET device of two side dark L shape base region structures of carborundum, include:
an epitaxial layer;
the base region is positioned on two sides of the epitaxial layer;
The drift layer is positioned on the lower surfaces of the epitaxial layer and the base region;
the substrate layer is positioned on the lower surface of the drift layer;
The drain electrode is positioned on the lower surface of the substrate layer;
The first source region is positioned on the upper surface of the preset region of the base region;
The second source region is positioned on the upper surface of the rest region of the base region;
The source electrode is positioned on the upper surfaces of the first source region and the second source region;
The gate dielectric layer is positioned on the upper surface of the epitaxial layer and is connected with the base region;
The polycrystalline silicon layer is positioned on the inner surface of the gate dielectric layer;
And the grid is positioned on the upper surface of the polycrystalline silicon layer.
In one embodiment of the present invention, the substrate layer is an N-type doped SiC substrate.
in one embodiment of the present invention, the thickness of the substrate layer is 2 to 5 μm.
In an embodiment of the present invention, the base region is a P-type base region having an L-shaped cross section.
in an embodiment of the present invention, the doping element of the base region is B element or Al element.
In an embodiment of the present invention, the doping concentration of the B element or the Al element is 1 × 1017～3×1017/cm3。
In an embodiment of the present invention, the doping element of the first source region is B element or Al element.
In an embodiment of the present invention, the doping element of the second source region is a P element or an N element.
In an embodiment of the present invention, the source electrode and the drain electrode are made of a Ni/Ti/Ni/Ag stacked metal material; the grid electrode is made of Al.
Compared with the prior art, the beneficial effects of the utility model are that:
1. the utility model reduces the gathering of the electric field at the corner of the groove grid and improves the breakdown voltage of the device by changing the structure of the P-type base region under the condition of not increasing the cellular area of the device;
2. The utility model reduces the capacitance coupling between the grid and the drain, reduces the Miller platform in the switching process of the device, increases the switching speed of the device, reduces the energy loss and reduces the heat dissipation requirement of the device under the high-frequency work by the structure of the P-type base region;
3. The utility model discloses a dark L shape base region low doping concentration, and contain the current diffusion layer for the channel of dark L shape base region both sides all can normally be electrically conductive, and improve the breakdown voltage of device through dark L shape base region bottom electric field shielding effect.
drawings
Fig. 1 is a schematic cross-sectional structural diagram of a MOSFET device with a deep L-shaped base region structure on two sides of silicon carbide according to an embodiment of the present invention;
Fig. 2 is a schematic flow chart of a method for manufacturing a MOSFET device with a deep L-shaped base region structure on two sides of silicon carbide according to an embodiment of the present invention;
Fig. 3 is a schematic cross-sectional structural diagram of a drift layer of a MOSFET device with a sic double-sided deep L-shaped base region structure according to an embodiment of the present invention;
fig. 4 is a schematic cross-sectional structural diagram of a base region of a MOSFET device having a deep L-shaped base region structure on two sides of silicon carbide according to an embodiment of the present invention;
Fig. 5 is a schematic cross-sectional structural diagram of a first source region and a second source region of a MOSFET device with a silicon carbide double-sided deep L-shaped base region structure according to an embodiment of the present invention;
fig. 6 is a schematic cross-sectional structure diagram of a trench of a MOSFET device with a sic double-sided deep L-shaped base region structure according to an embodiment of the present invention;
Fig. 7 is a schematic cross-sectional structure diagram of an epitaxial layer of a MOSFET device having a silicon carbide double-sided deep L-shaped base region structure according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the present invention is not limited thereto.
in this embodiment, the terms "upper", "lower", "left" and "right" refer to the positional relationship when the MOSFET device structure is in the illustrated state, "long" refers to the lateral dimension when the MOSFET device structure is in the illustrated state, and "thick" refers to the longitudinal dimension when the MOSFET device structure is in the illustrated state.
Example one
Referring to fig. 1, fig. 1 is a schematic cross-sectional structure diagram of a MOSFET device with a silicon carbide bilateral deep L-shaped base region structure according to an embodiment of the present invention.
A MOSFET device having a silicon carbide double-sided deep L-shaped base region structure, comprising:
An epitaxial layer 101;
Base regions 102 located on both sides of the epitaxial layer 101; the lower surface of the base region 102 and the lower surface of the epitaxial layer 101 are located in the same horizontal direction, and the thickness of the base region is the sum of the thickness of the epitaxial layer 101 and the thickness of the conductive channel.
A drift layer 103 located on the lower surfaces of the epitaxial layer 101 and the base region 102;
A substrate layer 104 positioned on the lower surface of the drift layer 103;
a drain electrode 105 positioned on the lower surface of the substrate layer 104;
A first source region 106 located on an upper surface of a predetermined region of the base region 102;
a second source region 107 located on the upper surface of the rest of the base region 102;
A source electrode 108 located on the upper surfaces of the first source region 106 and the second source region 107;
The gate dielectric layer 109 is positioned on the upper surface of the epitaxial layer 101 and is connected with the base region 102;
A polysilicon layer 110 positioned on the inner surface of the gate dielectric layer 109;
and a gate 111 on an upper surface of the polysilicon layer 110.
Further, the substrate layer 104 is an N-type doped SiC substrate, the doping element of the substrate layer 104 is P element or N element, and the doping concentration of the P element or the N element is 5 × 1018～1×1020/cm3The highly doped substrate layer 104 may reduce the on-resistance of the device, thereby improving the performance of the device.
in one embodiment, the thickness of the substrate layer 104 is 2-5 μm.
Further, the drift layer 103 is an N-type SiC drift layer 103, the doping element is a P element or an N element, and the doping concentration of the P element or the N element doped in the N-type drift layer 103 is 1 × 1015～1×1016/cm3. The drift layer 103 is mainly used to bear the voltage of the drain 105 when the device is turned off reversely, so as to prevent the device from breaking down.
in one embodiment, the drift layer 103 has a thickness of 8 to 10 μm. The appropriate thickness can increase the on-resistance and breakdown voltage of the device, so that the withstand voltage performance of the device is enhanced.
Furthermore, the epitaxial layer 101 is an N-type SiC epitaxial layer 101, the doping element is P element or N element, and the doping concentration of the P element or N element doped in the N-type epitaxial layer 101 is 5 × 1016～1×1017/cm3. The N-type epitaxial layer 101 is mainly used for improving the conduction characteristic of a device and reducing the conduction resistance, and the doping with lower concentration can improve the problems of increased gate-drain capacitance and specialized switching characteristic of the device.
Note that the trench gate refers to a structure formed by the gate dielectric layer 109 and the gate electrode 111.
Further, the base region 102 is a P-type SiC base region 102 having an L-shaped cross section, and a doping element of the P-type base region 102 is a B element or an Al element.
in one embodiment, the P-type base region 102 is doped with B or Al at a doping concentration of 1 × 1017～3×1017/cm3the longest length of the P-type base region 102 is 0.5-1 μm more than the sum of the lengths of the first source region and the second source region, the two P-type base regions extend to the bottom of the trench gate structure, and under the condition of not increasing additional connecting lines, the bottom of the trench gate is additionally provided with the P-type base regionsan N-type epitaxial layer 101 is added, a PN junction depletion region is formed by utilizing two downward extending P-type base regions 102 and an N-type drift layer 103, the electric field distribution at the bottom of a trench gate is changed, a drain 105 and a source 108 are isolated, a conductive channel is formed when a gate 111 is opened, so that the base region 102 can conduct normally, and the design of the P-type base region 102 reduces the electric field concentration at the corner of the trench gate under the condition of not increasing the cell area of a device, protects the corner of the trench gate, improves the breakdown voltage of the device, reduces the capacitive coupling between the drain 105 and the gate 111, reduces a Miller platform in the switching process of the device, increases the switching speed of the device, reduces the energy loss, reduces the heat dissipation requirement of the device under high-frequency operation, simultaneously, the T-type epitaxial layer 101 serves as a current diffusion layer here, and weakens the JFET effect of the two P-type base regions 102 and the N-type drift layer 103, the influence of the P-type base region 102 on the on-resistance of the MOSFET device is reduced.
Further, the first source region 106 is a P + -type source region, the material of the P + -type source region is SiC, the doping element of the P + -type source region is B element or Al element, and the doping concentration is 1 × 1019～1×1020/cm3。
in one embodiment, the first source region 106 has a length of 0.25 to 1 μm and a thickness of 0.25 to 1 μm, and the first source region 106 is used to connect the P-type base region 102 to the source electrode 108.
Further, the second source region 107 is an N + type source region, the material of the N + type source region is SiC, the doping element of the N + type source region is P element or N element, and the doping concentration is 1 × 1019～1×1020/cm3。
In one embodiment, the second source region 107 has a length of 0.25 to 1 μm and a thickness of 0.25 to 1 μm. The second source region 107 is used to collect current and conduct it to the source 108.
further, the cross section of the gate dielectric layer 109 is U-shaped, and the gate dielectric layer 109 is made of SiO2The thickness of the gate dielectric layer is 0.05-0.06 μm, and the gate dielectric layer 109 is used for forming a conductive channel.
Further, a polysilicon layer 110 is formed on the inner surface of the U-shaped region of the gate dielectric layer 109, and the polysilicon layer 110 fills the entire U-shapeThe polysilicon is doped P-type in the U-shaped region of the gate dielectric layer 109, the doping element is B element, and the doping concentration is 1 × 1019～1×1020/cm3。
further, the source electrode 108 and the drain electrode 105 are made of Ni/Ti/Ni/Ag laminated metal materials; the material of the gate electrode 111 is Al for forming an ohmic contact.
Referring to fig. 2, fig. 2 is a schematic flow chart of a method for manufacturing a MOSFET device with a silicon carbide bilateral deep L-shaped base region structure according to an embodiment of the present invention; the utility model discloses a preparation method of the two side MOSFET devices of dark L shape base region structure of carborundum still is proposed to another embodiment, include following step:
step 1: selecting a SiC substrate layer 104, and growing a drift layer 103 on the upper surface of the substrate layer 104.
referring to fig. 3, fig. 3 is a schematic cross-sectional structure diagram of a drift layer of a MOSFET device with a sic double-sided deep L-shaped base region structure according to an embodiment of the present invention; epitaxially growing an N-type drift layer 103 on the upper surface of the substrate layer 104 by using an epitaxial growth process, wherein the thickness of the drift layer 103 is 8-10 mu m, the doping element is P element or N element, and the doping concentration of the P element or the N element doped in the N-type drift layer 103 is 1 multiplied by 1015～1×1016/cm3。
Step 2: a base region 102 is grown on the upper surface of the drift layer 103.
referring to fig. 4, fig. 4 is a schematic cross-sectional structure diagram of a base region of a MOSFET device with a silicon carbide bilateral deep L-shaped base region structure according to an embodiment of the present invention; epitaxially growing a P-type base region 102 on the upper surface of the drift layer 103 by using an epitaxial growth process, wherein the thickness of the P-type base region 102 is 1.5-3 μm, the doping element is B element or Al element, and the doping concentration is 1 multiplied by 1017～3×1017/cm3。
And step 3: a first source region 106 is grown in a predetermined area of the base region 102.
Referring to fig. 5, fig. 5 is a schematic cross-sectional structure diagram of a first source region and a second source region of a MOSFET device with a silicon carbide bilateral deep L-shaped base region structure according to an embodiment of the present invention;Growing a P + type source region 106 in a preset region of the P type base region 102 by using an epitaxial growth process or an ion implantation process, wherein the doping element of the P + type source region is a B element or an Al element, and the doping concentration is 1 × 1019～1×1020/cm3。
And 4, step 4: a second source region 107 is grown in the remaining area of the base region 102.
Growing an N + type source region 107 in the rest region of the P type base region 102 by using an epitaxial growth process or an ion implantation process, wherein the doping element of the N + type source region is P element or N element, and the doping concentration is 1 multiplied by 1019～1×1020/cm3。
And 5: the second source region 107 is etched until reaching the upper surface of the drift layer 103, forming a trench with a T-shaped cross section.
Referring to fig. 6, fig. 6 is a schematic cross-sectional structure diagram of a trench of a MOSFET device with a sic bilateral deep L-shaped base region structure according to an embodiment of the present invention; etching the second source region 107 downwards until reaching the upper surface of the drift layer 103, and narrowing the length of the bottom of the trench to make the cross section of the trench in a T shape, so that the base regions 102 positioned at the left and right sides of the trench are in an L shape; wherein the length of the longer region of the trench is 1-4 μm, and the depth is 1-3 μm; the length of the shorter region of the trench is 0.5 to 2 μm and the depth is 0.5 to 1 μm.
step 6: an epitaxial layer 101 is grown in a predetermined region of the trench.
referring to fig. 7, fig. 7 is a schematic cross-sectional structure diagram of an epitaxial layer of a MOSFET device with a silicon carbide bilateral deep L-shaped base region structure according to an embodiment of the present invention; growing an N-type epitaxial layer 101 in a preset region of the groove by using an epitaxial growth process, wherein the doping element of the N-type epitaxial layer 101 is P element or N element, and the doping concentration of the P element or the N element doped in the N-type epitaxial layer 101 is 5 multiplied by 1016～1×1017/cm3。
The epitaxial layer 101 has a T-shaped cross section, is located in the same horizontal direction as the lower surface of the P-type base region 102, and has a thickness of 0.5 to 1.5 μm.
and 7: and oxidizing the inner surface of the rest area of the trench to form a gate dielectric layer 109.
oxidizing SiC around the rest area of the groove by using dry oxygen oxidation and wet oxygen oxidation processes to form a layer of SiO with the thickness of 0.05-0.06 mu m2And the cross section of the gate dielectric layer 109 is U-shaped.
And 8: a polysilicon layer 110 is grown within the gate dielectric layer 109.
Depositing a B-element doped P-type polysilicon layer 110 in the U-shaped region of the gate dielectric layer 109, wherein the doping concentration of the B element is 1 × 1019～1×1020/cm3。
And step 9: preparing and forming a gate 111 on the upper surface of the polysilicon layer 110; preparing and forming a source electrode 108 on the upper surfaces of the first source region 106 and the second source region 107; a drain electrode 105 is formed on the lower surface of the substrate layer 104.
Respectively depositing Al with the thickness of 1-5 mu m on the upper surface of the polycrystalline silicon layer 110 to form a grid 111; depositing a layer of Ni metal with the thickness of 100-500 nm on the upper surfaces of the first source region 106 and the second source region 107, and depositing Ti/Ni/Ag laminated metal with the thickness of 2-5 mu m on the upper surface of the Ni metal to form a source electrode 108; a layer of Ni metal with the thickness of 100-500 nm is deposited on the lower surface of the substrate layer 104, and Ti/Ni/Ag laminated metal with the thickness of 2-5 mu m is deposited on the lower surface of the Ni metal to form a drain electrode 105.
The embodiment of the utility model provides a MOSFET device through this kind of method preparation through the structure that changes the P type base region, under the condition that does not increase device cellular area, has reduced groove grid turning electric field gathering, has improved the breakdown voltage of device.
Furthermore, the embodiment of the utility model provides a P type base region coupling through two dark L shapes has played the effect at protection trench gate turning to compare with traditional trench gate MOSFET structure, not increase extra area, improved the reliability of device, and reduced the complexity and the design cost of device design.
furthermore, the embodiment of the utility model provides a through this kind of structure of P type base region, reduced the capacitive coupling between the grid leakage, reduced the miller platform of device switching in-process, increased the switching speed of device, reduced energy loss, reduced the heat dissipation requirement under the high frequency work of device.
Furthermore, the embodiment of the utility model provides a through dark L shape base region low doping concentration, and contain current diffusion layer (N type epitaxial layer) for the channel of dark L shape base region both sides all can normally be electrically conductive, and improve the breakdown voltage of device through dark L shape base region bottom electric field shielding effect.
in the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
The foregoing is a more detailed description of the present invention, taken in conjunction with the specific preferred embodiments thereof, and it is not intended that the invention be limited to the specific embodiments shown and described. To the utility model belongs to the technical field of ordinary technical personnel, do not deviate from the utility model discloses under the prerequisite of design, can also make a plurality of simple deductions or replacement, all should regard as belonging to the utility model discloses a protection scope.
Claims (9)
1. a MOSFET device with silicon carbide double-sided deep L-shaped base region structure, comprising:
an epitaxial layer;
The base region is positioned on two sides of the epitaxial layer;
The drift layer is positioned on the lower surfaces of the epitaxial layer and the base region;
The substrate layer is positioned on the lower surface of the drift layer;
The drain electrode is positioned on the lower surface of the substrate layer;
the first source region is positioned on the upper surface of the preset region of the base region;
The second source region is positioned on the upper surface of the rest region of the base region;
the source electrode is positioned on the upper surfaces of the first source region and the second source region;
The gate dielectric layer is positioned on the upper surface of the epitaxial layer and is connected with the base region;
the polycrystalline silicon layer is positioned on the inner surface of the gate dielectric layer;
And the grid is positioned on the upper surface of the polycrystalline silicon layer.
2. The MOSFET device with the double-sided deep L-shaped base region structure of silicon carbide according to claim 1, wherein the substrate layer is an N-type doped SiC substrate.
3. the MOSFET device with the silicon carbide double-side deep L-shaped base region structure as claimed in claim 2, wherein the thickness of the substrate layer is 2-5 μm.
4. The MOSFET device with the double-sided deep L-shaped base region structure of claim 1, wherein the base region is a P-type base region with an L-shaped cross section.
5. The MOSFET device with the silicon carbide double-sided deep L-shaped base region structure as claimed in claim 4, wherein the doping element of the base region is B element or Al element.
6. The MOSFET device with the silicon carbide double-sided deep L-shaped base region structure as claimed in claim 5, wherein the doping concentration of each of the B element or the Al element is 1 x 1017～3×1017/cm3。
7. The MOSFET device with the silicon carbide double-sided deep L-shaped base region structure as claimed in claim 1, wherein the doping element of the first source region is B element or Al element.
8. The MOSFET device with the silicon carbide double-sided deep L-shaped base region structure as claimed in claim 1, wherein the doping element of the second source region is P element or N element.
9. The MOSFET device with the sic double-sided deep L-shaped base region structure as claimed in claim 1, wherein the source electrode and the drain electrode are both made of Ni/Ti/Ni/Ag stacked metal material; the grid electrode is made of Al.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110190128A (en) * | 2019-05-29 | 2019-08-30 | 西安电子科技大学芜湖研究院 | A kind of MOSFET element and preparation method thereof of silicon carbide bilateral depth L shape base region structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110190128A (en) * | 2019-05-29 | 2019-08-30 | 西安电子科技大学芜湖研究院 | A kind of MOSFET element and preparation method thereof of silicon carbide bilateral depth L shape base region structure |
| CN110190128B (en) * | 2019-05-29 | 2024-03-19 | 西安电子科技大学芜湖研究院 | MOSFET device with silicon carbide double-side deep L-shaped base region structure and preparation method thereof |
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