JP3998454B2 - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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Publication number
JP3998454B2
JP3998454B2 JP2001335530A JP2001335530A JP3998454B2 JP 3998454 B2 JP3998454 B2 JP 3998454B2 JP 2001335530 A JP2001335530 A JP 2001335530A JP 2001335530 A JP2001335530 A JP 2001335530A JP 3998454 B2 JP3998454 B2 JP 3998454B2
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semiconductor layer
layer
semiconductor device
conductivity type
power
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JP2003142698A (en
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渉 齋藤
一郎 大村
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Toshiba Corp
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Toshiba Corp
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Description

【０００１】
【発明の属する技術分野】
本発明は、電力用半導体装置に係り、特にショッキーバリアダイオード（ＳＢＤ）の構造に関するもので、ＳＢＤ、ＳＢＤ搭載ＭＯＳパワートランジスタなどに使用されるものである。
【０００２】
【従来の技術】
ＳＢＤのオン電圧は、ショットキー障壁高さと電子が走行するドリフト層（伝導層）の電圧降下で決まり、それを下げるには、ショットキー障壁高さの低い金属を用いるか、ドリフト層の抵抗を下げる必要がある。
【０００３】
しかし、ショットキー障壁高さの低い金属を用いると、ダイオードの逆方向リーク電流が増加してしまう。また、ドリフト層の抵抗は、耐圧とトレードオフの関係があり、このトレードオフは材料により決まる。材料を変更せずにドリフト層の抵抗を下げるには、チップ面積を大きくする必要がある。
【０００４】
【発明が解決しようとする課題】
上記したように従来のＳＢＤは、オン電圧を低減しようとすると逆方向リーク電流の増加による逆方向特性の劣化や耐圧の劣化によるチップ面積の増大が伴ってしまうという問題があった。
【０００５】
本発明は上記の問題点を解決すべくなされたもので、ＳＢＤの逆方向特性の劣化やチップ面積の増大を伴わずに、ドリフト層の抵抗を下げ、オン電圧を低減し得る電力用半導体装置を提供することを目的とする。
【０００６】
【課題を解決するための手段】
本発明の電力用半導体装置は、第１導電型の第１の半導体層と、前記第１の半導体層上に形成され、前記第１の半導体層よりも不純物濃度が低い第１導電型の第２の半導体層と、前記第２の半導体層の表面から前記第１の半導体層に達するように形成された第１導電型の第３の半導体層と、前記第２の半導体層の表面から所定の深さまで形成された溝の底部の周辺部に形成された第２導電型の第４の半導体層と、前記溝の内部に埋め込まれて前記第４の半導体層と電気的に接続され、前記第２の半導体層とショットキー接合を形成する第１の主電極と、前記第１の半導体層に電気的に接続された第２の主電極とを具備することを特徴とする。
【０００７】
【発明の実施の形態】
以下、図面を参照して本発明の実施の形態を詳細に説明する。なお、以下の実施形態では、第１導電型をｎ型、第２導電型をｐ型としている。また、図面中の同一部分には同一符号を付している。
【０００８】
＜第１の実施形態＞
図１（ａ）は、本発明の第１の実施形態に係るＳＢＤの一部を模式的に示す断面図である。ここでは、ＳＢＤを形成する多数のＳＢＤセルのうちの１個分を取り出して示している。
【０００９】
図１（ｂ）は、同図（ａ）のＳＢＤのレイアウトパターンの一部を示す平面図である。
【００１０】
図１（ａ）、（ｂ）に示すＳＢＤにおいては、第１の半導体層であるｎ＋基板１上に第２の半導体層として形成されたｎ−ドリフト層２の表面の一部からｎ＋基板１まで達するようにｎ＋層３が形成されている。
【００１１】
また、上記ｎ−ドリフト層２の表面の一部から所定の深さまで形成された溝（トレンチ）の底部にはガードリングの役目をするｐ層４が形成されており、溝の内部には、ｎ−ドリフト層２に対してショットキー接合を形成するショットキー電極５が埋め込まれている。そして、ｎ＋基板表面にはオーミック電極６が形成されている。
【００１２】
前記ｎ−ドリフト層２は、例えば、約１０μｍの厚さで、１×１０16ｃｍ-3の不純物濃度を有する。前記ｎ＋層３は、例えば、約１×１０20ｃｍ-3の不純物濃度を有する多結晶シリコンで幅が１μｍのストライプ状に形成されている。
【００１３】
前記ガードリング用のｐ層４は、例えば接合深さが１μｍで形成されており、ショットキー電極５は、例えば、深さが７．５μｍで幅が１μｍのストライプ状に形成されている。
【００１４】
上記したようにｎ−ドリフト層２の表面部の溝内にｎ＋基板１まで達するｎ＋層３とｎ−ドリフト層２の中間まで達するショットキー電極５を形成し、ｎ＋基板１およびｎ＋層３に電気的に接続されているオーミック電極６を基板表面に形成した横型構造のＳＢＤを構成している。
【００１５】
このような横型構造のＳＢＤによれば、通常の縦型ＳＢＤと比べて逆方向特性は変化しない。しかも、チップ面積とは独立に溝の深さによりドリフト層に接合するショットキー電極の面積が決まり、溝を深くすることによりショットキー電極の面積を増やし、ドリフト層の抵抗を下げることが可能となり、低いオン電圧を実現することができる。
【００１６】
因みに、上記実施形態のＳＢＤによれば、例えば４０Ｖ程度の耐圧を保持したまま、チップ面積を増加させずに、ドリフト層の抵抗を通常の縦型ＳＢＤの半分程度に下げることができる。
【００１７】
＜第２の実施形態＞
第２の実施形態に係るＳＢＤは、図１（ａ）、（ｂ）を参照して前述した第１の実施形態に係るＳＢＤと構造は同一である。
【００１８】
図２は、本発明の第２の実施形態に係るＳＢＤのトレンチの深さｄとｎ−ドリフト層２のオン抵抗の関係の一例を示す特性図である。
【００１９】
図２に示すように、トレンチの深さ（Schottky接合の深さ）ｄを深くしていくと、ｎ−ドリフト層２の断面積が増えたことになり、ｎ−ドリフト層２の抵抗は小さくなる。この場合、トレンチ深さｄと、ショットキー電極５とｎ＋層３との距離（ｎ−ドリフト層２の長さ）ａの比を１．１以上とすることにより、ドリフト層断面積を大きくでき、ｎ−ドリフト層２のオン抵抗が通常の縦型ＳＢＤよりも低くなり、低オン電圧化に有効となる。
【００２０】
＜第３の実施形態＞
図３は、本発明の第３の実施形態に係るＳＢＤの一部を模式的に示す断面図である。
【００２１】
このＳＢＤは、図１（ａ）、（ｂ）を参照して前述した第１の実施形態に係るＳＢＤと基本構造は同一であるが、ガードリングｐ層４とｎ＋基板１との距離がガードリングｐ層４とｎ＋層３との距離よりも近い構造となっている点に特徴がある。
【００２２】
このような構造によれば、高電圧印加時にはガードリングｐ層４とｎ＋基板１との間の電界が高くなり、アバランシェ降伏が起きる。この降伏時に発生するホールと電子はそれぞれガードリングｐ層４とｎ＋基板１に速やかに流れ込み、ショットキー接合には影響を及ぼさないので、アバランシェ耐量が確保される。
【００２３】
＜第４の実施形態＞
図４（ａ）は、本発明の第４の実施形態に係るＳＢＤにおけるショットキー電極およびガードリングｐ層とｎ＋層３の１組を含む一部を取り出して模式的に示す斜視図である。
【００２４】
図４（ｂ）は、同図（ａ）中のＡ−Ａ´線に沿う断面構造を模式的に示す断面図である。
【００２５】
図４（ｃ）は、同図（ａ）中のＢ−Ｂ´線に沿う断面構造を模式的に示す断面図である。
【００２６】
図４（ａ）、（ｂ）、（ｃ）に示すＳＢＤは、図１（ａ）、（ｂ）を参照して前述した第１の実施形態に係るＳＢＤと比べて、基本構造は同一であるが、ガードリングｐ層４が溝の内部の第１の対をなす相対する側壁部の周辺部まで延びるように形成されている点が異なる。
【００２７】
したがって、ストライプ状に形成されているショットキー電極５は、溝の内部の第２の対をなす相対する側壁部でｎ−ドリフト層２とショットキー接合を形成している。
【００２８】
このようにショットキー電極５の底面部および一対の側端面部を囲むようにガードリングｐ層４を形成することにより、ショットキー電極５の底面・側端面の角部にショットキー接合が形成されなくなるので、ショットキー電極５の端部の電界集中を避け、逆方向リーク電流の増大を抑制することが可能になる。
【００２９】
＜第５の実施形態＞
図５（ａ）は、本発明の第５の実施形態に係るＳＢＤにおけるショットキー電極およびガードリングｐ層の一部を取り出して模式的に示す斜視図である。
【００３０】
図５（ｂ）は、同図（ａ）中のＡ−Ａ´線に沿う断面構造を模式的に示す断面図である。
【００３１】
図５（ａ）、（ｂ）に示すＳＢＤは、図４（ａ）、（ｂ）を参照して前述した第４の実施形態に係るＳＢＤと比べて、溝がその長さ方向において間欠的に分断された島状に形成されており、それに対応して溝に埋め込まれているショットキー電極５およびその底面部および一対の側端面部を囲むガードリングｐ層４も島状に形成されている点が異なる。
【００３２】
したがって、第４の実施形態のようにショットキー電極５をストライプ状に連続的に形成するよりも、ショットキー接合の面積が減少するので、逆方向リーク電流を減少することが可能になる。この際、第４の実施形態のようにショットキー電極５をストライプ状に連続的に形成するよりもショットキー電極５の面積が減少するので、広がり抵抗が増加し、ドリフト層の抵抗は微増するという犠牲が生じるが、前記した逆方向リーク電流の減少効果は十分に大きい。
【００３３】
＜第６の実施形態＞
図６（ａ）は、本発明の第６の実施形態に係るＳＢＤにおけるショットキー電極５およびガードリングｐ層４の一部を取り出して模式的に示す斜視図である。
【００３４】
図６（ｂ）は、同図（ａ）中のＡ−Ａ´線に沿う断面構造を模式的に示す断面図である。
【００３５】
図６（ａ）、（ｂ）に示すＳＢＤは、図５（ａ）、（ｂ）を参照して前述した第４の実施形態に係るＳＢＤと比べて、基本構造は同一であるが、ストライプ方向における島状のショットキー電極５が高密度で配列されており、その配列方向において隣り合うガードリングｐ層４の一端部同士が連なるように形成されている点が異なる。
【００３６】
したがって、リーク電流の抑制に関しては第５の実施形態と同様な効果が得られ、第５の実施形態と比べて、ショットキー電極５の面積が増加するので広がり抵抗を小さくすることができ、ドリフト層の抵抗の増加を抑制することが可能になる。
【００３７】
＜第７の実施形態＞
図７は、本発明の第７の実施形態に係るＳＢＤの一部を模式的に示す断面図である。
【００３８】
このＳＢＤは、図１（ａ）、（ｂ）を参照して前述した第１の実施形態に係るＳＢＤと基本構造は同一であるが、ｎ−ドリフト層２とｎ＋層３の各表面に形成された絶縁膜７上にもショットキー電極５が形成されている点に特徴がある。
【００３９】
このようにショットキー電極５が絶縁膜７を介してｎ−ドリフト層２とｎ＋層３の各表面上を覆うように形成されている構造によれば、絶縁膜７上のショットキー電極５がフィールドプレートの役目をするので、耐圧を十分に確保し、リーク電流を抑制することが可能になる。
【００４０】
因みに、耐圧４０Ｖの素子の場合、絶縁膜７として例えば厚さが１００ｎｍの酸化膜で形成することができる。
【００４１】
＜第８の実施形態＞
図８は、本発明の第８の実施形態に係るＳＢＤの一部を取り出して模式的に示す断面図である。
【００４２】
このＳＢＤは、図４を参照して前述した第４の実施形態に係るＳＢＤと比べて、基本構造は同一であるが、ショットキー電極５およびその側端部のガードリングｐ層４を囲むように形成されているｎ−ドリフト層２の外周を取り囲むようにｎ＋層３が形成されている点が異なる。
【００４３】
このようにｎ＋層３が素子の外周を取り囲む構造によれば、素子の終端部処理が不要となり、チップ面積を有効に使用することが可能になる。
【００４４】
＜第９の実施形態＞
図９（ａ）乃至（ｇ）は、第９の実施形態に係るＳＢＤのプロセスフローの一部を模式的に示す断面図である。
【００４５】
まず、ｎ＋基板１上にｎ−ドリフト層２が形成された元基板を形成し、全面にマスク材のパターン９１を形成し、表面の一部からｎ＋基板１まで達する溝９２を選択的に形成し、この溝９２内をｎ＋にドーピングされた多結晶シリコン（ｎ＋層）３で埋め込む。
【００４６】
次に、全面に例えば酸化膜７のパターンを形成し、ｎ−ドリフト層２の中間深さまで達する溝９３を選択的に形成し、上面からｐ型不純物のイオン注入を行う。この際、酸化膜７がイオン注入をブロックするマスクとなるので、溝９３の底面周辺部のみに選択的にガードリングｐ層４が形成される。
【００４７】
そして、ショットキー電極５を形成するための金属を全面に堆積するとともに溝９３内に埋め込み、最後に裏面にカソード電極６を形成する。
【００４８】
上記したように、前記ｎ＋層３を形成する際、溝９２内の埋め込み材料に多結晶シリコンを用いることにより埋め込みが容易となる。これに対して、溝９２を形成した後に上面からイオン注入を行い、拡散してもよいが、ｎ−ドリフト層２に対してｎ＋層３が占める割合が大きくなる。
【００４９】
また、ｎ＋層３を形成する際、溝９２を形成した後に斜め方向からイオン注入を行って溝９２の内壁に沿ってｎ＋層３を形成し、さらに溝９２内を絶縁物もしくは金属で埋め込んでもよい。
【００５０】
なお、前記溝を形成する際、ドライエッチングを用いてもアルカリ系エッチャントを用いたウェットエッチングでもよいが、ショットキー電極埋め込み用の溝９３を形成する際にドライエッチングを用いると、溝９３の内壁にエッチングのダメージにより欠陥が発生する。このままの状態でショットキー電極金属を蒸着してショットキー接合を形成すると、ショットキー接合面に含まれる欠陥に起因して逆方向リーク電流が増加してしまう。
【００５１】
そこで、本発明において溝を形成する際にドライエッチングを用いる場合は、エッチングで発生した欠陥を含むエッチング表面をショットキー接合面とせず、エッチング表面の結晶欠陥を取り除くために、溝９３内に蒸着されたショットキー電極金属を熱処理によりシリコン内に拡散させ、エッチング面でなくシリコン内側にショットキー接合面を形成する。これにより、欠陥の少ないショットキー接合を形成し、エッチングダメージによる逆方向リーク電流の増加を抑制することが可能になる。
【００５２】
なお、金属のシリコン内部への拡散の度合いは金属の種類により決まるので、ショットキー電極金属としては、高温熱処理を加えることで金属蒸着面からシリコン内部への拡散が生じ、且つ、ショットキー接合を形成することが可能なＣｏ、Ｎｉ、Ｖ、Ｐｔ等のいずれかを用いることが望ましい。
【００５３】
＜第１０の実施形態＞
図１０は、本発明の第１０の実施形態に係るＳＢＤの一部を取り出して模式的に示す断面図である。
【００５４】
このＳＢＤは、例えば図１を参照して前述した第１の実施形態に係るＳＢＤなどと比べて、ドリフト層にスーパージャンクション（超接合）構造と呼ばれるリサーフ構造を埋め込んだ構造を有する点が異なる。
【００５５】
即ち、ｎ−ドリフト層２上のショットキー電極５とｎ＋層３の間との間で、ｎ−ドリフト層２よりも高不純物濃度のｎ層８およびｐ層９が深さ方向において周期的に形成されている。
【００５６】
このようにドリフト層部分にｎ−ドリフト層２よりも高濃度のｎ層８を有するスーパージャンクション構造によれば、ドリフト層の抵抗をさらに下げることができるので、図２を参照して前述したショットキー電極埋め込み用の溝の深さｄとドリフト層の距離ａの比を１．１以下としても、通常の縦型ＳＢＤよりもオン抵抗を小さくすることが可能になる。
【００５７】
＜第１１の実施形態＞
図１１は、本発明の第１１の実施形態に係るＳＢＤの一部を取り出して模式的に示す断面図である。
【００５８】
このＳＢＤは、例えば図１を参照して前述した第１の実施形態に係るＳＢＤなどと比べて、ｎ−ドリフト層２の上部をｎ層１０、下部をｐ−層１１に変更した点が異なる。
【００５９】
このような構造によれば、ガードリングｐ層４とｎ層１０とのｐｎ接合面よりもｐ−層１１とｎ＋基板１およびｎ層３とのフラットな接合面を大きくすることができるので、電界集中を避け、耐量を増加することが可能である。
【００６０】
＜第１２の実施形態＞
図１２は、本発明の第１２の実施形態に係るＳＢＤの一部を取り出して模式的に示す断面図である。
【００６１】
このＳＢＤは、図１１を参照して前述した第１１の実施形態に係るＳＢＤと比べて、ｎ層１０のうちでショットキー電極埋め込み用の溝の側壁部付近を不純物濃度が低いｎ−層１２に変更した点が異なる。
【００６２】
このような構造によれば、ショットキー接合面に含まれる欠陥に起因する逆方向リーク電流を一層抑制することが可能である。
【００６３】
なお、図１を参照して前述した第１の実施形態に係るＳＢＤについても、ショットキー電極埋め込み用の溝の側壁部付近を不純物濃度が低いｎ−層に変更しても、ショットキー接合面に含まれる欠陥に起因する逆方向リーク電流を抑制することが可能である。
【００６４】
＜第１３の実施形態＞
ＭＯＳＦＥＴをスイッチング電源やインバータなどに応用する際、ＭＯＳＦＥＴとＳＢＤを同一半導体チップ上に形成する場合がある。
【００６５】
この場合、例えば図１３に示す平面図のように、半導体チップ１３上に前記各実施形態で説明したようなＳＢＤの領域１３１とＭＯＳＦＥＴの領域１３２とを絶縁分離して配置することが可能である。
【００６６】
＜第１４の実施形態＞
ＭＯＳＦＥＴとＳＢＤを同一半導体チップ上で上下方向に重ねて形成するとともに両者を接続して使用する場合には、例えば図１４に示す断面図のように、ｎ−ドリフト層２に溝を形成して電極５およびｎ＋層３を埋め込み、ｎ−ドリフト層２の下部をＳＢＤ領域、上部をＭＯＳＦＥＴ領域に割り当てる。
【００６７】
ｎ−ドリフト層２の表層部で溝内に埋め込まれた電極５とｎ＋層３との間の領域内に選択的にＭＯＳＦＥＴの例えばＰウエル領域１４を形成し、その表層部で電極５に隣接するようにＭＯＳＦＥＴのドレインまたはソースとなるｎ＋領域１５を形成する。そして、このｎ＋領域１５とｎ−ドリフト層２との間のＰウエル領域表層部（チャネル領域）上にゲート絶縁膜１６を介してゲート電極１７を形成する。したがって、電極５の下部をＳＢＤのショットキー電極、上部をＳＢＤとＭＯＳＦＥＴとの接続配線として用いている。
【００６８】
＜第１５の実施形態＞
図１５は、本発明の第１５の実施形態に係るＳＢＤの一部を取り出して模式的に示す断面図である。
【００６９】
このＳＢＤは、例えば図７を参照して前述したＳＢＤと比べて、横型構造である点は同じであるが、基本構造が若干異なる。
【００７０】
即ち、ｐ基板１８上にｎ−ドリフト層２が形成され、その表面の一部からｐ基板１８まで達するように形成された溝にショットキー電極５が埋め込まれている。このショットキー電極５は、ｎ−ドリフト層２に対してショットキー接合を形成し、ｐ基板１８に対して電気的に接続されており、このｐ基板１８の裏面にはアノード電極１９が形成されている。
【００７１】
そして、前記ｎ−ドリフト層２の表面の一部から中間の深さまで形成された溝にｎ＋層３が埋め込まれており、ｎ−ドリフト層２とｎ＋層３の各表面に形成された絶縁膜２０上にカソード電極６が形成されており、このカソード電極６は前記絶縁膜２０に形成されたコンタクトホールを通じてｎ＋層３に電気的に接続されている。
【００７２】
このような構造によれば、ショットキー電極５とｐ基板１８との平坦な部分にダイオードの接合面が形成されるので、電界集中が発生し難くなり、かつ、ショットキー接合に加わる電界を小さくすることができ、逆方向リーク電流を抑制することが可能になる。
【００７３】
図１６（ａ）は、図１５のＳＢＤのレイアウトパターンの一部を示す平面図である。
【００７４】
図１６（ｂ）は、同図（ａ）中のＡ−Ａ´線に沿う断面構造を模式的に示す断面図である。
【００７５】
図１６（ａ）、（ｂ）に示すＳＢＤは、ｎ−ドリフト層２の外周を取り囲むようにショットキー電極５が形成されている。
【００７６】
このようにショットキー電極５が素子の外周を取り囲む構造によれば、アノード電極１９と同電位になるショットキー接合で素子の外周が囲まれるので、素子の終端部構造が不要となり、素子面積の有効利用を図ることが可能になる。
【００７７】
なお、図２に示したＳＢＤと同様に、ショットキー電極５の深さをショットキー電極５とｎ＋層３との間の距離よりも大きくすることにより、高電圧印加時にアバランシェ降伏がｎ＋層３とｐ基板１８との間で生じ、ホールが速やかにｐ基板１８に流れ込むようになり、アバランシェ耐量を確保することが可能になる。
【００７８】
また、ショットキー電極５とｎ＋層３との間にスーパージャンクション構造を設けることにより、オン抵抗をさらに低くすることが可能になる。
【００７９】
＜第１６の実施形態＞
図１７は、本発明の第１６の実施形態に係るＳＢＤの一部を取り出して模式的に示す断面図である。
【００８０】
このＳＢＤは、例えば図７を参照して前述したＳＢＤと比べて、横型構造である点は同じであるが、アノード電極１９とカソード電極６の両方が基板上面に取り出されている点が異なる。
【００８１】
即ち、ｎ−層２の表面の一部からそれぞれ中間の深さまで形成された溝にショットキー電極５およびｎ＋層３が埋め込まれており、ｎ−層２とｎ＋層３の各表面に形成された絶縁膜２０上にアノード電極１９とカソード電極６が形成されている。アノード電極１９は絶縁膜２０に形成されたコンタクトホールを通じてショットキー電極５に電気的に接続されており、カソード電極６は絶縁膜２０に形成されたコンタクトホールを通じてｎ＋層３に電気的に接続されている。
【００８２】
このような構造によれば、基板裏面より電極を取り出す必要がなくなり、高濃度のｎ＋基板上にｎ−層をエピタキシャル成長させた半導体ウエハを用いる必要がない。
【００８３】
また、化合物半導体を用いてＳＢＤを形成する場合は、半絶縁性基板上にｎ−層２を形成しても上記構造を実施することが可能である。
【００８４】
なお、本発明は、前記各実施形態に限定されるものではなく、第１の導電型をｐ型、第２の導電型をｎ型としても実施可能である。また、ショットキー電極５やｎ＋層３およびそれらが埋め込まれている溝の平面パターンは、ストライプ状に限らず、格子状や千鳥状に形成してもよい。
【００８５】
また、半導体としては、シリコン（Ｓｉ）を用いた場合を説明したが、例えばシリコンカーバイト（ＳｉＣ）や窒化ガリウム（ＧａＮ）等の化合物半導体やダイアモンド（Ｃ）を用いることができる。
【００８６】
【発明の効果】
上述したように本発明の電力用半導体装置によれば、ＳＢＤの逆方向特性の劣化やチップ面積の増大を伴わずに、ドリフト層の抵抗を下げ、オン電圧を低減することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係るＳＢＤの一部を示す断面図および平面図。
【図２】本発明の第２の実施形態に係るＳＢＤのショットキー電極の深さｄとｎ−ドリフト層のオン抵抗の関係の一例を示す特性図。
【図３】本発明の第３の実施形態に係るＳＢＤの一部を示す断面図。
【図４】本発明の第４の実施形態に係るＳＢＤにおけるショットキー電極およびガードリングｐ層とｎ＋層の１組を含む一部を示す斜視図および図中のＡ−Ａ´線、Ｂ−Ｂ´線に沿う断面図。
【図５】本発明の第５の実施形態に係るＳＢＤにおけるショットキー電極およびガードリングｐ層の一部を示す斜視図および図中のＡ−Ａ´線に沿う断面図。
【図６】本発明の第６の実施形態に係るＳＢＤにおけるショットキー電極およびガードリングｐ層の一部を示す斜視図および図中のＡ−Ａ´線に沿う断面図。
【図７】本発明の第７の実施形態に係るＳＢＤの一部を示す断面図。
【図８】本発明の第８の実施形態に係るＳＢＤの一部を示す断面図。
【図９】本発明の第９の実施形態に係るＳＢＤのプロセスフローの一部を示す断面図。
【図１０】本発明の第１０の実施形態に係るＳＢＤの一部を示す断面図。
【図１１】本発明の第１１の実施形態に係るＳＢＤの一部を示す断面図。
【図１２】本発明の第１２の実施形態に係るＳＢＤの一部を示す断面図。
【図１３】本発明の第１３の実施形態に係るＳＢＤとＭＯＳＦＥＴが同一チップ上に形成されている半導体装置を概略的に示す平面図。
【図１４】本発明の第１３の実施形態に係るＳＢＤとＭＯＳＦＥＴが同一半導体チップ上で上下方向に重ねられて形成されるとともに両者が接続されている半導体装置の一部を概略的に示す断面図。
【図１５】本発明の第１５の実施形態に係るＳＢＤの一部を示す断面図。
【図１６】図１５のＳＢＤのレイアウトパターンの一部を示す平面図および図中のＡ−Ａ´線に沿う断面図。
【図１７】本発明の第１６の実施形態に係るＳＢＤの一部を断面図。
【符号の説明】
１…ｎ＋基板（第１の半導体層）、
２…ｎ−ドリフト層（第２の半導体層）、
３…ｎ＋層（第３の半導体層）、
４…ガードリングｐ層（第４の半導体層）、
５…ショットキー電極（第１の主電極）
６…オーミック電極（第２の主電極）、
７…絶縁膜。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power semiconductor device, and more particularly to a structure of a Shocky Barrier Diode (SBD), which is used for an SBD, an SBD-mounted MOS power transistor, and the like.
[0002]
[Prior art]
The on-voltage of the SBD is determined by the Schottky barrier height and the voltage drop of the drift layer (conducting layer) where electrons travel. To lower it, use a metal with a low Schottky barrier height or change the resistance of the drift layer. Need to lower.
[0003]
However, using a metal with a low Schottky barrier height increases the reverse leakage current of the diode. Further, the resistance of the drift layer has a trade-off relationship with the withstand voltage, and this trade-off is determined by the material. In order to reduce the resistance of the drift layer without changing the material, it is necessary to increase the chip area.
[0004]
[Problems to be solved by the invention]
As described above, the conventional SBD has a problem that when the on-voltage is reduced, the reverse characteristic is deteriorated due to the increase of the reverse leakage current and the chip area is increased due to the breakdown voltage.
[0005]
The present invention has been made to solve the above problems, and a power semiconductor device capable of reducing the resistance of the drift layer and reducing the on-voltage without deteriorating the reverse characteristics of the SBD and increasing the chip area. The purpose is to provide.
[0006]
[Means for Solving the Problems]
A power semiconductor device according to the present invention includes a first conductivity type first semiconductor layer and a first conductivity type first semiconductor layer formed on the first semiconductor layer and having an impurity concentration lower than that of the first semiconductor layer. Two semiconductor layers, a third semiconductor layer of the first conductivity type formed so as to reach the first semiconductor layer from the surface of the second semiconductor layer, and a predetermined amount from the surface of the second semiconductor layer. A fourth semiconductor layer of the second conductivity type formed at the periphery of the bottom of the groove formed to a depth of, and embedded in the groove and electrically connected to the fourth semiconductor layer, A first main electrode that forms a Schottky junction with the second semiconductor layer, and a second main electrode electrically connected to the first semiconductor layer are provided.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type. Moreover, the same code | symbol is attached | subjected to the same part in drawing.
[0008]
<First Embodiment>
FIG. 1A is a cross-sectional view schematically showing a part of the SBD according to the first embodiment of the present invention. Here, one of a number of SBD cells forming the SBD is taken out.
[0009]
FIG. 1B is a plan view showing a part of the layout pattern of the SBD of FIG.
[0010]
In the SBD shown in FIGS. 1A and 1B, the n + substrate 1 is formed from a part of the surface of the n− drift layer 2 formed as the second semiconductor layer on the n + substrate 1 which is the first semiconductor layer. The n + layer 3 is formed so as to reach the maximum.
[0011]
A p layer 4 serving as a guard ring is formed at the bottom of a groove (trench) formed from a part of the surface of the n-drift layer 2 to a predetermined depth. Inside the groove, A Schottky electrode 5 forming a Schottky junction is embedded in the n − drift layer 2. An ohmic electrode 6 is formed on the surface of the n + substrate.
[0012]
The n − drift layer 2 has a thickness of about 10 μm and an impurity concentration of 1 × 10 16 cm −3 , for example. The n + layer 3 is formed of, for example, polycrystalline silicon having an impurity concentration of about 1 × 10 20 cm −3 in a stripe shape having a width of 1 μm.
[0013]
The guard ring p-layer 4 is formed with a junction depth of 1 μm, for example, and the Schottky electrode 5 is formed in a stripe shape with a depth of 7.5 μm and a width of 1 μm, for example.
[0014]
As described above, the n + layer 3 reaching the n + substrate 1 and the Schottky electrode 5 reaching the middle of the n− drift layer 2 are formed in the groove in the surface portion of the n− drift layer 2, and the n + substrate 1 and the n + layer 3 are formed on the n + substrate 1. An SBD having a lateral structure in which an ohmic electrode 6 that is electrically connected is formed on the substrate surface is formed.
[0015]
According to the SBD having such a horizontal structure, the reverse characteristics do not change as compared with a normal vertical SBD. In addition, the area of the Schottky electrode to be joined to the drift layer is determined by the depth of the groove independently of the chip area, and by increasing the depth of the groove, the area of the Schottky electrode can be increased and the resistance of the drift layer can be lowered. A low on-voltage can be realized.
[0016]
Incidentally, according to the SBD of the above embodiment, the resistance of the drift layer can be lowered to about half that of a normal vertical SBD without increasing the chip area while maintaining a breakdown voltage of, for example, about 40V.
[0017]
<Second Embodiment>
The SBD according to the second embodiment has the same structure as the SBD according to the first embodiment described above with reference to FIGS.
[0018]
FIG. 2 is a characteristic diagram showing an example of the relationship between the trench depth d of the SBD and the on-resistance of the n− drift layer 2 according to the second embodiment of the present invention.
[0019]
As shown in FIG. 2, when the trench depth (Schottky junction depth) d is increased, the cross-sectional area of the n-drift layer 2 increases, and the resistance of the n-drift layer 2 decreases. Become. In this case, the drift layer cross-sectional area can be increased by setting the ratio of the trench depth d and the distance (the length of the n− drift layer 2) a between the Schottky electrode 5 and the n + layer 3 to 1.1 or more. The on-resistance of the n − drift layer 2 is lower than that of a normal vertical SBD, which is effective for lowering the on-voltage.
[0020]
<Third Embodiment>
FIG. 3 is a cross-sectional view schematically showing a part of the SBD according to the third embodiment of the present invention.
[0021]
This SBD has the same basic structure as that of the SBD according to the first embodiment described above with reference to FIGS. 1A and 1B, but the distance between the guard ring p layer 4 and the n + substrate 1 is a guard. It is characterized in that the structure is closer than the distance between the ring p layer 4 and the n + layer 3.
[0022]
According to such a structure, when a high voltage is applied, the electric field between the guard ring p layer 4 and the n + substrate 1 becomes high, and avalanche breakdown occurs. The holes and electrons generated at the time of breakdown flow quickly into the guard ring p layer 4 and the n + substrate 1 respectively and do not affect the Schottky junction, so that avalanche resistance is ensured.
[0023]
<Fourth Embodiment>
FIG. 4A is a perspective view schematically showing a part including one set of a Schottky electrode, a guard ring p layer, and an n + layer 3 in an SBD according to the fourth embodiment of the present invention.
[0024]
FIG. 4B is a cross-sectional view schematically showing a cross-sectional structure along the line AA ′ in FIG.
[0025]
FIG. 4C is a cross-sectional view schematically showing a cross-sectional structure along the line BB ′ in FIG.
[0026]
The SBD shown in FIGS. 4A, 4B, and 4C has the same basic structure as the SBD according to the first embodiment described above with reference to FIGS. 1A and 1B. There is a difference in that the guard ring p layer 4 is formed so as to extend to the peripheral portions of the opposing side wall portions forming the first pair inside the groove.
[0027]
Accordingly, the Schottky electrode 5 formed in a stripe shape forms a Schottky junction with the n-drift layer 2 at the opposing side wall portions forming the second pair inside the trench.
[0028]
Thus, by forming the guard ring p layer 4 so as to surround the bottom surface portion of the Schottky electrode 5 and the pair of side end surface portions, a Schottky junction is formed at the corner portions of the bottom surface and the side end surfaces of the Schottky electrode 5. Therefore, it is possible to avoid the concentration of the electric field at the end of the Schottky electrode 5 and to suppress an increase in reverse leakage current.
[0029]
<Fifth Embodiment>
FIG. 5A is a perspective view schematically showing a part of the Schottky electrode and the guard ring p layer in the SBD according to the fifth embodiment of the present invention.
[0030]
FIG. 5B is a cross-sectional view schematically showing a cross-sectional structure along the line AA ′ in FIG.
[0031]
The SBD shown in FIGS. 5 (a) and 5 (b) is intermittent in the length direction compared to the SBD according to the fourth embodiment described above with reference to FIGS. 4 (a) and 4 (b). Correspondingly, the Schottky electrode 5 embedded in the groove and the guard ring p layer 4 surrounding the bottom surface portion and the pair of side end surface portions are also formed in the island shape. Is different.
[0032]
Accordingly, since the area of the Schottky junction is reduced as compared with the case where the Schottky electrodes 5 are continuously formed in a stripe shape as in the fourth embodiment, the reverse leakage current can be reduced. At this time, since the area of the Schottky electrode 5 is reduced as compared with the case where the Schottky electrode 5 is continuously formed in a stripe shape as in the fourth embodiment, the spreading resistance is increased and the resistance of the drift layer is slightly increased. However, the effect of reducing the reverse leakage current is sufficiently large.
[0033]
<Sixth Embodiment>
FIG. 6A is a perspective view schematically showing a part of the Schottky electrode 5 and the guard ring p layer 4 in the SBD according to the sixth embodiment of the present invention.
[0034]
FIG. 6B is a cross-sectional view schematically showing a cross-sectional structure along the line AA ′ in FIG.
[0035]
The SBD shown in FIGS. 6A and 6B has the same basic structure as the SBD according to the fourth embodiment described above with reference to FIGS. islands Schottky electrode 5 in the direction are arranged at a high density, that it is formed as one end portions of the guard ring p layer 4 adjacent in the arrangement direction thereof is contiguous differ.
[0036]
Accordingly, the same effect as that of the fifth embodiment can be obtained with respect to the suppression of the leakage current, and the area of the Schottky electrode 5 is increased as compared with the fifth embodiment, so that the spreading resistance can be reduced and the drift can be reduced. It becomes possible to suppress an increase in the resistance of the layer.
[0037]
<Seventh Embodiment>
FIG. 7 is a cross-sectional view schematically showing a part of the SBD according to the seventh embodiment of the present invention.
[0038]
This SBD has the same basic structure as the SBD according to the first embodiment described above with reference to FIGS. 1A and 1B, but is formed on each surface of the n− drift layer 2 and the n + layer 3. The Schottky electrode 5 is also formed on the insulating film 7 formed.
[0039]
Thus, according to the structure in which the Schottky electrode 5 is formed so as to cover the surfaces of the n− drift layer 2 and the n + layer 3 through the insulating film 7, the Schottky electrode 5 on the insulating film 7 is Since it functions as a field plate, it is possible to secure a sufficient breakdown voltage and suppress a leakage current.
[0040]
Incidentally, in the case of an element having a withstand voltage of 40 V, the insulating film 7 can be formed of, for example, an oxide film having a thickness of 100 nm.
[0041]
<Eighth Embodiment>
FIG. 8 is a cross-sectional view schematically showing a part of the SBD according to the eighth embodiment of the present invention.
[0042]
The SBD has the same basic structure as the SBD according to the fourth embodiment described above with reference to FIG. 4, but surrounds the Schottky electrode 5 and the guard ring p layer 4 at the side end thereof. The difference is that the n + layer 3 is formed so as to surround the outer periphery of the n− drift layer 2.
[0043]
As described above, according to the structure in which the n + layer 3 surrounds the outer periphery of the element, the termination process of the element is unnecessary, and the chip area can be used effectively.
[0044]
<Ninth Embodiment>
FIGS. 9A to 9G are cross-sectional views schematically showing a part of the process flow of the SBD according to the ninth embodiment.
[0045]
First, an original substrate on which an n− drift layer 2 is formed is formed on an n + substrate 1, a mask material pattern 91 is formed on the entire surface, and a groove 92 extending from a part of the surface to the n + substrate 1 is selectively formed. The trench 92 is filled with polycrystalline silicon (n + layer) 3 doped with n +.
[0046]
Next, for example, a pattern of the oxide film 7 is formed on the entire surface, a groove 93 reaching the intermediate depth of the n − drift layer 2 is selectively formed, and ion implantation of p-type impurities is performed from the upper surface. At this time, since the oxide film 7 serves as a mask for blocking ion implantation, the guard ring p layer 4 is selectively formed only at the peripheral portion of the bottom surface of the groove 93.
[0047]
Then, a metal for forming the Schottky electrode 5 is deposited on the entire surface and buried in the groove 93, and finally the cathode electrode 6 is formed on the back surface.
[0048]
As described above, when the n + layer 3 is formed, the filling is facilitated by using polycrystalline silicon as the filling material in the groove 92. On the other hand, ion implantation may be performed from the upper surface after the trench 92 is formed and diffused, but the ratio of the n + layer 3 to the n− drift layer 2 is increased.
[0049]
Further, when forming the n + layer 3, even if the groove 92 is formed, ion implantation is performed from an oblique direction to form the n + layer 3 along the inner wall of the groove 92, and the groove 92 is filled with an insulator or metal. Good.
[0050]
When forming the groove, dry etching or wet etching using an alkaline etchant may be used. However, when dry etching is used when forming the groove 93 for embedding the Schottky electrode, the inner wall of the groove 93 is formed. In addition, defects occur due to etching damage. If a Schottky electrode metal is deposited in this state to form a Schottky junction, reverse leakage current increases due to defects included in the Schottky junction surface.
[0051]
Therefore, when dry etching is used in forming the groove in the present invention, the etching surface including defects generated by etching is not used as a Schottky junction surface, and vapor deposition is performed in the groove 93 in order to remove crystal defects on the etching surface. The formed Schottky electrode metal is diffused into the silicon by heat treatment to form a Schottky junction surface inside the silicon instead of the etched surface. As a result, a Schottky junction with few defects can be formed, and an increase in reverse leakage current due to etching damage can be suppressed.
[0052]
Since the degree of diffusion of metal into the silicon is determined by the type of metal, as a Schottky electrode metal, diffusion from the metal deposition surface into the silicon occurs by applying a high temperature heat treatment, and a Schottky junction is formed. It is desirable to use any of Co, Ni, V, Pt, etc. that can be formed.
[0053]
<Tenth Embodiment>
FIG. 10 is a cross-sectional view schematically showing a part of the SBD according to the tenth embodiment of the present invention.
[0054]
This SBD is different from the SBD according to the first embodiment described above with reference to FIG. 1 in that the resurf structure called a super junction structure is embedded in the drift layer.
[0055]
That is, between the Schottky electrode 5 on the n − drift layer 2 and the n + layer 3, the n layer 8 and the p layer 9 having a higher impurity concentration than the n − drift layer 2 are periodically formed in the depth direction. Is formed.
[0056]
In this way, according to the super junction structure having the n layer 8 having a higher concentration than the n − drift layer 2 in the drift layer portion, the resistance of the drift layer can be further reduced, so that the shot described above with reference to FIG. Even if the ratio of the depth d of the groove for embedding the key electrode to the distance a of the drift layer is 1.1 or less, the on-resistance can be made smaller than that of a normal vertical SBD.
[0057]
<Eleventh embodiment>
FIG. 11 is a cross-sectional view schematically showing a part of the SBD according to the eleventh embodiment of the present invention.
[0058]
This SBD is different from the SBD according to the first embodiment described above with reference to FIG. 1 in that the upper part of the n-drift layer 2 is changed to the n layer 10 and the lower part is changed to the p-layer 11. .
[0059]
According to such a structure, the flat junction surface between the p− layer 11, the n + substrate 1 and the n layer 3 can be made larger than the pn junction surface between the guard ring p layer 4 and the n layer 10. It is possible to avoid electric field concentration and increase the withstand capability.
[0060]
<Twelfth Embodiment>
FIG. 12 is a cross-sectional view schematically showing a part of the SBD according to the twelfth embodiment of the present invention.
[0061]
Compared to the SBD according to the eleventh embodiment described above with reference to FIG. 11, this SBD has an n− layer 12 having a lower impurity concentration in the vicinity of the sidewall of the Schottky electrode embedding groove in the n layer 10. The point that changed to is different.
[0062]
According to such a structure, it is possible to further suppress reverse leakage current caused by defects included in the Schottky junction surface.
[0063]
In the SBD according to the first embodiment described above with reference to FIG. 1, even if the vicinity of the side wall of the groove for embedding the Schottky electrode is changed to an n− layer having a low impurity concentration, the Schottky junction surface It is possible to suppress the reverse leakage current due to the defects included in.
[0064]
<13th Embodiment>
When a MOSFET is applied to a switching power supply or an inverter, the MOSFET and the SBD may be formed on the same semiconductor chip.
[0065]
In this case, for example, as shown in the plan view of FIG. 13, the SBD region 131 and the MOSFET region 132 as described in the above embodiments can be disposed on the semiconductor chip 13 while being insulated and separated. .
[0066]
<Fourteenth embodiment>
When the MOSFET and the SBD are formed on the same semiconductor chip so as to be stacked in the vertical direction and are used by connecting both, a groove is formed in the n-drift layer 2 as shown in the cross-sectional view of FIG. The electrode 5 and the n + layer 3 are embedded, and the lower part of the n− drift layer 2 is assigned to the SBD region and the upper part is assigned to the MOSFET region.
[0067]
For example, a P well region 14 of a MOSFET is selectively formed in a region between the electrode 5 embedded in the groove in the surface layer portion of the n − drift layer 2 and the n + layer 3, and adjacent to the electrode 5 in the surface layer portion. Thus, the n + region 15 that becomes the drain or source of the MOSFET is formed. Then, a gate electrode 17 is formed on the P well region surface layer portion (channel region) between the n + region 15 and the n− drift layer 2 via the gate insulating film 16. Therefore, the lower part of the electrode 5 is used as a SBD Schottky electrode, and the upper part is used as a connection wiring between the SBD and the MOSFET.
[0068]
<Fifteenth embodiment>
FIG. 15 is a cross-sectional view schematically showing a part of the SBD according to the fifteenth embodiment of the present invention.
[0069]
The SBD is the same as the SBD described above with reference to FIG. 7, for example, but has a slightly different basic structure.
[0070]
That is, the n − drift layer 2 is formed on the p substrate 18, and the Schottky electrode 5 is embedded in a groove formed so as to reach the p substrate 18 from a part of the surface thereof. The Schottky electrode 5 forms a Schottky junction with the n − drift layer 2 and is electrically connected to the p substrate 18. An anode electrode 19 is formed on the back surface of the p substrate 18. ing.
[0071]
An n + layer 3 is embedded in a groove formed from a part of the surface of the n− drift layer 2 to an intermediate depth, and an insulating film formed on each surface of the n− drift layer 2 and the n + layer 3. A cathode electrode 6 is formed on 20, and this cathode electrode 6 is electrically connected to the n + layer 3 through a contact hole formed in the insulating film 20.
[0072]
According to such a structure, the junction surface of the diode is formed on the flat portion between the Schottky electrode 5 and the p substrate 18, so that electric field concentration hardly occurs and the electric field applied to the Schottky junction is reduced. And reverse leakage current can be suppressed.
[0073]
FIG. 16A is a plan view showing a part of the layout pattern of the SBD of FIG.
[0074]
FIG. 16B is a cross-sectional view schematically showing a cross-sectional structure along the line AA ′ in FIG.
[0075]
In the SBD shown in FIGS. 16A and 16B, the Schottky electrode 5 is formed so as to surround the outer periphery of the n − drift layer 2.
[0076]
Thus, according to the structure in which the Schottky electrode 5 surrounds the outer periphery of the element, the outer periphery of the element is surrounded by the Schottky junction having the same potential as the anode electrode 19, so that the structure of the terminal portion of the element becomes unnecessary, and the element area is reduced. Effective use can be achieved.
[0077]
Similar to the SBD shown in FIG. 2, the depth of the Schottky electrode 5 is made larger than the distance between the Schottky electrode 5 and the n + layer 3, so that the avalanche breakdown is reduced when the high voltage is applied. And the p-type substrate 18 are generated, and the holes immediately flow into the p-type substrate 18 so that the avalanche resistance can be ensured.
[0078]
Further, by providing a super junction structure between the Schottky electrode 5 and the n + layer 3, the on-resistance can be further reduced.
[0079]
<Sixteenth Embodiment>
FIG. 17 is a cross-sectional view schematically showing a part of the SBD according to the sixteenth embodiment of the present invention.
[0080]
This SBD is the same as the SBD described above with reference to FIG. 7, for example, but is different in that both the anode electrode 19 and the cathode electrode 6 are taken out to the upper surface of the substrate.
[0081]
That is, the Schottky electrode 5 and the n + layer 3 are buried in a groove formed from a part of the surface of the n− layer 2 to an intermediate depth, and formed on each surface of the n− layer 2 and the n + layer 3. An anode electrode 19 and a cathode electrode 6 are formed on the insulating film 20. The anode electrode 19 is electrically connected to the Schottky electrode 5 through a contact hole formed in the insulating film 20, and the cathode electrode 6 is electrically connected to the n + layer 3 through a contact hole formed in the insulating film 20. ing.
[0082]
According to such a structure, it is not necessary to take out an electrode from the back surface of the substrate, and it is not necessary to use a semiconductor wafer in which an n− layer is epitaxially grown on a high concentration n + substrate.
[0083]
Moreover, when forming SBD using a compound semiconductor, the said structure can be implemented even if it forms the n <-> layer 2 on a semi-insulating board | substrate.
[0084]
The present invention is not limited to the above-described embodiments, and can be implemented even when the first conductivity type is p-type and the second conductivity type is n-type. Further, the planar pattern of the Schottky electrode 5 and the n + layer 3 and the groove in which they are embedded is not limited to the stripe shape, and may be formed in a lattice shape or a staggered shape.
[0085]
Further, although the case where silicon (Si) is used as the semiconductor has been described, for example, a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN) or diamond (C) can be used.
[0086]
【The invention's effect】
As described above, according to the power semiconductor device of the present invention, the resistance of the drift layer can be lowered and the on-voltage can be reduced without deteriorating the reverse characteristics of the SBD and increasing the chip area.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view and a plan view showing a part of an SBD according to a first embodiment of the present invention.
FIG. 2 is a characteristic diagram showing an example of a relationship between a depth d of a Schottky electrode of an SBD and an on-resistance of an n-drift layer according to a second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a part of an SBD according to a third embodiment of the present invention.
FIG. 4 is a perspective view showing a part including one set of a Schottky electrode and a guard ring p layer and an n + layer in an SBD according to a fourth embodiment of the present invention, and a line AA ′, B− in FIG. Sectional drawing which follows a B 'line.
FIG. 5 is a perspective view showing a part of a Schottky electrode and a guard ring p layer in an SBD according to a fifth embodiment of the present invention, and a cross-sectional view taken along the line AA ′ in the drawing.
FIG. 6 is a perspective view showing a part of a Schottky electrode and a guard ring p layer in an SBD according to a sixth embodiment of the present invention, and a sectional view taken along the line AA ′ in the drawing.
FIG. 7 is a cross-sectional view showing a part of an SBD according to a seventh embodiment of the present invention.
FIG. 8 is a sectional view showing a part of an SBD according to an eighth embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a part of a process flow of an SBD according to a ninth embodiment of the present invention.
FIG. 10 is a cross-sectional view showing a part of an SBD according to a tenth embodiment of the present invention.
FIG. 11 is a sectional view showing a part of an SBD according to an eleventh embodiment of the present invention.
FIG. 12 is a cross-sectional view showing a part of an SBD according to a twelfth embodiment of the present invention.
FIG. 13 is a plan view schematically showing a semiconductor device in which an SBD and a MOSFET according to a thirteenth embodiment of the present invention are formed on the same chip.
FIG. 14 is a cross-sectional view schematically showing a part of a semiconductor device in which an SBD and a MOSFET according to a thirteenth embodiment of the present invention are formed in the vertical direction on the same semiconductor chip and connected to each other Figure.
FIG. 15 is a sectional view showing a part of an SBD according to a fifteenth embodiment of the present invention.
16 is a plan view showing a part of the layout pattern of the SBD of FIG. 15 and a cross-sectional view taken along the line AA ′ in the drawing.
FIG. 17 is a cross-sectional view of a part of an SBD according to a sixteenth embodiment of the present invention.
[Explanation of symbols]
1 ... n + substrate (first semiconductor layer),
2 ... n-drift layer (second semiconductor layer),
3 ... n + layer (third semiconductor layer),
4 ... guard ring p layer (fourth semiconductor layer),
5 ... Schottky electrode (first main electrode)
6 ... Ohmic electrode (second main electrode),
7: Insulating film.

Claims (19)

第１導電型の第１の半導体層と、
前記第１の半導体層上に形成され、前記第１の半導体層よりも不純物濃度が低い第１導電型の第２の半導体層と、
前記第２の半導体層の表面から前記第１の半導体層に達するように形成された第１導電型の第３の半導体層と、
前記第２の半導体層の表面から所定の深さまで形成された溝の底部の周辺部に形成された第２導電型の第４の半導体層と、
前記溝の内部に埋め込まれて前記第４の半導体層と電気的に接続され、前記第２の半導体層とショットキー接合を形成する第１の主電極と、
前記第１の半導体層に電気的に接続された第２の主電極
とを具備することを特徴とする電力用半導体装置。A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a first conductivity type formed on the first semiconductor layer and having an impurity concentration lower than that of the first semiconductor layer;
A third semiconductor layer of a first conductivity type formed so as to reach the first semiconductor layer from the surface of the second semiconductor layer;
A second conductivity type fourth semiconductor layer formed at the periphery of the bottom of the groove formed from the surface of the second semiconductor layer to a predetermined depth;
A first main electrode embedded in the trench and electrically connected to the fourth semiconductor layer to form a Schottky junction with the second semiconductor layer;
A power semiconductor device comprising: a second main electrode electrically connected to the first semiconductor layer. 前記溝の深さと前記第１の主電極・第３の半導体層間の距離との比が１．１以上であることを特徴とする請求項１記載の電力用半導体装置。  2. The power semiconductor device according to claim 1, wherein a ratio of the depth of the groove to the distance between the first main electrode and the third semiconductor layer is 1.1 or more. 前記第４の半導体層と前記第１の半導体層との間の距離が、前記第１の主電極・第３の半導体層間の距離よりも短いことを特徴とする請求項１または２記載の電力用半導体装置。  3. The electric power according to claim 1, wherein a distance between the fourth semiconductor layer and the first semiconductor layer is shorter than a distance between the first main electrode and the third semiconductor layer. Semiconductor device. 前記第４の半導体層は、前記溝の内部の第１の対をなす相対する側壁部の周辺部まで延びるように形成されており、前記第１の主電極は、前記溝の内部の第２の対をなす相対する側壁部で前記第２の半導体層とショットキー接合を形成していることを特徴とする請求項１乃至３のいずれか１項に記載の電力用半導体装置。  The fourth semiconductor layer is formed so as to extend to the peripheral portions of the opposing side wall portions forming the first pair inside the groove, and the first main electrode is a second inside the groove. 4. The power semiconductor device according to claim 1, wherein a Schottky junction is formed with the second semiconductor layer at opposite side wall portions forming a pair of the first semiconductor layer and the second semiconductor layer. 5. 前記溝は、その長さ方向において間欠的に分断された島状に形成されていることを特徴とする請求項４記載の電力用半導体装置。  5. The power semiconductor device according to claim 4, wherein the groove is formed in an island shape intermittently divided in a length direction thereof. 前記第２の半導体層および前記第３の半導体層の各表面に形成された絶縁膜をさらに具備し、前記第１の主電極が前記絶縁膜の表面を覆っていることを特徴とする請求項１乃至５のいずれか１項に記載の電力用半導体装置。  The insulating film formed on each surface of the second semiconductor layer and the third semiconductor layer is further provided, and the first main electrode covers the surface of the insulating film. The power semiconductor device according to any one of 1 to 5. 前記第３の半導体層は、前記溝の内部の前記第１の主電極および第４の半導体層を囲むように形成されている前記第２の半導体層の外周を取り囲むように形成されていることを特徴とする請求項１乃至６のいずれか１項に記載の電力用半導体装置。  The third semiconductor layer is formed so as to surround an outer periphery of the second semiconductor layer formed so as to surround the first main electrode and the fourth semiconductor layer inside the groove. The power semiconductor device according to claim 1, wherein: 前記第３の半導体層は、多結晶半導体で形成されていることを特徴とする請求項１乃至７のいずれか１項に記載の電力用半導体装置。  The power semiconductor device according to claim 1, wherein the third semiconductor layer is formed of a polycrystalline semiconductor. 前記第１の主電極は、前記溝の内部に堆積された後に高温熱処理を加えられることにより前記半導体層へ拡散し、金属蒸着面よりも半導体層側でショットキー接合が形成される金属で形成されていることを特徴とする請求項１乃至８のいずれか１項に記載の電力用半導体装置。  The first main electrode is formed of a metal that is deposited in the groove and then diffused into the semiconductor layer by being subjected to a high-temperature heat treatment, so that a Schottky junction is formed on the semiconductor layer side of the metal deposition surface. The power semiconductor device according to claim 1, wherein the power semiconductor device is a power semiconductor device. 前記金属は、Ｃｏ、Ｎｉ、Ｐｔ、Ｖのいずれかが用いられていることを特徴とする請求項９記載の電力用半導体装置。  10. The power semiconductor device according to claim 9, wherein any one of Co, Ni, Pt, and V is used as the metal. 前記第２の半導体層の内部で深さ方向において前記第２の半導体層における前記ショットキー電極と前記第３の半導体層との間の部分に周期的に埋め込まれた第１導電型の第５の半導体層および第２導電型の第６の半導体層を含むスーパージャンクション構造が設けられたことを特徴とする請求項１乃至１０のいずれか１項に記載の電力用半導体装置。A first conductivity type fifth element periodically embedded in a portion of the second semiconductor layer between the Schottky electrode and the third semiconductor layer in the depth direction inside the second semiconductor layer. 11. The power semiconductor device according to claim 1, further comprising a super junction structure including a second semiconductor layer and a second conductivity type sixth semiconductor layer. 11. 前記第４の半導体層と前記第１の半導体層との間で前記第３の半導体層側に延在するように設けられた第２導電型の第７の半導体層をさらに具備することを特徴とする請求項１乃至１０のいずれか１項に記載の電力用半導体装置。 And a second conductivity type seventh semiconductor layer provided to extend to the third semiconductor layer side between the fourth semiconductor layer and the first semiconductor layer. The power semiconductor device according to any one of claims 1 to 10. 前記第２の半導体層において前記溝の側壁部付近に隣接する部分の不純物濃度をそれ以外の部分の不純物濃度よりも低くしたことを特徴とする請求項１２記載の電力用半導体装置。  13. The power semiconductor device according to claim 12, wherein an impurity concentration in a portion adjacent to the vicinity of the side wall portion of the groove in the second semiconductor layer is made lower than an impurity concentration in other portions. 同一半導体チップ上に、ＭＯＳＦＥＴの形成領域と請求項１乃至１３のいずれか１項に記載の構造を有するＳＢＤの形成領域が絶縁分離されて配置されていることを特徴とする電力用半導体装置。  A power semiconductor device, wherein a MOSFET formation region and an SBD formation region having the structure according to any one of claims 1 to 13 are disposed on the same semiconductor chip so as to be insulated and separated. 前記第２の半導体層の表面に前記第１の主電極に接するように形成された第２導電型の第８の半導体層と、
前記第８の半導体層の表面に前記第１の主電極に接するように形成された第１導電型の第９の半導体層と、
前記第９の半導体層と前記第２の半導体層との間の前記第８の半導体層の表層部上にゲート絶縁膜を介して形成されたＭＯＳＦＥＴのゲート電極をさらに具備することを特徴とする請求項１乃至１３のいずれか１項に記載の電力用半導体装置。 An eighth semiconductor layer of a second conductivity type formed on the surface of the second semiconductor layer so as to be in contact with the first main electrode;
A ninth semiconductor layer of a first conductivity type formed on the surface of the eighth semiconductor layer so as to be in contact with the first main electrode;
And a MOSFET gate electrode formed on a surface layer portion of the eighth semiconductor layer between the ninth semiconductor layer and the second semiconductor layer via a gate insulating film. The power semiconductor device according to claim 1. 第１導電型の第１の半導体層と、
前記第１の半導体層上に形成された第２導電型の第２の半導体層と、
前記第２の半導体層の表面から所定の深さまで形成され、前記第２の半導体層よりも不純物濃度が高い第２導電型の第３の半導体層と、
前記第２の半導体層の表面から前記第１の半導体層に達するように形成された溝の内部に埋め込まれて前記第１の半導体層と電気的に接続され、前記第２の半導体層とショットキー接合を形成するショットキー電極と、
前記第２の半導体層および前記第３の半導体層の各表面に形成された絶縁膜と、
前記第１の半導体層に電気的に接続された第１の主電極と、
前記絶縁膜に形成されたコンタクトホールを通じて前記第３の半導体層に電気的に接続された第２の主電極
とを具備することを特徴とする電力用半導体装置。A first semiconductor layer of a first conductivity type;
A second conductivity type second semiconductor layer formed on the first semiconductor layer;
A third semiconductor layer of a second conductivity type formed from the surface of the second semiconductor layer to a predetermined depth and having a higher impurity concentration than the second semiconductor layer;
Embedded in a groove formed so as to reach the first semiconductor layer from the surface of the second semiconductor layer and electrically connected to the first semiconductor layer, and shot with the second semiconductor layer A Schottky electrode forming a key junction;
An insulating film formed on each surface of the second semiconductor layer and the third semiconductor layer;
A first main electrode electrically connected to the first semiconductor layer;
A power semiconductor device comprising: a second main electrode electrically connected to the third semiconductor layer through a contact hole formed in the insulating film. 前記ショットキー電極の深さは、当該ショットキー電極と前記第３の半導体層との間の距離よりも大きいことを特徴とする請求項１６記載の電力用半導体装置。  17. The power semiconductor device according to claim 16, wherein a depth of the Schottky electrode is larger than a distance between the Schottky electrode and the third semiconductor layer. 前記第２の半導体層の内部で深さ方向において前記第２の半導体層における前記ショットキー電極と前記第３の半導体層との間の部分に周期的に埋め込まれた第１導電型の第４の半導体層および第２導電型の第５の半導体層を含むスーパージャンクション構造が設けられたことを特徴とする請求項１６または１７記載の電力用半導体装置。A first conductivity type fourth periodically embedded in a portion of the second semiconductor layer between the Schottky electrode and the third semiconductor layer in the depth direction inside the second semiconductor layer. 18. The power semiconductor device according to claim 16 , further comprising a super junction structure including the second semiconductor layer and the second conductivity type fifth semiconductor layer . 前記ショットキー電極は、前記第２の半導体層の外周を取り囲むように形成されていることを特徴とする請求項１６乃至１８のいずれか１項に記載の電力用半導体装置。  The power semiconductor device according to claim 16, wherein the Schottky electrode is formed so as to surround an outer periphery of the second semiconductor layer.
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