JP7067698B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device.

Conventionally, in a power rectifier device using a semiconductor having a wider bandgap than silicon (hereinafter referred to as a wide bandgap semiconductor), a low conduction loss is required, so that a low forward voltage is required. For example, by using silicon carbide (SiC), which is a wide bandgap semiconductor, it can be applied to a Schottky barrier diode (SBD) even if it has a withstand voltage of 1200 V class. Further, since the Schottky barrier diode has a large contact resistance (contact resistance) at the Schottky junction surface, a trench type SBD capable of reducing the contact resistance by increasing the area of the Schottky junction surface by a trench has been proposed. ing.

A case where silicon carbide is used as the wide bandgap semiconductor will be described as an example of the conventional trench type SBD. FIG. 16 is a cross-sectional view showing the structure of a conventional semiconductor device. In the trench type SBD shown in FIG. 16, an n ^- type silicon carbide layer 131 serving as an n ^- type drift region 102 is epitaxially grown on an n ⁺ type support substrate (hereinafter referred to as an n ⁺ type silicon carbide substrate) 101 made of silicon carbide. It is manufactured by using the made epitaxial substrate (semiconductor substrate) 110. An n-type current diffusion region 103 is provided on the front surface side of the semiconductor substrate 110. A trench 105 is provided at a predetermined depth from the front surface 110a of the semiconductor substrate 110.

The bottom surface 105a of the trench 105 is covered with a p ⁺ type region 104 because an electric field is concentrated when it is off. A conductive layer 106 is provided on the front surface 110a of the semiconductor substrate 110 so as to be embedded in the trench 105. A Schottky junction 111 between the conductive layer 106 and the n-type current diffusion region 103 is formed along the front surface 110a of the semiconductor substrate 110 and the side wall 105b of the trench 105 (the portion surrounded by the frame of the alternate long and short dash line). .. A trench type SBD is formed by this Schottky joint 111. Reference numerals 107 and 108 are the anode electrode and the cathode electrode of the trench type SBD, respectively.

As such a trench-type SBD, a p-type silicon carbide layer is formed along the bottom surface and side surfaces of the trench formed in the n-type drift layer, and p-type polysilicon is formed inside the trench so as to be in contact with the p-type silicon carbide layer. A device in which a layer is embedded and a shotkey barrier is formed between the layer and the drift layer has been proposed (see, for example, Patent Document 1 below (paragraphs 0029,0042 to 0047, FIG. 3) below).

Further, as another trench type SBD, a conductive layer is embedded along the inner wall of the trench via an oxide film, and a shot key of a barrier metal film and a semiconductor layer is formed on the upper end surface between adjacent trenches (mesa region). An apparatus in which a joint is formed has been proposed (see, for example, Patent Document 2 below (paragraphs 0026, 0055, FIG. 1 (f)) below).

Further, as another trench type SBD, a p-type impurity region is provided so as to cover the bottom surface of the trench, a p-type impurity region is provided at the upper corner of the trench, and further, the semiconductor layer is provided in the trench and on the semiconductor layer. A device having a metal electrode forming a Schottky barrier has been proposed (see, for example, Patent Document 3 below (paragraphs 0201 to 0202, FIG. 16)).

Japanese Unexamined Patent Publication No. 2013-140824 Japanese Unexamined Patent Publication No. 2001-06688 Japanese Unexamined Patent Publication No. 2015-050436

However, in the conventional trench type SBD (see FIG. 16), there are a plurality of different plane orientations on the Schottky junction 111 planes. For example, the front surface 110a of the semiconductor substrate 110 is a Si surface or a C surface, and the side wall 105b of the trench 105 is an m surface. Various crystal planes are present in the upper corner portion 105c of the trench 105. The Si plane is a (0001) plane. The C plane is the (000-1) plane. The m plane is a general term for {1-100} planes perpendicular to the C plane, and is a (10-10) plane, a (-1010) plane, a (1-100) plane, a (-1100) plane, and a (01-10) plane. ) Plane and (0-110) plane. The upper corner portion 105c of the trench 105 is a boundary between the side wall 105b of the trench 105 and the front surface 110a of the semiconductor substrate 110.

FIG. 15 is a characteristic diagram showing the height of the Schottky barrier for each plane direction. As shown in FIG. 15, the height of the Schottky barrier at the Schottky junction 111 plane varies depending on the plane orientation of the Schottky junction 111 plane. Therefore, in the conventional trench type SBD, a plurality of Schottky barriers having different barrier heights exist in one unit cell (constituent unit of the element). FIG. 15 shows the height of the Schottky barrier on the Si surface, the C surface, and the m surface when silicon carbide is used as the semiconductor material and the conductive layer 106 is titanium (Ti). The same characteristics as in FIG. 15 are exhibited when the metal material of the above is used or when it is formed of polysilicon (poly-Si). The horizontal axis of FIG. 15 is the temperature of annealing performed after the conductive layer 106 is formed, and the vertical axis is the height of the Schottky barrier at the Schottky junction 111 plane.

When a plurality of Schottky barriers having different barrier heights exist in one unit cell of the trench type SBD, the following two problems arise. First, since the Schottky barrier height is lowered by the Schottky junction 111 formed on the Si surface and the C surface, the leakage current increases when the trench type SBD is turned off, and the withstand voltage (withstand voltage) increases. The problem is that it will decline. The second problem is that the shot key characteristics of the trench type SBD are not stable because the shot key characteristics of the trench type SBD are in a plurality of stages, such as the on / off characteristics of the trench type SBD being deteriorated.

An object of the present invention is to provide a semiconductor device capable of preventing a decrease in withstand voltage and stably obtaining a predetermined Schottky characteristic in order to solve the above-mentioned problems caused by the prior art.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A second conductive type first semiconductor region is selectively provided inside a first conductive type semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon. A second conductive type second semiconductor region is provided on the surface layer of the front surface of the semiconductor substrate, separated from the first semiconductor region. The third semiconductor region of the first conductive type is a portion of the semiconductor substrate other than the first semiconductor region and the second semiconductor region. The trench penetrates the second semiconductor region from the front surface of the semiconductor substrate and reaches the first semiconductor region. A conductive layer is provided inside the trench. The conductive layer forms a Schottky junction with the third semiconductor region on the side wall of the trench. The first electrode is electrically connected to the conductive layer. The second electrode is provided on the back surface of the semiconductor substrate. An active region in which an element configured by the Schottky junction is arranged, a terminal region surrounding the active region, and a connecting region between the active region and the terminal region are provided. A step is provided in which the front surface of the semiconductor substrate is lowered on the second electrode side on the second surface in the terminal region than on the first surface in the active region and the connecting region. The third semiconductor region is terminated inside the third surface connecting the first surface and the second surface of the front surface of the semiconductor substrate. In the connecting region, the third semiconductor region and the fourth semiconductor region are provided between the trench and the third surface. The fourth semiconductor region is a first conductive type region having a lower impurity concentration than the third semiconductor region, or a second conductive type region having a different conductive type from the third semiconductor region.

Further, in order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A second conductive type first semiconductor region is selectively provided inside a first conductive type semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon. The third semiconductor region of the first conductive type is a portion of the semiconductor substrate other than the first semiconductor region. A trench is provided that reaches the first semiconductor region at a predetermined depth from the front surface of the semiconductor substrate. The insulating film covers a portion of the front surface of the semiconductor substrate other than the trench forming region. A conductive layer is provided inside the trench. The conductive layer forms a Schottky junction with the third semiconductor region on the side wall of the trench. The first electrode is electrically connected to the conductive layer. The second electrode is provided on the back surface of the semiconductor substrate. An active region in which an element configured by the Schottky junction is arranged, a terminal region surrounding the active region, and a connecting region between the active region and the terminal region are provided. A step is provided in which the front surface of the semiconductor substrate is lowered on the second electrode side on the second surface in the terminal region than on the first surface in the active region and the connecting region. The third semiconductor region is terminated inside the third surface connecting the first surface and the second surface of the front surface of the semiconductor substrate. In the connecting region, the third semiconductor region and the fourth semiconductor region are provided between the trench and the third surface. The fourth semiconductor region is a first conductive type region having a lower impurity concentration than the third semiconductor region, or a second conductive type region having a different conductive type from the third semiconductor region.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the first semiconductor region covers the bottom surface and the bottom surface corner portion of the trench.

Further, in order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A second conductive type first semiconductor region is selectively provided inside a first conductive type semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon. A second conductive type second semiconductor region is provided on the surface layer of the front surface of the semiconductor substrate, separated from the first semiconductor region. The third semiconductor region of the first conductive type is a portion of the semiconductor substrate other than the first semiconductor region and the second semiconductor region. The trench penetrates the second semiconductor region from the front surface of the semiconductor substrate and faces the first semiconductor region in the depth direction. An insulating layer is provided inside the trench. The insulating layer covers the bottom surface and bottom corners of the trench. A conductive layer is provided on the insulating layer inside the trench. The conductive layer forms a Schottky junction with the third semiconductor region on the side wall of the trench. The first electrode is electrically connected to the conductive layer. The second electrode is provided on the back surface of the semiconductor substrate. An active region in which an element configured by the Schottky junction is arranged, a terminal region surrounding the active region, and a connecting region between the active region and the terminal region are provided. A step is provided in which the front surface of the semiconductor substrate is lowered on the second electrode side on the second surface in the terminal region than on the first surface in the active region and the connecting region. Between the trench and the third surface connecting the first surface and the second surface of the front surface of the semiconductor substrate, a second conductive type fourth semiconductor region extends over the entire area of the connecting region. It is provided.

Further, in the above-described invention, the semiconductor device according to the present invention covers the entire surface of the first surface, the third surface, and the second surface of the front surface of the semiconductor substrate from the connecting region to the terminal region. It is characterized by further providing an insulating film. Further, in the semiconductor device according to the present invention, in the above-described invention, the insulating film has the first surface, the third surface and the second surface of the front surface of the semiconductor substrate from the active region to the terminal region. It is characterized by covering the entire surface. Further, in the semiconductor device according to the present invention, in the above-described invention, the first semiconductor region facing the bottom surface of the outermost trench in the depth direction extends outward from the active region of the semiconductor substrate. It reaches the third surface of the front surface. The second semiconductor region extends outward from the active region along the first surface and the third surface of the front surface of the semiconductor substrate and reaches the terminal region. The fourth semiconductor region is characterized in that it is provided between the second semiconductor region and the first semiconductor region. Further, in the semiconductor device according to the present invention, in the above-described invention, the first semiconductor region facing the bottom surface of the outermost trench in the depth direction extends outward from the active region of the semiconductor substrate. It reaches the third surface of the front surface. The fourth semiconductor region is characterized in that it is provided between the first surface and the third surface of the front surface of the semiconductor substrate and the first semiconductor region. Further, in the semiconductor device according to the present invention, in the above-described invention, a plurality of the trenches are arranged at predetermined intervals. The predetermined interval is characterized in that it is equal to or less than the width in the depth direction of the Schottky junction between the third semiconductor region and the conductive layer on the side wall of the trench.

Further, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the Schottky junction is formed only on the side wall of the trench.

Further, in the semiconductor device according to the present invention, in the above-described invention, the trench is arranged in a striped layout extending in a direction parallel to the front surface of the semiconductor substrate, and in the connecting region. It is terminated. The second semiconductor regions adjacent to each other with the trench interposed therebetween are characterized in that at least a part thereof is connected in the connecting region.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the second semiconductor region is provided on the entire surface region of the front surface of the semiconductor substrate in the joint region. ..

Further, in the semiconductor device according to the present invention, in the above-described invention, the trench is arranged in a striped layout extending in a direction parallel to the front surface of the semiconductor substrate, and in the connecting region. It is characterized by being terminated.

According to the semiconductor device according to the present invention, since the Schottky characteristic is determined only by one surface orientation (the surface orientation of the side wall of the trench), it is possible to prevent a decrease in withstand voltage and to stabilize a predetermined Schottky characteristic. It has the effect of being able to be obtained.

It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the modification of FIG. 2A. It is a top view which shows the layout of each part of the plane cut by the cutting line CC of FIG. 1 and the cutting line CC'of FIGS. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 2. FIG. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 2. FIG. It is sectional drawing which shows the modification of FIG. 11A. It is a top view which shows the layout of each part which saw the plane cut by the cutting line FF of FIG. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 3. FIG. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 3. FIG. It is a characteristic diagram which shows the height of the Schottky barrier for each plane direction. It is sectional drawing which shows the structure of the conventional semiconductor device.

Hereinafter, preferred embodiments of the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that the electron or hole is a large number of carriers in the layer or region marked with n or p, respectively. Further, + and-attached to n and p mean that the concentration of impurities is higher and the concentration of impurities is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted. Further, in the present specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after that, and "-" is added before the index to indicate a negative index.

(Embodiment 1)
The semiconductor device according to the first embodiment is configured by using a semiconductor having a bandgap wider than that of silicon (referred to as a wide bandgap semiconductor). The structure of the semiconductor device according to the first embodiment will be described by exemplifying a case where, for example, silicon carbide (SiC) is used as the wide bandgap semiconductor. 1 and 2A are cross-sectional views showing the structure of the semiconductor device according to the first embodiment. FIG. 2B is a cross-sectional view showing a modified example of FIG. 2A. FIG. 3 is a plan view showing the layout of each part of the plane cut by the cutting lines CC of FIG. 1 and the cutting lines CC'of FIGS. 2A and 2B as viewed from the front surface side of the semiconductor substrate.

FIG. 1 is a cross-sectional structure taken along the cutting line AA of FIG. FIG. 1 shows the cross-sectional structure of the active region 21 of FIG. Further, FIG. 1 shows one unit cell (a constituent unit of an element) of the trench type SBD and 1/2 of the unit cells adjacent to both sides of the unit cell, and the other unit cells are not shown in the figure (FIG. 1). The same applies to 3 to 9, 10, 12, and 13). 2A and 2B are cross-sectional structures at the cutting line BB'in FIG. 2A and 2B show the cross-sectional structure of the region (hereinafter referred to as a connecting region) 22 between the active region 21 and the edge termination region 23 and the edge termination region 23. The structure of the connecting region 22 is different between FIGS. 2A and 2B. Reference numeral 24 is a boundary between the conductive layer 7 and the field oxide film 12.

The active region 21 is a region in which a current flows when the semiconductor device is in the ON state. The edge termination region 23 is a region between the active region 21 and the side surface of the semiconductor substrate (semiconductor chip) 10, and is the substrate front surface (front surface 10a of the semiconductor substrate 10) of the n ^- type drift region 2. This is the area where the withstand voltage (withstand voltage) is maintained by relaxing the electric field on the) side. In the edge termination region 23, for example, a p-type region constituting a guard ring or a junction termination extension (JTE) structure, and a pressure resistant structure such as a field plate or a resurf are arranged. The withstand voltage is the voltage limit at which the semiconductor device does not malfunction or break. FIGS. 2A and 2B show a case where the JTE structure is arranged in the edge end region 23.

In the semiconductor device according to the first embodiment shown in FIGS. 1, 2A and 3, a trench having a Schottky junction 11 formed on a side wall 6b of a trench 6 provided on the front surface 10a side of a semiconductor substrate 10 made of silicon carbide. Type SBD. The semiconductor substrate 10 is an epitaxial substrate obtained by epitaxially growing an n ^- type silicon carbide layer 31 which is an n ^- type drift region 2 on an n ⁺ type support substrate (n ⁺ type silicon carbide substrate) 1 made of silicon carbide. The n ⁺ type silicon carbide substrate 1 functions as an n ⁺ type cathode region. For example, the semiconductor substrate 10 is provided with an active region 21 in the central portion, and an edge termination region 23 is provided so as to surround the periphery of the active region 21.

As shown in FIG. 1, the active region 21 reaches the n ⁺ type silicon carbide substrate 1 in the depth direction Z from the front surface (the surface on the n ⁻ type silicon carbide layer 31 side) 10a of the semiconductor substrate 10. The trench 6 is provided at a predetermined depth. The depth direction Z is a direction from the front surface 10a of the semiconductor substrate 10 toward the back surface. The trench 6 is arranged, for example, in a striped layout extending in a direction X parallel to the front surface of the semiconductor substrate 10 when viewed from the front surface side of the semiconductor substrate 10, and is arranged in a longitudinal direction (striped shape) thereof. The end of the direction X) extending to is terminated, for example, at the connecting region 22 (see FIGS. 2A, 2B, 3). The trenches 6 are arranged apart from each other in a direction Y orthogonal to the direction X in which each trench 6 extends in a striped shape.

An n-type region (hereinafter referred to as an n-type current diffusion region (third semiconductor region)) 3 is provided on the surface layer of the n ^- type silicon carbide layer 31 between adjacent trenches 6 (mesa region). The n-type current diffusion region 3 is a so-called current diffusion layer (Current Spreading Layer: CSL) that reduces the spread resistance of carriers. The n-type current diffusion region 3 is uniformly provided in a direction parallel to the front surface 10a of the semiconductor substrate 10 and reaches a position deeper on the cathode side (back surface electrode 9 side) than the bottom surface 6a of the trench 6 to reach the trench. Covers the inner walls 6a to 6d of 6. Further, the n-type current diffusion region 3 extends from the active region 21 to the outside (chip side surface side) and terminates near the boundary between the connecting region 22 and the edge termination region 23 (see FIGS. 2A and 2B). The portion of the n ^- type silicon carbide layer 31 other than the n-type current diffusion region 3 is the n ^- type drift region 2.

Inside the n-type current diffusion region 3, a p ⁺ type region (hereinafter referred to as a p ⁺ type surface region (second semiconductor region)) is provided at a depth shallower than the trench 6 from the front surface 10a of the semiconductor substrate 10. 4 is provided. The p ⁺ type surface region 4 is exposed on the front surface 10a of the semiconductor substrate 10 and reaches the side walls 6b of the trench 6 on both sides thereof to cover the upper corner portion 6c of the trench 6. The exposure on the front surface 10a of the semiconductor substrate 10 means that the semiconductor substrate 10 is arranged so as to be in contact with the conductive layer 7, the interlayer insulating film (not shown), or the field oxide film 12 on the front surface 10a of the semiconductor substrate 10. Is. The upper corner portion 6c of the trench 6 is a boundary between the side wall 6b of the trench 6 and the front surface 10a of the semiconductor substrate 10. The p ⁺ type surface region 4 is uniformly provided in the direction parallel to the front surface 10a of the semiconductor substrate 10, extends outward from the active region 21 and terminates at the edge termination region 23 (FIG. 2A). , 2B). Further, the p ⁺ type surface region 4 is provided so as to surround the periphery of the trench 6 when viewed from the front surface 10a of the semiconductor substrate 10 (see FIG. 3).

Further, a p ⁺ type region (first semiconductor region) 5 is selectively provided inside the n-type current diffusion region 3. The p ⁺ type region 5 covers the bottom surface 6a of the trench 6. That is, the trench 6 penetrates the p ⁺ type surface region 4 from the front surface 10a of the semiconductor substrate 10 in the depth direction Z to reach the n-type current diffusion region 3 and terminates inside the p ⁺ type region 5. Is provided. The p ⁺ type region 5 preferably covers the bottom surface 6a and the bottom surface corner portion 6d of the trench 6 from the bottom surface 6a of the trench 6 to the bottom surface corner portion 6d. The p ⁺ type region 5 has a function of depleting when the trench type SBD is off and relaxing the electric field applied to the bottom surface 6a and the bottom surface corner portion 6d of the trench 6. As a result, it is possible to shorten the cell pitch and reduce the on-resistance while maintaining the withstand voltage.

The bottom corner portion 6d of the trench 6 is a boundary between the bottom surface 6a and the side wall 6b of the trench 6, and is, for example, an arc shape curved with a predetermined curvature. The bottom surface 6a of the trench 6 is a portion of the inner wall of the trench 6 that is deepest from the substrate front surface 10a and is a surface substantially parallel to the substrate front surface 10a. The smaller the curvature of the bottom corner portion 6d of the trench 6, the larger the proportion of the bottom corner portion 6d, and the cross-sectional shape of the trench 6 at the cutting line AA is the cross-sectional shape in which the bottom surface 6a approaches a point (vertex). Become. The side wall 6b of the trench 6 is an inner wall of the trench 6 that is continuous with the substrate front surface 10a and is substantially orthogonal to the substrate front surface 10a.

Further, the p ⁺ type region 5 is arranged at a position deeper on the cathode side than the interface between the p ⁺ type surface region 4 and the n-type current diffusion region 3 and separated from the p ⁺ type surface region 4. The cathode side end of the p ⁺ type region 5 may be terminated inside the n-type current diffusion region 3, the interface between the n-type current diffusion region 3 and the n ^- type drift region 2, or the n ^- type. It may be terminated inside the drift region 2. That is, the pn junction between the p ⁺ type region 5 and the n-type current diffusion region 3 (or the n ^- type drift region 2) may be located deeper on the cathode side than the bottom surface 6a of the trench 6. FIGS. 1, 2A and 2B show the case where the cathode side end of the p ⁺ type region 5 is terminated inside the n-type current diffusion region 3 (the same applies to FIGS. 4 to 14). The p ⁺ type region 5 extends from the active region 21 to the edge termination region 23 and terminates at the edge termination region 23 (see FIGS. 2A and 2B).

The conductive layer 7 is embedded on the front surface 10a of the semiconductor substrate 10 so as to embed the inside of the trench 6. The conductive layer 7 is in contact with the p ⁺ type surface region 4 at the front surface 10a of the semiconductor substrate 10 and the upper corner portion 6c of the trench 6 between the trenches 6, and is in contact with the n-type current diffusion region 3 at the side wall 6b of the trench 6. .. Further, the conductive layer 7 is in contact with the p ⁺ type region 5 at the bottom surface 6a of the trench 6 (preferably the bottom surface 6a and the bottom surface corner portion 6d of the trench 6). The conductive layer 7 is made of, for example, a metal layer made of a metal material such as titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), a polysilicon (poly-Si) layer, or the like. The conductive layer 7 may extend on the front surface 10a (the surface of the p ⁺ type surface region 4) of the semiconductor substrate 10 outward from the longitudinal end portion of the trench 6 (FIGS. 2A and 2B). reference).

A Schottky junction 11 is formed by the conductive layer 7 and the n-type current diffusion region 3. As described above, the p ⁺ type surface region 4 is exposed on the front surface 10a of the semiconductor substrate 10 and the upper corner portion 6c of the trench 6. Further, the bottom surface 6a and the bottom surface corner portion 6d of the trench 6 are covered with the p ⁺ type region 5. Therefore, the Schottky junction 11 between the conductive layer 7 and the n-type current diffusion region 3 is formed only on the side wall 6b of the trench 6 along the side wall 6b of the trench 6, and has one surface orientation (side wall 6b of the trench 6). The Schottky characteristic of the trench type SBD is determined only by the height of the Schottky barrier based on the surface orientation of the trench type SBD. The Schottky junction 11 formed on the side wall 6b of one trench 6 constitutes one unit cell of the trench type SBD.

Each unit cell of the trench type SBD extends in the direction X in which the trench 6 extends in a stripe shape, and its area (surface area of the Schottky junction 11) is the depth of the trench 6 and the length in the longitudinal direction of the trench 6. It is adjustable. Further, by arranging the p ⁺ type surface region 4, the surface area of the Schottky junction 11 is reduced and the contact resistance is increased, but p + is formed from the interface between the p ⁺ type surface region 4 and the n-type current diffusion region 3 ^. If the cell pitch (= mesa width w10) is narrowed with respect to the distance t2 to the anode side end of the mold region 5, the loss due to the surface area reduction of the Schottky junction 11 can be reduced. This distance t2 corresponds to the width w11 in the depth direction of the Schottky junction 11, and the length in the longitudinal direction of the trench 6 corresponds to the width w12 in the direction parallel to the substrate front surface 10a of the Schottky junction 11. The surface area of the Schottky junction 11 is the product of the width w11 of the Schottky junction 11 in the depth direction and the width w12 of the Schottky junction 11 in the direction parallel to the substrate front surface 10a.

The surface area of the Schottky junction 11 is preferably equal to or larger than the surface area of the front surface 10a of the semiconductor substrate 10 between the trenches 6, for example. Therefore, the cell pitch (mesa width w10) is preferably set to the width w11 or less in the depth direction of the Schottky junction 11 (w10 ≦ w11). That is, the cell pitch may be set to a distance t2 or less from the interface between the p ⁺ type surface region 4 and the n-type current diffusion region 3 to the anode-side end of the p ⁺ type region 5 (w10 ≦ t2). Further, by covering the bottom surface 6a and the bottom surface corner portion 6d of the trench 6 with the p ⁺ type region 5, the portion surrounded by the p ⁺ type region 5 of the trench 6 becomes an invalid region that does not form the trench type SBD. Since this invalid region also exists in the conventional structure (see FIG. 16), there is no loss in shotkey characteristics as compared with the conventional structure.

The front surface electrode (first electrode) 8 is in contact with the conductive layer 7 and electrically connected via a contact hole opened in the field oxide film 12. The field oxide film 12 may be, for example, a silicon oxide (SiO ₂ ) film. The front surface electrode 8 may extend to the field oxide film 12. The front surface electrode 8 functions as an anode electrode. Further, the front surface electrode 8 also serves as, for example, an anode electrode pad. The field oxide film 12 covers the entire front surface 10a, 10a'of the semiconductor substrate 10 and the entire surface of the steer 40a of the step 40 described later from the connecting region 22 to the edge termination region 23. A back surface electrode (second electrode) 9 is provided on the back surface of the semiconductor substrate 10 (the back surface of the n ⁺ type silicon carbide substrate 1). The back surface electrode 9 functions as a cathode electrode.

As shown in FIGS. 2A and 2B, the n-type current diffusion region 3, the p ⁺ type surface region 4 and the p ⁺ type region 5 extend from the active region 21 to the connecting region 22 as described above. Also at the longitudinal end of the trench 6, the upper corner 6c is covered by the p ⁺ -shaped surface region 4. Inside the steer 40a of the step 40 so that a part 31a of the n ^- type silicon carbide layer 31 remains between the n-type current diffusion region 3 and the p ⁺ type surface region 4 in the steer 40a of the step 40 described later. The n-type current diffusion region 3 may be terminated at (the center side of the chip) (FIG. 2A). By leaving a part 31a of the n ^- type silicon carbide layer 31 between the n-type current diffusion region 3 and the p ⁺ type surface region 4 in the steer 40a of the step 40 described later, a mesa region (between adjacent trenches 6). It is possible to reduce the resistance of the p ⁺ type surface region 4 of the above (make it easier for the Hall current to flow). Alternatively, n- is formed so that the portion sandwiched ^between the p ⁺ type surface region 4 and the p ⁺ type region 5 reaches the p ⁺ type surface region 4 in the steer 40a of the step 40 from the longitudinal end portion of the trench 6. A mold or p ⁺ type region 13 may be provided (FIG. 2B). When the region 13 is n ^- type, the process can be simplified, and when the region 13 is p ⁺ type, the resistance of the p ⁺ type surface region 4 of the mesa region can be reduced. can.

In the edge termination region 23, the surface layer of the front surface 10a of the semiconductor substrate 10 (the surface layer of the n ^- type silicon carbide layer 31) is removed to a predetermined thickness, and the front surface 10a of the semiconductor substrate 10 is activated. A step 40 lower than the region 21 and the connecting region 22 (recessed toward the cathode side) is formed. The flat surface (the front surface of the substrate in the edge termination region 23) outside the step 40 of the front surface 10a of the semiconductor substrate 10 is indicated by reference numeral 10a'. The connecting portion (hereinafter referred to as the steer of the step 40) 40a between the substrate front surfaces 10a and 10a'(upper and lower stages) between the connecting region 22 and the edge termination region 23 is the substrate front surface 10a, 10a'. It may have an inclination with respect to the relative, or it may be substantially vertical.

In the steer 40a of the step 40, the p ⁺ type surface region 4 extending from the connecting region 22 along the steer 40a of the step 40 is exposed on the surface of the n ^- type silicon carbide layer 31. The p ⁺ type surface region 4 extends further outward from the steer 40a of the step 40 and covers the boundary 40b between the steer 40a of the step 40 and the substrate front surface 10a'outside the steer 40a. The p ⁺ type region 5 extends from the connecting region 22 to the outside of the p ⁺ type surface region 4, and at the boundary 40b between the steer 40a of the step 40 and the substrate front surface 10a'outside the steer 40a. Covers the end of the p ⁺ type surface area 4. Each p ⁺ type surface region 4 of the mesa region (between adjacent trenches 6) is connected in the connecting region 22. Specifically, for example, the p ⁺ type surface region 4 is uniformly provided over the entire front surface 10a of the semiconductor substrate 10 in the mesa region, and extends from the active region 21 to the connecting region 22 to be connected. It is uniformly provided over the entire front surface 10a of the semiconductor substrate 10 in the region 22 (see FIG. 3). Alternatively, the p ⁺ type surface region 4 may extend from the active region 21 to the connecting region 22 and may be partially provided on the front surface 10a of the semiconductor substrate 10 in the connecting region 22. In this case, the p ⁺ type surface regions 4 adjacent to each other across the trench 6 may be partially connected in the connecting region 22 (not shown). The p ⁺ type region 5 is in contact with the first JTE region 41 described later in the edge termination region 23.

A pressure-resistant structure such as a JTE structure and an n ⁺ type stopper region 43 are provided on the surface layer of the substrate front surface 10a'outside the steer 40a of the step 40. In the JTE structure, a plurality of p-type regions (here, two; hereinafter referred to as the first and second JTE regions 41 and 42) having a concentric circle surrounding the active region 21 and having a lower impurity concentration as they are arranged outside are formed. Be adjacent. The first JTE region (p-type region) 41 is provided on the innermost side of the edge termination region 23 and is in contact with the p ⁺ type region 5. The second JTE region (p ^- type region) 42 is provided outside the first JTE region 41 and is in contact with the first JTE region 41. Further, the n ⁺ type stopper region 43 is provided outside the second JTE region 42 so as to be exposed on the side surface of the chip, away from the second JTE region 42, and so as to surround the periphery of the second JTE region 42. ..

Although not particularly limited, for example, the dimensions of each part near the Schottky junction 11 take the following values. Distance from the anode side (front surface electrode 8 side) end of the p ⁺ type region 5 to the bottom surface 6a of the trench 6 (thickness of the portion of the conductive layer 7 protruding inside the p ⁺ type region 5). For example, t1 may be about 0.01 μm or more and 0.1 μm or less. The distance t2 from the interface between the p ⁺ type surface region 4 and the n-type current diffusion region 3 to the anode-side end of the p ⁺ type region 5 may be, for example, about 1.0 μm or more and 2.0 μm or less. The distance t3 from the front surface 10a of the semiconductor substrate 10 to the interface between the p ⁺ type surface region 4 and the n-type current diffusion region 3 (that is, the thickness of the p ⁺ type surface region 4) is, for example, 0.1 μm or more and 0. It may be about 3 μm or less. The distance between the adjacent trenches 6 (mesa width w10) may be, for example, about 1.0 μm or more and 2.0 μm or less.

Next, the method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 1, 2A, 3, 4 to 9. 4 to 9 are cross-sectional views showing a state in which the semiconductor device according to the first embodiment is in the process of being manufactured. First, as shown in FIG. 4, an n ⁺ type silicon carbide substrate 1 serving as an n ⁺ type cathode region is prepared. Next, the n ^- type silicon carbide layer 31 is epitaxially grown on the front surface of the n ⁺ type silicon carbide substrate 1. Next, as shown in FIG. 5, a p ⁺ type region 5 is selectively formed on the surface layer of the n ⁻ type silicon carbide layer 31 by photolithography and ion implantation of a p-type impurity.

Next, by photolithography and ion implantation of n-type impurities, for example, the n-type region (hereinafter referred to as n-type partial region) 3a is formed on the surface layer of the n ^- type silicon carbide layer 31 from the active region 21 to the connecting region 22. Form. The n-type partial region 3a is a part of the n-type current diffusion region 3. At this time, the depth of the n-type partial region 3a can be variously changed. FIG. 5 shows a case where the depth of the n-type partial region 3a is deeper than that of the p ⁺ type region 5 (the same applies to FIGS. 6 to 9). The portion of the n ^- type silicon carbide layer 31 on the cathode side of the n-type partial region 3a is the n ^- type drift region 2. The formation order of the n-type partial region 3a and the p ⁺ type region 5 may be exchanged.

Next, as shown in FIG. 6, an n ^- type silicon carbide layer is further epitaxially grown on the n ^- type silicon carbide layer 31, and the thickness of the n ^- type silicon carbide layer 31 is increased. As a result, the silicon carbide substrate (semiconductor wafer) 10 in which the n ^- type silicon carbide layer 31 having a predetermined thickness is deposited on the n ⁺ type silicon carbide substrate 1 is formed. Next, by photolithography and ion implantation of n-type impurities, for example, from the active region 21 to the connecting region 22, the thickness of the n ^- type silicon carbide layer 31 is increased to the portion 31a, and the depth reaches the n-type partial region 3a. Form an n-type partial region 3b. The impurity concentration of the n-type partial region 3b is substantially the same as that of the n-type partial region 3a. By connecting the n-type partial regions 3a and 3b in the depth direction, the n-type current diffusion region 3 is formed.

Next, by removing the surface layer of the n ^- type silicon carbide layer 31 at a predetermined thickness in the edge termination region 23 by photolithography and etching, the front surface 10a of the semiconductor substrate 10 is connected to the active region 21. A step 40 lower than the region 22 is formed (see FIG. 2A). Next, as shown in FIG. 7, by photolithography and ion implantation of a p-type impurity, the surface layer of the n ^- type silicon carbide layer 31 is outside the steer 40a of the step 40 and the steer 40a from the active region 21. The p ⁺ type surface region 4 is formed so as to cover up to the boundary 40b with the substrate front surface 10a'.

Next, the steps of photolithography and ion implantation are repeated under different conditions, and the first and second JTE regions 41 and 42 are formed on the surface layer of the substrate front surface 10a'outside the steer 40a of the step 40. And the n ⁺ type stopper region 43 are selectively formed. The formation order of the p ⁺ type surface region 4, the first and second JTE regions 41, 42 and the n ⁺ type stopper region 43 may be changed. Then, heat treatment (activation annealing) for activating impurities is performed on all the regions formed by ion implantation.

Next, as shown in FIG. 8, a trench 6 is formed that penetrates the p ⁺ type surface region 4 and reaches the p ⁺ type region 5 inside the n-type current diffusion region 3. Next, the field oxide film 12 is formed on the front surface 10a of the semiconductor substrate 10. Next, the field oxide film 12 is selectively removed by photolithography and etching to expose the portion of the front surface 10a of the semiconductor substrate 10 corresponding to the active region 21. At this time, the opening of the field oxide film 12 may be exposed up to the portion of the connecting region 22 on the active region 21 side.

Next, as shown in FIG. 9, the conductive layer 7 is deposited on the front surface 10a of the semiconductor substrate 10 so as to be embedded in the trench 6 by, for example, a deposition method. Next, the conductive layer 7 is etched back and left only on the inside of the trench 6 and on the front surface 10a of the semiconductor substrate 10 exposed to the opening of the field oxide film 12. Next, the front surface electrode 8 and the back surface electrode 9 are formed by a general method. Then, by dicing (cutting) the semiconductor wafer and individualizing it into individual chips, the trench type SBD shown in FIGS. 1, 2A and 3 is completed.

As described above, according to the first embodiment, a p ⁺ type surface region covering the front surface of the semiconductor substrate and the upper corner portion of the trench is formed between adjacent trenches (mesa region). Moreover, a p ⁺ type region is formed so as to cover the bottom surface and the bottom corner portion of the trench. As a result, the Schottky junction between the conductive layer and the n-type current diffusion region is formed only on the side wall of the trench. Therefore, the Schottky barrier height based on one surface orientation (the surface orientation of the side wall of the trench) is the trench type. The Schottky characteristics of the SBD are determined. Therefore, the leakage current does not increase due to the existence of a plurality of Schottky barriers in the trench type SBD. Further, by designing the trench so that the surface orientation does not become the Si surface or the C surface having a low Schottky barrier height, it is possible to prevent the leakage current from increasing and prevent the withstand voltage from decreasing. Moreover, a predetermined Schottky characteristic can be stably obtained based on the Schottky barrier height of only one surface direction. Further, according to the first embodiment, by narrowing the cell pitch, the decrease in the surface area of the Schottky junction can be made smaller than the cell pitch. Therefore, the loss due to the reduction in the surface area of the Schottky junction can be reduced, and the chip can be reduced in size. Further, according to the first embodiment, the surface area of the Schottky junction can be increased with respect to the cell pitch by setting the cell pitch to be equal to or less than the width in the depth direction of the Schottky junction. This makes it possible to reduce the contact resistance at the Schottky joint surface.

(Embodiment 2)
Next, the structure of the semiconductor device according to the second embodiment will be described. 10 and 11A are cross-sectional views showing the structure of the semiconductor device according to the second embodiment. 11B is a cross-sectional view showing a modified example of FIG. 11A. FIG. 12 is a plan view showing the layout of each part of the plane cut by the cutting line FF of FIG. 10 and the cutting line FF'of FIGS. 11A and 11B as viewed from the front surface side of the semiconductor substrate. FIG. 10 is a cross-sectional structure taken along the cutting line DD of FIG. FIG. 10 shows the cross-sectional structure of the active region 21 of FIG. 11A and 11B are cross-sectional structures at the cutting line EE'of FIG. 11A and 11B show the cross-sectional structures of the connecting region 22 and the edge ending region 23. The structure of the connecting region 22 is different between FIGS. 11A and 11B.

The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in that the adjacent trench 6 is provided by the field oxide film 12 instead of the p ⁺ type surface region (corresponding to reference numeral 4 in FIG. 1). It is a point that covers the front surface 10a (the surface of the n ^- type silicon carbide layer 31) of the semiconductor substrate 10 in the space (mesa region). The conductive layer 7 projects outward from the inside of the trench 6 with respect to the front surface 10a of the semiconductor substrate 10. The conductive layer 7 may extend on the field oxide film 12 in the active region 21. The distance t4 from the front surface 10a of the semiconductor substrate 10 to the anode-side end of the p ⁺ type region may be, for example, about 1.0 μm or more and 2.0 μm or less. This distance t4 corresponds to the width w11 in the depth direction of the Schottky junction 11. The thickness t5 of the field oxide film 12 may be, for example, 0.01 μm or more and 1.0 μm or less. An insulating film different from the field oxide film 12 may cover the front surface 10a of the semiconductor substrate 10 between the trenches 6.

The field oxide film 12 is provided so as to surround the circumference of the trench 6 when viewed from the front surface 10a of the semiconductor substrate 10 (see FIG. 12). Since the front surface 10a of the semiconductor substrate 10 between the trenches 6 is covered with the field oxide film 12, the conductive layer 7 does not come into contact with the front surface 10a of the semiconductor substrate 10 between the trenches 6. Therefore, the Schottky junction 11 between the conductive layer 7 and the n-type current diffusion region 3 extends from the interface between the front surface 10a of the semiconductor substrate 10 and the field oxide film 12 to the anode-side end of the p ⁺ type region 5. It is formed only along the side wall 6b of the trench 6 at the portion of the distance t4, and is not formed at the upper corner portion 6c of the trench 6. The configuration of the connecting region 22 and the edge ending region 23 is the same as that of the first embodiment (see FIGS. 2A and 2B) except that the p ⁺ type surface region is not provided.

The method for manufacturing a semiconductor device according to the second embodiment omits the step of forming a p ⁺ type surface region in the method for manufacturing a semiconductor device according to the first embodiment. Further, the field oxide film 12 remains on the front surface 10a of the semiconductor substrate 10 in the connecting region 22 and the edge termination region 23 and the front surface 10a of the semiconductor substrate 10 between the trenches 6. 12 may be selectively removed.

As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained by covering the front surface of the semiconductor substrate between the trenches with the insulating film.

(Embodiment 3)
Next, the structure of the semiconductor device according to the third embodiment will be described. 13 and 14 are cross-sectional views showing the structure of the semiconductor device according to the third embodiment. The layout of each part of the plane cut by the cutting line CC of FIG. 13 and the cutting line CC'of FIG. 14 as viewed from the front surface side of the semiconductor substrate is the same as that of the first embodiment (see FIG. 3). .. FIG. 13 is a cross-sectional structure taken along the cutting line AA of FIG. FIG. 13 shows the cross-sectional structure of the active region 21 of FIG. FIG. 14 is a cross-sectional structure taken along the cutting line BB'of FIG. FIG. 14 shows the cross-sectional structure of the connecting region 22 and the edge ending region 23. Reference numeral 24 is a boundary between the conductive layer 7 and the field oxide film 12.

The semiconductor device according to the third embodiment is different from the semiconductor device according to the first embodiment in the following three points.

The first difference is that the insulating layer 14 is provided inside the trench 6 so as to embed the bottom surface 6a to the bottom surface corner portion 6d of the trench 6. The thickness of the insulating layer 14 (distance from the interface between the conductive layer 7 and the insulating layer 14 to the bottom surface 6a of the trench 6) t6 may be, for example, about 0.01 μm or more and 0.2 μm or less. The distance t7 from the interface between the p ⁺ type surface region 4 and the n-type current diffusion region 3 to the interface between the conductive layer 7 and the insulating layer 14 may be, for example, about 1.0 μm or more and 2.0 μm or less. This distance t7 corresponds to the width w11 in the depth direction of the Schottky junction 11. The conductive layer 7 is embedded on the insulating layer 14 inside the trench 6.

The second difference is that the trench 6 is provided at a depth that does not reach the p ⁺ type region 5 from the substrate front surface 10a. That is, instead of the p ⁺ type region 5, the bottom surface 6a and the bottom surface corner portion 6d of the trench 6 are covered from the inside of the trench 6 by the insulating layer 14. With this insulating layer 14, the Schottky junction 11 between the conductive layer 7 and the n-type current diffusion region 3 can be configured so as not to be formed on the bottom surface 6a and the bottom surface corner portion 6d of the trench 6. The p ⁺ type region 5 is arranged apart from the trench 6 and faces the bottom surface 6a and the bottom surface corner portion 6d of the trench 6 in the depth direction.

The third difference is that in the connecting region 22, p + in the steer 40a of the step 40 from the longitudinal end of the trench 6 to the portion sandwiched between the p ⁺ type surface region 4 and the p ⁺ type region 5 ^. The point is that the p ⁺ type region 15 is provided so as to reach the mold surface region 4. The p ⁺ -shaped region 15 covers the bottom corner portion 6d at the longitudinal end of the trench 6. The p ⁺ type region 15 has a function of relaxing the electric field concentration on the bottom corner portion 6d of the longitudinal end portion of the trench 6.

The configuration of the connecting region 22 and the edge ending region 23 is the same as that of the first embodiment (see FIG. 2A) except for a third difference.

As described above, according to the third embodiment, the insulating layer is provided on the bottom surface side of the trench, and the insulating layer covers the bottom surface and the bottom corner portion of the trench from the inside of the trench. A similar effect can be obtained.

In the above, the present invention can be variously modified without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, and the like are set variously according to the required specifications and the like. Further, in the above-described embodiment, the case where an epitaxial substrate obtained by epitaxially growing a silicon carbide layer on the silicon carbide substrate is described as an example, but each region constituting the semiconductor device according to the present invention is described by, for example, ions. It may be formed on a silicon carbide substrate by implantation or the like. Further, the present invention has the same effect when applied to a wide bandgap semiconductor other than silicon carbide (for example, gallium (Ga)). Further, the present invention is similarly established even if the conductive type (n type, p type) is inverted.

As described above, the semiconductor device according to the present invention is useful for the trench type SBD.

1 n ⁺ type silicon carbide substrate 2 n ^- type drift region 3 n-type current diffusion region 3a, 3b n-type partial region 4 p ⁺ type surface region 5,15 p ⁺ type region 6 Trench 6a Trench bottom surface 6b Trench side wall 6c Top corner of trench 6d Bottom corner of trench 7 Conductive layer 8 Front surface electrode 9 Back surface electrode 10 Semiconductor substrate 10a, 10a'Front surface of semiconductor substrate 11 Shotkey junction 12 Field oxide film 13 n ^- type? p ⁺ type region 14 Insulation layer 21 Active region 22 Connecting region 23 Edge termination region 24 Boundary between conductive layer and field oxide film 31 n ^- type silicon carbide layer 31an ^- type silicon carbide layer thickened part 40 Step 40a on the front surface of the semiconductor substrate 40b Steer on the step 40b Boundary between the steer on the step and the front surface of the substrate outside the steer 41,42 JTE region 43 n ⁺ type stopper region t1 p ⁺ type region anode Distance from the side end to the bottom of the trench t2 Distance from the interface between the p ⁺ type surface region and the n-type current diffusion region to the anode side end of the p ⁺ type region t3 From the front surface of the semiconductor substrate to the p ⁺ type Distance from the interface between the surface region and the n-type current diffusion region t4 Distance from the front surface of the semiconductor substrate to the anode-side end of the p ⁺ type region t5 Field oxide film thickness t6 Insulation layer thickness t7 p Distance from the interface between the ⁺ type surface region and the n-type current diffusion region to the interface between the conductive layer and the insulating layer w10 Mesa width w11 Width in the depth direction of the Shotkey junction w12 Parallel to the substrate front surface of the Shotkey junction Width of direction X Direction in which the trench extends in a striped manner Y Direction in which the trench extends in a striped manner perpendicular to the direction Z Depth direction

Claims (13)

A first conductive semiconductor substrate made of a semiconductor with a wider bandgap than silicon,
A second conductive type first semiconductor region selectively provided inside the semiconductor substrate,
A second conductive type second semiconductor region provided on the surface layer of the front surface of the semiconductor substrate apart from the first semiconductor region,
A first conductive type third semiconductor region, which is a portion of the semiconductor substrate other than the first semiconductor region and the second semiconductor region,
A trench that penetrates the second semiconductor region from the front surface of the semiconductor substrate and reaches the first semiconductor region.
A conductive layer provided inside the trench and forming a Schottky bond with the third semiconductor region on the side wall of the trench.
The first electrode electrically connected to the conductive layer and
The second electrode provided on the back surface of the semiconductor substrate and
The active region in which the element configured by the Schottky junction is arranged and
A terminal region that surrounds the active region and
The connecting region between the active region and the terminal region,
A step in which the front surface of the semiconductor substrate is lowered toward the second electrode side in the second surface in the terminal region rather than the first surface in the active region and the connecting region.
Equipped with
The third semiconductor region is terminated inside the third surface connecting the first surface and the second surface of the front surface of the semiconductor substrate.
In the connecting region, the third semiconductor region and the fourth semiconductor region are provided between the trench and the third surface.
The fourth semiconductor region is a first conductive type region having a lower impurity concentration than the third semiconductor region, or a second conductive type region having a different conductive type from the third semiconductor region. .. A first conductive semiconductor substrate made of a semiconductor with a wider bandgap than silicon,
A second conductive type first semiconductor region selectively provided inside the semiconductor substrate,
The third semiconductor region of the first conductive type, which is a portion of the semiconductor substrate other than the first semiconductor region,
A trench provided at a predetermined depth from the front surface of the semiconductor substrate and reaching the first semiconductor region,
An insulating film covering a portion of the front surface of the semiconductor substrate other than the trench forming region,
A conductive layer provided inside the trench and forming a Schottky bond with the third semiconductor region on the side wall of the trench.
The first electrode electrically connected to the conductive layer and
The second electrode provided on the back surface of the semiconductor substrate and
The active region in which the element configured by the Schottky junction is arranged and
A terminal region that surrounds the active region and
The connecting region between the active region and the terminal region,
A step in which the front surface of the semiconductor substrate is lowered toward the second electrode side in the second surface in the terminal region rather than the first surface in the active region and the connecting region.
Equipped with
The third semiconductor region is terminated inside the third surface connecting the first surface and the second surface of the front surface of the semiconductor substrate.
In the connecting region, the third semiconductor region and the fourth semiconductor region are provided between the trench and the third surface.
The fourth semiconductor region is a first conductive type region having a lower impurity concentration than the third semiconductor region, or a second conductive type region having a different conductive type from the third semiconductor region. .. The semiconductor device according to claim 1 or 2, wherein the first semiconductor region covers the bottom surface and the bottom surface corner portion of the trench. A first conductive semiconductor substrate made of a semiconductor with a wider bandgap than silicon,
A second conductive type first semiconductor region selectively provided inside the semiconductor substrate,
A second conductive type second semiconductor region provided on the surface layer of the front surface of the semiconductor substrate apart from the first semiconductor region,
A first conductive type third semiconductor region, which is a portion of the semiconductor substrate other than the first semiconductor region and the second semiconductor region,
A trench that penetrates the second semiconductor region from the front surface of the semiconductor substrate and faces the first semiconductor region in the depth direction.
An insulating layer provided inside the trench and covering the bottom surface and bottom corners of the trench,
A conductive layer provided on the insulating layer inside the trench and forming a Schottky bond with the third semiconductor region on the side wall of the trench.
The first electrode electrically connected to the conductive layer and
The second electrode provided on the back surface of the semiconductor substrate and
The active region in which the element configured by the Schottky junction is arranged and
A terminal region that surrounds the active region and
The connecting region between the active region and the terminal region,
A step in which the front surface of the semiconductor substrate is lowered toward the second electrode side in the second surface in the terminal region rather than the first surface in the active region and the connecting region.
Equipped with
Between the trench and the third surface connecting the first surface and the second surface of the front surface of the semiconductor substrate, a second conductive type fourth semiconductor region extends over the entire area of the connecting region. A semiconductor device characterized by being provided . 1. The semiconductor device described in. The second aspect of the present invention, wherein the insulating film covers the entire surface of the first surface, the third surface, and the second surface of the front surface of the semiconductor substrate from the active region to the terminal region. Semiconductor device. The first semiconductor region facing the bottom surface of the outermost trench in the depth direction extends outward from the active region and reaches the third surface of the front surface of the semiconductor substrate.
The second semiconductor region extends outward from the active region along the first surface and the third surface of the front surface of the semiconductor substrate and reaches the terminal region.
The semiconductor device according to any one of claims 1, 4, and 5, wherein the fourth semiconductor region is provided between the second semiconductor region and the first semiconductor region. The first semiconductor region facing the bottom surface of the outermost trench in the depth direction extends outward from the active region and reaches the third surface of the front surface of the semiconductor substrate.
According to claim 2 or 6, the fourth semiconductor region is provided between the first surface and the third surface of the front surface of the semiconductor substrate and the first semiconductor region. The semiconductor device described. A plurality of the trenches are arranged at predetermined intervals, and the trenches are arranged at predetermined intervals.
The predetermined interval is one of claims 1 to 8, wherein the predetermined interval is not more than or equal to the width in the depth direction of the Schottky junction between the third semiconductor region and the conductive layer on the side wall of the trench. The semiconductor device described. The semiconductor device according to any one of claims 1 to 9, wherein the Schottky junction is formed only on the side wall of the trench. The trenches are arranged in a striped layout extending in a direction parallel to the front surface of the semiconductor substrate, and are terminated at the connecting region.
The semiconductor device according to claim 7, wherein at least a part of the second semiconductor regions adjacent to each other with the trench interposed therebetween is connected to each other in the connecting region. The semiconductor device according to claim 7 or 11, wherein the second semiconductor region is provided on the entire surface of the surface region of the front surface of the semiconductor substrate in the connecting region. The semiconductor device according to claim 2, wherein the trench is arranged in a striped layout extending in a direction parallel to the front surface of the semiconductor substrate, and is terminated at the connecting region.

Images