CN216980573U - Semiconductor field effect transistor and electronic equipment - Google Patents
Semiconductor field effect transistor and electronic equipment Download PDFInfo
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- CN216980573U CN216980573U CN202122410836.7U CN202122410836U CN216980573U CN 216980573 U CN216980573 U CN 216980573U CN 202122410836 U CN202122410836 U CN 202122410836U CN 216980573 U CN216980573 U CN 216980573U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
Abstract
The application discloses semiconductor field effect transistor includes: the semiconductor device comprises a substrate, a first drift layer, a super junction structure, a well region, a contact region, a source region, a gate groove and a gate structure. The super junction structure is positioned on one side, far away from the substrate, of the first drift layer and comprises two first heavily doped regions and at least one second heavily doped region positioned between the first heavily doped regions, and the doping concentration of the first heavily doped regions is greater than that of the first drift layer; the well region is positioned on one side of the super junction structure far away from the substrate; the source region is positioned at one side of the well region far away from the super junction structure; the contact region is positioned on one side of the first drift layer far away from the substrate; the grid groove penetrates through the well region and the source region; filling the grid groove with the grid structure; the substrate, the first drift layer, the first heavily doped layer and the source region are of a first doping type, the second heavily doped layer and the well region are of a second doping type, and the first doping type and the second doping type are opposite doping types.
Description
Technical Field
The present disclosure relates to the Field of Semiconductor technologies, and in particular, to a Metal Oxide Semiconductor Field Effect Transistor (mosfet) and an electronic device.
Background
With the development of technology, the conventional Si material cannot meet the requirements in extreme scenes of high temperature, high frequency, high power, etc. due to the limitations of physical properties and structures. Because the third-generation semiconductor material, namely silicon carbide SiC, has the characteristics of wide forbidden band, high critical breakdown electric field, high saturation drift rate and the like, a semiconductor device made of SiC can work well in the extreme scenes, and further, the performance of hardware facilities and software systems is remarkably improved.
In a power device, compared with a Junction Field-Effect Transistor (JFET), the MOSFET has the advantages of high input impedance, high stability of switching speed, low on-resistance, and the like, and the gate current of the MOSFET is very low and the input impedance is high, thereby greatly simplifying a driving circuit. Compared to a Bipolar Junction Transistor (BJT), a MOSFET conducts majority carriers without a process of minority carrier injection, and thus can operate at a higher frequency.
Meanwhile, MOSFETs in semiconductor devices are gradually changed from planar MOSFETs to trench MOSFETs. Compared with a planar MOSFET, the trench MOSFET has no Junction Field-Effect Transistor (JFET) region of a Diffused Metal Oxide Semiconductor (LDMOSFET), so that the current density of a conductive channel is increased when the trench MOSFET is turned on, and a resistance component caused by the JFET region when the planar MOSFET is turned on is removed. And the conducting channel of the groove type MOSFET is vertical to the substrate plane of the MOSFET, so that the length of the conducting channel of the groove type MOSFET is shorter, the on-resistance is small, and the power consumption of the device can be reduced.
However, in the existing trench MOSFET, the electric field strength at both sides of the gate oxide layer at the corner of the trench in the MOSFET is increased due to the electric field concentration effect at the corner of the trench, so that the breakdown voltage of the gate oxide layer in the MOSFET is smaller than that of the PN junction at the corner of the trench, and therefore, the maximum blocking voltage of the trench MOSFET in the prior art is limited by the thickness of the gate oxide layer.
SUMMERY OF THE UTILITY MODEL
The application provides a semiconductor field effect transistor, which can increase the maximum blocking voltage and reduce the on-resistance under the condition of not obviously increasing the size of the semiconductor field effect transistor.
In one aspect, an embodiment of the present application provides a semiconductor field effect transistor, including: the drift-type transistor comprises a base substrate and a first drift layer located on one side of the substrate, wherein the doping concentration of the first drift layer is smaller than that of the substrate.
The super junction structure is positioned on one side, far away from the substrate, of the first drift layer and comprises two first heavily doped regions and at least one second heavily doped region positioned between the first heavily doped regions.
And the well region is positioned on one side of the super junction structure far away from the substrate. And the source region is positioned on one side of the well region far away from the super junction structure.
The contact region is positioned on one side, far away from the substrate, of the first drift layer, and the contact region is positioned on two sides of the source region along the direction parallel to the substrate.
The grid groove penetrates through the well region and the source region, and the width of the grid groove is the same as that of the second heavily doped region along the direction parallel to the substrate.
A gate structure filling the gate trench.
The substrate, the first drift layer, the first heavily doped region and the source region have a first doping type, the second heavily doped region and the well region have a second doping type, and the first doping type and the second doping type are opposite doping types.
In a second aspect, the present application provides an electronic device comprising the above semiconductor field effect transistor. Additional aspects and advantages of the utility model will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the utility model.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a semiconductor field effect transistor provided in the related art;
fig. 2 is a schematic structural diagram of a semiconductor field effect transistor according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another semiconductor field effect transistor provided in an embodiment of the present application;
fig. 4 is a schematic structural diagram of another semiconductor field effect transistor according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of another semiconductor field effect transistor provided in an embodiment of the present application;
fig. 6 is a schematic structural diagram of another semiconductor field effect transistor according to an embodiment of the present disclosure;
fig. 7a is a schematic structural diagram of another semiconductor field effect transistor according to an embodiment of the present disclosure;
fig. 7b is a schematic structural diagram of another semiconductor field effect transistor according to an embodiment of the present disclosure;
reference numerals are as follows:
100-a substrate; 101-a drift layer; 102-well region; 103-a source region; 104-a contact zone; 105-a trench; 106-gate oxide layer; 107-gate; 108-interlayer dielectric layer; 109-source electrode; 110-a drain electrode; 200-a substrate; 201-a first drift layer; 210-super junction structure; 220-well region; 230-a source region; 231-a contact zone; 232-source trenches; 240-gate trenches; 250-a gate structure; 260-a second drift layer; 270-a third drift layer; 280-interlayer dielectric layer; 290-source metal layer; 300-a drain electrode; 2101-a first heavily doped region; 2102-a second heavily doped region; 2501-gate; 2502-gate; 240 a-the bottom of the gate trench; 232 a-the bottom of the source trench.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making creative efforts shall fall within the protection scope of the present application.
Technical solutions in some embodiments of the present disclosure will be described below clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only some, but not all embodiments of the present disclosure. All other embodiments, which come within the meaning of the claims herein and derived by the person of ordinary skill in the art based on the examples provided in the disclosure, are to be understood as being open-ended, inclusive, and all other forms, such as the third-named singular form "comprising" and the present participle form "comprising" are to be interpreted as being encompassed by the present disclosure unless the context requires otherwise. In the description of the specification, the terms "one embodiment(s)", some embodiments(s) "," exemplary embodiments (examples) "," specific examples (specific examples) "or" some examples (examples) "etc. are intended to indicate that a particular feature, structure, material or characteristic associated with the embodiment(s) or example(s) is included in at least one embodiment or example of the present disclosure. The schematic representations of the terms used above are not necessarily referring to the same embodiment or example.
Furthermore, the particular features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples. The terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, unless otherwise specified, "a plurality" means two or more, and in describing one such embodiment, expressions of "connected" and derivatives thereof may be used. For example, the term "connected" may be used in describing embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As used herein, "about" or "approximately" includes the stated value as well as the average value within an acceptable deviation range for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).
Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device.
Before the technical scheme of the application is introduced, the related knowledge of the application is introduced as follows:
in the related art, as shown in fig. 1, the trench type semiconductor field effect transistor includes a substrate 100, a drift layer 101, a well region 102, a source region 103, a contact region 104, a gate trench 105, a gate oxide layer 106, a gate 107, an interlayer dielectric layer 108, a source 109, and a drain 110.
The doping type of the substrate 100 is a first doping type, for example, the first doping type is an N type, and the material of the substrate 100 is one or more of semiconductor materials such as silicon Si, silicon carbide SiC, germanium Ge, and the like.
The drift layer 101 is located on one side of the substrate 100, the drift layer 101 is formed by epitaxial growth on the substrate 100, the doping type of the drift layer 101 is the same as that of the substrate 100, and the doping concentration of the drift layer 101 is smaller than that of the substrate 100, for example. The substrate 100 is heavily doped and the drift layer 101 is lightly doped.
The well region 102 is located on a side of the drift layer 101 facing away from the substrate 100, and a doping type of the well region 102 is a second doping type. For example, when the first doping type is N-type and the second doping type is P-type, the well region 102 may be formed by an ion implantation process.
The source region 103 is located on a side of the well region 102 facing away from the drift layer 101, a doping type of the source region 103 is a first doping type, and the source region 103 is formed by a photolithography process and an ion implantation process, wherein the photolithography process is used for determining a range for performing the ion implantation.
The contact region 104 is located on a side of the well region 102 facing away from the drift layer 101, a doping type of the contact region 104 is a second doping type, and the contact region 104 is formed through a photolithography process and an ion implantation process, wherein the photolithography process is used for determining a range for performing the ion implantation.
The gate oxide layer 106 is located on the surface of the trench 105, and the gate 107 is filled in the trench 105, that is, the gate oxide layer 106 is used to isolate the gate 107 from the drift layer 101, isolate the gate 107 from the well region 102, and isolate the gate 107 from the source region 103. The source region 103 is closer to the gate oxide layer 106 than the contact region 104. Illustratively, the material of the gate 107 is single crystal silicon, polycrystalline silicon, or a mixture of single crystal silicon and polycrystalline silicon, etc.
The interlayer dielectric layer 108 covers the surface of the gate 107, and the material of the interlayer dielectric layer 108 is an oxide of a semiconductor material.
The source 109 covers at least the surface of the interlayer dielectric layer 108, and the source 109 is located on the side of the source region 103 away from the well region 102, and the source 109 is located on the side of the contact region 104 away from the well region 102. The source electrode 109 is a metal electrode, and the material of the source electrode 109 is, for example, one or more of titanium Ti, nickel Ni, gold Au, and silver Ag.
The drain electrode 110 is located on a side of the substrate 100 facing away from the drift layer 101, and the material of the drain electrode 110 is, for example, one or more of Ti, Ni, Au, and Ag.
When a reverse voltage (for example, a positive voltage is applied to the drain and a 0V voltage is applied to the source) is applied to the trench type semiconductor field effect source 109 and the drain 110 in the related art, an electric field concentration effect is generated at the bottom of the gate trench 105 (a portion within a dotted line frame in fig. 1) in the trench type semiconductor field effect transistor shown in fig. 1 due to electric field unevenness, and the gate oxide layer 106 is likely to be broken down. At this time, the PN junction formed between the drift layer 101 and the well region 102 at the bottom of the gate trench 105 has not been broken down. Thus, the breakdown voltage of the trench type mosfet is limited by the breakdown voltage of the gate oxide layer 106, not the breakdown voltage of the PN junction.
In addition, if a larger withstand voltage is desired for the trench type semiconductor field effect transistor, the thickness of the drift layer 101 can be increased to reduce the doping concentration of the drift layer 101, which inevitably increases the on-resistance of the trench type semiconductor field effect transistor, and at the same time, increasing the thickness of the drift layer 101 also increases the manufacturing cost of the trench type semiconductor field effect transistor
In order to solve the above problem, as shown in fig. 2, an embodiment of the present application provides a semiconductor field effect transistor, including: the structure comprises a substrate 200, a first drift layer 201, a super junction structure 210, a well region 220, a source region 230, and a gate trench 240 and a gate structure 250.
The substrate 200 has a first doping type, which is N-type, and the material of the substrate 200 is one or more of semiconductor materials such as silicon Si, silicon carbide SiC, and germanium Ge.
The first drift layer 201 has a first doping type, a doping concentration of the first drift layer 201 is less than a doping concentration of the substrate 200, and a concentration of the first drift layer 201 is less than a concentration of the first heavily doped region 2101. Illustratively, the doping concentration of the substrate 200 is between 1x1018cm-3 and 1x1019cm-3, and the doping concentration of the first drift layer 201 is between 1x1015cm-3 and 2x1016 cm-3. The first drift layer 201 is formed by a Metal-Organic Chemical Vapor Deposition (MOCVD) process.
The first drift layer 201 provides a larger maximum blocking voltage for the mosfet. The thickness and doping concentration of the first drift layer 201 determine the on-resistance and maximum blocking voltage of the semiconductor field effect transistor, and if the doping concentration is not changed, the larger the thickness of the first drift layer 201, the larger the maximum blocking voltage of the semiconductor field effect transistor, but at the same time, the larger the on-resistance of the semiconductor field effect transistor.
Illustratively, the thickness of the first drift layer 201 is 4um to 5um, and the doping impurity of the first drift layer 201 is nitrogen N or phosphorus P.
The super junction structure 210 is located on a side of the first drift layer 201 of the substrate 200 away from the substrate 200, and includes two first heavily doped regions 2101 and a second heavily doped region 2102 located between the first heavily doped regions 2101. The first heavily doped region 2101 has the same doping type as the substrate 200, and the second heavily doped region 2102 has a second doping type, and the first doping type and the second doping type are opposite doping types. Illustratively, in the case where the first doping type is N-type, the second doping type is P-type.
The doping levels of the first heavily doped region 2101 and the second heavily doped region 2102 are both heavily doped, and for example, the doping concentration of the first heavily doped region 2101 is between 1x1018cm-3 and 2x1019cm-3, and the doping concentration of the second heavily doped region is between 1x1018cm-3 and 2x1019 cm-3. The first heavily doped region 2101 and the second heavily doped region 2102 are formed by an ion implantation process.
The well region 220 is located on a side of the super junction structure 210 away from the substrate 200, the well region 220 has the second doping type, and the well region 220 is used for forming a conductive channel in a semiconductor field effect transistor.
A source region 230, the source region 230 being located at a side of the well region 220 facing away from the super junction structure 210, the source region 230 having the first doping type, the source region 230 being for collecting carriers in the conducting channel. The doping level of the source region 230 is heavily doped, and the doping concentration of the source region 230 is, for example, between 2x1018cm-3 and 4x1019 cm-3.
A contact region 231, the contact region 231 being located on a side of the first drift layer 201 remote from the substrate 200, the contact region 231 being located on both sides of the source region 230 in a direction parallel to the substrate 200.
The gate trench 240 penetrates the well region 220 and the source region 230, the well region 220 includes two portions located at two sides of the gate trench 240 along a direction parallel to the substrate 200, the source region 230 includes two portions located at two sides of the gate trench 240, and a width of the gate trench 240 is the same as a width of the second heavily doped region 2102. Illustratively, the width of the gate trench is 2um-3 um.
The gate structure 250 fills the gate trench 240, and the gate structure 250 is used for providing a gate voltage for the mosfet, when the gate voltage is smaller than a turn-on voltage of the mosfet, a conductive channel cannot be formed between the substrate 200 and the source region 230, and the mosfet is turned off. When the gate voltage is greater than the turn-on voltage of the mosfet, an inversion layer is formed at a side of the well region 220 close to the gate trench 240 to generate a conduction channel, so that the carriers collected by the source region 230 flow to the substrate 200 through the conduction channel, and the mosfet is turned on. Thus, the basic function of the semiconductor field effect transistor is realized.
The maximum voltage difference that can be sustained between the substrate 200 and the source region 230 when the semiconductor fet is not applying the gate voltage is referred to as the maximum blocking voltage of the semiconductor fet.
On the basis, the first heavily doped region 2101 and the second heavily doped region 2102 form a PN junction, and under the condition that no voltage is applied to the semiconductor field effect transistor, due to the diffusion effect of carriers, a depletion region is formed at the part where the first heavily doped region 2101 and the second heavily doped region 2102 are in contact, and the number of carriers in the depletion region is small, so that the depletion region is a high-resistance region, and thus, the maximum blocking voltage of the semiconductor field effect transistor can be increased. Under the condition that a reverse voltage is applied to the gate structure 250 of the semiconductor field effect transistor, carriers are further diffused to form a wider depletion region, so that the maximum blocking voltage of the semiconductor field effect transistor can be further increased.
In some embodiments, the doping concentration of the first heavily doped region 2101 is greater than the doping concentration of the first drift layer 201.
On this basis, the first heavily doped region 2101 may be formed by an ion implantation process, which simplifies the fabrication process. Meanwhile, the on-resistance when the semiconductor field effect transistor is turned on can be reduced.
In some embodiments, as shown in fig. 3, further comprising: and a second drift layer 260.
The second drift layer 260 is at least between the bottom 240a of the gate trench 240 and the second heavily doped region, and the second drift layer 260 has a thickness of 1um-2um, for example. In a direction perpendicular to the substrate 200, the thickness of the first heavily doped region 2101 is greater than the thickness of the second heavily doped region 2102, and the thickness of the first heavily doped region 2101 is, for example, 0.1um to 0.2um greater than the thickness of the second heavily doped region 2102. The first drift layer 260 has a first doping type, i.e. the doping type of the second drift layer 260 is the same as the doping type of said substrate 200, and the doping concentration of the second drift layer 260 is lower than the doping concentration of the second heavily doped region 2102.
In some embodiments, the gate structure 250 includes a gate oxide layer 2501 and a gate 2502, the gate oxide layer 2501 is located on the surface of the gate trench 240; the gate 2501 is filled in the gate trench 240. Illustratively, the material of the gate electrode 2502 is one or more of single crystal silicon, polycrystalline silicon, or a conductive metal.
Based on this, the doping concentration of the second drift layer 260 is lower, so that a better growth interface is provided for forming the gate oxide layer 2501, and the quality of the gate oxide layer 2501 is improved.
In some embodiments, as shown in fig. 4, the second drift layer 260 is also located between the well region 220 and the first heavily doped region 2101.
Based on this, when the mosfet is turned on, the second drift layer 260 provides a channel for the flow of carriers, which is beneficial to reducing the on-resistance of the mosfet.
In some embodiments, the gate oxide 2501 has a thickness of
In some embodiments, as shown in fig. 5, the semiconductor field effect transistor further includes a third drift layer 270. The third drift layer 270 is located between the second drift layer 260 and the well region 220, the third drift layer 270 has the first doping type, and the doping concentration of the third drift layer 270 is greater than that of the second drift layer 260. Illustratively, the doping concentration of the third drift layer 270 is between 1x1015cm-3 and 1x1016cm-3, and the thickness of the third drift layer 270 is 0.5um-1 um. Illustratively, the third drift layer 270 is formed by a MOCVD process.
Based on this, when the mosfet is turned on, the third drift layer 270 provides a channel for the flow of carriers, which is beneficial to reducing the on-resistance of the mosfet.
In some embodiments, as shown in fig. 6, the mosfet further comprises an interlayer dielectric layer 280, a source metal layer 290 and a drain 300.
The interlayer dielectric layer 280 is located on one side of the gate structure 250 away from the super junction structure, and the interlayer dielectric layer 280 is used for protecting the gate structure 250 and isolating the gate structure 250 and the source metal layer 290. Illustratively, an interlevel dielectric layer 280 is disposed on the surface of the gate structure 250.
The drain electrode 300 is located on a side of the substrate 200 facing away from the super junction structure 210, the material of the drain electrode 300 is a conductive metal, for example, the material of the drain electrode 300 is one or a combination of titanium Ti, nickel Ni, gold Au and silver Ag, and the thickness of the drain electrode 300 is 3um to 5 um.
In some embodiments, the semiconductor field effect transistor further comprises: the source trenches 232. A source trench 232 extends through at least the source and well regions 220, a bottom 232a of the source trench being flush with a top of the contact region 231, and a source metal layer 290 filling the source trench 232.
On the basis, the semiconductor structure for forming the contact region 231 by etching can be simultaneously manufactured when the semiconductor structure for forming the second heavily doped region 2102 by etching is manufactured, so that the manufacturing process is simplified.
In some embodiments, the source trenches 232 are plural; the source trenches 232 are spaced apart in a direction parallel to the substrate 200, and the width of the source trenches 232 is the same as the width of the space between two adjacent source trenches 232.
Based on this, it can be ensured that the super junction structure at the bottom of the source trench 232 is not affected.
In some embodiments, as shown in fig. 7b, the bottom 232a of the source trench 232 is lower than the gate trench bottom 240 a. Illustratively, the bottom 232a of the source trench 232 is 0.1um-0.2um lower than the gate trench bottom 240 a. On the basis, the contact region 231 can be etched at the same time of etching the second heavily doped region 2102, so that the manufacturing process is simplified.
In some embodiments, the material of the interlayer dielectric layer 280 is one or more of TEOS, PBSG, BSG, and PSG.
In some embodiments, the material of the substrate 200, the first drift layer 201, and the well region 220 is silicon carbide SiC.
Experiments were designed based on the above and the results were recorded. The experimental conditions are as follows:
testing the on-resistance RDSON of the semiconductor field effect transistor under the conditions that the grid voltage VGS is 20V and the drain current ID is 40A; where VGS > Vth, and ID is equal to the saturation current.
The maximum blocking voltage BVdss of the semiconductor field effect transistor is tested with the gate voltage VGS 0 and the drain current ID 100 uA.
The experimental results are as follows:
| test parameters | Prior Art | The embodiments of the present application |
| RDSON(mΩ) | 80 | 65 |
| BVdss(V) | 1286 | 1502 |
Based on the above, the on-resistance RDSON of the semiconductor field effect transistor provided in the embodiment of the present application is smaller than the on-resistance RDSON in the semiconductor field effect transistor in the prior art, the maximum blocking voltage BVdss is smaller than the maximum blocking voltage BVdss in the semiconductor field effect transistor in the prior art, and the overall performance is superior to that in the prior art.
In another aspect, an embodiment of the present application provides an electronic device, which includes the above semiconductor field-effect transistor.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (14)
1. A semiconductor field effect transistor, comprising:
the drift-type semiconductor device comprises a substrate and a first drift layer positioned on one side of the substrate; the doping concentration of the first drift layer is smaller than that of the substrate; the super junction structure is positioned on one side, far away from the substrate, of the first drift layer and comprises two first heavily doped regions and at least one second heavily doped region positioned between the first heavily doped regions;
the well region is positioned on one side, far away from the substrate, of the super junction structure; the source region is positioned on one side, far away from the super junction structure, of the well region;
the contact region is positioned on one side, far away from the substrate, of the first drift layer and is positioned on two sides of the source region along the direction parallel to the substrate;
the grid groove penetrates through the well region and the source region, and the width of the grid groove is the same as that of the second heavily doped region along the direction parallel to the substrate;
a gate structure filling the gate trench;
the substrate, the first drift layer, the first heavily doped region and the source region have a first doping type, the contact region, the second heavily doped region and the well region have a second doping type, and the first doping type and the second doping type are opposite doping types.
2. The semiconductor field effect transistor of claim 1, wherein a doping concentration of the first heavily doped region is greater than a doping concentration of the first drift layer.
3. The semiconductor field effect transistor of claim 1, further comprising: a second drift layer; the second drift layer is at least positioned between the bottom of the grid groove and the second heavily doped region;
the thickness of the first heavily doped region is greater than that of the second heavily doped region along the direction perpendicular to the substrate;
the second drift layer has a first doping type, and the doping concentration of the second drift layer is lower than that of the second heavily doped region.
4. The semiconductor field effect transistor of claim 3 wherein the second drift layer is further located between the well region and the first heavily doped region.
5. The semiconductor field effect transistor of claim 4, further comprising:
the third drift layer is located between the first drift layer and the well region, the doping concentration of the third drift layer is larger than that of the first drift layer, and the doping type of the third drift layer is of the first doping type.
6. The mosfet of any of claims 1-5, wherein the gate structure comprises:
the gate oxide layer is positioned on the surface of the gate groove;
and the grid electrode is filled in the grid electrode groove.
7. The semiconductor field effect transistor of claim 6 wherein the gate oxide layer has a thickness of
8. The semiconductor field effect transistor of claim 6, further comprising:
the interlayer dielectric layer is positioned on one side of the grid structure far away from the super junction structure; the source metal layer is positioned on one side, far away from the substrate, of the source region, one side, far away from the substrate, of the contact region and one side, far away from the gate structure, of the interlayer dielectric layer;
and the drain electrode is positioned on one side of the substrate, which is far away from the super junction structure.
9. The semiconductor field effect transistor of claim 8, further comprising: at least two source trenches; the source electrode groove at least penetrates through the source electrode area and the well area, the bottom of the source electrode groove is flush with the top of the contact area, and the source electrode metal layer fills the source electrode groove.
10. The mosfet of claim 9, wherein the source trench is plural; the source electrode grooves are arranged at intervals along the direction parallel to the substrate, and the width of each source electrode groove is the same as the width of the interval between every two adjacent source electrode grooves.
11. The mosfet of claim 10 wherein the bottom of the source trench is lower than the bottom of the gate trench.
12. The mosfet of claim 11, wherein the interlayer dielectric layer is made of TEOS, PBSG, BSG, and PSG.
13. The semiconductor field effect transistor of claim 1, wherein the material of the substrate and the well region is silicon carbide.
14. An electronic device, characterized in that the electronic device comprises a semiconductor field effect transistor according to any of claims 1 to 13.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116435335A (en) * | 2023-03-22 | 2023-07-14 | 瑶芯微电子科技(上海)有限公司 | Groove type MOSFET electric field shielding protection structure and preparation method |
| CN117457731A (en) * | 2023-12-22 | 2024-01-26 | 深圳天狼芯半导体有限公司 | SiC vertical IGBT with P-type space layer below grid electrode and preparation method |
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2021
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116435335A (en) * | 2023-03-22 | 2023-07-14 | 瑶芯微电子科技(上海)有限公司 | Groove type MOSFET electric field shielding protection structure and preparation method |
| CN116435335B (en) * | 2023-03-22 | 2024-03-22 | 瑶芯微电子科技(上海)有限公司 | Groove type MOSFET electric field shielding protection structure and preparation method |
| CN117457731A (en) * | 2023-12-22 | 2024-01-26 | 深圳天狼芯半导体有限公司 | SiC vertical IGBT with P-type space layer below grid electrode and preparation method |
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