JP2003101022A - Power semiconductor device - Google Patents
Power semiconductor deviceInfo
- Publication number
- JP2003101022A JP2003101022A JP2001298311A JP2001298311A JP2003101022A JP 2003101022 A JP2003101022 A JP 2003101022A JP 2001298311 A JP2001298311 A JP 2001298311A JP 2001298311 A JP2001298311 A JP 2001298311A JP 2003101022 A JP2003101022 A JP 2003101022A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor layer
- semiconductor
- power
- impurity concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 103
- 239000012535 impurity Substances 0.000 claims abstract description 54
- 239000012212 insulator Substances 0.000 claims description 9
- 238000011084 recovery Methods 0.000 abstract description 43
- 230000002441 reversible effect Effects 0.000 description 18
- 238000000034 method Methods 0.000 description 15
- 230000008569 process Effects 0.000 description 14
- 238000009826 distribution Methods 0.000 description 11
- 230000005684 electric field Effects 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 10
- 235000012431 wafers Nutrition 0.000 description 10
- 239000000758 substrate Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000004377 microelectronic Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000002829 reductive effect Effects 0.000 description 4
- -1 Boron ions Chemical class 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 101100408296 Autographa californica nuclear polyhedrosis virus AC24 gene Proteins 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電力用半導体素子
に係り、特に伝導層（ドリフト層）部分にリサーフ構造
を有する電力用半導体素子に関するもので、例えば縦形
パワーＭＯＳＦＥＴ、ＳＢＤ（ショッキーバリアダイオ
ード）やＳＩＴ（静電誘導型トランジスタ）、ＩＧＢＴ
（絶縁ゲート型バイポーラトランジスタ）などに使用さ
れるものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device having a resurf structure in a conductive layer (drift layer) portion, for example, a vertical power MOSFET and an SBD (Shocky barrier diode). And SIT (static induction transistor), IGBT
(Insulated gate bipolar transistor) and the like.
【０００２】[0002]
【従来の技術】縦形パワーＭＯＳＦＥＴにおいて、その
オン抵抗は、伝導層（ドリフト層）部分の電気抵抗に大
きく依存する。このドリフト層の電気抵抗を決定するド
ープ濃度は、ベースとドリフト層が形成するｐｎ接合の
耐圧に応じて限界以上には上げられない。このため、素
子耐圧とオン抵抗にはトレードオフの関係が存在し、こ
のトレードオフを改善することが低消費電力素子には重
要となる。このトレードオフには素子材料により決まる
限界があり、この限界を越えることが既存のパワー素子
を越える低オン抵抗素子の実現への道である。2. Description of the Related Art In a vertical power MOSFET, its on-resistance largely depends on the electric resistance of a conductive layer (drift layer). The doping concentration that determines the electrical resistance of the drift layer cannot be increased beyond the limit depending on the breakdown voltage of the pn junction formed by the base and the drift layer. Therefore, there is a trade-off relationship between the element breakdown voltage and the on-resistance, and it is important for the low power consumption element to improve this trade-off. This trade-off has a limit determined by the element material, and exceeding this limit is the way to realize a low on-resistance element that exceeds existing power elements.
【０００３】この問題を解決するパワーＭＯＳＦＥＴの
一例として、ドリフト層にスーパージャンクション（超
接合）構造と呼ばれるリサーフ構造を埋め込んだ構造が
知られている。As an example of a power MOSFET that solves this problem, there is known a structure in which a resurf structure called a super junction (super junction) structure is embedded in a drift layer.
【０００４】図１８は、従来のパワーＭＯＳＦＥＴの構
成を模式的に示す断面図である。FIG. 18 is a sectional view schematically showing the structure of a conventional power MOSFET.
【０００５】このＭＯＳＦＥＴは、ｎ−型ドリフト層１
０３の一方の表面にｎ＋型ドレイン層１０１が形成さ
れ、このｎ＋型ドレイン層１０１上にはドレイン電極１
０５が形成されている。また、ｎ−型ドリフト層１０３
の他方の表面には複数のｐ型ベース層１０６が選択的
（横方向に周期的）に形成され、この各ｐ型ベース層１
０６表面にはｎ＋型ソース層１０７が選択的に形成され
ている。This MOSFET has an n--type drift layer 1
N + type drain layer 101 is formed on one surface of the drain electrode 03, and the drain electrode 1 is formed on the n + type drain layer 101.
05 is formed. In addition, the n − type drift layer 103
A plurality of p-type base layers 106 are selectively formed (periodically in the lateral direction) on the other surface of each of the p-type base layers 1.
An n + type source layer 107 is selectively formed on the surface of 06.
【０００６】さらに、ｎ＋型ソース層１０７およびｐ型
ベース層１０６からｎ−型ドリフト層１０３を介して隣
りのｐ型ベース層１０６およびｎ＋型ソース層１０７に
至る領域上、つまり、横方向に隣り合うｎ＋型ソース層
１０７相互間でｐ型ベース層１０６の表面上およびｎ−
型ドリフト層１０３の表面上にゲート絶縁膜１０９を介
してゲート電極１１０が形成されている。また、ゲート
絶縁膜１０９を介してゲート電極１１０を両側から挟む
ように、ｐ型ベース層１０６およびｎ＋型ソース層１０
７の表面に接合するソース電極１０８が形成されてい
る。Further, on the region from the n + type source layer 107 and the p type base layer 106 to the adjacent p type base layer 106 and the n + type source layer 107 through the n− type drift layer 103, that is, in the lateral direction. On the surface of the p-type base layer 106 between the matching n + -type source layers 107 and n−.
A gate electrode 110 is formed on the surface of the mold drift layer 103 via a gate insulating film 109. Further, the p-type base layer 106 and the n + -type source layer 10 are sandwiched so as to sandwich the gate electrode 110 from both sides with the gate insulating film 109 interposed therebetween.
A source electrode 108 is formed so as to be joined to the surface of 7.
【０００７】そして、ｎ−型ドリフト層１０３の中に
は、ｐ型ベース層１０６に接続されたｐ型リサーフ層１
０４が所定の深さで縦方向に形成されており、このｐ型
リサーフ層１０４とｎ−層１０３の一部が交互に横方向
に繰り返す縦型リサーフ構造が形成されている。この場
合、リサーフ間隔（セル幅）を狭くすることにより、ｎ
−層１０３の不純物濃度を増やすことが可能となり、オ
ン抵抗が下がる。In the n-type drift layer 103, the p-type RESURF layer 1 connected to the p-type base layer 106 is provided.
04 is formed in a vertical direction at a predetermined depth, and a part of the p-type RESURF layer 104 and the n-layer 103 are alternately repeated in the horizontal direction to form a vertical RESURF structure. In this case, by narrowing the RESURF interval (cell width), n
-It becomes possible to increase the impurity concentration of the layer 103, and the on-resistance decreases.
【０００８】ところで、ＭＯＳＦＥＴをスイッチング電
源やインバータなどに応用する場合、ＭＯＳＦＥＴと並
列に高速ダイオードを接続せずに、ｎ−型ドリフト層１
０３とｐ型ベース層１０６で形成される内蔵ダイオード
を動作させることがある。By the way, when the MOSFET is applied to a switching power supply or an inverter, the n-type drift layer 1 is not connected to the MOSFET in parallel with the high speed diode.
03 and the p-type base layer 106 may operate the built-in diode.
【０００９】この場合には、ＭＯＳＦＥＴのオン特性や
スイッチング特性に加えて、内蔵ダイオードの回復特性
も重要な特性の一つとなる。中でも内蔵ダイオードのオ
ン状態からオフ状態に移る逆回復特性が重要な特性とな
る。通常のＭＯＳＦＥＴの内蔵ダイオード逆回復特性
は、通常の高速ダイオードと逆回復電流や逆回復時間の
大小はあるものの、電流波形が滑らかなソフトなリカバ
リー波形となる。In this case, the recovery characteristics of the built-in diode are one of the important characteristics in addition to the on characteristics and switching characteristics of the MOSFET. Among them, the reverse recovery characteristic in which the built-in diode shifts from the ON state to the OFF state is an important characteristic. The built-in diode reverse recovery characteristic of a normal MOSFET has a soft recovery waveform with a smooth current waveform, although the reverse recovery current and the reverse recovery time are different from those of a normal high speed diode.
【００１０】しかし、ドリフト層にスーパージャンクシ
ョン構造を有するＭＯＳＦＥＴの内蔵ダイオード逆回復
特性は、電流が急激に変化するハードなリカバリー波形
となり、ノイズの原因となる。However, the built-in diode reverse recovery characteristic of the MOSFET having a super junction structure in the drift layer causes a hard recovery waveform in which the current changes abruptly, which causes noise.
【００１１】この原因は、ドリフト層空乏化の様子の違
いにある。通常のＭＯＳＦＥＴのドリフト層は、印加電
圧が大きくなると徐々に空乏化が進むが、スーパージャ
ンクション構造は、少しの印加電圧で完全に空乏するの
で、ドリフト層１０３内のキャリアが速やかになくな
る。このため、内蔵ダイオードの逆回復時には、流れて
いる電流が急激に零となるハードなリカバリー波形とな
ってしまう。The cause is the difference in the state of depletion of the drift layer. The drift layer of a normal MOSFET is gradually depleted as the applied voltage increases, but the superjunction structure is completely depleted with a small applied voltage, so that carriers in the drift layer 103 disappear quickly. Therefore, at the time of reverse recovery of the built-in diode, the flowing current becomes a hard recovery waveform in which the current suddenly becomes zero.
【００１２】[0012]
【発明が解決しようとする課題】上記したように従来の
スーパージャンクション構造を有するＭＯＳＦＥＴの内
蔵ダイオード逆回復特性は、電流が急激に変化するハー
ドなリカバリー波形となり、ノイズの原因となるという
問題があった。As described above, the built-in diode reverse recovery characteristic of the MOSFET having the conventional super junction structure has a problem that it causes a hard recovery waveform in which the current changes rapidly and causes noise. It was
【００１３】本発明は上記の問題点を解決すべくなされ
たもので、スーパージャンクション構造によりオン抵抗
を下げつつ、内蔵ダイオードの逆回復特性がソフトなリ
カバリー波形となる電力用半導体素子を提供することを
目的とする。The present invention has been made to solve the above problems, and provides a power semiconductor element in which the reverse recovery characteristic of a built-in diode is a soft recovery waveform while reducing the on-resistance by a super junction structure. With the goal.
【００１４】[0014]
【課題を解決するための手段】本発明の電力用半導体素
子は、第１導電型の第１の半導体層と、前記第１の半導
体層上に形成され、深さ方向とは直交する方向の面内で
周期的に配置された第１導電型の第２の半導体層および
第２導電型の第３の半導体層と、前記第１の半導体層に
電気的に接続された第１の主電極と、前記第２の半導体
層と第３の半導体層表面に選択的に形成された第２導電
型の第４の半導体層と、前記第４の半導体層の表面に選
択的に形成された第１導電型の第５の半導体層と、前記
第４の半導体層および第５の半導体層の各表面に接合す
るように形成された第２の主電極と、前記第４の半導体
層と、第５の半導体層、第２の半導体層のそれぞれにゲ
ート絶縁膜を介して形成された制御電極とを具備し、前
記第１の主電極と第２の主電極との間に所定の電圧を加
えた時に前記第２の半導体層と第３の半導体層が完全に
空乏化し、前記第１の半導体層の不純物濃度が第２の半
導体層の不純物濃度よりも低いことを特徴とする。A power semiconductor device of the present invention is formed on a first conductive type first semiconductor layer and the first semiconductor layer, and is formed in a direction orthogonal to a depth direction. A second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type, which are periodically arranged in a plane, and a first main electrode electrically connected to the first semiconductor layer. A second conductive type fourth semiconductor layer selectively formed on the surfaces of the second semiconductor layer and the third semiconductor layer, and a fourth semiconductor layer selectively formed on the surface of the fourth semiconductor layer. A fifth semiconductor layer of one conductivity type, a second main electrode formed so as to be bonded to each surface of the fourth semiconductor layer and the fifth semiconductor layer, the fourth semiconductor layer, 5 semiconductor layers, and a control electrode formed on each of the second semiconductor layers via a gate insulating film, the first main electrode and When a predetermined voltage is applied between the second semiconductor layer and the second main electrode, the second semiconductor layer and the third semiconductor layer are completely depleted, and the impurity concentration of the first semiconductor layer is the impurity of the second semiconductor layer. It is characterized by being lower than the concentration.
【００１５】[0015]
【発明の実施の形態】以下、図面を参照して本発明の実
施の形態を詳細に説明する。なお、以下の実施形態で
は、第１導電型をｎ型、第２導電型をｐ型としている。
また、図面中の同一名称の部分には同一番号を付してい
る。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type.
Moreover, the same number is attached to the part of the same name in the drawings.
【００１６】＜第１の実施形態＞図１は、本発明の第１
の実施形態に係るパワーＭＯＳＦＥＴの構成を模式的に
示す断面図である。<First Embodiment> FIG. 1 shows a first embodiment of the present invention.
3 is a cross-sectional view schematically showing the configuration of the power MOSFET according to the embodiment of FIG.
【００１７】このパワーＭＯＳＦＥＴは、第１の半導体
層であるｎ−型ドリフト層（以下、ｎ−層と記す）２の
一方の表面には、縦型のリサーフ構造（スーパージャン
クション構造）が形成されている。つまり、第２の半導
体層であるｎ層３と第３の半導体層であるｐ型リサーフ
層４が、それぞれ深さ方向（縦方向）に形成されるとと
もに深さ方向とは直交する方向（横方向）の面内で交互
に繰り返すように形成されている。このように、ドリフ
ト層は、スーパージャンクション構造とｎ−層２の二つ
の領域で形成されている。In this power MOSFET, a vertical RESURF structure (super junction structure) is formed on one surface of an n-type drift layer (hereinafter referred to as an n-layer) 2 which is a first semiconductor layer. ing. That is, the n-layer 3 that is the second semiconductor layer and the p-type RESURF layer 4 that is the third semiconductor layer are formed in the depth direction (vertical direction), respectively, and at the same time (in the horizontal direction). Direction) in a plane. Thus, the drift layer is formed of two regions, the super junction structure and the n− layer 2.
【００１８】前記ｎ−層２の他方の表面には、高濃度半
導体層であるｎ＋型ドレイン層１が形成され、このｎ＋
型ドレイン層１上には第１の主電極としてドレイン電極
５が形成されている。On the other surface of the n-layer 2, an n + type drain layer 1 which is a high concentration semiconductor layer is formed.
A drain electrode 5 is formed on the mold drain layer 1 as a first main electrode.
【００１９】なお、前記ｎ−層２とｎ＋型ドレイン層１
の形成方法は、ｎ−層２の片面に不純物拡散をして形成
しても、ｎ＋型ドレイン層１を基板としてｎ−層２を結
晶成長しても良い。The n-layer 2 and the n + type drain layer 1
The method of forming the n-layer 2 may be formed by diffusing impurities on one surface of the n-layer 2, or the n-layer 2 may be crystal-grown using the n + type drain layer 1 as a substrate.
【００２０】前記スーパージャンクション構造の表面に
は、第４の半導体層であるｐ型ベース層６が選択的（横
方向に周期的、平面ストライプ形状）に形成され、この
ｐ型ベース層６の表面には第５の半導体層であるｎ＋型
ソース層７が選択的、且つ、平面ストライプ形状に拡散
形成されている。この場合、ｐ型ベース層６の中央部の
下部に前記ｐ型リサーフ層４が形成されている。On the surface of the super junction structure, a p-type base layer 6 which is a fourth semiconductor layer is selectively formed (periodically in the lateral direction, in a plane stripe shape), and the surface of the p-type base layer 6 is formed. The n + type source layer 7 which is the fifth semiconductor layer is selectively diffused in a plane stripe shape. In this case, the p-type RESURF layer 4 is formed below the central portion of the p-type base layer 6.
【００２１】ここで、ｐ型ベース層６は、一例として、
約３×１０17ｃｍ-3の不純物濃度で、約２．０μｍの深
さに形成され、ｎ＋型ソース層７は、一例として、約１
×１０20ｃｍ-3の不純物濃度で、約０．２μｍの深さに
形成されている。Here, the p-type base layer 6 is, for example,
The n + type source layer 7 is formed with an impurity concentration of about 3 × 10 17 cm −3 to a depth of about 2.0 μm.
The impurity concentration is × 10 20 cm -3 and the depth is about 0.2 μm.
【００２２】さらに、ｎ＋型ソース層７およびｐ型ベー
ス層６からｎ層３を介して隣りのｐ型ベース層６および
ｎ＋型ソース層７に至る領域上、つまり、横方向に隣り
合うｎ＋型ソース層７相互間でｐ型ベース層６の表面上
およびｎ層３の表面上に、膜厚約０．１μｍのゲート絶
縁膜（例えばＳｉ酸化膜）９を介して第１の制御電極と
してゲート電極１０が平面ストライプ形状に形成されて
いる。Further, on the region extending from the n + type source layer 7 and the p type base layer 6 to the adjacent p type base layer 6 and the n + type source layer 7 through the n layer 3, that is, the n + type adjacent in the lateral direction. A gate as a first control electrode is formed between the source layers 7 on the surface of the p-type base layer 6 and the surface of the n layer 3 with a gate insulating film (for example, a Si oxide film) 9 having a film thickness of about 0.1 μm interposed. The electrode 10 is formed in a plane stripe shape.
【００２３】また、ゲート絶縁膜９を介してゲート電極
１０を両側から挟み、ｐ型ベース層６およびｎ＋型ソー
ス層７の表面に接合するように第２の主電極としてソー
ス電極８が平面ストライプ形状に形成されている。Further, the source electrode 8 as a second main electrode is a planar stripe so as to sandwich the gate electrode 10 from both sides with the gate insulating film 9 interposed therebetween and to be bonded to the surfaces of the p-type base layer 6 and the n + type source layer 7. It is formed in a shape.
【００２４】６００Ｖ系素子の設計の一例として、ｎ＋
型ドレイン層１は、不純物濃度が約６×１０18ｃｍ-3、
厚さが２００μｍ、ｎ−型層２は、不純物濃度５×１０
14ｃｍ-3、厚さ２６μｍとする。As an example of the design of a 600V system element, n +
The type drain layer 1 has an impurity concentration of about 6 × 10 18 cm −3 ,
The thickness of the n − type layer 2 is 200 μm, and the impurity concentration is 5 × 10 5.
The thickness is 14 cm −3 and the thickness is 26 μm.
【００２５】また、スーパージャンクション構造を形成
するｎ層３とｐ型リサーフ層４は、不純物濃度２×１０
15ｃｍ-3、厚さ２０μｍ、幅８μｍとする。この設計例
では、スーパージャンクション部とｎ−層２部でそれぞ
れ３００Ｖづつの耐圧を分担している。ｎ−層２の厚さ
を厚くすれば、ｎ−層２での耐圧分担は多くなり、オン
抵抗は増加し、ｎ−層２の厚さを薄くすれば、オン抵抗
は低くなる。The n layer 3 and the p-type RESURF layer 4 forming the super junction structure have an impurity concentration of 2 × 10.
The thickness is 15 cm −3 , the thickness is 20 μm, and the width is 8 μm. In this design example, the breakdown voltage of 300 V is shared by the super junction part and the n− layer 2 part. When the thickness of the n-layer 2 is increased, the breakdown voltage sharing in the n-layer 2 is increased and the on-resistance is increased, and when the thickness of the n-layer 2 is decreased, the on-resistance is decreased.
【００２６】図２は、図１中のｎ−層２の厚さLn- とド
リフト層全体の厚さ(Lsj+Ln-) の比Ln-/(Lsj+Ln-) に対
するオン抵抗Ron の変化を示す。FIG. 2 shows changes in the on-resistance Ron with respect to the ratio Ln-/ (Lsj + Ln-) of the thickness Ln- of the n-layer 2 and the total thickness (Lsj + Ln-) of the drift layer in FIG. Indicates.
【００２７】図３は、図１中のｎ−層２の厚さLn- がド
リフト層全体の厚さ(Lsj+Ln-) の比Ln-/(Lsj+Ln-) に占
める割合が変化した場合の内蔵ダイオード逆回復特性を
示す。FIG. 3 shows that the ratio of the thickness Ln- of the n-layer 2 in FIG. 1 to the ratio Ln-/ (Lsj + Ln-) of the total thickness (Lsj + Ln-) of the drift layer changes. The reverse recovery characteristics of the built-in diode in the case of
【００２８】図２において、厚さの比Ln-/(Lsj+Ln-) が
零ならば、ドリフト層の全てがスーパージャンクション
構造であることとなり、厚さの比Ln-/(Lsj+Ln-) が１な
らば、通常のＭＯＳＦＥＴ構造である。In FIG. 2, if the thickness ratio Ln-/ (Lsj + Ln-) is zero, it means that all of the drift layers have a super junction structure, and the thickness ratio Ln-/ (Lsj + Ln-). ) Is 1, it is a normal MOSFET structure.
【００２９】図３において、スーパージャンクション構
造の場合の逆回復特性は、電流が急激に零となるハード
なリカバリー波形になっているのに対して、通常のＭＯ
Ｓ構造では緩やかに電流が減少するソフトなリカバリー
波形になっている。In FIG. 3, the reverse recovery characteristic in the case of the super junction structure has a hard recovery waveform in which the current suddenly becomes zero, whereas the normal MO
The S structure has a soft recovery waveform in which the current gradually decreases.
【００３０】図２に示すように、厚さの比Ln-/(Lsj+Ln
-) が小さいほどオン抵抗Ron は低くなる。つまり、オ
ン抵抗Ron のみに注目すると、ｎ−層２の占める割合を
小さくする程良い。As shown in FIG. 2, the thickness ratio Ln-/ (Lsj + Ln
The lower the-), the lower the on-resistance Ron. That is, if attention is paid only to the on-resistance Ron, it is better to reduce the proportion occupied by the n − layer 2.
【００３１】しかし、図３に示すように、内蔵ダイオー
ドの逆回復特性は、ｎ−層２の占める割合が大きいほ
ど、通常のＭＯＳ構造の場合の特性に近づき、ソフトな
リカバリー波形となる。However, as shown in FIG. 3, the reverse recovery characteristic of the built-in diode becomes closer to the characteristic of the normal MOS structure as the ratio of the n-layer 2 increases, and becomes a soft recovery waveform.
【００３２】図４は、図１中のｎ−層２の厚さLn- がド
リフト層全体の厚さ(Lsj+Ln-) の比Ln-/(Lsj+Ln-) に占
める割合が変化した場合の図３に示した逆回復時電流特
性（ソフトなリカバリー波形）の傾斜の変化を示す。FIG. 4 shows that the ratio of the thickness Ln- of the n-layer 2 in FIG. 1 to the ratio Ln-/ (Lsj + Ln-) of the total thickness (Lsj + Ln-) of the drift layer changes. In the case of FIG. 3, the change of the inclination of the reverse recovery current characteristic (soft recovery waveform) shown in FIG.
【００３３】ｎ−層２の厚さLn- が占める割合が０．２
１を越えると、スーパージャンクション構造のみのＭＯ
ＳＦＥＴよりも逆回復電流の傾斜が小さくなり、ｎ−層
２の厚さLn- が占める割合が０．８程度で通常のＭＯＳ
ＦＥＴとほぼ同等なる。The ratio of the thickness Ln- of the n-layer 2 is 0.2.
If it exceeds 1, MO with super junction structure only
The slope of the reverse recovery current is smaller than that of the SFET, and the ratio of the thickness Ln- of the n- layer 2 is about 0.8.
It is almost the same as FET.
【００３４】これより、オン抵抗Ron を下げつつ、ソフ
トなリカバリー波形となる内蔵ダイオードの実現には、
ｎ−層２の厚さLn- の割合を０．２１から０．８の範囲
内とすることが望ましい。From this, in order to realize a built-in diode having a soft recovery waveform while lowering the on-resistance Ron,
It is desirable that the ratio of the thickness Ln- of the n-layer 2 be within the range of 0.21 to 0.8.
【００３５】また、本実施形態のようなｎ−層２の挿入
は、順方向安全動作領域の拡大にも効果があることにつ
いて、以下に説明する。Further, it will be described below that the insertion of the n-layer 2 as in this embodiment is also effective in expanding the forward safe operation area.
【００３６】図５は、図１に示したパワーＭＯＳＦＥＴ
のゲート電圧Vgを閾値電圧Vth ＋3Vとした場合の電流−
電圧特性を示す。FIG. 5 shows the power MOSFET shown in FIG.
Current when the gate voltage Vg of the threshold voltage is Vth + 3V −
The voltage characteristics are shown.
【００３７】スーパージャンクション構造のＭＯＳＦＥ
Ｔでは６００Ｖ程度で電流が急激に増加するのに対し
て、通常のＭＯＳＦＥＴでは７００Ｖ程度で電流が増加
し、通常のＭＯＳ構造の方が安全動作領域は１００Ｖ程
度広い。この理由は、高電圧印加時のドレイン近傍の層
電界が、スーパージャンクション構造では通常のＭＯＳ
ＦＥＴ構造に比べて高くなるからである。Superjunction structure MOSFE
In T, the current sharply increases at about 600V, whereas in the normal MOSFET, the current increases at about 700V, and the safe operation area of the normal MOS structure is wider by about 100V. The reason for this is that the layer electric field near the drain when a high voltage is applied is a normal MOS in the super junction structure.
This is because the cost is higher than that of the FET structure.
【００３８】ｎ−層２を挿入することにより、高電圧印
加時のドレイン近傍の層電界を減少することができるの
で、安全動作領域を広げることが可能となる。ｎ−層２
が占める割合を多くすると、通常のＭＯＳ構造に近づ
き、安全動作領域は広がっていく。By inserting the n-layer 2, the layer electric field in the vicinity of the drain when a high voltage is applied can be reduced, so that the safe operation area can be widened. n-layer 2
When the ratio occupied by is increased, it approaches a normal MOS structure and the safe operation area is expanded.
【００３９】また、本実施形態のようなｎ−層２の挿入
は、製造上も効果があることについて、以下に説明す
る。The fact that the insertion of the n-layer 2 as in this embodiment is also effective in manufacturing will be described below.
【００４０】ｎ−層２が占める割合が多い程、複雑な構
造であるスーパージャンクション構造の厚さが減るの
で、製造も容易となる。例えば、スーパージャンクショ
ン構造の厚みが同じであってｎ−層２の厚みの違うウェ
ハを用意すれば、異なる耐圧の素子を同じ製造工程で実
現することが可能となる。As the proportion of the n-layer 2 increases, the thickness of the super junction structure, which is a complicated structure, decreases, and the manufacturing becomes easier. For example, if wafers having the same superjunction structure and different n-layer 2 thicknesses are prepared, it becomes possible to realize devices having different breakdown voltages in the same manufacturing process.
【００４１】即ち、本実施形態のパワーＭＯＳＦＥＴに
よれば、スーパージャンクション構造の一部をなすｎ層
３の不純物濃度よりも、スーパージャンクション構造の
下層のｎ−層２の不純物濃度が低い。これにより、ドレ
イン電極５とソース電極８との間に高電圧を加えた時に
は、スーパージャンクション構造をなすｎ層３とｐ型リ
サーフ層４が完全に空乏化した後も、空乏層がｎ−層２
内に徐々に伸びるので、内蔵ダイオードの逆回復特性を
通常ダイオードに近いソフトな特性に近づけることが可
能となる。That is, according to the power MOSFET of this embodiment, the impurity concentration of the n − layer 2 below the super junction structure is lower than the impurity concentration of the n layer 3 forming a part of the super junction structure. As a result, when a high voltage is applied between the drain electrode 5 and the source electrode 8, even after the n layer 3 and the p-type RESURF layer 4 forming the super junction structure are completely depleted, the depletion layer is an n-layer. Two
Since it gradually extends inward, the reverse recovery characteristic of the built-in diode can be approximated to a soft characteristic close to that of a normal diode.
【００４２】＜第２の実施形態＞図６（ａ）乃至（ｄ）
は、本発明の第２の実施形態に係るパワーＭＯＳＦＥＴ
の断面構造の一部とドリフト層深さ方向における不純物
プロファイルと高電圧印加時の電界強度分布を示してい
る。<Second Embodiment> FIGS. 6A to 6D.
Is a power MOSFET according to the second embodiment of the present invention.
7 shows a part of the cross-sectional structure of the semiconductor device, an impurity profile in the depth direction of the drift layer, and an electric field intensity distribution when a high voltage is applied.
【００４３】図６（ａ）に示す第２の実施形態に係るパ
ワーＭＯＳＦＥＴにおいても、図１に示した第１の実施
形態に係るパワーＭＯＳＦＥＴと同様に、ドリフト層は
スーパージャンクション構造とｎ−層２の二つの領域で
形成されている。Also in the power MOSFET according to the second embodiment shown in FIG. 6A, as in the power MOSFET according to the first embodiment shown in FIG. 1, the drift layer has a super junction structure and an n-layer. It is formed by two regions of 2.
【００４４】そして、ドリフト層の不純物濃度は、第１
の実施形態に係るパワーＭＯＳＦＥＴと同様に、例えば
図６（ｂ）に示すように、ｎ−層２よりもスーパージャ
ンクション構造部の方が高くなっている。The impurity concentration of the drift layer is the first
Similar to the power MOSFET according to the embodiment, the super junction structure portion is higher than the n − layer 2 as shown in FIG. 6B, for example.
【００４５】スーパージャンクション構造とｎ−層２と
では電界強度分布が異なる。スーパージャンクション構
造では、低電圧で完全に空乏化してしまうので、等価的
に不純物濃度が低い層となり、電界強度分布は平坦とな
る。The electric field intensity distribution is different between the super junction structure and the n-layer 2. Since the super junction structure is completely depleted at a low voltage, the layer equivalently has a low impurity concentration and the electric field intensity distribution becomes flat.
【００４６】これに対して、ｎ−層２では、空乏化がス
ーパージャンクション構造側から徐々に進むので、電界
強度は傾斜する。この場合、ｎ−層２の不純物濃度が低
ければ、ｎ−層２の空乏化が速やかに起こるので、ｎ−
層２の電界強度分布はスーパージャンクション構造部と
同様に平坦に近くなる。これに対して、ｎ−層２の不純
物濃度が高ければ、ｎ−層２の空乏化が進まなくなるの
で、ｎ−層２の電界強度分布の傾斜がきつくなる。On the other hand, in the n-layer 2, the depletion gradually progresses from the side of the super junction structure, so that the electric field strength is inclined. In this case, if the impurity concentration of the n-layer 2 is low, depletion of the n-layer 2 occurs quickly, so that n-
The electric field intensity distribution of the layer 2 becomes nearly flat as in the super junction structure portion. On the other hand, if the impurity concentration of the n-layer 2 is high, depletion of the n-layer 2 does not proceed, so that the gradient of the electric field intensity distribution of the n-layer 2 becomes sharp.
【００４７】内蔵ダイオードの逆回復特性をソフトなリ
カバリー波形にするためには、通常のＭＯＳＦＥＴと同
様に、ｎ−層２の空乏化が徐々に進むようにｎ−層２の
濃度を設計する必要がある。In order to make the reverse recovery characteristic of the built-in diode a soft recovery waveform, it is necessary to design the concentration of the n-layer 2 so that the depletion of the n-layer 2 proceeds gradually as in the case of a normal MOSFET. There is.
【００４８】この場合、ｎ−層２の濃度を低くしすぎる
と、空乏層がｎ＋層１にすぐに到達してしまうので、ｎ
−層２を挿入した効果がなく、ｎ−層２での抵抗が大き
くなり、オン抵抗Ron が増加してしまう。これに対し
て、ｎ−層２の不純物濃度を高くすると、空乏層が伸び
難くなるので、ｎ−層２を挿入した効果が薄くなるが、
オン抵抗Ron は低い。In this case, if the concentration of the n-layer 2 is too low, the depletion layer reaches the n + layer 1 immediately, so that n
There is no effect of inserting the layer 2, and the resistance in the n-layer 2 increases, and the on-resistance Ron increases. On the other hand, when the impurity concentration of the n-layer 2 is increased, the depletion layer becomes difficult to expand, so that the effect of inserting the n-layer 2 is reduced.
ON resistance Ron is low.
【００４９】６００Ｖ系素子の設計例を挙げると、スー
パージャンクション部の厚さを１０μｍとし、ｎ−層２
の厚さを３９μｍ、ｎ−層２の不純物濃度を３．３×１
０14ｃｍ-3とすると、オン抵抗Ron は７２ｍΩｃｍ
2 （通常のＭＯＳＦＥＴより低い）となり、内蔵ダイオ
ードの特性は通常のＭＯＳＦＥＴとほぼ同様な特性を得
ることが可能である。To give an example of designing a 600V system element, the thickness of the super junction part is set to 10 μm, and the n-layer 2
Has a thickness of 39 μm, and the impurity concentration of the n− layer 2 is 3.3 × 1.
0 14 cm -3 , the on-resistance Ron is 72 mΩcm
2 (lower than that of a normal MOSFET), and the characteristics of the built-in diode can be almost the same as those of a normal MOSFET.
【００５０】また、スーパージャンクション部の厚さを
３０μｍとし、ｎ−層２の厚さを１３μｍ、ｎ−層２の
不純物濃度を１×１０15ｃｍ-3とすると、オン抵抗Ron
は３５ｍΩｃｍ2 となり、スーパージャンクションＭＯ
ＳＦＥＴとほぼ同等なオン抵抗Ron を保ちながら、内蔵
ダイオードのリカバリー特性をソフトにすることが可能
である。When the thickness of the super junction portion is 30 μm, the thickness of the n− layer 2 is 13 μm, and the impurity concentration of the n− layer 2 is 1 × 10 15 cm −3 , the on-resistance Ron is
Is 35 mΩcm 2 and Super Junction MO
It is possible to soften the recovery characteristics of the built-in diode while maintaining the on-resistance Ron almost equal to that of the SFET.
【００５１】オン抵抗Ron を低く保ちつつソフトなリカ
バリー波形を実現するには、ｎ−層２の不純物濃度とし
て、２つの主電極間に定格電圧を加えた時に図６（ｄ）
に示すようにドリフト層が完全に空乏化するように設定
することが望ましい。そして、素子耐圧をスーパージャ
ンクション構造とｎ−層２で分担する様に設計を行う。In order to realize a soft recovery waveform while keeping the on-resistance Ron low, the impurity concentration of the n-layer 2 is set as shown in FIG. 6 (d) when a rated voltage is applied between the two main electrodes.
It is desirable to set so that the drift layer is completely depleted as shown in FIG. The device breakdown voltage is designed to be shared by the super junction structure and the n − layer 2.
【００５２】ｎ−層２の部分の抵抗と耐圧の関係は通常
のＭＯＳＦＥＴのオン抵抗／耐圧トレードオフと同様で
あるので、ｎ−層２の最適な不純物濃度は、定格電圧を
印加した時にドリフト層が完全に空乏化する程度の不純
物濃度となる。そして、このような濃度とすれば、定格
電圧まで徐々に空乏化が進むので、内蔵ダイオードのリ
カバリー波形もソフトなものとなる。Since the relationship between the resistance and the breakdown voltage of the n-layer 2 is similar to the on-resistance / breakdown voltage trade-off of a normal MOSFET, the optimum impurity concentration of the n-layer 2 is drift when a rated voltage is applied. The impurity concentration is such that the layer is completely depleted. With such a concentration, depletion gradually progresses up to the rated voltage, so that the recovery waveform of the built-in diode becomes soft.
【００５３】なお、前記した定格電圧印加時にｎ−層２
が完全に空乏化していないことが望ましいが、通常、電
源電圧を定格電圧の半分程度として使用すると、素子に
は定格電圧の半分程度の電圧しか加わらないので、定格
電圧の半分が加わった時点でｎ−層２が完全に空乏化し
なければ、前記とほぼ同様の効果が得られる。When the rated voltage is applied, the n-layer 2
Is not completely depleted, but normally, when the power supply voltage is used as about half the rated voltage, only half the rated voltage is applied to the element, so when half the rated voltage is applied, If the n-layer 2 is not completely depleted, the same effect as described above can be obtained.
【００５４】また、ｎ−層２の裏面からの拡散によりｎ
＋層１を形成した場合やｎ−層２の表面からの拡散によ
りスーパージャンクション構造を形成した場合などに
は、ｎ−層２の不純物濃度の分布は、図６（ｂ）に示す
ような矩形状の分布でなく、図６（ｃ）に示すような緩
やかな分布となるが、不純物濃度の大小関係が、ｎ＋層
１＞スーパージャンクション部のｎ層３＞ｎ−層２とな
っていれば、前記とほぼ同様な効果が得られる。Further, the n-layer 2 is diffused from the back surface thereof to n.
When the + layer 1 is formed or when the super junction structure is formed by diffusion from the surface of the n− layer 2, the impurity concentration distribution of the n− layer 2 has a rectangular shape as shown in FIG. The distribution is not a shape distribution but a gentle distribution as shown in FIG. 6C. However, if the magnitude relation of the impurity concentrations is n + layer 1> n layer 3 of super junction part> n− layer 2, The same effect as described above can be obtained.
【００５５】この場合、スーパージャンクション構造の
ｐリサーフ層４との接合からｎ＋層１に近づいてスーパ
ージャンクション部と同等な不純物濃度まで上がったと
ころまでをｎ−層２の厚さとし、この厚さ部分の平均濃
度をｎ−層２の不純物濃度として設計すれば、ｎ−層２
の不純物濃度の分布を矩形状とした場合とほぼ同等の効
果が得られる。In this case, the thickness from the junction with the p-resurf layer 4 of the super junction structure to the point where the impurity concentration equivalent to that at the super junction portion is increased from the junction with the p RESURF layer 4 to the n + layer 1 is defined as this thickness portion. If the average concentration of n-layer 2 is designed as the impurity concentration of n-layer 2,
The same effect can be obtained as when the impurity concentration distribution is rectangular.
【００５６】＜第３の実施形態＞図７（Ａ）乃至（Ｆ）
は、本発明の第３の実施形態に係わるパワーＭＯＳＦＥ
Ｔの製造工程を模式的に示すプロセスフローである。<Third Embodiment> FIGS. 7A to 7F.
Is a power MOSFE according to the third embodiment of the present invention.
It is a process flow which shows the manufacturing process of T typically.
【００５７】ここでは、図１中と同一部分の詳しい説明
は省略し、異なる部分についてのみ説明する。ｎ＋基板
１上にｎ−層２とｎ層３が形成されたウェハ上に例えば
ボロンイオンの注入を行い、選択的にｐ層を形成する。
その後、ｐ層を埋め込むエピタキシャル成長を行い、再
度イオン注入により選択的にｐ層を形成する。そして、
先に埋め込まれたｐ層と上部のｐ層とを接続させるよう
にアニールにより拡散を行い、ｐリサーフ層４を形成す
る。その後、表面にＭＯＳ構造を形成するプロセスなど
を行い、図１に示した第１の実施形態に係るパワーＭＯ
ＳＦＥＴとほぼ同様の構造のＭＯＳＦＥＴを完成する。Here, detailed description of the same parts as those in FIG. 1 will be omitted, and only different parts will be described. Boron ions, for example, are implanted into the wafer in which the n− layer 2 and the n layer 3 are formed on the n + substrate 1 to selectively form the p layer.
After that, epitaxial growth is performed to embed the p layer, and the p layer is selectively formed by ion implantation again. And
Diffusion is performed by annealing so as to connect the previously buried p layer and the upper p layer, and the p RESURF layer 4 is formed. Then, a process of forming a MOS structure on the surface is performed, and the power MO according to the first embodiment shown in FIG.
A MOSFET having substantially the same structure as the SFET is completed.
【００５８】このような工程によりスーパージャンクシ
ョン構造を形成すると、不純物濃度が深さ方向に一定で
なく分布する。When the super junction structure is formed by such a process, the impurity concentration is not constant and distributed in the depth direction.
【００５９】なお、前記ｐ層の埋め込み工程を複数回繰
り返すことによりスーパージャンクション構造を厚くす
ることが可能である。また、ｎ＋基板１上にｎ−層２が
形成されたウェハ上に、ｐリサーフ層４と同様にイオン
注入によりｎ層３を形成することも可能である。The super junction structure can be thickened by repeating the step of filling the p layer a plurality of times. It is also possible to form the n layer 3 by ion implantation in the same manner as the p RESURF layer 4 on the wafer in which the n− layer 2 is formed on the n + substrate 1.
【００６０】＜第４の実施形態＞図８は、本発明の第４
の実施形態に係わるパワーＭＯＳＦＥＴの断面構造を模
式的に示したものである。<Fourth Embodiment> FIG. 8 shows a fourth embodiment of the present invention.
2 schematically shows the cross-sectional structure of the power MOSFET according to the embodiment of FIG.
【００６１】第４の実施形態に係るパワーＭＯＳＦＥＴ
は、図１に示した第１の実施形態に係るパワーＭＯＳＦ
ＥＴと比べて、スーパージャンクション構造の基本単位
となるｐリサーフ層４とｎ層３の間に絶縁物１１がｎ−
層２に達する深さで挿入されている点が異なり、ドリフ
ト層がスーパージャンクション構造とｎ−層２の二つの
領域で形成されているなどの基本構造は同じである。Power MOSFET According to Fourth Embodiment
Is a power MOSF according to the first embodiment shown in FIG.
Compared to ET, the insulator 11 is n− between the p RESURF layer 4 and the n layer 3 which are basic units of the super junction structure.
The basic structure is the same except that the drift layer is inserted at a depth reaching the layer 2, and the drift layer is formed of two regions of the super junction structure and the n− layer 2.
【００６２】図９（Ａ）乃至（Ｆ）は、図８の構造を形
成するプロセスフローを示す。FIGS. 9A-9F show the process flow for forming the structure of FIG.
【００６３】まず、ｎ＋基板１上にｎ−層２とｎ層３が
形成されたウェハ表面からエッチングを行ってトレンチ
溝を形成する。その後、斜め方向から例えばボロンイオ
ンの注入を行い、トレンチ溝側壁にｐリサーフ層４を形
成する。その後、トレンチ溝内を絶縁物１１で埋め込
み、表面にＭＯＳ構造を形成するプロセスなどを行い、
図８に示したパワーＭＯＳＦＥＴを完成する。First, a trench groove is formed by etching the surface of the wafer on which the n− layer 2 and the n layer 3 are formed on the n + substrate 1. After that, for example, boron ions are implanted from an oblique direction to form the p RESURF layer 4 on the side wall of the trench groove. Then, the trench groove is filled with an insulator 11, and a process of forming a MOS structure on the surface is performed.
The power MOSFET shown in FIG. 8 is completed.
【００６４】このような工程によりスーパージャンクシ
ョン構造を形成すると、絶縁物１１が横方向に周期的に
形成されているので、不純物濃度が横方向に一定でなく
分布する。なお、トレンチ溝の埋め込み材に低濃度半導
体もしくは、絶縁物と半導体を組み合わせても電気的に
問題はない。埋め込み材に用いる半導体は、単結晶半導
体でも多結晶半導体でもよい。When the super junction structure is formed by such a process, since the insulators 11 are periodically formed in the lateral direction, the impurity concentration is not uniformly distributed in the lateral direction. There is no electrical problem even if a low-concentration semiconductor or an insulator and a semiconductor are combined in the trench groove filling material. The semiconductor used for the filling material may be a single crystal semiconductor or a polycrystalline semiconductor.
【００６５】また、図８に示したパワーＭＯＳＦＥＴの
トレンチ溝は、ｎ−層２に到達する程度に形成されてい
るが、ｎ＋層１に到達する深さまで形成してもよい。Although the trench groove of the power MOSFET shown in FIG. 8 is formed to reach the n− layer 2, it may be formed to a depth reaching the n + layer 1.
【００６６】なお、ｎ＋基板１上にｎ−層２が形成され
たウェハ上に、ｐリサーフ層４と同様にイオン注入によ
りｎ層３を形成することも可能である。It is also possible to form the n layer 3 by ion implantation in the same manner as the p RESURF layer 4 on the wafer in which the n− layer 2 is formed on the n + substrate 1.
【００６７】＜第４の実施形態の変形例１＞図１０は、
本発明の第４の実施形態の変形例に係わるパワーＭＯＳ
ＦＥＴの断面構造を模式的に示したものである。<Modification 1 of Fourth Embodiment> FIG.
Power MOS According to Modification of Fourth Embodiment of the Present Invention
1 schematically shows a cross-sectional structure of an FET.
【００６８】このパワーＭＯＳＦＥＴは、図８に示した
第４の実施形態に係るパワーＭＯＳＦＥＴと比べて、絶
縁物１１が各ｐリサーフ層４の横方向中心部に形成され
ている点が異なり、その他の基本構造は同じである。This power MOSFET is different from the power MOSFET according to the fourth embodiment shown in FIG. 8 in that an insulator 11 is formed at the lateral center of each p RESURF layer 4, and the other points. Have the same basic structure.
【００６９】図１０に示す構造では、スーパージャンク
ション構造のセル幅が図８に示す構造の半分となり、ス
ーパージャンクション部のオン抵抗を半分とすることが
可能となる。In the structure shown in FIG. 10, the cell width of the super junction structure is half that of the structure shown in FIG. 8, and the ON resistance of the super junction portion can be halved.
【００７０】図１０の構造を形成するプロセスフロー
は、前述した図８の構造を形成するプロセスフローのう
ちで図９（Ｃ）に示したトレンチ溝側壁に対する斜め方
向からのイオン注入を、トレンチ溝側壁の両面に対応し
て両方向から行ってトレンチ溝側壁の両面にｐリサーフ
層４を形成するように変更すればよい。The process flow for forming the structure of FIG. 10 is the same as the process flow for forming the structure of FIG. 8 described above, except that the ion implantation from the oblique direction to the side wall of the trench groove shown in FIG. It may be changed so that the p RESURF layer 4 is formed on both sides of the trench groove side wall in both directions corresponding to both sides of the side wall.
【００７１】＜第４の実施形態の変形例２＞図９に示し
たプロセスフローにおいて、トレンチ溝を形成した後、
エピタキシャル成長によりｐリサーフ層４を溝内に形成
してスーパージャンクション構造を形成することも可能
である。ｐリサーフ層４の埋め込み成長を溝内が完全に
埋め込まれる前に止め、その後絶縁物で溝内を完全に埋
め込むことにより結晶成長界面を安定化させることも可
能である。<Modification 2 of Fourth Embodiment> In the process flow shown in FIG. 9, after forming the trench groove,
It is also possible to form the p-resurf layer 4 in the groove by epitaxial growth to form a super junction structure. It is possible to stabilize the crystal growth interface by stopping the buried growth of the p-resurf layer 4 before the groove is completely filled and then completely filling the groove with an insulator.
【００７２】また、斜め方向からのイオン注入とトレン
チ溝内の埋め込み成長を組み合わせたプロセスでもスー
パージャンクション構造は形成可能である。The super junction structure can also be formed by a process combining ion implantation from an oblique direction and burying growth in the trench groove.
【００７３】＜第５の実施形態＞図１１（ａ）乃至
（ｃ）は、本発明の第５の実施形態に係わるパワーＭＯ
ＳＦＥＴの断面構造の一部とドリフト層深さ方向におけ
る不純物プロファイルを示している。<Fifth Embodiment> FIGS. 11A to 11C show a power MO according to a fifth embodiment of the present invention.
The partial profile of the SFET and the impurity profile in the depth direction of the drift layer are shown.
【００７４】この実施形態に係るパワーＭＯＳＦＥＴ
は、図６に示した第２の実施形態に係るパワーＭＯＳＦ
ＥＴと比べて、スーパージャンクション構造の下層が二
段階の濃度のｎ−層２とｎ層２ａで構成されている（ｎ
−層２の下部がｎ層２ａとなっている）、つまり、ｎ−
層２とｎ層２ａとｎ＋ドレイン層１の不純物濃度が段階
的に変化している点が異なり、その他の構造は同じであ
る。Power MOSFET according to this embodiment
Is a power MOSF according to the second embodiment shown in FIG.
Compared with ET, the lower layer of the super junction structure is composed of n-layer 2 and n layer 2a having two-stage concentration (n
-The lower part of the layer 2 is the n-layer 2a), that is, n-
The other structures are the same, except that the impurity concentrations of the layer 2, the n layer 2a, and the n + drain layer 1 are changed stepwise.
【００７５】この場合、ｎ−層２の濃度は、スーパージ
ャンクション構造のｎ層３の濃度より低いことが望まし
く、ｎ層２ａの濃度は、ｎ−層２の濃度とｎ＋層１の濃
度との中間であって、スーパージャンクション構造のｎ
層３の濃度と同程度から３倍程度がよい。In this case, the concentration of the n− layer 2 is preferably lower than the concentration of the n layer 3 of the super junction structure, and the concentration of the n layer 2a is the concentration of the n− layer 2 and the concentration of the n + layer 1. N in the middle and having a super junction structure
The concentration is preferably about the same as the concentration of the layer 3 or about 3 times.
【００７６】このようにｎ層２ａを有することにより、
製造時に空乏層の広がる領域の制御が容易であり、か
つ、ｎ層２ａはｎ＋ドレイン層１に比べて濃度が低いの
で、内蔵ダイオードのリカバリー特性をソフトにするこ
とに寄与する。By thus having the n layer 2a,
It is easy to control the region where the depletion layer spreads during manufacturing, and the n layer 2a has a lower concentration than the n + drain layer 1, which contributes to softening the recovery characteristics of the built-in diode.
【００７７】なお、上記例では、スーパージャンクショ
ン構造の下層のｎ−層２の濃度を２段階に変化させた
が、それ以上の段階に変化させてもよく、また、不純物
濃度が徐々に変化していくように濃度勾配を持たせるよ
うにしてもよい。In the above example, the concentration of the lower n-layer 2 of the super junction structure is changed in two steps, but it may be changed in two or more steps, and the impurity concentration is gradually changed. You may make it give a density gradient so that it may go.
【００７８】＜第６の実施形態＞図１２（ａ）乃至
（ｃ）は、本発明の第６の実施形態に係わるパワーＭＯ
ＳＦＥＴの断面構造の一部とドリフト層深さ方向におけ
る不純物プロファイルを示している。<Sixth Embodiment> FIGS. 12A to 12C show a power MO according to a sixth embodiment of the present invention.
The partial profile of the SFET and the impurity profile in the depth direction of the drift layer are shown.
【００７９】この実施形態に係るパワーＭＯＳＦＥＴ
は、図６に示した第２の実施形態に係るパワーＭＯＳＦ
ＥＴと比べて、スーパージャンクション構造の下層が二
段階の濃度のｎ層２ａとｎ−層２で構成されている（ｎ
−層２の上部がｎ層２ａとなっている）、つまり、ｎ層
２ａとｎ−層２とｎ＋ドレイン層１の不純物濃度が段階
的に変化している点が異なり、その他の構造は同じであ
る。Power MOSFET According to This Embodiment
Is a power MOSF according to the second embodiment shown in FIG.
Compared with ET, the lower layer of the super junction structure is composed of n layer 2a and n- layer 2 having two-stage concentration (n
− The upper part of the layer 2 is the n layer 2a), that is, the impurity concentrations of the n layer 2a, the n− layer 2 and the n + drain layer 1 are changed stepwise, and the other structures are the same. Is.
【００８０】この場合、ｎ−層２の濃度は、スーパージ
ャンクション構造のｎ層３の濃度より低いことが望まし
く、ｎ層２ａの濃度は、ｎ−層２の濃度とｎ＋層１の濃
度との中間であって、スーパージャンクション構造のｎ
層３の濃度と同程度から３倍程度がよい。In this case, the concentration of the n− layer 2 is preferably lower than the concentration of the n layer 3 of the super junction structure, and the concentration of the n layer 2a is the concentration of the n− layer 2 and the concentration of the n + layer 1. N in the middle and having a super junction structure
The concentration is preferably about the same as the concentration of the layer 3 or 3 times.
【００８１】このようにｎ層２ａを有することにより、
スーパージャンクション構造部より広がる空乏層がｎ層
２ａへ広がり難くなる。そして、ｎ層２ａの下部のｎ−
層２を緩やかに空乏化させることができるので、内蔵ダ
イオードのリカバリー特性をソフトにすることに寄与す
る。By having the n layer 2a in this way,
It is difficult for the depletion layer that spreads from the super junction structure to spread to the n layer 2a. Then, n− under the n layer 2a
Since the layer 2 can be depleted gently, it contributes to softening the recovery characteristic of the built-in diode.
【００８２】なお、上記例では、スーパージャンクショ
ン構造の下層のｎ−層２の濃度を２段階に変化させた
が、それ以上の段階に変化させてもよく、また、不純物
濃度が徐々に変化していくように濃度勾配を持たせるよ
うにしてもよい。In the above example, the concentration of the n-layer 2 which is the lower layer of the super junction structure is changed in two steps, but it may be changed in two or more steps, and the impurity concentration is gradually changed. You may make it give a density gradient so that it may go.
【００８３】＜第７の実施形態＞図１３は、本発明の第
７の実施形態に係わるパワーＭＯＳＦＥＴの断面構造を
模式的に示したものである。<Seventh Embodiment> FIG. 13 schematically shows a sectional structure of a power MOSFET according to a seventh embodiment of the present invention.
【００８４】この実施形態に係るパワーＭＯＳＦＥＴ
は、図１に示した第１の実施形態に係るパワーＭＯＳＦ
ＥＴと比べて、ｎ−層２の下部に、ｎ−層２より不純物
濃度が高いｎ＋層１７が横方向に間欠的に配置されてい
る、つまり、ｎ−層２の下部に、ｎ−層２およびｎ＋層
１７が横方向に交互に配置されており、ｎ＋層１７はｎ
＋ドレイン層１と高濃度で接している点が異なり、その
他の構造は同じである。Power MOSFET according to this embodiment
Is a power MOSF according to the first embodiment shown in FIG.
An n + layer 17 having an impurity concentration higher than that of the n− layer 2 is intermittently arranged in the lateral direction below the n− layer 2, that is, below the n− layer 2, that is, below the n− layer 2, an n− layer is formed. 2 and n + layers 17 are alternately arranged in the lateral direction, and the n + layers 17 are n
The difference is that the + drain layer 1 is in high-concentration contact, and the other structures are the same.
【００８５】このようにｎ＋層１７を有することによ
り、ｎ−層２とｎ＋ドレイン層１との界面領域に凹凸形
状が設けられ、凹部には内蔵ダイオードのリカバリー電
流に寄与する正孔キャリアが多く蓄積され、逆回復後に
緩やかに空乏層を流れるようになるので、リカバリー特
性をソフトにすることが可能になる。また、ｎ−層２の
厚さが同じ場合には、その深さ方向に占めるｎ＋層１７
の割合が大きい方が、オン抵抗を低くすることが可能に
なる。Since the n + layer 17 is provided in this manner, a concavo-convex shape is provided in the interface region between the n- layer 2 and the n + drain layer 1, and many hole carriers that contribute to the recovery current of the built-in diode are present in the recess. It is accumulated and gradually flows through the depletion layer after reverse recovery, so that the recovery characteristic can be softened. If the n− layer 2 has the same thickness, the n + layer 17 occupies the depth direction thereof.
The higher the ratio of, the lower the on-resistance can be.
【００８６】図１４（Ａ）乃至（Ｄ）は、図１３の構造
を形成するプロセスフローを示す。FIGS. 14A-14D show a process flow for forming the structure of FIG.
【００８７】ｎ＋基板１上にｎ−層２が形成されたウェ
ハ上に例えばリンイオンの注入を行い、選択的にｎ＋層
を形成する。その後、上記ｎ＋層を埋め込むエピタキシ
ャル成長を行い、アニール処理を行ってｎ＋基板１と接
続させることにより、ｎ＋層１７が形成される。この
後、第３の実施形態あるいは第４の実施形態で示したよ
うなプロセスフローを用いることにより、ウェハ表面に
スーパージャンクション構造を形成し、さらに、ＭＯＳ
構造を形成するプロセスなどを行い、図１３に示した第
７の実施形態に係るパワーＭＯＳＦＥＴを完成する。For example, phosphorus ions are implanted into the wafer having the n-layer 2 formed on the n + substrate 1 to selectively form the n + layer. After that, epitaxial growth for embedding the n + layer is performed, and annealing treatment is performed to connect to the n + substrate 1, whereby the n + layer 17 is formed. After that, a super junction structure is formed on the wafer surface by using the process flow as shown in the third embodiment or the fourth embodiment.
A process of forming a structure and the like are performed to complete the power MOSFET according to the seventh embodiment shown in FIG.
【００８８】なお、ｎ−層２とｎ＋層１７を横方向に交
互に配置して形成する工程は、上記例に限らず、ｎ＋基
板１に選択的にトレンチ溝を形成し、それにｎ−層を埋
め込むようにしても可能である。The step of alternately arranging the n-layer 2 and the n + layer 17 in the lateral direction is not limited to the above example, but a trench groove is selectively formed in the n + substrate 1 and the n- layer is formed therein. It is also possible to embed.
【００８９】また、ｎ＋層１７を横方向に配置する周期
は、スーパージャンクション構造の周期と同じでなくて
もよく、ｎ＋層１７の横方向の幅もスーパージャンクシ
ョン構造のピッチと無関係でもよい。Further, the cycle of arranging the n + layers 17 in the lateral direction need not be the same as the cycle of the super junction structure, and the lateral width of the n + layers 17 may be independent of the pitch of the super junction structure.
【００９０】＜第８の実施形態＞図１５は、本発明の第
８の実施形態に係わるパワーＭＯＳＦＥＴの構成を模式
的に示す断面図である。<Eighth Embodiment> FIG. 15 is a sectional view schematically showing the structure of a power MOSFET according to an eighth embodiment of the present invention.
【００９１】このＭＯＳＦＥＴは、素子中央部は前記各
実施形態に係わるパワーＭＯＳＦＥＴと同様に形成され
ており、素子終端部は、素子中央部と同様にスーパージ
ャンクション構造が形成され、その上に絶縁膜１２を介
して金属もしくは導電性膜からなるフィールドプレート
１３が形成された構造を有する。そして、素子最外周に
は、空乏化を止めるフィールドストッパｎ層１４が形成
されている。In this MOSFET, the central portion of the element is formed in the same manner as the power MOSFET according to each of the above-mentioned embodiments, and the element termination portion is formed with a super junction structure as in the central portion of the element, and an insulating film is formed thereon. It has a structure in which a field plate 13 made of a metal or a conductive film is formed via 12 A field stopper n layer 14 that stops depletion is formed on the outermost periphery of the element.
【００９２】このような構成によれば、高電圧印加時に
は、フィールドプレート１３の作用により、素子終端部
のスーパージャンクション構造部が速やかに空乏化して
等価的に低不純物濃度層となるので、素子終端部の電界
集中が抑制され、耐圧が保持される。また、終端部表面
にリサーフ層４を形成しても、フィールドプレート１３
と同様にスーパージャンクション部が速やかに空乏化
し、上記と同様な効果が得られる。With such a structure, when a high voltage is applied, the superjunction structure portion of the element termination portion is quickly depleted by the action of the field plate 13 to become an equivalently low impurity concentration layer. The electric field concentration in the area is suppressed and the breakdown voltage is maintained. Even if the RESURF layer 4 is formed on the surface of the end portion, the field plate 13
Similar to the above, the super junction portion is quickly depleted, and the same effect as above can be obtained.
【００９３】＜第９の実施形態＞図１６は、本発明の第
９の実施形態に係わるパワーＭＯＳＦＥＴの構成を模式
的に示す断面図である。<Ninth Embodiment> FIG. 16 is a sectional view schematically showing the structure of a power MOSFET according to a ninth embodiment of the present invention.
【００９４】このＭＯＳＦＥＴは、素子中央部は前記各
実施形態に係わるパワーＭＯＳＦＥＴと同様に形成され
ており、素子終端部は、スーパージャンクション構造が
形成されないでｎ−層１５が形成されており、その表面
にはガードリング１６が形成されている。In this MOSFET, the central part of the element is formed in the same manner as the power MOSFET according to each of the above-mentioned embodiments, and the n-layer 15 is formed in the terminal part of the element without forming the super junction structure. A guard ring 16 is formed on the surface.
【００９５】このような構成によれば、ｎ−層１５の不
純物濃度を充分に低く設定することにより、横方向の電
界が緩和され、素子終端部での耐圧低下が抑制される。
ｎ−層１５を速やかに空乏化させるためには、その不純
物濃度をｎ−層２の不純物濃度よりも低くすることが望
ましい。According to such a structure, by setting the impurity concentration of n − layer 15 to be sufficiently low, the electric field in the lateral direction is alleviated and the breakdown voltage at the element termination portion is suppressed.
In order to quickly deplete n-layer 15, it is desirable that its impurity concentration be lower than that of n-layer 2.
【００９６】＜第１０の実施形態＞図１７は、本発明の
第１０の実施形態に係わるパワーＭＯＳＦＥＴの構成を
模式的に示す断面図である。<Tenth Embodiment> FIG. 17 is a sectional view schematically showing a structure of a power MOSFET according to a tenth embodiment of the present invention.
【００９７】このＭＯＳＦＥＴは、横型素子にスーパー
ジャンクション構造を適用したものである。図１７にお
いて、ｎ＋ドレイン層１上に低不純物濃度層１５が形成
され、この低不純物濃度層１５の表面に選択的（横方向
に周期的）にｐ型リサーフ層４およびｎ−ドリフト層２
が形成されている。This MOSFET is a lateral device to which a super junction structure is applied. 17, a low impurity concentration layer 15 is formed on the n + drain layer 1, and the p-type RESURF layer 4 and the n− drift layer 2 are selectively (laterally periodically) formed on the surface of the low impurity concentration layer 15.
Are formed.
【００９８】前記ｐ型リサーフ層４の表面にｎ層３が形
成されることによりスーパージャンクション構造が形成
されている。このスーパージャンクション構造の表面に
は、ｐ型ベース層６が選択的に形成され、このｐ型ベー
ス層６の表面にはｎ＋型ソース層７が選択的に拡散形成
されている。A super junction structure is formed by forming the n layer 3 on the surface of the p-type RESURF layer 4. A p-type base layer 6 is selectively formed on the surface of this super junction structure, and an n + -type source layer 7 is selectively diffused on the surface of this p-type base layer 6.
【００９９】さらに、ｎ＋型ソース層７からｐ型ベース
層６を介してｎ層３に至る表面上にはゲート絶縁膜９を
介して第１の制御電極としてゲート電極１０が形成され
ている。Further, a gate electrode 10 is formed as a first control electrode via the gate insulating film 9 on the surface from the n + type source layer 7 to the n layer 3 via the p type base layer 6.
【０１００】また、ｎ＋ドレイン層１の表面に接合する
ように、前記ゲート電極１０との間の領域（ｎ層３の表
面の一部からｎ＋ドレイン層１の表面の一部に至る領
域）に絶縁膜９ａを介して第１の主電極としてドレイン
電極５が形成されている。Further, in a region between the gate electrode 10 and a region (a region from a part of the surface of the n layer 3 to a part of the surface of the n + drain layer 1) so as to be bonded to the surface of the n + drain layer 1. A drain electrode 5 is formed as a first main electrode via the insulating film 9a.
【０１０１】また、ｐ型ベース層６およびｎ＋型ソース
層７の表面に接合するように、前記ゲート電極１０との
間にゲート絶縁膜９を介して第２の主電極としてソース
電極８が形成されている。A source electrode 8 is formed as a second main electrode so as to be bonded to the surfaces of the p-type base layer 6 and the n + -type source layer 7 with the gate insulating film 9 interposed between the source electrode 8 and the gate electrode 10. Has been done.
【０１０２】上記したように横型素子にドリフト層にス
ーパージャンクション構造を用いた場合にも、縦型素子
と同様にオン抵抗を低減できるが、内蔵ダイオードのリ
カバリー特性がハードとなる。そこで、ｎ＋ドレイン層
１とスーパージャンクション構造の間にｎ−層２を挿入
することで、低オン抵抗を保ちつつ、ソフトなリカバリ
ー特性とすることが可能となる。As described above, even when the super junction structure is used for the drift layer in the lateral element, the on resistance can be reduced as in the vertical element, but the recovery characteristic of the built-in diode becomes hard. Therefore, by inserting the n− layer 2 between the n + drain layer 1 and the superjunction structure, it becomes possible to obtain a soft recovery characteristic while maintaining low on-resistance.
【０１０３】図１７では、スーパージャンクション構造
のｐ／ｎセルを１段で形成しているが、２段以上で形成
して実施することも可能である。また、図１７では、ス
ーパージャンクション構造のｐ／ｎセルを積層して形成
しているが、ｐ／ｎセルを平面方向に形成して実施する
ことも可能である。In FIG. 17, the p / n cell of the super junction structure is formed in one stage, but it is also possible to form it in two or more stages. Further, in FIG. 17, p / n cells having a super junction structure are formed by stacking, but it is also possible to form and implement the p / n cells in the plane direction.
【０１０４】また、図１７では、ｎ＋ドレイン層１をウ
ェハ下部に形成しているが、ｎ＋ドレイン層１は無くと
も実施可能である。また、ウェハをＳＯＩ（Silicon on
insulator）ウェハとしても実施可能であり、この場合
は、低不純物濃度層１５が不要となる。Further, in FIG. 17, the n + drain layer 1 is formed in the lower part of the wafer, but it can be implemented without the n + drain layer 1. In addition, the wafer is SOI (Silicon on
It can also be implemented as an (insulator) wafer, and in this case, the low impurity concentration layer 15 becomes unnecessary.
【０１０５】また、ＭＯＳゲート構造をトレンチゲート
とし、スーパージャンクション構造を複数段積み重ねる
ことで層面積を増やすことにより、オン抵抗を低減する
ことが可能となる。Further, the on-resistance can be reduced by increasing the layer area by stacking a plurality of superjunction structures with a trench gate as the MOS gate structure.
【０１０６】なお、本発明は前記各実施形態に限定され
るものではなく、各種の変形実施が可能である。即ち、
第１の導電型をｐ型、第２の導電型をｎ型としても実施
することも可能である。The present invention is not limited to the above-mentioned embodiments, and various modifications can be made. That is,
The first conductivity type may be p-type and the second conductivity type may be n-type.
【０１０７】また、縦型リサーフ構造のｐ層の平面パタ
ーンは、前記ストライプ状に限らず、格子状や千鳥状に
形成してもよい。また、ｐ型ベース層およびｎ＋型ソー
ス層の平面パターンも、前記ストライプ状に限らず、格
子状および千鳥状に形成してもよく、ストライプ状に形
成する場合には、スーパージャンクション構造と平行に
限らず、直交するように形成してもよい。また、ＭＯＳ
ゲート構造は、前記プレナー構造に限らず、トレンチ構
造でも実施可能である。Further, the plane pattern of the p layer of the vertical RESURF structure is not limited to the stripe shape, but may be formed in a lattice shape or a zigzag shape. Further, the plane patterns of the p-type base layer and the n + -type source layer are not limited to the stripe shape, but may be formed in a lattice shape or a zigzag shape. In the case of forming the stripe shape, the plane pattern is parallel to the super junction structure. Not limited to this, they may be formed so as to be orthogonal to each other. Also, MOS
The gate structure is not limited to the planar structure, but may be a trench structure.
【０１０８】また、前記各実施形態では半導体としてシ
リコン（Ｓｉ）を用いたＭＯＳＦＥＴを説明したが、半
導体としては、例えばシリコンカーバイト（ＳｉＣ）や
窒化ガリウム（ＧａＮ）等の化合物半導体を用いること
ができる。In each of the above embodiments, the MOSFET using silicon (Si) as the semiconductor has been described. However, as the semiconductor, a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN) may be used. it can.
【０１０９】また、前記各実施形態ではスーパージャン
クション構造を有するＭＯＳＦＥＴで説明したが、縦型
リサーフ構造を有する素子であれば、ＳＢＤやＳＩＴ、
ＩＧＢＴなどの素子でも本発明を適用可能である。In each of the above embodiments, the MOSFET having the super junction structure has been described, but if the device has the vertical RESURF structure, the SBD, SIT,
The present invention can be applied to an element such as an IGBT.
【０１１０】[0110]
【発明の効果】上述したように本発明の電力用半導体素
子によれば、低オン抵抗を保持しつつ、内蔵ダイオード
がソフトなリカバリー特性を持つようにすることができ
る。As described above, according to the power semiconductor device of the present invention, the built-in diode can have a soft recovery characteristic while maintaining a low on-resistance.
【図１】本発明の第１の実施形態に係るスーパージャン
クション構造を有する縦形パワーＭＯＳＦＥＴの断面構
造を模式的に示した図。FIG. 1 is a diagram schematically showing a cross-sectional structure of a vertical power MOSFET having a super junction structure according to a first embodiment of the present invention.
【図２】図１中のｎ−層２の厚さLn- とドリフト層全体
の厚さ(Lsj+Ln-) の比Ln-/(Lsj+Ln-) に対するオン抵抗
Ron の変化を示す特性図。FIG. 2 is an on-resistance with respect to the ratio Ln − / (Lsj + Ln−) of the thickness Ln− of the n− layer 2 and the total thickness (Lsj + Ln−) of the drift layer in FIG.
A characteristic diagram showing changes in Ron.
【図３】図１中のｎ−層２の厚さLn- がドリフト層全体
の厚さ(Lsj+Ln-) の比Ln-/(Lsj+Ln-) に占める割合が変
化した場合の内蔵ダイオード逆回復特性を示す特性図。FIG. 3 shows a case where the ratio of the thickness Ln− of the n− layer 2 in FIG. 1 to the ratio Ln − / (Lsj + Ln−) of the total thickness (Lsj + Ln−) of the drift layer changes. The characteristic view which shows a diode reverse recovery characteristic.
【図４】図１中のｎ−層２の厚さLn- がドリフト層全体
の厚さ(Lsj+Ln-) の比Ln-/(Lsj+Ln-) に占める割合が変
化した場合の図３に示した逆回復時電流特性（ソフトな
リカバリー波形）の傾斜の変化を示す特性図。FIG. 4 is a diagram when the ratio of the thickness Ln− of the n− layer 2 in FIG. 1 to the ratio Ln − / (Lsj + Ln−) of the total thickness (Lsj + Ln−) of the drift layer changes. FIG. 4 is a characteristic diagram showing a change in slope of the reverse recovery current characteristic (soft recovery waveform) shown in FIG.
【図５】図１に示したパワーＭＯＳＦＥＴのゲート電圧
Vgを閾値電圧Vth ＋3Vとした場合の電流−電圧特性を示
す。5 is a gate voltage of the power MOSFET shown in FIG.
The current-voltage characteristic when Vg is the threshold voltage Vth + 3V is shown.
【図６】本発明の第２の実施形態に係るパワーＭＯＳＦ
ＥＴの断面構造の一部とドリフト層深さ方向における不
純物プロファイルと高電圧印加時の電界強度分布を示す
図。FIG. 6 is a power MOSF according to a second embodiment of the present invention.
The figure which shows a part of ET sectional structure, the impurity profile in the drift layer depth direction, and the electric field strength distribution at the time of high voltage application.
【図７】本発明の第３の実施形態に係わるパワーＭＯＳ
ＦＥＴの製造工程を模式的に示す断面図。FIG. 7 is a power MOS according to a third embodiment of the present invention.
Sectional drawing which shows the manufacturing process of FET typically.
【図８】本発明の第４の実施形態に係わるパワーＭＯＳ
ＦＥＴの構造を模式的に示す断面図。FIG. 8 is a power MOS according to a fourth embodiment of the present invention.
Sectional drawing which shows the structure of FET typically.
【図９】図８の構造の製造工程を模式的に示す断面図。FIG. 9 is a cross-sectional view schematically showing the manufacturing process of the structure of FIG.
【図１０】本発明の第４の実施形態の変形例に係わるパ
ワーＭＯＳＦＥＴの構造を模式的に示す断面図。FIG. 10 is a sectional view schematically showing the structure of a power MOSFET according to a modified example of the fourth embodiment of the present invention.
【図１１】本発明の第５の実施形態に係わるパワーＭＯ
ＳＦＥＴの断面構造の一部とドリフト層深さ方向におけ
る不純物プロファイルを示す図。FIG. 11 is a power MO according to a fifth embodiment of the present invention.
The figure which shows a part of cross-section of SFET, and the impurity profile in the drift layer depth direction.
【図１２】本発明の第６の実施形態に係わるパワーＭＯ
ＳＦＥＴの断面構造の一部とドリフト層深さ方向におけ
る不純物プロファイルを示す図。FIG. 12 is a power MO according to a sixth embodiment of the present invention.
The figure which shows a part of cross-sectional structure of SFET, and the impurity profile in the depth direction of a drift layer.
【図１３】本発明の第７の実施形態に係わるパワーＭＯ
ＳＦＥＴの断面構造を模式的に示す断面図。FIG. 13 is a power MO according to the seventh embodiment of the present invention.
Sectional drawing which shows the cross-sectional structure of SFET typically.
【図１４】図１３の構造を形成するプロセスフローを示
す断面図。14 is a sectional view showing a process flow for forming the structure of FIG.
【図１５】本発明の第８の実施形態に係わるパワーＭＯ
ＳＦＥＴの構成を模式的に示す断面図。FIG. 15 is a power MO according to the eighth embodiment of the present invention.
Sectional drawing which shows the structure of SFET typically.
【図１６】本発明の第９の実施形態に係わるパワーＭＯ
ＳＦＥＴの構成を模式的に示す断面図。FIG. 16 is a power MO according to a ninth embodiment of the present invention.
Sectional drawing which shows the structure of SFET typically.
【図１７】本発明の第１０の実施形態に係わるパワーＭ
ＯＳＦＥＴの構成を模式的に示す断面図。FIG. 17 is a power M according to the tenth embodiment of the present invention.
Sectional drawing which shows the structure of OSFET typically.
【図１８】従来のパワーＭＯＳＦＥＴの構成を模式的に
示す断面図。FIG. 18 is a sectional view schematically showing the configuration of a conventional power MOSFET.
１…ｎ＋型ドレイン層、 ２…ｎ−型層（第１の半導体層） ３…ｎ層（第２の半導体層） ４…ｐ型リサーフ層（第３の半導体層）、 ５…ドレイン電極（第１の主電極）、 ６…ｐ型ベース層（第４の半導体層）、 ７…ｎ＋ソース層（第５の半導体層） ８…ソース電極（第２の主電極） ９…Ｓｉ酸化膜（ゲート絶縁膜）、 １０…ゲート電極（第１の制御電極）。 1 ... n + type drain layer, 2 ... N-type layer (first semiconductor layer) 3 ... n layer (second semiconductor layer) 4 ... p-type RESURF layer (third semiconductor layer), 5 ... drain electrode (first main electrode), 6 ... p-type base layer (fourth semiconductor layer), 7 ... n + source layer (fifth semiconductor layer) 8 ... Source electrode (second main electrode) 9 ... Si oxide film (gate insulating film), 10 ... Gate electrode (first control electrode).
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大村 一郎 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝マイクロエレクトロニクスセン ター内 (72)発明者 山口 正一 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝マイクロエレクトロニクスセン ター内 (72)発明者 相田 聡 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝マイクロエレクトロニクスセン ター内 (72)発明者 小野 昇太郎 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝マイクロエレクトロニクスセン ター内 Ｆターム(参考） 5F140 AA00 AA30 AC21 AC23 AC24 BA02 BA06 BF43 BH01 BH12 BH13 BH30 BH34 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Ichiro Omura 1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Ceremony Company Toshiba Microelectronics Sen Inside (72) Inventor Shoichi Yamaguchi 1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Ceremony Company Toshiba Microelectronics Sen Inside (72) Inventor Satoshi Aida 1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Ceremony Company Toshiba Microelectronics Sen Inside (72) Inventor Shotaro Ono 1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Ceremony Company Toshiba Microelectronics Sen Inside F-term (reference) 5F140 AA00 AA30 AC21 AC23 AC24 BA02 BA06 BF43 BH01 BH12 BH13 BH30 BH34
Claims (12)
る方向の面内で周期的に配置された第１導電型の第２の
半導体層および第２導電型の第３の半導体層と、 前記第１の半導体層に電気的に接続された第１の主電極
と、 前記第２の半導体層と第３の半導体層表面に選択的に形
成された第２導電型の第４の半導体層と、 前記第４の半導体層の表面に選択的に形成された第１導
電型の第５の半導体層と、 前記第４の半導体層および第５の半導体層の各表面に接
合するように形成された第２の主電極と、 前記第４の半導体層と、第５の半導体層、第２の半導体
層のそれぞれにゲート絶縁膜を介して形成された制御電
極とを具備し、 前記第１の主電極と第２の主電極との間に所定の電圧を
加えた時に前記第２の半導体層と第３の半導体層が完全
に空乏化し、前記第１の半導体層の不純物濃度が第２の
半導体層の不純物濃度よりも低いことを特徴とする電力
用半導体素子。1. A first semiconductor layer of a first conductivity type, and a first conductivity type formed on the first semiconductor layer and periodically arranged in a plane orthogonal to the depth direction. Second semiconductor layer and a third semiconductor layer of a second conductivity type, a first main electrode electrically connected to the first semiconductor layer, the second semiconductor layer and a third semiconductor A fourth semiconductor layer of a second conductivity type selectively formed on the surface of the layer, a fifth semiconductor layer of a first conductivity type selectively formed on the surface of the fourth semiconductor layer, A second main electrode formed so as to be bonded to the respective surfaces of the fourth semiconductor layer and the fifth semiconductor layer; and the fourth semiconductor layer, the fifth semiconductor layer, and the second semiconductor layer A control electrode formed via a gate insulating film, and a predetermined voltage is applied between the first main electrode and the second main electrode. Wherein the second semiconductor layer and the third semiconductor layer completely depleted, the impurity concentration of the first semiconductor layer is a power semiconductor device characterized by lower than the impurity concentration of the second semiconductor layer.
の半導体層の厚さおよび前記第２の半導体層の厚さの和
との比が、０．２１から０．８の範囲内であることを特
徴とする請求項１記載の電力用半導体素子。2. The thickness of the first semiconductor layer and the first semiconductor layer
2. The power semiconductor device according to claim 1, wherein the ratio of the thickness of the semiconductor layer to the sum of the thicknesses of the second semiconductor layers is in the range of 0.21 to 0.8.
極と第２の主電極との間に定格電圧以上の電圧が加わっ
た時に完全に空乏化することを特徴とする請求項１また
は２記載の電力用半導体素子。3. The first semiconductor layer is completely depleted when a voltage higher than a rated voltage is applied between the first main electrode and the second main electrode. 1. The power semiconductor device according to 1 or 2.
極と第２の主電極との間に定格電圧の半分以上の電圧が
加わった時に完全に空乏化することを特徴とする請求項
１または２記載の電力用半導体素子。4. The first semiconductor layer is completely depleted when a voltage more than half the rated voltage is applied between the first main electrode and the second main electrode. The power semiconductor device according to claim 1 or 2.
体層の片方もしくは両方は、深さ方向において不純物濃
度が一定でなく分布していることを特徴とする請求項１
乃至４のいずれか１項に記載の電力用半導体素子。5. The impurity concentration in one or both of the second semiconductor layer and the third semiconductor layer is not constant and distributed in the depth direction.
5. The power semiconductor device according to any one of items 1 to 4.
層の間に周期的に絶縁物が挿入されていることを特徴と
する請求項１乃至５のいずれか１項に記載の電力用半導
体素子。6. The power according to claim 1, wherein an insulator is periodically inserted between the second semiconductor layer and the third semiconductor layer. Semiconductor device.
半導体層の中に絶縁物が挿入されていることを特徴とす
る請求項１乃至５のいずれか１項に記載の電力用半導体
素子。7. The power semiconductor device according to claim 1, wherein an insulator is inserted in the second semiconductor layer or the third semiconductor layer. .
半導体層の不純物濃度が横方向に一定でなく分布してい
ることを特徴とする請求項６または７記載の電力用半導
体素子。8. The power semiconductor device according to claim 6, wherein the impurity concentration of the second semiconductor layer or the third semiconductor layer is not laterally constant but distributed.
導体層は、素子終端部においても素子中央部と同様に形
成されていることを特徴とする請求項１乃至８のいずれ
か１項に記載の電力用半導体素子。9. The device according to claim 1, wherein the second semiconductor layer and the third semiconductor layer are formed in the element termination portion similarly to the element central portion. The semiconductor element for electric power according to 1.
が低い第１導電型の第６の半導体層が素子終端部に形成
されていることを特徴とする請求項１乃至８のいずれか
１項に記載の電力用半導体素子。10. The sixth semiconductor layer of the first conductivity type having a lower impurity concentration than that of the second semiconductor layer is formed at the device termination portion. The semiconductor element for electric power according to the item.
いて不純物濃度が一定でないことを特徴とする請求項１
乃至８のいずれか１項に記載の電力用半導体素子。11. The impurity concentration of the first semiconductor layer is not constant in the depth direction.
9. The power semiconductor device according to any one of items 1 to 8.
１の半導体層およびそれより不純物濃度が高い第１導電
型の第６の半導体層が横方向に交互に配置されているこ
とを特徴とする請求項１乃至８のいずれか１項に記載の
電力用半導体素子。12. The first semiconductor layer and the sixth semiconductor layer of the first conductivity type having a higher impurity concentration than that of the first semiconductor layer are laterally alternately arranged below the first semiconductor layer. 9. The power semiconductor device according to claim 1, wherein the power semiconductor device is a power semiconductor device.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001298311A JP2003101022A (en) | 2001-09-27 | 2001-09-27 | Power semiconductor device |
| EP02012374A EP1267415A3 (en) | 2001-06-11 | 2002-06-06 | Power semiconductor device having resurf layer |
| US10/163,651 US6693338B2 (en) | 2001-06-11 | 2002-06-07 | Power semiconductor device having RESURF layer |
| KR10-2002-0032304A KR100491989B1 (en) | 2001-06-11 | 2002-06-10 | Power semiconductor device having resurf layer and method of fabricating thereof |
| CNB021482292A CN1329999C (en) | 2001-06-11 | 2002-06-11 | Power semiconducter device with RESURF layer |
| US10/714,916 US6919610B2 (en) | 2001-06-11 | 2003-11-18 | Power semiconductor device having RESURF layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001298311A JP2003101022A (en) | 2001-09-27 | 2001-09-27 | Power semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| JP2003101022A true JP2003101022A (en) | 2003-04-04 |
Family
ID=19119228
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001298311A Pending JP2003101022A (en) | 2001-06-11 | 2001-09-27 | Power semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP2003101022A (en) |
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