JP3792734B2 - High voltage semiconductor element - Google Patents

Description

横方向及び縦方向の電界強度は、ポアソン方程式を解くことによって得られる。 ｎ（ｘ）＝（ε_s ／ｑ）（ｄＥ_x ／ｄ_x ＋ｄＥ_y ／ｄ_y ）
ここでε_s はＳｉに対する誘電率、ｑは素電荷である。素子のアバランシェ耐圧を求めるためには、下記数２に示すようにイオン化積分を行う。
【００２６】
Ｉ＝∫α（Ｅ）ｄＸ
ここでα（Ｅ）はイオン化係数であって、次式で求められる。
【００２７】
α（Ｅ）＝Ａ・ｅｘｐ（−Ｂ／Ｅ）
ここでＡ及びＢは定数である。一般にポアソン方程式及びイオン化積分は解析的に求めることが出来ないので、数値計算を行う。この結果、ｎ₀ とａには次式で示される関係があることがわかった。
【００２８】
ｎ₀ ／ａ^1/2 ≦１×１０¹⁹
従って、濃度勾配の最大値Δｎ_max が次式を満足することが必要である。
【００２９】
Δｎ_max ≦０．８５７７６×１０¹⁹／ａ^1/2
一方、階段のステップ部分では、横方向の電界強度は段差部分と比べて非常に小さいので、階段の間隔を小さくするほうがよい。しかし、階段の間隔が小さ過ぎると、隣接する階段間で干渉が生じ、電界が強くなってしまう。従って、階段間の間隔は、拡散長の２倍以上、好ましくは３〜４倍程度とするのがよい。
【００３０】
拡散長を変化させたときのブレ−クダウン電圧を図５２に、拡散数を変化させたときのブレ−クダウン電圧を図５３にそれぞれ示す。これらの図から、第２の発明によると、ドリフト領域の長さを長くすることなく、高耐圧の誘電体分離半導体素子を実現することが可能である。
【００３１】
【実施例】
以下、図面を参照しながら本発明の実施例を説明する。
【００３２】
図１は、本発明の第１の実施例に係わる高耐圧ダイオードの素子構造を示す断面図である。シリコン基板１０上に、シリコン酸化膜（分離絶縁膜）１１を介して、ｎ^- 型の高抵抗シリコン層（活性層）１２が形成されている。この構造は、例えばシリコン基板１０の表面にシリコン酸化膜１１を形成し、これに表面が鏡面に研磨された別のシリコン基板を直接接着し、該基板を薄く加工することにより形成される。また、シリコン酸化膜１１は１〜５μｍ程度の厚さとする。ｎ^- 型活性層１２は、不純物総量が１×１０¹⁰ｃｍ^-2〜２×１０¹²ｃｍ^-2の範囲、より好ましくは０．５〜１．８×１０¹²ｃｍ^-2の範囲に設定されており、その厚さは約１０μｍとした。
【００３３】
活性層１２には、所定距離離れてｐ型アノード層１３とｎ型カソード層１４が形成されている。ｐ型アノード層１３とｎ型カソード層１４は、図示のように活性層底部のシリコン酸化膜１１に達する深さまで拡散形成されている。さらに、ｎ型カソード層１４は拡散窓の幅と拡散深さを変えて３重の拡散層１４ａ，１４ｂ，１４ｃとなっている。１４ａ以外の拡散層、即ちここでは１４ｂ，１４ｃの拡散層の不純物総量は１×１０¹¹ｃｍ^-2〜３×１０¹²ｃｍ^-2の範囲に設定する。ｐ型アノード層１３とｎ型カソード層１４にはそれぞれ、アノード電極１５，カソード電極１６が形成されている。これらの電極１５，１６間の活性層１２上には、シリコン酸化膜１７を介して、高抵抗体膜１８が配設されている。高抵抗体膜１８は、例えばＳＩＰＯＳ（Semi-Insulating Polycrystalline Silicom ）であり、この高抵抗体膜１８の両端部は電極１５，１６にそれぞれ接続されている。そして、高抵抗体膜１８の表面は、保護膜としてのシリコン酸化膜１９により覆われている。
【００３４】
このような構成において、ｐ型アノード層１３と基板１０を接地して、ｎ型カソード層１４に正の高電圧を印加した場合について考える。ｎ型カソード層１４は、活性層底部に達する深さに形成されていることから、縦方向には、ｎ型カソード層１４に印加されている電圧は全てシリコン酸化膜１１で分担される。ここで、シリコン酸化膜１１は活性層１２に比較してその耐圧が十分に高いものである。
【００３５】
また、アノード・カソード間電圧により、活性層１２の表面に形成された高抵抗体膜１８には微小電流が流れて、横方向に一様な電位分布が形成される。この高抵抗体膜１８内の電位分布の影響を受けて、高抵抗体膜直下の活性層表面も横方向に一様な電位分布が形成される。さらに、ｎ型カソード層１４を３重に拡散することで、拡散層底部の曲面部分での不純物濃度勾配が緩和され、この影響で等電位線の間隔が拡がり、極端な電界集中が防げる。以上の結果、素子内部の電界集中は緩和され、高耐圧が実現される。
【００３６】
なお、上記のような構成においては、活性層１２の不純物総量を変えると耐圧も変わる。図２３は、活性層１２の不純物総量と耐圧との関係を示す特性図である。不純物総量が１×１０¹⁰ｃｍ^-2以上では不純物総量が大きくなるほど耐圧は高くなり、不純物総量が３×１０¹²ｃｍ^-2を越えると耐圧が急激に低下する。従って活性層１２の不純物総量としては、１×１０¹⁰ｃｍ^-2〜２×１０¹²ｃｍ^-2の範囲が望ましい。
【００３７】
このように本実施例によれば、ｎ型カソード層１４を３重拡散により形成すると共に、シリコン酸化膜１１に達する深さまで形成し、さらに活性層１２の上に高抵抗体膜１８を形成することにより、素子内部の電界集中を緩和することができ、活性層１２を薄くしても高耐圧のダイオードを実現することができる。
【００３８】
第１の実施例における変形例を、図２〜図１０に示す。図２は、第１の実施例において、ｐ型アノード層１３をシリコン酸化膜１１より浅く形成したものである。図３は、ｎ型カソード層１４をシリコン酸化膜１１より浅く形成したものである。図４は、ｐ型アノード層１３及びｎ型カソード層１４を、共にシリコン酸化膜１１より浅く形成したものである。このような構成であっても、ｎ型カソード層１４のエッジ部における電界集中が緩和されるため、第１の実施例と同様な効果が得られる。
【００３９】
図５は、ｎ型カソード層１４の深さはシリコン酸化膜１１に達する深さで一定とし、３重拡散における横方向の拡散窓の長さを変えたものである。ここで、１４ａ，１４ｂ，１４ｃは順に不純物濃度が薄くなっている。このような構成であっても、横方向の等電位線の間隔を拡げることにより、極端な電界集中が防ぐことができ、第１の実施例と同様に効果が得られる。なお、不純物濃度の異なる複数回の拡散を行う代わりに、不純物濃度を連続的に可変してもよい。
【００４０】
図６は、図５の構成に加えて図２の考えを適用したものである。図７は、ｎ型カソード層１４を３重拡散ではなく、２重拡散で形成したものである。
【００４１】
図８は、高抵抗体膜１８を電極１５，１６と共にｐ型アノード層１３，ｎ型カソード層１４に直接接続したものである。図９は、高抵抗体膜１８を活性層１２上に直接形成したものである。この場合であっても、高抵抗体膜１８の抵抗が十分に高いため、アノード層１３，カソード層１４間が短絡されることはなく、これらの間の電位分布を均一化することができる。
【００４２】
図１０は高抵抗体膜１８を用いることなく、活性層１２上に保護絶縁膜１９のみを形成したものである。この場合、高抵抗体膜１８による電位分布の均一化はできないが、ｎ型カソード層１４を３重拡散により形成し、さらに拡散深さをシリコン酸化膜１１に達する深さに形成していることから、これらによる電界集中の緩和効果が得られる。
【００４３】
図１１は、本発明の第２の実施例に係わる高耐圧ＭＯＳトランジスタの素子構造を示す断面図である。なお、図１と同一部分には同一符号を付して、その詳しい説明は省略する。
【００４４】
基板１０上にシリコン酸化膜１１を介してｎ^- 型活性層１２が形成される構造は図１と同様である。活性層１２の不純物総量も第１の実施例と同様である。活性層１２には、第１の実施例におけるｐ型アノード層１３，ｎ型カソード層１４に対応するｐ型ベース層２３，ｎ型ドレイン層２４が形成されている。
【００４５】
ｐ型ベース層２３内にはｎ型ソース層２２が形成され、このｎ型ソース層２２とｎ^- 型活性層１２により挟まれたｐ型ベース層２３の表面部をチャネル領域として、この上に６０ｎｍ程度のゲート酸化膜を介してゲート電極２１が形成されている。
【００４６】
ｐ型ベース層２３とｎ型ドレイン層２４により挟まれた活性層の表面には、第１の実施例と同様に、シリコン酸化膜１７を介して高抵抗体膜１８が形成されており、高抵抗体膜１８の上はシリコン酸化膜１９で覆われている。
【００４７】
ソース電極２５はｎ型ソース層２２とｐ型ベース層２３に同時にコンタクトするようにこれらの上に形成され、ドレイン電極２６はｎ型ドレイン層２４上に形成されている。高抵抗体膜１８の端部は、ゲート電極２１とドレイン電極２６とにそれぞれ接続されている。ここで、ゲート電極２１はオフ時には０Ｖで接地と同じであり、オン時でもドレイン電極２６に掛かる高電圧よりも十分に低い電圧であるので、高抵抗体膜１８はゲート電極２１とドレイン電極２６との間に接続しても、第１の実施例と同様の機能を果たす。
【００４８】
この実施例のＭＯＳＦＥＴも、ｎ型ドレイン層２４の３重拡散、シリコン酸化膜１１に達する拡散、及び高抵抗体膜１８の作用により、第１の実施例のダイオードと同様に優れた高耐圧特性が得られる。
【００４９】
第２の実施例における変形例を、図１２〜図１６に示す。図１２は、ｎ型ソース層２２を酸化膜１１に達する深さまで形成したものである。図１３は、高抵抗体膜１８を活性層１２上に直接形成したものである。図１４は、高抵抗体膜１８をゲート電極２１ではなく、ソース電極２５に接続したものである。
【００５０】
図１５は、高抵抗体膜１８のドレイン側端部を不純物ドープの多結晶シリコン膜２８を介してドレイン電極２６に接続したものである。ここで、高抵抗体膜１８とドレイン電極２６とのコンタクト抵抗は大きいが、高抵抗体膜１８と不純物ドープ多結晶シリコン膜２８とのコンタクト抵抗は極めて小さく、またドレイン電極２６と不純物ドープ多結晶シリコン膜２８とのコンタクト抵抗も極めて小さいため、不純物ドープ多結晶シリコン膜２８を介在させることにより、高抵抗体膜１８とドレイン電極２６とのコンタクト抵抗を小さくすることができる。
【００５１】
図１６は、高抵抗体膜１８を省略したものである。また、図には示さないが、第１の実施例における図２〜図４と同様に、ｐ型ベース層２３やｎ型ドレイン層２４等をシリコン酸化膜１１よりも浅く形成してもよい。さらに、図５の例と同様に、ｎ型ドレイン層２４を、３重拡散における横方向の拡散窓の長さを変え、拡散深さを一定としてもよい。
【００５２】
図１７は、本発明の第３の実施例に係わるＩＧＢＴ（Insulated Gate Bipolar Transistor ）の素子構造を示す断面図である。なお、図１１と同一部分には同一符号を付して、その詳しい説明は省略する。
【００５３】
基本的な構成は図１１と同様であるが、この実施例では図１１のｎ型ドレイン層２４に相当するものがｎ型ベース層３４であり、このｎ型ベース層３４内にｐ型ドレイン層３６が形成されている。
【００５４】
このような構成であれば、バイポーラトランジスタとパワーＭＯＳＦＥＴを１つのチップ内にモノリシックで複合化した横型のＩＧＢＴを実現することができる。そしてこの場合、第１の実施例と同様に、ｎ型ベース層３４の３重拡散，シリコン酸化膜１１に達する拡散，及び高抵抗体膜１８の作用により、ｎ型ベース層３４のエッジ部における電界集中を緩和することができ、耐圧向上をはかることができる。
【００５５】
第３の実施例における変形例を、図１８〜図２２に示す。図１８は、図１２の例と同様にｎ型ソース層２２及びｐ型ドレイン層３６がシリコン酸化膜１１に達する深さとなるように活性層１２を薄くしたものである。このとき、ｐ型ドレイン層３６がシリコン酸化膜１１に接しているため、活性層底部にｐ型反転層によるチャネルが形成されることがある。これを防ぐには、ｎ型ベース層３４の不純物濃度を高く設定する必要があり、具体的にはｎ型ベース層３４の不純物濃度が１×１０¹⁷ｃｍ^-3以上であればよい。または、図１７の例のようにｐ型ドレイン層３６がシリコン酸化膜１１に達していない構成であれば、活性層底部のｐ型反転層によるチャネル形成を避けることができる。
【００５６】
図１９は、高抵抗体膜１８を活性層１２上に直接形成したものである。図２０は、高抵抗体膜１８をゲート電極２１ではなく、ソース電極２５に接続したものである。
【００５７】
図２１は、高抵抗体膜１８のドレイン側端部を不純物ドープの多結晶シリコン膜２８を介してドレイン電極２６に接続したものである。この場合も、図１５の例と同様に、不純物ドープ多結晶シリコン膜２８を介在させることにより、高抵抗体膜１８とドレイン電極２６のコンタクト抵抗を小さくすることができる。
【００５８】
図２２は、高抵抗体膜１８を省略したものである。また、図には示さないが、第１の実施例における図２〜図４と同様に、ｐ型ベース層２３やｎ型ベース層３４等をシリコン酸化膜１１よりも浅く形成してもよい。さらに、図５の例と同様に、ｎ型ベース層３４を、３重拡散における横方向の拡散窓の長さを変え、拡散深さを一定としてもよい。
【００５９】
次に、本発明の別の実施例について説明する。図２４は、第４の実施例の概略構成を示す断面図である。この実施例は、横型ＩＧＢＴの例である。シリコン基板５０上にシリコン酸化膜５１を介して、厚さ５μｍ以下のｎ^- 型高抵抗シリコン層（活性層）５２が形成されている。
【００６０】
シリコン酸化膜５１は１〜５μｍ程度の厚さとする。活性層５２に、シリコン酸化膜５１に達する深さで所定距離離れてｐベース５３層，ｎベース層（バッファ層）５４を拡散により形成する。さらに、ｐベース層５３中にｎ⁺ 型ソース層５５を、ｎベース層５４中にｐ⁺ 型ドレイン層５６を拡散により形成する。ｎ⁺ 型ソース層５５とｎ^- 型活性層５２により挟まれたｐベース層５３の表面部をチャネル領域として、この上に６０ｎｍ程度のゲート酸化膜を介してゲート電極５７が形成されている。ソース電極５８はｎ⁺ 型ソース層５５とｐベース層５３に同時にコンタクトするように形成され、ドレイン電極５９はｐ型ドレイン層５６にコンタクトするように形成されている。また、電極５８，５９間の活性層５２上には絶縁保護膜６０が形成されている。
【００６１】
図２５は、図２４の構成でｎ型活性層５２を厚く形成しｎ型バッファ層５４の底部にｎ型活性層５２が残るようにしたものである。ｎ型活性層５２の表面にｎ型バッファ層５４が形成され、その中にｐ型ドレイン層５６が形成されている。ｎ型バッファ層５４はパンチスルーを防いで耐圧を高める働きをする。また、ｐ型ドレイン層５６からの正孔の注入効率を下げる働きがあるため、素子のオン抵抗が高くなる代わりにターンオフ速度は速くなる。
【００６２】
この構造の素子のｎ型活性層５２の厚さとオン抵抗，１００Ａ／ｃｍ² の電流を流したときのオン抵抗及びターンオフ時のフォールタイムの関係を図２６に示す。破線の部分はシミュレーション結果である。ｎ型活性層５２が薄くなるとオン抵抗は少しずつ高くなるが、ターンオフ速度は著しく速くなる。特に、厚さ１０μｍ以下になるとその効果は顕著である。一方、薄くし過ぎるとオン抵抗が急激に上がってしまうので、ｎ型活性層５２の厚さを４μｍ以上１０μｍ以下の範囲に設定することが望ましい。
【００６３】
図２７は、図２４の構造を基本として、活性層５２の表面全体からｎ型不純物層６１を拡散した実施例である。活性層５２の厚さは１０μｍ以下、好ましくは５μｍ以下とする。この構造では、活性層５２中に縦方向の濃度勾配がつき、活性層底部での電界集中が効果的に緩和されてトレードオフの向上と共により高耐圧が得られる。
【００６４】
図２８は、図２７の構造でｎ^- 型活性層５２の代わりにｐ^- 型の活性層６２を用いた実施例であり、活性層６２の表面全体からｎ型不純物層６１を拡散してある。この場合も、図２４の実施例と同様の理由で高耐圧が得られる。
【００６５】
図２９は、図２４の構造を基本として、活性層５２の底面全体からｎ型不純物層６３を拡散した実施例である。この構造でも、活性層５２中に縦方向の濃度勾配がつき、活性層底部での電界集中が緩和されてトレードオフの向上と共に高耐圧が得られる。
【００６６】
図３０は、図２４の構造を基本として、ｎベース層５４を拡散窓の幅を変え２重以上に拡散した実施例である。この構造でも２重以上の拡散層５４′，５４″の効果により横方向の電界が緩和され、図２７の実施例と同様にトレードオフの向上と共に高耐圧が得られる。
【００６７】
図３１〜図３３は、図３０の構造を基本として、図２７〜図２９の例と同様の活性層の変形を行った実施例である。これらの構造でも、図３０の実施例と同様にトレードオフの向上と共に高耐圧が得られる。
【００６８】
図３４は、図２４の構造で一部変形したサイリスタの実施例である。なお、図３４において図２４と異なる符号７７はゲート、７８はカソード、７９はアノードである。本発明は、他の横型構造の高耐圧素子、例えば、ＥＳＴ，ＭＣＴ，ＧＴＯなどに適用することも可能である。
【００６９】
図３５は、図２５の実施例においてドレイン部分を変形した横型ＩＧＢＴの例である。ｐ型ドレイン層５６の表面に高濃度のｎ型層６５とｐ型層６６が形成され、ドレイン電極５９はこれらの両方にコンタクトしている。ｎ型層６５は正孔の注入効率を制限するために設けられたもので、ターンオフを速くする働きがある。平面的にはｎ型層６５は１本のストライプ状でも複数に分かれた島状でもよい。ｐ型層６６はドレインのコンタクトを良くするために設けられているが、なくてもよい。この実施例においても、ｎ型活性層５２が薄く、好ましくは１０μｍ以下に設定されていることにより、ターンオフ速度がさらに速くなっている。
【００７０】
図３６も、図２５の実施例のドレイン部分を変形したものである。ｎ型バッファ層５４の一部がドレイン電極５９とコンタクトしているアノードショート型のＩＧＢＴであり、ターンオフ速度が速くなっている。さらに、ｎ型活性層５２が薄く設定されていることにより、ターンオフ速度がより速くなっている。この実施例では、ｎ型バッファ層５４とドレイン電極５９のコンタクト部分に、コンタクト抵抗を下げるための高濃度のｎ型層を設けてもよい。
【００７１】
図３７は、図２５の実施例を変形したものである。ｎ型活性層５２の底部に、ｎ型活性層５２よりも不純物濃度の高いｎ型層６７が形成されている。一般に、ｎ型活性層５２の厚さが薄くなると、電圧印加時にドレインの下での縦方向の電界が強くなり、耐圧が低くなる。図３７の素子ではｎ型層６７が空乏化して生じる空間電荷により、酸化膜５１中の電界が大きくなる代わりに活性層５２中の電界が緩和されるので、高耐圧が保たれる。この実施例でも、ｎ型活性層５２が薄いことにより、速いターンオフ速度が得られる。
【００７２】
図３８は、図２５の実施例を変形したものである。酸化膜５１の上はｐ型シリコン層６８であり、その表面にｎ型活性層５２が拡散形成され、そこに素子が作られている。ｎ型活性層５２を含めたｐ型半導体層６８の厚さを薄く、望ましくは１０μｍ以下に設定していることにより、ターンオフ速度の速い横型ＩＧＢＴが得られている。
【００７３】
図３９は、図２５の実施例を変形したものである。図３８の例と同じく酸化膜５１によってシリコン基板（支持基板）５０から分離されたｐ型シリコン層６８の表面にｎ型活性層５２が拡散形成され、そこに図３５と同じ構成の素子が形成されている。
【００７４】
図４０は、図２５の実施例を変形したものであるが、これまでの変形例とは異なる誘電体分離基板を用いている。高耐圧化をはかるためにｎ型活性層５２と酸化膜５１との間にＳＩＰＯＳ膜６９が設けられている。これは、ＳＩＰＯＳ膜６９以外の高抵抗膜や高誘電率膜でもよい。この実施例においても、ｎ型活性層５２を薄く設定していることにより、ターンオフ速度が速くなっている。
【００７５】
なお、図２４，２５，２７〜４０の実施例において、導電型を全て反対にしたｐチャネル横型ＩＧＢＴに適用できるのは勿論である。
【００７６】
次に、本発明の第５の実施例について説明する。図４１は、第５の実施例に係わる高耐圧ダイオードを示す素子構造断面図である。シリコン基板１０上にシリコン酸化膜１１を介してｎ^- 型の高抵抗シリコン活性層１２が形成されている。シリコン活性層１２に所定距離離れてアノード領域となる高不純物濃度のｐ⁺ 型層１３と、カソード領域となる高不純物濃度層のｎ⁺ 型層１４が形成されている。ｐ⁺ 型層１３にはアノード電極１５が形成され、ｎ⁺ 型層１４にはカソード電極１６が形成されている。そして、シリコン活性層１２の底部にはｎ型バッファ層７１が形成されている。
【００７７】
このように構成された高耐圧ダイオードにおいて、基板１０及び電極１５を接地して電極１６に正の電位を印加すると、ｐｎ接合は逆バイアスされてシリコン活性層１２内に空乏層が広がる。酸化膜１１とシリコン活性層１２の界面からも上に向かって空乏層が広がる。印加電圧がある値以上になると、シリコン活性層１２は空乏層で満たされた状態になり、シリコン活性層１２内にはｎ⁺ 型層１３から下方に向かう強い電界が生じる。
【００７８】
また、シリコン活性層１２の底部に形成したｎ型バッファ層７１は逆バイアスを与えてバッファ層７１が空乏化すると、ここに正の空間電荷が生じる。この空間電荷がシリコン活性層１２内の電界を緩和する働きをする結果、シリコン活性層底部の中間酸化膜でより多くの印加電圧が分担され、高耐圧特性が得られる。このバッファ層７１の不純物総量は３×１０¹²ｃｍ^-2以下、より望ましくは５×１０¹¹〜２×１０¹²ｃｍ^-2となるように設定される。
【００７９】
図４３は、このｎ型バッファ層７１の拡散長２×（Ｄｔ）^1/2 と素子の耐圧との関係を示したものであり、各々の拡散長において不純物ドープ量を最適にしている。これは、ｎ型バッファ層７１の不純物総量を決めると得られるカーブである。拡散長が１／２０００ｃｍより小さい範囲では拡散長が短くなるにつれて耐圧の向上が見られ、かつ高耐圧が得られている。また、２００Ｖ系で動作させるには５００Ｖの耐圧を保証しなければならないが、拡散長が１／４０００ｃｍより小さい範囲であれば５００Ｖ以上の高耐圧を得ることが可能となる。
【００８０】
図４２は、図４１の構造を基本として、シリコン活性層１２の底部のｎ型バッファ層７１を選択的に形成したものである。印加電圧はドレイン直下部分のシリコン活性層１２により大きく掛かってくるわけだから、この部分のみ選択的にｎ型バッファ層７２を形成して電界を緩和すれば高耐圧が得られる。
【００８１】
図４４は、図４１の構造に対して活性層１２の厚さが薄い場合の例である。活性層１２が薄いとｎ型不純物層が活性層下の酸化膜に達するが、この場合もｎ型バッファ層を活性層底部に形成した方が高耐圧が得られる。
【００８２】
図４５は，図４２の構造に対して活性層１２の厚さが薄い場合の例である。ｎ型不純物層が酸化膜に達している構造でも、選択的にｎ型バッファ層を入れて同様の効果が得られる。
【００８３】
このように本実施例によれば、拡散長の短いｎ型バッファ層を活性層底部に形成することによって、薄い活性層で十分な高耐圧を得ることができる。また、本実施例のように活性層の下にｎ型バッファ層を設ける構成は、図１〜図１０に示す第１の実施例に適用することも可能である。
【００８４】
次に、本発明の別の実施例について説明する。この実施例は、誘電体分離基板に高速ダイオードを形成したものである。
【００８５】
図４６は第６の実施例に係わる高速ダイオードを示す素子構造断面図である。半導体基板８１と高抵抗のｎ型半導体基板８２の間に絶縁膜８３を形成して誘電体分離基板が構成されている。誘電体分離基板の高抵抗のｎ型半導体基板８２の表面にｐ型のアノード層８４，ｎ型のカソード層８５が形成され、アノード層８４の表面にはアノード電極８６が、カソード層８５の表面にはカソード電極８７が形成されている。
【００８６】
ここまでは従来構造と同じであるが、本実施例ではこれに加えて、アノード層８４にｎ⁺ 型の不純物層８８を選択的に形成し、カソード層８５にｐ⁺ 型の不純物層８９を選択的に形成し、アノード電極８６はアノード層８４及びｎ⁺ 型の不純物層８８の双方にオーミックコンタクトし、カソード電極８７はカソード層８５及びｐ⁺ 型の不純物層８９の双方にオーミックコンタクトするようになっている。そして、アノード層８４，カソード層８５が形成される半導体基板８２の厚さは２〜１０μｍに設定してある。
【００８７】
図４７は、誘電体分離基板に形成したダイオードのオン電圧Ｖf 及び逆回復時間ｔrrと半導体基板８２の厚さｔs の関係を示す。逆回復時間ｔrrは基板８２の厚さｔs が薄くなるほど短くなり、ｔs ≦１０μｍになるとｔrr≦０．３μsec を満足することが認められた。しかし、オン電圧Ｖf はｔs ≦２μｍになると急激に上昇することが分かった。このことから、半導体基板８２の厚さｔs は２〜１０μｍに設定すれば、電子線照射などのライフタイムコントロールをすることなく逆回復時間の高速化をはかったダイオードを実現することができる。
【００８８】
次に、本発明の第７の実施例について説明する。この実施例は、半導体基板の中間に絶縁膜層を有する誘電体分離半導体基板に関する。図４８は、第７の実施例に係わる誘電体分離半導体基板の構成を示し、（ａ）は裏面から見た平面図、（ｂ）そのＡ−Ａ′断面図である。２枚のシリコン基板９１，９３が酸化膜９２を介して一体化され、シリコン基板９１の表面は所定の厚さまで研磨されている。そして、シリコン基板９３には格子状の溝９４が形成され、この溝９４に酸化膜９５を埋め込んだ構造にしてある。
【００８９】
図４９にこの誘電体分離半導体基板の製造工程を示す。シリコン直接接合後、図４９（ａ）に示すようにシリコン基板９３に幅数μｍ、望ましくは１μｍ以下、深さ数μｍ〜数十μｍの格子状の溝９４を形成する。続いて、図４９（ｂ）に示すように、この溝９４を酸化膜９５で埋め込む。このとき、溝幅を約１μｍ以下にしておけば、熱酸化で溝９４を完全に埋め込むことができる。この後、図４９（ｂ）に示すように、シリコン基板９１の表面を所定の厚さまで研磨する。
【００９０】
この誘電体分離半導体基板では、シリコン基板９３を挟むように酸化膜９２と酸化膜９５が形成されているから、基板の反りは小さく抑えることができる。また、素子形成時の基板表面に形成した酸化膜を除去する工程においても、酸化膜９５が除去されるのはその表面だけであり、溝９４内には酸化膜９５は残る。従って、従来のような裏面の酸化膜が除去されないように保護膜を設ける必要がなく、工程を簡略化することができる。
【００９１】
このように本実施例によれば、中間酸化膜の厚さを厚くしても反りの小さな誘電体分離半導体基板を実現することができ、工程の簡略化がはかられ、低コストのパワーＩＣの実現に寄与することが可能となる。
【００９２】
図５０は、図４８の実施例の変形例である。図４８と異なる点は、酸化膜９５の表面に減圧ＣＶＤ法によりポリシリコン９６を形成したことである。この実施例は、溝９４の幅が１μｍ以上のとき有効である。溝９４の幅が１μｍ以上になると、熱酸化だけで溝９４を埋め込むことは困難になる。そこで、埋め込み不足を生じた部分をポリシリコン９６で埋め込んだものである。また、この実施例では基板の裏面がポリシリコン９６であることから、素子形成時の酸化膜を除去する工程においても、酸化膜９５は全く除去されない利点がある。
【００９３】
第７の実施例では、半導体基板にシリコン、絶縁膜に酸化膜を用いて説明したが、本発明はこれに限らず他の材料を用いても適用することが可能である。また、本実施例では２枚の半導体基板を直接接合して得られる誘電体分離半導体基板を用いたが、他の方法で得られる誘電体分離半導体基板を用いた場合も有効である。 図５４は、本発明の第８の実施例に係る誘電体分離半導体素子の一例を示す断面図である。シリコン基板１０１上に、シリコン酸化膜（分離絶縁膜）１０２を介して、ｎ^- 型の高抵抗シリコン層（活性層）１０３が形成されている。シリコン酸化膜１０２の厚さは３μｍ、ｎ^- 型活性層１０３の厚さは０．１μｍである。ｎ^- 型活性層１０３の不純物濃度は１．０×１０¹⁷／ｃｍ³ である。ｎ^- 型活性層１０３には、ドレイン領域１０４、ソ−ス領域１０５がそれぞれ形成され、これらドレイン領域１０４、ソ−ス領域１０５の上には、それぞれドレイン電極１０６、ソ−ス電極１０７が形成されている。なお、参照数字１０８、１０９はそれぞれ絶縁膜、ゲ−ト電極である。
【００９４】
ｎ^- 型活性層１０３の横方向の不純物濃度分布は、３段の階段状となっている。この階段状の不純物濃度分布は、次のようにして得ることが出来る。
【００９５】
即ち、ｎ^- 型活性層１０３の上に第１のマスクを形成し、２×１０¹²ｃｍ^-2のド−ズ量で燐をイオン注入する。次いで、横方向の開口部が第１のマスクよりも広い第２のマスクを用いて、２×１０¹²ｃｍ^-2のド−ズ量で燐をイオン注入する。更に、横方向の開口部が第２のマスクよりも広い第３のマスクを用いて、２×１０¹²ｃｍ^-2のド−ズ量で燐をイオン注入する。なお、マスクの横方向の開口部の差は、いずれも拡散長の２倍以上、好ましくは３〜４倍である。
【００９６】
次いで、約１２００℃で熱処理して、イオン注入した燐を拡散させることにより、図５５に示すような、横方向に３段の階段状の不純物濃度分布が得られる。図５４に示す誘電体分離半導体素子のアバランシェ耐圧を測定したところ、７００Ｖであった。
【００９７】
図５４に示す例では、階段状不純物濃度分布の段数を３段としたが、２〜１０段の範囲で適宜変えることが可能である。段数を増やした場合には、拡散長を小さくしても同様の耐圧を得ることが出来る。一方、段数を減少させた場合には、拡散長を大きくする必要がある。
【００９８】
図５５は、半導体素子の耐圧をパラメ−タ−とした場合の、階段数とそれに対応する拡散長との関係を示すグラフである。図中の曲線は、下記の式で表される。
【００９９】
（ｎ＋１）［ａ＋（Ｖ_ｂ／２００）＋１．５］＝Ｖ_ｂ ² ／１３６００
式中、Ｖ_ｂは耐圧（Ｖ）、ａは拡散長（μｍ）、ｎは段数を示す。
【０１００】
以上説明したように、本発明の第８の実施例によると、活性層の厚さが０．３μｍ以下であっても、ドリフト領域の長さを大きくすることなく、高耐圧の横型誘電体分離半導体素子を実現することが可能である。
【０１０１】
【発明の効果】
以上詳述したように第１の発明によれば、２重以上の拡散により拡散層の形状を工夫することにより、拡散層のエッジ部（特に底部の曲面部付近）における電界集中を緩和させることができ、これによって薄い活性層で十分な高耐圧特性を得ることを可能とした誘電体分離構造の高耐圧半導体素子を実現することが可能となる。
【０１０２】
また、第２の発明によれば、活性層の厚さが０．３μｍ以下であっても、活性層の横方向の不純物濃度分布を、それぞれガウス分布である２〜１０段の階段状とし、各階段の間隔を拡散長の２倍以上とすることによって、ドリフト領域の長さを大きくすることなく、高耐圧の横型誘電体分離半導体素子を実現することが可能である。
【図面の簡単な説明】
【図１】本発明の第１の実施例に係わる高耐圧ダイオードの素子構造を示す断面図。
【図２】第１の実施例でｐ型アノード層を酸化膜よりも浅く形成した例を示す断面図。
【図３】第１の実施例でｎ型カソード層を酸化膜よりも浅く形成した例を示す断面図。
【図４】第１の実施例でｐ型アノード層及びｎ型カソード層を酸化膜よりも浅く形成した例を示す断面図。
【図５】第１の実施例でｎ型カソード層の３重拡散深さを一定とした例を示す断面図。
【図６】図５の例でｐ型アノード層を酸化膜よりも浅く形成した例を示す断面図。
【図７】第１の実施例においてｎ型カソード層を２重拡散で形成した例を示す断面図。
【図８】第１の実施例で高抵抗体膜をｐ型アノード層及びｎ型カソード層に接続した例を示す断面図。
【図９】第１の実施例において高抵抗体膜を活性層上に直接形成した例を示す断面図。
【図１０】第１の実施例で高抵抗体膜を省略した例を示す断面図。
【図１１】本発明の第２の実施例に係わる高耐圧ＭＯＳＦＥＴの素子構造を示す断面図。
【図１２】第２の実施例でｎ型ソース層を酸化膜に達するよう形成した例を示す断面図。
【図１３】第２の実施例で高抵抗体膜を活性層上に直接形成した例を示す断面図。
【図１４】第２の実施例で高抵抗体膜の両端を電極に接続した例を示す断面図。
【図１５】第２の実施例で高抵抗体膜の一端を不純物ドープ多結晶シリコン膜を介して電極に接続した例を示す断面図。
【図１６】第２の実施例において高抵抗体膜を省略した例を示す断面図。
【図１７】第３の実施例に係わる横型ＩＧＢＴの素子構造を示す断面図。
【図１８】第３の実施例でｎ型ソース層及びｐ型ドレイン層を酸化膜に達する深さまで形成した例を示す断面図。
【図１９】第３の実施例で高抵抗体膜を活性層上に直接形成した例を示す断面図。
【図２０】第３の実施例で高抵抗体膜の両端を電極に接続した例を示す断面図。
【図２１】第３の実施例で高抵抗体膜の一端を不純物ドープ多結晶シリコン膜を介して電極に接続した例を示す断面図。
【図２２】第３の実施例において高抵抗体膜を省略した例を示す断面図。
【図２３】活性層の不純物総量と耐圧との関係を示す特性図。
【図２４】本発明の第４の実施例に係わる横型ＩＧＢＴの素子構造を示す断面図。
【図２５】図２４の構成で活性層を厚く形成した実施例を示す断面図。
【図２６】活性層厚さに対するオン電圧とスイッチングオフ時間の関係を示す特性図。
【図２７】図２４の構造を基本として、活性層の表面全体からｎ型不純物層を拡散した実施例を示す断面図、
【図２８】図２７の構造でｎ^- 型活性層の代わりにｐ^- 型の活性層を用いた実施例を示す断面図。
【図２９】図２４の構造を基本として、活性層の底面全体からｎ型不純物層を拡散した実施例を示す断面図。
【図３０】図２４の構造を基本として、ｎベース層を拡散窓の幅を変えて２重以上に拡散した実施例を示す断面図。
【図３１】図３０の構造を基本として、活性層の表面全体からｎ型不純物層を拡散した実施例を示す断面図。
【図３２】図３１の構造でｎ^- 型活性層の代わりにｐ^- 型の活性層を用いた実施例を示す断面図。
【図３３】図３０の構造を基本として、活性層の底面全体からｎ型不純物層を拡散した実施例を示す断面図。
【図３４】図２４の構造で一部変形したサイリスタの実施例を示す断面図。
【図３５】図２５の実施例においてドレイン部分を変形した横型ＩＧＢＴの例を示す断面図。
【図３６】図２５の実施例のドレイン部分を変形した例を示す断面図。
【図３７】図２５の実施例を変形した例を示す断面図。
【図３８】図２５の実施例を変形した例を示す断面図。
【図３９】図２５の実施例を変形した例を示す断面図。
【図４０】図２５の実施例を変形した例を示す断面図。
【図４１】本発明の第５の実施例に係わる高耐圧ダイオードを示す素子構造断面図。
【図４２】図４１の構造を基本として、活性層底部のｎ型バッファ層を選択的に形成した例を示す断面図。
【図４３】バッファ層の拡散長２×（Ｄｔ）^1/2 と素子耐圧との関係を示す特性図。
【図４４】図４１の構造を基本として、活性層の底部のバッファ層を選択的に形成した例を示す断面図。
【図４５】図４１の構造に対して活性層の厚さが薄い場合の例を示す断面図。
【図４６】本発明の第６の実施例に係わる高速ダイオードを示す素子構造断面図。
【図４７】誘電体分離基板に形成したダイオードのオン電圧Ｖf 及び逆回復時間ｔrrと半導体基板の厚さｔs の関係を示す特性図。
【図４８】本発明の第７の実施例に係わる誘電体分離半導体基板の概略構成を示す平面図及び断面図。
【図４９】図４８の誘電体分離半導体基板の製造工程を示す断面図。
【図５０】図４８の実施例の変形例を示す断面図。
【図５１】誘電体分離構造を用いた横型の高耐圧ダイオードの従来例を示す断面図。
【図５２】拡散長とブレ−クダウン電圧との関係を示す特性図。
【図５３】階段数とブレ−クダウン電圧との関係を示す特性図。
【図５４】本発明の第８の実施例に係る誘電体分離半導体素子の一例を示す断面図。
【図５５】活性層に３回の拡散を行なったときの活性層の横方向の不純物濃度分布を示す特性図。
【図５６】素子のブレ−クダウン電圧をパラメ−タ−としたときの階段数と拡散長との関係を示す特性図。
【図５７】誘電体分離構造を用いた横型の高耐圧ダイオードの従来例を示す断面図。
【符号の説明】
１０…シリコン基板
１１…シリコン酸化膜（分離絶縁膜）
１２…ｎ^- 型高抵抗シリコン層（活性層）
１３…ｐ型アノード層（第２導電型不純物層）
１４…ｎ型カソード層（第１導電型不純物層）
１５…アノード電極
１６…カソード電極
１８…高抵抗体膜
２１…ゲート電極
２３…ｐ型ベース層
２４…ｎ型ドレイン層
２５…ソース電極
２６…ドレイン電極
２８…不純物ドープ多結晶シリコン膜
３４…ｎ型ベース層
３６…ｐ型ドレイン層。[0001]
[Industrial application fields]
The present invention relates to a high breakdown voltage semiconductor element having a dielectric isolation structure, and more particularly to a high breakdown voltage semiconductor element having an improved diffusion layer shape.
[0002]
[Prior art]
Conventionally, various high voltage semiconductor elements using a dielectric isolation structure have been proposed. FIG. 51 shows a conventional example of a lateral type high voltage diode using a dielectric isolation structure. N on the semiconductor substrate 1 through the isolation insulating film 2^-A type silicon layer (active layer) 3 is formed. In addition, a p-type anode layer 5 and an n-type cathode layer 6 spaced apart from the p-type anode layer 5 are formed on the surface portion of the active layer 3, and an anode electrode 7 and a cathode electrode 8 are formed respectively.
[0003]
In such a horizontal diode, consider a reverse bias state in which, for example, the substrate 1 and the anode electrode 7 are grounded and a positive voltage is applied to the cathode electrode 8. At this time, the voltage applied to the n-type cathode layer 6 is shared by the depletion layer extending to the active layer 3 below the n-type cathode layer 6 and the isolation insulating film 2. Therefore, if the thickness of the active layer portion under the n-type cathode layer 6 is thin, a large electric field is shared here, and electric field concentration occurs at the edge portion (near the curved portion at the bottom) of the n-type cathode layer 6. Avalanche breakdown occurs at low applied voltage. In order to avoid this and realize a sufficiently high breakdown voltage, conventionally, the thickness of the active layer 3 has been set to 20 μm or more.
[0004]
However, if the thickness of the active layer is large, a deep isolation groove is required when element isolation in the lateral direction is performed by a V-shaped groove or the like, and the area of the isolation groove region is large. Therefore, not only is the processing difficult, but the effective area of the element on the wafer is reduced, resulting in an increase in the cost of the integrated circuit of the high breakdown voltage element.
[0005]
On the other hand, the dielectric isolation structure makes it possible to create a high voltage element and a logic circuit on the same substrate. In that case, according to SOI (Silicon on insulator) technology for forming an element in a semiconductor layer (active layer) formed on an insulating film, it is possible to completely separate a high voltage element and a logic circuit.
[0006]
Such a semiconductor device using an SOI substrate is known to be able to obtain a high breakdown voltage in the vertical direction because of an insulating film even if the thickness of the active layer is reduced to 0.3 μm or less. Since element isolation using a groove is possible, this element isolation structure is a powerful structure in a power IC.
[0007]
However, when the active layer is thin like this, in order to increase the lateral breakdown voltage, the impurity doping concentration of the n drift region in the active layer has to be lowered. The length of the n drift region is necessary. In order to avoid this, for example, as shown in FIG. 57, a method of uniforming the electric field strength in the lateral direction by forming a SIPOS (semi-insulating doped silicon) layer 18 along the drift region, As disclosed in Japanese Patent No. 4-309234, a method of forming a linear doping concentration distribution in the lateral direction is conceivable. However, these methods require special steps and are difficult to implement.
[0008]
[Problems to be solved by the invention]
As described above, the conventional high breakdown voltage semiconductor element having a dielectric isolation structure has a problem that a sufficient breakdown voltage cannot be obtained if the active layer is thin, and lateral isolation becomes difficult if the active layer is thick. It was.
[0009]
In the drift region, when the active layer is thin, the impurity doping concentration of the n drift region in the active layer must be lowered in order to increase the lateral breakdown voltage. There is a problem that it is necessary to increase the length of the drift region, which makes it difficult to miniaturize the element.
[0010]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a high breakdown voltage semiconductor element having a dielectric isolation structure capable of obtaining a sufficiently high breakdown voltage characteristic with a thin active layer. There is.
[0011]
Another object of the present invention is to provide a high breakdown voltage semiconductor element having a dielectric isolation structure that can obtain a sufficiently high breakdown voltage characteristic without increasing the length of the drift region.
[0012]
[Means for Solving the Problems]
The gist of the present invention is to alleviate the electric field concentration at the edge portion (especially near the curved surface portion of the bottom portion) of the diffusion layer by devising the shape of the diffusion layer.
[0013]
  That is, the first aspect of the first invention is a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and an active layer made of a high-resistance semiconductor of the first conductivity type formed on the insulating layer. A first impurity layer of a first conductivity type formed in the active layer, and a second impurity of a second conductivity type formed in the active layer and formed at a predetermined distance from the first impurity layer. 2 impurity layers, a first electrode formed on the first impurity layer, and a second electrode formed on the second impurity layer, and the first impurity The layer includes a plurality of mutually stacked diffusion layers having different diffusion window widths or diffusion depths, and the first impurity layer and the second impurity layer reach the bottom of the active layer. A high voltage semiconductor device is provided.
  According to a second aspect of the first invention, a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and an active layer made of a high-resistance semiconductor of the first conductivity type formed on the insulating layer. A first impurity layer of a first conductivity type formed in the active layer, and a second impurity of a second conductivity type formed in the active layer and formed at a predetermined distance from the first impurity layer. 2 impurity layers, a third impurity layer of the second conductivity type formed in the first impurity layer, a first electrode formed on the third impurity layer, and the second electrode A second electrode formed on the impurity layer, wherein the first impurity layer comprises a plurality of mutually stacked diffusion layers having different diffusion window widths or diffusion depths. And the first impurity layer and the second impurity layer reach the bottom of the active layer. To provide a semiconductor element.
[0014]
Further, as preferred embodiments of the first invention, the following may be mentioned.
[0015]
  (1) A high resistance film is formed on the active layer between the impurity layers of the first conductivity type and the second conductivity type.
[0016]
  (2)The total amount of impurities in the active layer is 1 × 10¹⁰cm^-2~ 2x10¹²cm^-2Set to the range.
[0017]
A second invention is a high voltage semiconductor device comprising a semiconductor substrate and an active layer formed on the semiconductor substrate through an insulating film and having a thickness of 0.3 μm or less made of a high resistance semiconductor. The active layer is characterized in that the lateral impurity concentration distribution has a step shape of 2 to 10 steps each having a Gaussian distribution, and the interval between the steps is at least twice the diffusion length.
[0018]
[Action]
In the high breakdown voltage semiconductor element having a dielectric isolation structure, it is assumed that a high voltage with a reverse bias is applied to the first conductivity type impurity layer in a state where the second conductivity type impurity layer and the substrate are grounded. At this time, the voltage applied to the first conductivity type impurity layer is shared by the active layer and the insulating film in the vertical direction. Here, when electric field concentration occurs in the vicinity of the curved surface portion at the bottom of the first conductivity type impurity layer, avalanche breakdown occurs at a low voltage.
[0019]
In the first invention, the first conductivity type impurity layer is formed in a double or more diffusion layer while changing the width and diffusion depth of the diffusion window, thereby concentrating the electric field in the vicinity of the curved surface at the bottom of the diffusion layer. Can be relaxed. That is, the electric field concentration inside the active layer, particularly the electric field concentration in the vicinity of the curved surface of the bottom of the diffusion layer can be alleviated, and an unprecedented high breakdown voltage device can be realized. Furthermore, since the thickness of the active layer can be reduced, lateral element isolation is also facilitated.
[0020]
Further, by forming the first conductivity type and second conductivity type impurity layers to a depth reaching the insulating film, the voltage applied to the first conductivity type impurity layer can be shared only by the insulating film, The longitudinal electric field of the layer is kept small. Further, by providing a high resistance film on the surface of the active layer, the lateral potential distribution on the surface of the active layer can be made uniform according to the uniform potential distribution formed in the film. As a result, the electric field concentration inside the active layer can be effectively mitigated, and a thin and unprecedented high breakdown voltage device can be realized.
[0021]
In the second invention, a general impurity diffusion technique is performed a plurality of times to make the concentration distribution in the lateral direction of the active layer stepwise, so that even if the thickness of the active layer is 0.3 μm or less, the drift Provided is a dielectric isolation semiconductor element capable of achieving a high breakdown voltage without increasing the length of the region.
[0022]
The reason why the dielectric isolation semiconductor device according to the second invention exhibits a high breakdown voltage is considered to be based on the following principle.
[0023]
The horizontal direction is the x axis and the vertical direction is the y axis. If the thickness of the active layer is 0.3 μm or less, it is considered that the impurity concentration distribution in the vertical direction when impurities are diffused is substantially uniform. Thus, assuming that the lateral impurity concentration distribution is a Gaussian distribution, the following expression is given.
[0024]
n (x, y) = n_oexp (-x²/ A²)
Where a is the diffusion length (a = 2D_t ^1/2, N₀Represents a difference in impurity concentration in the staircase portion. At this time, the maximum value of the concentration gradient Δn_maxX = a · 2^-1/2Is obtained as shown in the following formula.
[0025]

The electric field strength in the horizontal direction and the vertical direction can be obtained by solving the Poisson equation. n (x) = (ε_s/ Q) (dE_x/ D_x+ DE_y/ D_y)
Where ε_sIs the dielectric constant for Si and q is the elementary charge. In order to obtain the avalanche breakdown voltage of the element, ionization integration is performed as shown in the following formula 2.
[0026]
I = ∫α (E) dX
Here, α (E) is an ionization coefficient and is obtained by the following equation.
[0027]
α (E) = A · exp (−B / E)
Here, A and B are constants. In general, the Poisson equation and the ionization integral cannot be obtained analytically, so numerical calculation is performed. As a result, n₀It was found that and a have the relationship represented by the following formula.
[0028]
n₀/ A^1/2≦ 1 × 10¹⁹
Therefore, the maximum concentration gradient Δn_maxMust satisfy the following equation.
[0029]
Δn_max≦ 0.85776 × 10¹⁹/ A^1/2
On the other hand, in the step portion of the staircase, the electric field strength in the lateral direction is much smaller than that of the step portion, so it is better to reduce the interval between the staircases. However, if the interval between the steps is too small, interference occurs between adjacent steps and the electric field becomes strong. Therefore, the interval between steps should be at least twice the diffusion length, preferably about 3 to 4 times.
[0030]
  FIG. 52 shows a breakdown voltage when the diffusion length is changed, and FIG. 53 shows a breakdown voltage when the diffusion number is changed. From these figures,Second inventionAccording to this, it is possible to realize a high breakdown voltage dielectric isolation semiconductor element without increasing the length of the drift region.
[0031]
【Example】
Embodiments of the present invention will be described below with reference to the drawings.
[0032]
FIG. 1 is a cross-sectional view showing an element structure of a high voltage diode according to a first embodiment of the present invention. N on a silicon substrate 10 with a silicon oxide film (isolation insulating film) 11 interposed therebetween.^-A high-resistance silicon layer (active layer) 12 of the type is formed. This structure is formed, for example, by forming a silicon oxide film 11 on the surface of the silicon substrate 10, directly bonding another silicon substrate having a mirror-polished surface, and processing the substrate thinly. The silicon oxide film 11 has a thickness of about 1 to 5 μm. n^-The type active layer 12 has a total impurity amount of 1 × 10^Tencm^-2~ 2x10¹²cm^-2In the range of 0.5 to 1.8 × 10, more preferably¹²cm^-2The thickness was set to about 10 μm.
[0033]
A p-type anode layer 13 and an n-type cathode layer 14 are formed on the active layer 12 at a predetermined distance. The p-type anode layer 13 and the n-type cathode layer 14 are diffused to a depth that reaches the silicon oxide film 11 at the bottom of the active layer as shown in the figure. Further, the n-type cathode layer 14 has triple diffusion layers 14a, 14b, and 14c by changing the width and diffusion depth of the diffusion window. The total amount of impurities in the diffusion layers other than 14a, that is, the diffusion layers 14b and 14c here is 1 × 10¹¹cm^-2~ 3x10¹²cm^-2Set to the range. An anode electrode 15 and a cathode electrode 16 are formed on the p-type anode layer 13 and the n-type cathode layer 14, respectively. A high resistance film 18 is disposed on the active layer 12 between these electrodes 15 and 16 via a silicon oxide film 17. The high resistance film 18 is, for example, SIPOS (Semi-Insulating Polycrystalline Silicon), and both ends of the high resistance film 18 are connected to the electrodes 15 and 16, respectively. The surface of the high resistance film 18 is covered with a silicon oxide film 19 as a protective film.
[0034]
In this configuration, consider a case where the p-type anode layer 13 and the substrate 10 are grounded and a positive high voltage is applied to the n-type cathode layer 14. Since the n-type cathode layer 14 is formed to a depth reaching the bottom of the active layer, all voltages applied to the n-type cathode layer 14 are shared by the silicon oxide film 11 in the vertical direction. Here, the silicon oxide film 11 has a sufficiently high breakdown voltage compared to the active layer 12.
[0035]
In addition, a minute current flows through the high resistance film 18 formed on the surface of the active layer 12 due to the anode-cathode voltage, and a uniform potential distribution is formed in the lateral direction. Under the influence of the potential distribution in the high resistance film 18, a uniform potential distribution is also formed in the lateral direction on the surface of the active layer immediately below the high resistance film. Furthermore, by diffusing the n-type cathode layer 13 in a triple manner, the impurity concentration gradient at the curved surface portion at the bottom of the diffusion layer is relaxed, and this causes the interval between equipotential lines to be widened and extreme electric field concentration to be prevented. As a result, the electric field concentration inside the device is relaxed and a high breakdown voltage is realized.
[0036]
In the configuration as described above, the breakdown voltage also changes when the total amount of impurities in the active layer 12 is changed. FIG. 23 is a characteristic diagram showing the relationship between the total amount of impurities in the active layer 12 and the breakdown voltage. Total amount of impurities is 1 × 10^Tencm^-2As described above, the breakdown voltage increases as the total amount of impurities increases, and the total amount of impurities becomes 3 × 10 5.¹²cm^-2If it exceeds, the pressure resistance will drop rapidly. Therefore, the total amount of impurities in the active layer 12 is 1 × 10^Tencm^-2~ 2x10¹²cm^-2A range of is desirable.
[0037]
As described above, according to this embodiment, the n-type cathode layer 14 is formed by triple diffusion, is formed to a depth reaching the silicon oxide film 11, and the high resistance film 18 is formed on the active layer 12. As a result, the electric field concentration inside the device can be alleviated, and a high breakdown voltage diode can be realized even if the active layer 12 is thinned.
[0038]
Modifications of the first embodiment are shown in FIGS. FIG. 2 shows the p-type anode layer 13 formed shallower than the silicon oxide film 11 in the first embodiment. In FIG. 3, the n-type cathode layer 14 is formed shallower than the silicon oxide film 11. In FIG. 4, the p-type anode layer 13 and the n-type cathode layer 14 are both formed shallower than the silicon oxide film 11. Even with such a configuration, since the electric field concentration at the edge portion of the n-type cathode layer 14 is relaxed, the same effect as in the first embodiment can be obtained.
[0039]
In FIG. 5, the depth of the n-type cathode layer 14 is constant at the depth reaching the silicon oxide film 11, and the length of the lateral diffusion window in triple diffusion is changed. Here, the impurity concentration of 14a, 14b, and 14c decreases in order. Even with such a configuration, by increasing the interval between the equipotential lines in the lateral direction, extreme electric field concentration can be prevented, and the same effect as in the first embodiment can be obtained. Note that the impurity concentration may be continuously varied instead of performing multiple diffusions with different impurity concentrations.
[0040]
FIG. 6 applies the idea of FIG. 2 to the configuration of FIG. In FIG. 7, the n-type cathode layer 14 is formed by double diffusion instead of triple diffusion.
[0041]
In FIG. 8, the high resistance film 18 is directly connected to the p-type anode layer 13 and the n-type cathode layer 14 together with the electrodes 15 and 16. In FIG. 9, the high resistance film 18 is formed directly on the active layer 12. Even in this case, since the resistance of the high-resistance film 18 is sufficiently high, the anode layer 13 and the cathode layer 14 are not short-circuited, and the potential distribution between them can be made uniform.
[0042]
In FIG. 10, only the protective insulating film 19 is formed on the active layer 12 without using the high resistance film 18. In this case, the potential distribution cannot be made uniform by the high resistance film 18, but the n-type cathode layer 14 is formed by triple diffusion and the diffusion depth is formed to a depth reaching the silicon oxide film 11. Therefore, the effect of reducing the electric field concentration by these can be obtained.
[0043]
FIG. 11 is a cross-sectional view showing the element structure of a high voltage MOS transistor according to the second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 1 and an identical part, and the detailed description is abbreviate | omitted.
[0044]
N on the substrate 10 via the silicon oxide film 11.^-The structure in which the mold active layer 12 is formed is the same as in FIG. The total amount of impurities in the active layer 12 is the same as in the first embodiment. In the active layer 12, a p-type base layer 23 and an n-type drain layer 24 corresponding to the p-type anode layer 13 and the n-type cathode layer 14 in the first embodiment are formed.
[0045]
An n-type source layer 22 is formed in the p-type base layer 23, and the n-type source layer 22 and n^-Using the surface portion of the p-type base layer 23 sandwiched between the p-type active layers 12 as a channel region, a gate electrode 21 is formed thereon with a gate oxide film of about 60 nm interposed therebetween.
[0046]
A high resistance film 18 is formed on the surface of the active layer sandwiched between the p-type base layer 23 and the n-type drain layer 24 via the silicon oxide film 17 as in the first embodiment. The resistor film 18 is covered with a silicon oxide film 19.
[0047]
The source electrode 25 is formed on the n-type source layer 22 and the p-type base layer 23 so as to be in contact with each other simultaneously, and the drain electrode 26 is formed on the n-type drain layer 24. The ends of the high resistance film 18 are connected to the gate electrode 21 and the drain electrode 26, respectively. Here, the gate electrode 21 is 0 V when off and is the same as the ground, and even when it is on, the voltage is sufficiently lower than the high voltage applied to the drain electrode 26, so that the high-resistance film 18 includes the gate electrode 21 and the drain electrode 26. Even if they are connected to each other, the same function as in the first embodiment is achieved.
[0048]
The MOSFET of this embodiment also has excellent high breakdown voltage characteristics similar to the diode of the first embodiment due to the triple diffusion of the n-type drain layer 24, the diffusion reaching the silicon oxide film 11, and the action of the high resistance film 18. Is obtained.
[0049]
Modifications of the second embodiment are shown in FIGS. In FIG. 12, the n-type source layer 22 is formed to a depth that reaches the oxide film 11. In FIG. 13, the high-resistance film 18 is formed directly on the active layer 12. In FIG. 14, the high resistance film 18 is connected to the source electrode 25 instead of the gate electrode 21.
[0050]
In FIG. 15, the drain side end portion of the high resistance film 18 is connected to the drain electrode 26 through the impurity-doped polycrystalline silicon film 28. Here, the contact resistance between the high-resistance film 18 and the drain electrode 26 is large, but the contact resistance between the high-resistance film 18 and the impurity-doped polycrystalline silicon film 28 is extremely small, and the drain electrode 26 and the impurity-doped polycrystalline film. Since the contact resistance with the silicon film 28 is also extremely small, the contact resistance between the high resistance film 18 and the drain electrode 26 can be reduced by interposing the impurity-doped polycrystalline silicon film 28.
[0051]
In FIG. 16, the high resistance film 18 is omitted. Although not shown in the drawing, the p-type base layer 23, the n-type drain layer 24, etc. may be formed shallower than the silicon oxide film 11 as in FIGS. 2 to 4 in the first embodiment. Further, similarly to the example of FIG. 5, the n-type drain layer 24 may have a constant diffusion depth by changing the length of the lateral diffusion window in triple diffusion.
[0052]
FIG. 17 is a sectional view showing the element structure of an IGBT (Insulated Gate Bipolar Transistor) according to the third embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 11 and an identical part, and the detailed description is abbreviate | omitted.
[0053]
The basic configuration is the same as that of FIG. 11, but in this embodiment, the n-type base layer 34 corresponds to the n-type drain layer 24 of FIG. 36 is formed.
[0054]
With such a configuration, it is possible to realize a lateral IGBT in which a bipolar transistor and a power MOSFET are monolithically combined in one chip. In this case, as in the first embodiment, the triple diffusion of the n-type base layer 34, the diffusion reaching the silicon oxide film 11, and the action of the high resistance film 18 cause the edge portion of the n-type base layer 34. Electric field concentration can be relaxed and breakdown voltage can be improved.
[0055]
Modifications of the third embodiment are shown in FIGS. 18, the active layer 12 is thinned so that the n-type source layer 22 and the p-type drain layer 36 reach the silicon oxide film 11 as in the example of FIG. At this time, since the p-type drain layer 36 is in contact with the silicon oxide film 11, a channel of the p-type inversion layer may be formed at the bottom of the active layer. In order to prevent this, it is necessary to set the impurity concentration of the n-type base layer 34 high. Specifically, the impurity concentration of the n-type base layer 34 is 1 × 10 5.¹⁷cm^-3That is all you need. Alternatively, if the p-type drain layer 36 does not reach the silicon oxide film 11 as in the example of FIG. 17, channel formation by the p-type inversion layer at the bottom of the active layer can be avoided.
[0056]
In FIG. 19, the high resistance film 18 is formed directly on the active layer 12. In FIG. 20, the high resistance film 18 is connected to the source electrode 25 instead of the gate electrode 21.
[0057]
In FIG. 21, the drain side end of the high resistance film 18 is connected to the drain electrode 26 through the impurity-doped polycrystalline silicon film 28. Also in this case, the contact resistance between the high resistance film 18 and the drain electrode 26 can be reduced by interposing the impurity-doped polycrystalline silicon film 28 as in the example of FIG.
[0058]
In FIG. 22, the high resistance film 18 is omitted. Although not shown in the drawing, the p-type base layer 23, the n-type base layer 34, and the like may be formed shallower than the silicon oxide film 11 as in FIGS. 2 to 4 in the first embodiment. Further, similarly to the example of FIG. 5, the n-type base layer 34 may have a constant diffusion depth by changing the length of the lateral diffusion window in triple diffusion.
[0059]
Next, another embodiment of the present invention will be described. FIG. 24 is a cross-sectional view showing a schematic configuration of the fourth embodiment. This embodiment is an example of a lateral IGBT. N having a thickness of 5 μm or less is formed on the silicon substrate 50 via a silicon oxide film 51.^-A type high resistance silicon layer (active layer) 52 is formed.
[0060]
The silicon oxide film 51 has a thickness of about 1 to 5 μm. A p base 53 layer and an n base layer (buffer layer) 54 are formed by diffusion in the active layer 52 at a depth reaching the silicon oxide film 51 at a predetermined distance. Further, n in the p base layer 53⁺Type source layer 55 in the n base layer 54⁺A mold drain layer 56 is formed by diffusion. n⁺Type source layer 55 and n^-A surface portion of the p base layer 53 sandwiched between the p-type active layers 52 is used as a channel region, and a gate electrode 57 is formed thereon with a gate oxide film of about 60 nm interposed therebetween. The source electrode 58 is n⁺The source electrode 55 is formed so as to contact the p-type source layer 55 and the p base layer 53 simultaneously, and the drain electrode 59 is formed so as to contact the p-type drain layer 56. An insulating protective film 60 is formed on the active layer 52 between the electrodes 58 and 59.
[0061]
FIG. 25 shows the structure of FIG. 24 in which the n-type active layer 52 is formed thick and the n-type active layer 52 remains at the bottom of the n-type buffer layer 54. An n-type buffer layer 54 is formed on the surface of the n-type active layer 52, and a p-type drain layer 56 is formed therein. The n-type buffer layer 54 functions to prevent punch-through and increase the breakdown voltage. In addition, since the hole injection efficiency from the p-type drain layer 56 is lowered, the turn-off speed is increased instead of increasing the on-resistance of the element.
[0062]
The thickness and on-resistance of the n-type active layer 52 of the device having this structure, 100 A / cm²FIG. 26 shows the relationship between the on-resistance and the turn-off fall time when a current of. The broken line part is the simulation result. As the n-type active layer 52 becomes thinner, the on-resistance gradually increases, but the turn-off speed is remarkably increased. In particular, when the thickness is 10 μm or less, the effect is remarkable. On the other hand, if the thickness is too thin, the on-resistance increases rapidly, so it is desirable to set the thickness of the n-type active layer 52 in the range of 4 μm to 10 μm.
[0063]
FIG. 27 shows an embodiment in which the n-type impurity layer 61 is diffused from the entire surface of the active layer 52 based on the structure of FIG. The thickness of the active layer 52 is 10 μm or less, preferably 5 μm or less. In this structure, a concentration gradient in the vertical direction is formed in the active layer 52, and the electric field concentration at the bottom of the active layer is effectively mitigated, so that a higher breakdown voltage can be obtained with an improved trade-off.
[0064]
FIG. 28 shows the structure of FIG.^-P instead of type active layer 52^-In this embodiment, the n-type impurity layer 61 is diffused from the entire surface of the active layer 62. Also in this case, a high breakdown voltage can be obtained for the same reason as in the embodiment of FIG.
[0065]
FIG. 29 shows an embodiment in which the n-type impurity layer 63 is diffused from the entire bottom surface of the active layer 52 based on the structure of FIG. Even in this structure, there is a vertical concentration gradient in the active layer 52, the electric field concentration at the bottom of the active layer is relaxed, and a high breakdown voltage is obtained with an improved trade-off.
[0066]
FIG. 30 shows an embodiment in which the n base layer 54 is diffused twice or more by changing the width of the diffusion window based on the structure of FIG. Even in this structure, the electric field in the lateral direction is relaxed by the effect of the double or more diffusion layers 54 ′ and 54 ″, and a high breakdown voltage can be obtained with an improved trade-off as in the embodiment of FIG.
[0067]
FIGS. 31 to 33 are examples in which the active layer is modified in the same manner as the examples of FIGS. 27 to 29 on the basis of the structure of FIG. Even in these structures, a high breakdown voltage can be obtained with an improved trade-off as in the embodiment of FIG.
[0068]
FIG. 34 shows an embodiment of a thyristor partially modified with the structure of FIG. In FIG. 34, reference numeral 77 different from FIG. 24 is a gate, 78 is a cathode, and 79 is an anode. The present invention can also be applied to other lateral structure high voltage devices such as EST, MCT, GTO and the like.
[0069]
FIG. 35 is an example of a lateral IGBT in which the drain portion is modified in the embodiment of FIG. A high-concentration n-type layer 65 and a p-type layer 66 are formed on the surface of the p-type drain layer 56, and the drain electrode 59 is in contact with both of them. The n-type layer 65 is provided to limit the hole injection efficiency and has a function of speeding up the turn-off. In plan view, the n-type layer 65 may be a single stripe or a plurality of islands. The p-type layer 66 is provided to improve the drain contact, but may not be provided. Also in this embodiment, since the n-type active layer 52 is thin and preferably set to 10 μm or less, the turn-off speed is further increased.
[0070]
FIG. 36 is also a modification of the drain portion of the embodiment of FIG. An anode short type IGBT in which a part of the n-type buffer layer 54 is in contact with the drain electrode 59, and the turn-off speed is high. Further, since the n-type active layer 52 is set thin, the turn-off speed is higher. In this embodiment, a high-concentration n-type layer for reducing the contact resistance may be provided at the contact portion between the n-type buffer layer 54 and the drain electrode 59.
[0071]
FIG. 37 is a modification of the embodiment of FIG. An n-type layer 67 having an impurity concentration higher than that of the n-type active layer 52 is formed at the bottom of the n-type active layer 52. Generally, when the thickness of the n-type active layer 52 is reduced, the vertical electric field under the drain is increased when a voltage is applied, and the breakdown voltage is reduced. In the element of FIG. 37, the space charge generated by depletion of the n-type layer 67 relaxes the electric field in the active layer 52 instead of increasing the electric field in the oxide film 51, so that a high breakdown voltage is maintained. Also in this embodiment, since the n-type active layer 52 is thin, a fast turn-off speed can be obtained.
[0072]
FIG. 38 is a modification of the embodiment of FIG. Above the oxide film 51 is a p-type silicon layer 68, on which an n-type active layer 52 is diffused to form an element. By making the thickness of the p-type semiconductor layer 68 including the n-type active layer 52 thin, preferably 10 μm or less, a lateral IGBT having a high turn-off speed is obtained.
[0073]
FIG. 39 is a modification of the embodiment of FIG. As in the example of FIG. 38, the n-type active layer 52 is diffused and formed on the surface of the p-type silicon layer 68 separated from the silicon substrate (support substrate) 50 by the oxide film 51, and an element having the same configuration as that of FIG. Has been.
[0074]
FIG. 40 is a modification of the embodiment of FIG. 25, but uses a dielectric isolation substrate different from the previous modification. In order to increase the breakdown voltage, a SIPOS film 69 is provided between the n-type active layer 52 and the oxide film 51. This may be a high resistance film or a high dielectric constant film other than the SIPOS film 69. Also in this embodiment, the turn-off speed is increased by setting the n-type active layer 52 thin.
[0075]
Of course, the embodiments shown in FIGS. 24, 25, and 27 to 40 can be applied to p-channel lateral IGBTs whose conductivity types are all reversed.
[0076]
Next, a fifth embodiment of the present invention will be described. FIG. 41 is a sectional view of an element structure showing a high voltage diode according to the fifth embodiment. N on the silicon substrate 10 via the silicon oxide film 11.^-A high-resistance silicon active layer 12 of the type is formed. A high impurity concentration p which becomes an anode region at a predetermined distance from the silicon active layer 12⁺N of the mold layer 13 and the high impurity concentration layer serving as the cathode region⁺A mold layer 14 is formed. p⁺An anode electrode 15 is formed on the mold layer 13, and n⁺A cathode electrode 16 is formed on the mold layer 14. An n-type buffer layer 71 is formed at the bottom of the silicon active layer 12.
[0077]
In the high breakdown voltage diode configured as described above, when the substrate 10 and the electrode 15 are grounded and a positive potential is applied to the electrode 16, the pn junction is reverse-biased and a depletion layer spreads in the silicon active layer 12. A depletion layer also spreads upward from the interface between the oxide film 11 and the silicon active layer 12. When the applied voltage exceeds a certain value, the silicon active layer 12 is filled with the depletion layer, and there is n in the silicon active layer 12.⁺A strong electric field is generated downward from the mold layer 13.
[0078]
Further, when the n-type buffer layer 71 formed at the bottom of the silicon active layer 12 is applied with a reverse bias and the buffer layer 71 is depleted, positive space charges are generated here. As a result of the space charge acting to relax the electric field in the silicon active layer 12, more applied voltage is shared by the intermediate oxide film at the bottom of the silicon active layer, and high breakdown voltage characteristics are obtained. The total amount of impurities in the buffer layer 71 is 3 × 10.¹²cm^-2Below, more desirably 5 × 10¹¹~ 2x10¹²cm^-2Is set to be
[0079]
FIG. 43 shows the diffusion length 2 × (Dt) of the n-type buffer layer 71.^1/2And the breakdown voltage of the device, the impurity doping amount is optimized for each diffusion length. This is a curve obtained when the total amount of impurities in the n-type buffer layer 71 is determined. In the range where the diffusion length is smaller than 1/2000 cm, the breakdown voltage is improved as the diffusion length is shortened, and a high breakdown voltage is obtained. In order to operate in the 200V system, a withstand voltage of 500V must be guaranteed, but a high withstand voltage of 500V or more can be obtained if the diffusion length is in a range smaller than 1/4000 cm.
[0080]
FIG. 42 shows a structure in which an n-type buffer layer 71 at the bottom of the silicon active layer 12 is selectively formed based on the structure of FIG. Since the applied voltage is greatly applied to the silicon active layer 12 immediately below the drain, a high breakdown voltage can be obtained by selectively forming the n-type buffer layer 72 only in this portion and relaxing the electric field.
[0081]
FIG. 44 shows an example in which the active layer 12 is thinner than the structure of FIG. If the active layer 12 is thin, the n-type impurity layer reaches the oxide film below the active layer. In this case, a higher breakdown voltage can be obtained by forming the n-type buffer layer at the bottom of the active layer.
[0082]
FIG. 45 shows an example in which the active layer 12 is thinner than the structure of FIG. Even in the structure in which the n-type impurity layer reaches the oxide film, the same effect can be obtained by selectively inserting the n-type buffer layer.
[0083]
As described above, according to the present embodiment, by forming the n-type buffer layer having a short diffusion length at the bottom of the active layer, a sufficiently high breakdown voltage can be obtained with a thin active layer. The configuration in which the n-type buffer layer is provided under the active layer as in this embodiment can also be applied to the first embodiment shown in FIGS.
[0084]
Next, another embodiment of the present invention will be described. In this embodiment, a high-speed diode is formed on a dielectric isolation substrate.
[0085]
FIG. 46 is a sectional view of an element structure showing a high-speed diode according to the sixth embodiment. An insulating film 83 is formed between the semiconductor substrate 81 and the high resistance n-type semiconductor substrate 82 to form a dielectric isolation substrate. A p-type anode layer 84 and an n-type cathode layer 85 are formed on the surface of a high-resistance n-type semiconductor substrate 82 of the dielectric isolation substrate. An anode electrode 86 is formed on the surface of the anode layer 84, and a surface of the cathode layer 85 is formed. Is formed with a cathode electrode 87.
[0086]
Up to this point, the structure is the same as that of the conventional structure, but in this embodiment, in addition to this, the anode layer 84 has n.⁺Type impurity layer 88 is selectively formed and p is formed on cathode layer 85.⁺An impurity layer 89 of a type is selectively formed, and an anode electrode 86 is connected to the anode layer 84 and n⁺The ohmic contact is made to both of the impurity layer 88 of the type, and the cathode electrode 87 is connected to the cathode layer 85 and p.⁺An ohmic contact is made with both of the impurity layers 89 of the type. The thickness of the semiconductor substrate 82 on which the anode layer 84 and the cathode layer 85 are formed is set to 2 to 10 μm.
[0087]
FIG. 47 shows the relationship between the on-voltage Vf and reverse recovery time trr of the diode formed on the dielectric isolation substrate and the thickness ts of the semiconductor substrate 82. The reverse recovery time trr was shortened as the thickness ts of the substrate 82 was reduced, and it was found that when ts ≦ 10 μm, trr ≦ 0.3 μsec was satisfied. However, it has been found that the on-voltage Vf increases rapidly when ts ≤ 2 µm. From this, if the thickness ts of the semiconductor substrate 82 is set to 2 to 10 μm, a diode capable of increasing the reverse recovery time without performing lifetime control such as electron beam irradiation can be realized.
[0088]
Next, a seventh embodiment of the present invention will be described. This embodiment relates to a dielectric isolation semiconductor substrate having an insulating film layer in the middle of the semiconductor substrate. 48A and 48B show the structure of a dielectric isolation semiconductor substrate according to the seventh embodiment, in which FIG. 48A is a plan view seen from the back surface, and FIG. 48B is a cross-sectional view taken along line AA ′. Two silicon substrates 91 and 93 are integrated via an oxide film 92, and the surface of the silicon substrate 91 is polished to a predetermined thickness. A lattice-like groove 94 is formed in the silicon substrate 93, and an oxide film 95 is buried in the groove 94.
[0089]
FIG. 49 shows a manufacturing process of this dielectric isolation semiconductor substrate. After silicon direct bonding, as shown in FIG. 49A, a lattice-shaped groove 94 having a width of several μm, preferably 1 μm or less and a depth of several μm to several tens of μm is formed in the silicon substrate 93. Subsequently, as shown in FIG. 49B, the trench 94 is filled with an oxide film 95. At this time, if the groove width is about 1 μm or less, the groove 94 can be completely embedded by thermal oxidation. Thereafter, as shown in FIG. 49B, the surface of the silicon substrate 91 is polished to a predetermined thickness.
[0090]
In this dielectric isolation semiconductor substrate, since the oxide film 92 and the oxide film 95 are formed so as to sandwich the silicon substrate 93, the warpage of the substrate can be suppressed small. In the step of removing the oxide film formed on the substrate surface at the time of element formation, the oxide film 95 is removed only on the surface, and the oxide film 95 remains in the trench 94. Therefore, it is not necessary to provide a protective film so that the oxide film on the back surface is not removed as in the prior art, and the process can be simplified.
[0091]
As described above, according to this embodiment, even if the thickness of the intermediate oxide film is increased, a dielectric-isolated semiconductor substrate having a small warp can be realized, the process can be simplified, and a low-cost power IC can be realized. It becomes possible to contribute to realization.
[0092]
FIG. 50 is a modification of the embodiment of FIG. The difference from FIG. 48 is that polysilicon 96 is formed on the surface of oxide film 95 by low pressure CVD. This embodiment is effective when the width of the groove 94 is 1 μm or more. When the width of the groove 94 is 1 μm or more, it becomes difficult to fill the groove 94 only by thermal oxidation. Therefore, the portion where the embedding is insufficient is buried with polysilicon 96. Further, in this embodiment, since the back surface of the substrate is polysilicon 96, there is an advantage that the oxide film 95 is not removed at all in the step of removing the oxide film at the time of element formation.
[0093]
In the seventh embodiment, silicon is used for the semiconductor substrate and an oxide film is used for the insulating film. However, the present invention is not limited to this and can be applied to other materials. In this embodiment, the dielectric isolation semiconductor substrate obtained by directly joining two semiconductor substrates is used. However, it is effective to use a dielectric isolation semiconductor substrate obtained by another method. FIG. 54 is a sectional view showing an example of a dielectric isolation semiconductor device according to the eighth example of the present invention. N on a silicon substrate 101 with a silicon oxide film (isolation insulating film) 102 interposed therebetween.^-A high-resistance silicon layer (active layer) 103 of the type is formed. The thickness of the silicon oxide film 102 is 3 μm, n^-The thickness of the mold active layer 103 is 0.1 μm. n^-The impurity concentration of the type active layer 103 is 1.0 × 10¹⁷/ Cm^ThreeIt is. n^-A drain region 104 and a source region 105 are formed in the type active layer 103, and a drain electrode 106 and a source electrode 107 are formed on the drain region 104 and the source region 105, respectively. Yes. Reference numerals 108 and 109 denote an insulating film and a gate electrode, respectively.
[0094]
n^-The impurity concentration distribution in the lateral direction of the type active layer 103 has a three-step shape. This step-like impurity concentration distribution can be obtained as follows.
[0095]
That is, n^-A first mask is formed on the mold active layer 103 to form 2 × 10¹²cm^-2Phosphorus ions are implanted with a dose of Then, using a second mask having a lateral opening wider than the first mask, 2 × 10¹²cm^-2Phosphorus ions are implanted with a dose of Furthermore, using a third mask having a lateral opening wider than the second mask, 2 × 10¹²cm^-2Phosphorus ions are implanted with a dose of Note that the difference between the openings in the lateral direction of the mask is at least twice the diffusion length, preferably 3 to 4 times.
[0096]
Next, heat treatment is performed at about 1200 ° C. to diffuse the ion-implanted phosphorus, thereby obtaining a three-stage stepwise impurity concentration distribution in the horizontal direction as shown in FIG. The avalanche breakdown voltage of the dielectric isolation semiconductor element shown in FIG. 54 was measured and found to be 700V.
[0097]
In the example shown in FIG. 54, the number of steps of the stepped impurity concentration distribution is three, but can be appropriately changed within a range of 2 to 10 steps. When the number of stages is increased, the same breakdown voltage can be obtained even if the diffusion length is reduced. On the other hand, when the number of stages is reduced, it is necessary to increase the diffusion length.
[0098]
FIG. 55 is a graph showing the relationship between the number of steps and the corresponding diffusion length when the breakdown voltage of the semiconductor element is a parameter. The curve in the figure is represented by the following formula.
[0099]
(N + 1) [a + (V_b/200)+1.5]=V_b ²/ 13600
Where V_bIs the breakdown voltage (V), a is the diffusion length (μm), and n is the number of stages.
[0100]
  As explained above, the present inventionEighth embodimentAccording to this, even when the thickness of the active layer is 0.3 μm or less, it is possible to realize a high breakdown voltage lateral dielectric isolation semiconductor element without increasing the length of the drift region.
[0101]
【The invention's effect】
As described in detail above, according to the first invention, the electric field concentration in the edge portion of the diffusion layer (especially in the vicinity of the curved surface portion at the bottom) can be alleviated by devising the shape of the diffusion layer by diffusing twice or more. Thus, it is possible to realize a high breakdown voltage semiconductor element having a dielectric isolation structure that can obtain a sufficiently high breakdown voltage characteristic with a thin active layer.
[0102]
According to the second invention, even if the thickness of the active layer is 0.3 μm or less, the impurity concentration distribution in the lateral direction of the active layer is a stepped shape of 2 to 10 steps each having a Gaussian distribution, By setting the interval between the steps to be twice or more the diffusion length, it is possible to realize a high breakdown voltage lateral dielectric isolation semiconductor element without increasing the length of the drift region.
[Brief description of the drawings]
FIG. 1 is a sectional view showing an element structure of a high voltage diode according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing an example in which a p-type anode layer is formed shallower than an oxide film in the first embodiment.
FIG. 3 is a sectional view showing an example in which an n-type cathode layer is formed shallower than an oxide film in the first embodiment.
FIG. 4 is a cross-sectional view showing an example in which a p-type anode layer and an n-type cathode layer are formed shallower than an oxide film in the first embodiment.
FIG. 5 is a cross-sectional view showing an example in which the triple diffusion depth of the n-type cathode layer is constant in the first embodiment.
6 is a cross-sectional view showing an example in which a p-type anode layer is formed shallower than an oxide film in the example of FIG.
7 is a cross-sectional view showing an example in which an n-type cathode layer is formed by double diffusion in the first embodiment. FIG.
FIG. 8 is a cross-sectional view showing an example in which the high resistance film is connected to the p-type anode layer and the n-type cathode layer in the first embodiment.
FIG. 9 is a cross-sectional view showing an example in which a high resistance film is directly formed on an active layer in the first embodiment.
FIG. 10 is a cross-sectional view showing an example in which the high resistance film is omitted in the first embodiment.
FIG. 11 is a sectional view showing an element structure of a high voltage MOSFET according to a second embodiment of the present invention.
FIG. 12 is a cross-sectional view showing an example in which an n-type source layer is formed to reach an oxide film in the second embodiment.
FIG. 13 is a sectional view showing an example in which a high resistance film is directly formed on an active layer in the second embodiment.
FIG. 14 is a sectional view showing an example in which both ends of a high resistance film are connected to electrodes in the second embodiment.
FIG. 15 is a sectional view showing an example in which one end of a high resistance film is connected to an electrode through an impurity-doped polycrystalline silicon film in the second embodiment.
FIG. 16 is a cross-sectional view showing an example in which the high resistance film is omitted in the second embodiment.
FIG. 17 is a cross-sectional view showing an element structure of a lateral IGBT according to a third embodiment.
FIG. 18 is a sectional view showing an example in which an n-type source layer and a p-type drain layer are formed to a depth reaching an oxide film in the third embodiment.
FIG. 19 is a sectional view showing an example in which a high resistance film is directly formed on an active layer in the third embodiment.
FIG. 20 is a cross-sectional view showing an example in which both ends of a high-resistance film are connected to electrodes in the third embodiment.
FIG. 21 is a sectional view showing an example in which one end of a high resistance film is connected to an electrode through an impurity-doped polycrystalline silicon film in the third embodiment.
FIG. 22 is a sectional view showing an example in which the high resistance film is omitted in the third embodiment.
FIG. 23 is a characteristic diagram showing the relationship between the total amount of impurities in the active layer and the withstand voltage.
FIG. 24 is a cross-sectional view showing the device structure of a lateral IGBT according to a fourth embodiment of the present invention.
25 is a cross-sectional view showing an embodiment in which an active layer is formed thick with the configuration of FIG. 24;
FIG. 26 is a characteristic diagram showing a relationship between an on-voltage and a switching-off time with respect to the active layer thickness.
27 is a cross-sectional view showing an example in which an n-type impurity layer is diffused from the entire surface of the active layer based on the structure of FIG. 24;
FIG. 28 is n in the structure of FIG.^-P instead of type active layer^-Sectional drawing which shows the Example using the active layer of a type | mold.
29 is a cross-sectional view showing an embodiment in which an n-type impurity layer is diffused from the entire bottom surface of an active layer based on the structure of FIG. 24;
30 is a cross-sectional view showing an embodiment in which an n base layer is diffused twice or more by changing the width of a diffusion window based on the structure of FIG. 24;
FIG. 31 is a cross-sectional view showing an embodiment in which an n-type impurity layer is diffused from the entire surface of an active layer based on the structure of FIG. 30;
32 is n in the structure of FIG.^-P instead of type active layer^-Sectional drawing which shows the Example using the active layer of a type | mold.
33 is a cross-sectional view showing an embodiment in which an n-type impurity layer is diffused from the entire bottom surface of an active layer based on the structure of FIG. 30;
34 is a cross-sectional view showing an embodiment of a thyristor partially modified with the structure of FIG. 24. FIG.
35 is a cross-sectional view showing an example of a lateral IGBT in which the drain portion is modified in the embodiment of FIG.
36 is a cross-sectional view showing an example in which the drain portion of the embodiment of FIG. 25 is modified.
FIG. 37 is a cross-sectional view showing an example in which the embodiment of FIG. 25 is modified.
38 is a cross-sectional view showing an example in which the embodiment of FIG. 25 is modified.
39 is a cross-sectional view showing an example in which the embodiment of FIG. 25 is modified.
40 is a cross-sectional view showing an example in which the embodiment of FIG. 25 is modified.
FIG. 41 is a sectional view of an element structure showing a high voltage diode according to a fifth embodiment of the present invention.
42 is a sectional view showing an example in which an n-type buffer layer at the bottom of an active layer is selectively formed based on the structure of FIG.
FIG. 43 shows diffusion length of buffer layer 2 × (Dt)^1/2And FIG. 6 is a characteristic diagram showing the relationship between device breakdown voltage.
44 is a sectional view showing an example in which the buffer layer at the bottom of the active layer is selectively formed based on the structure of FIG. 41;
45 is a cross-sectional view showing an example in which the active layer is thin with respect to the structure of FIG.
FIG. 46 is a sectional view of an element structure showing a high-speed diode according to a sixth embodiment of the present invention.
FIG. 47 is a characteristic diagram showing the relationship between the ON voltage Vf and reverse recovery time trr of the diode formed on the dielectric isolation substrate and the thickness ts of the semiconductor substrate.
48A and 48B are a plan view and a cross-sectional view showing a schematic configuration of a dielectric isolation semiconductor substrate according to a seventh embodiment of the present invention.
49 is a cross-sectional view showing a manufacturing step of the dielectric isolation semiconductor substrate of FIG. 48;
50 is a sectional view showing a modification of the embodiment of FIG. 48. FIG.
FIG. 51 is a cross-sectional view showing a conventional example of a lateral type high breakdown voltage diode using a dielectric isolation structure.
FIG. 52 is a characteristic diagram showing the relationship between the diffusion length and the breakdown voltage.
FIG. 53 is a characteristic diagram showing the relationship between the number of steps and the breakdown voltage.
54 is a sectional view showing an example of a dielectric isolation semiconductor device according to an eighth example of the present invention. FIG.
FIG. 55 is a characteristic diagram showing the impurity concentration distribution in the lateral direction of the active layer when diffusion is performed three times in the active layer.
FIG. 56 is a characteristic diagram showing the relationship between the number of steps and the diffusion length when the breakdown voltage of the element is a parameter.
FIG. 57 is a cross-sectional view showing a conventional example of a lateral type high-breakdown-voltage diode using a dielectric isolation structure.
[Explanation of symbols]
10 ... Silicon substrate
11 ... Silicon oxide film (isolation insulating film)
12 ... n^-Type high resistance silicon layer (active layer)
13 ... p-type anode layer (second conductivity type impurity layer)
14: n-type cathode layer (first conductivity type impurity layer)
15 ... Anode electrode
16 ... Cathode electrode
18 ... High resistance film
21 ... Gate electrode
23 ... p-type base layer
24 ... n-type drain layer
25 ... Source electrode
26 ... Drain electrode
28 ... Impurity doped polycrystalline silicon film
34 ... n-type base layer
36: p-type drain layer.

Claims (7)

  A semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active layer made of a high-resistance semiconductor of the first conductivity type formed on the insulating layer, and a first conductivity formed in the active layer A first impurity layer of a type, a second impurity layer of a second conductivity type formed in the active layer and spaced apart from the first impurity layer, and on the first impurity layer A first electrode formed on the second impurity layer, and a second electrode formed on the second impurity layer, wherein the first impurity layer has at least a width or a diffusion depth of a diffusion window. A high breakdown voltage semiconductor element comprising a plurality of mutually overlapping diffusion layers, one of which is different, wherein the first impurity layer and the second impurity layer reach the bottom of the active layer.   A semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active layer made of a high-resistance semiconductor of the first conductivity type formed on the insulating layer, and a first conductivity formed in the active layer A first impurity layer of a type, a second impurity layer of a second conductivity type formed in the active layer and spaced apart from the first impurity layer, and in the first impurity layer A second impurity layer of the second conductivity type formed on the first impurity layer; a first electrode formed on the third impurity layer; and a second electrode formed on the second impurity layer. And the first impurity layer includes a plurality of mutually stacked diffusion layers having different diffusion window widths or diffusion depths, wherein the first impurity layer and the second impurity layer The high breakdown voltage semiconductor element, wherein the layer reaches the bottom of the active layer.   3. The high breakdown voltage semiconductor element according to claim 1, wherein the plurality of impurity layers have the same diffusion depth and different diffusion window widths.   3. The high withstand voltage semiconductor element according to claim 1, further comprising a high resistance layer on a portion of the active layer located between the first and second impurity layers.   The high withstand voltage semiconductor device according to claim 4, further comprising an insulating film formed on the active layer, wherein the high resistance layer is formed on the insulating film.   The fourth impurity layer of the first conductivity type formed in the second impurity layer at a predetermined distance from the active layer, and the active layer located between the active layer and the fourth impurity layer. 3. The high breakdown voltage semiconductor element according to claim 1, further comprising an insulator formed on the second impurity layer and a third electrode formed on the insulator. .   The high withstand voltage semiconductor device according to claim 1, wherein the active layer has a thickness of 10 μm or less.

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