JP3409244B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar semiconductor device having a MOS gate, and more particularly to a semiconductor device suitable for a thyristor.

[0002]

BACKGROUND AND PROBLEMS TO BE SOLVED BY THE INVENTION MOS
A MOS thyristor, which is a combination of a FET and a thyristor structure, uses a MOS gate to supply electrons from the cathode region to the floating emitter region and further to inject holes from the anode region to the base region, so that the thyristor is internally formed. It is an element that operates. In particular, in the case of an element requiring a high breakdown voltage, the breakdown voltage of the element is increased by increasing the thickness of the epitaxial layer forming the base region (drift region).
However, increasing the thickness of the epitaxial layer is
It becomes a factor to increase the on-resistance of the element.

In order to reduce the ON resistance of the element, there is a technique disclosed in, for example, Japanese Patent Application Laid-Open No. 4-146674. In this technique, a floating emitter is formed inside the device, and the area of this floating emitter is formed so as to occupy most of the device area. Then, a cathode region is formed on the surface of the element, and the cathode region and the floating emitter are connected by a trench gate to form a MOS structure. In this semiconductor device, since the floating emitter is widely formed in the main surface direction of the substrate, the electron injection passage is widened, and as a result, the resistance in the base region can be reduced and the on-voltage can be reduced. It However,
In the semiconductor device having this structure, the turn-on and turn-off times have not been sufficiently shortened.

An object of the present invention is to provide a bipolar type semiconductor device including a MOS gate, which has short turn-on and turn-off times as well as an on-voltage.

[0005]

The semiconductor device of the present invention comprises:
A first conductive type first semiconductor layer, a second conductive type second semiconductor layer formed on one main surface side of the first semiconductor layer and containing a low concentration of impurities, and a surface portion of the second semiconductor layer. A third semiconductor layer of the first conductivity type selectively formed on the first semiconductor layer, a fourth semiconductor layer of the second conductivity type selectively formed on the surface portion of the third semiconductor layer, and inside the third semiconductor layer. A fifth semiconductor layer of a second conductivity type selectively formed apart from the fourth semiconductor layer;
A gate formed through an insulating film in a trench that penetrates the fourth semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, and the third semiconductor layer and further reaches the inside of the second semiconductor layer. An electrode, the third semiconductor layer, and the fourth
It includes a first main electrode formed commonly on both surfaces of the semiconductor layer, and a second main electrode formed on the other main surface side of the first semiconductor layer.

In this semiconductor device, the gate electrode has a fourth semiconductor layer functioning as a source region, a third semiconductor layer functioning as a region (base region) capable of forming a first channel region, a drain region and a floating region. It has a trench gate structure which penetrates the fifth semiconductor layer functioning as an emitter region and the third semiconductor layer functioning as a base region and further reaches the inside of the second semiconductor layer. The MOSFET having the trench gate structure, the second semiconductor layer functioning as a drift region (base layer) and the first semiconductor layer functioning as an emitter layer are used to form the IGBT.
(Insulated Gate Bipolar T
A transistor element is formed. Also, the first
A thyristor is formed by the second, third and fifth semiconductor layers. In this way, the turn-on time of the device can be shortened by controlling the IGBT and the thyristor using the same trench gate.

Further, another semiconductor device according to the present invention is
A first conductive type first semiconductor layer, a second conductive type second semiconductor layer formed on one main surface side of the first semiconductor layer and containing a low concentration of impurities, and a surface portion of the second semiconductor layer. A third semiconductor layer of the first conductivity type selectively formed on the first semiconductor layer, a fourth semiconductor layer of the second conductivity type selectively formed on the surface portion of the third semiconductor layer, and inside the third semiconductor layer. A fifth semiconductor layer of a second conductivity type selectively formed apart from the fourth semiconductor layer;
A first gate electrode formed through an insulating film in a trench penetrating the fourth semiconductor layer and the third semiconductor layer and reaching at least the fifth semiconductor layer, and the fourth semiconductor of the second conductivity type. A second gate electrode formed on the surface of the third semiconductor layer of the first conductivity type adjacent to the layer through an insulating film, and common to both surfaces of the third semiconductor layer and the fourth semiconductor layer. A formed first main electrode, and a second main electrode formed on the other main surface side of the first semiconductor layer,
including.

In this semiconductor device, the MOSFET
A fourth semiconductor layer functioning as a source region of the semiconductor, a third semiconductor layer functioning as a region (base region) where a channel region can be formed.
It has a first gate electrode having a trench structure which penetrates the semiconductor layer and further reaches a fifth semiconductor layer which functions as a drain region and a floating emitter region. And
In addition to this MOS gate, an IGBT is formed in a route different from this MOS gate. This IGBT is
Consists of a second gate electrode, a fourth semiconductor layer that functions as a source region of the MOSFET, a third semiconductor layer that can form a channel region, a second semiconductor layer that functions as a drift region, and a first semiconductor layer that functions as an emitter layer. To be done. Then, by independently controlling the MOS gate having the first gate electrode and the IGBT having the second gate electrode, the turn-on and turn-off operations of the element can be quickly performed.

In the semiconductor device, a metal layer capable of forming a Schottky junction with the third semiconductor layer may be formed instead of the fifth semiconductor layer. As described above, by forming the Schottky junction between the third semiconductor layer functioning as the base region and the fifth semiconductor layer functioning as the floating emitter region, the forward characteristic is improved as compared with the pn junction.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a sectional view schematically showing a thyristor 100 (MOS gate thyristor) 100 controlled by a MOS gate to which the present invention is applied. It is a top view which shows the thyristor shown in FIG. 1 in the state which removed the upper electrode layer.

(Constitution) This MOS gate thyristor 10
0, the n ⁺ type buffer layer 12 is formed on one main surface of the p ⁺ type silicon substrate (first semiconductor layer) 10 functioning as an emitter layer, and the surface of the buffer layer 12 serves as a drift region. A functional n ⁻ type base region (second semiconductor layer) 14 is formed. A p ⁻ -type base region (third semiconductor layer) 16 is formed on the surface of the n ⁻ -type base region 14, and an n ⁺ -type that functions as a source region of a MOS device is formed on the surface of the base region 16. Impurity diffusion layers (fourth semiconductor layers) 18a and 18b are selectively formed. Further, an n ⁺ type floating emitter region (fifth semiconductor layer) 22 is selectively formed inside the p ⁻ type base region 16 at a position apart from the n ⁺ type impurity diffusion layers 18a and 18b. There is.

Then, in the p ^- type base region 16,
A gate electrode 30 having a trench structure is formed. The gate electrode 30 is composed of the n ⁺ -type impurity diffusion layers 18a, 1
8b, the p ⁻ type base region 16, the n ⁺ type floating emitter region 22, the p ⁻ type base region 16 and a trench penetrating a part of the n ⁻ type base region 14 with an insulating film 32 interposed therebetween. For example, it is formed by forming a conductive layer 34 made of doped polysilicon.

The n ⁺ -type impurity diffusion regions 18a,
A cathode electrode 50 serving as a first main electrode is formed on the surfaces of 18b and the p ⁻ type base region 16. And
The gate electrode 30 and the cathode electrode 50 are electrically separated by an insulating layer 70. Also, the p
^An anode electrode 60, which is a second main electrode, is formed on the other main surface of the ⁺ type emitter layer 10.

In this MOS gate thyristor 100, the n ⁺ -type floating emitter region 22, the p ⁻ -type base region 16, the n ⁻ -type base region 14, the n ⁺ -type buffer layer 12 and the p ⁺ -type emitter layer 10 allow the npnp thyristor. Is configured.

Further, n ⁺ type impurity diffusion regions (source regions) 18a, 18b, first channel regions 20a, n ⁺
Type floating emitter region 22, second channel region 20b, n ⁻ type base region 14, n ⁺ type buffer layer 12
The p ⁺ type emitter layer 10 constitutes an IGBT. The first channel region 20a is formed between the n ⁺ -type impurity diffusion layers 18a and 18b and the floating emitter region 22 adjacent to the gate insulating film 32 of the gate electrode 30, and the second channel region 20a is formed. The region 20b is formed between the floating emitter region 22 and the base region 14 adjacent to the gate insulating film 32 of the gate electrode 30.

(Operation) Next, the MOS according to the present embodiment
The operation of the gate thyristor 100 will be described.

First, the gate electrode 30 and the anode electrode 60
The IGBT is operated by applying a predetermined positive voltage to and. In the operation of the IGBT, electrons are n ⁺
From the impurity diffusion layers 18a and 18b to the n ⁺ type floating emitter 22 through the first channel region 20a and further along the gate insulating film 32 of the gate electrode 30 inside the floating emitter region 22. Flow into the n ⁻ -type base region 14 through the second channel region 20b. At the same time, since a positive voltage is applied to the anode electrode 60, holes flow from the p ⁺ type emitter layer 10 through the n ⁺ type buffer layer 12 into the n ⁻ type base region 14. In this way, the n ⁻ type base region 14 is filled with electrons and holes, and the operation mode of the IGBT is set.

Further, by increasing the voltage of the anode electrode 60, the holes injected from the p ⁺ -type emitter layer 10 flow into the p ⁻ -type base region 16 immediately below the n ⁺ -type floating emitter region 22 and the p ⁻ -type The resistance of the base region 16 is lowered, and the p ⁺ type emitter layer 10, the n ⁺ type buffer layer 12 and the n ⁻ type base region 14, the p ⁻ type base region 16 and the n ⁺ type floating emitter region 22.
The pnpn thyristor composed of is brought into a latch-up state and causes thyristor operation. During the operation of the thyristor, since the floating emitter region 22 is formed in a state of extending in the direction of the main surface of the silicon substrate 10, it is possible to widen the electron injection path, so that the current easily flows and the on-voltage is reduced. it can.

Thus, the IGBT element functions as a trigger for causing the thyristor operation. And
Since the MOSFET portion of the IGBT element is formed along the gate electrode 30, the injection of holes from the p ⁺ -type emitter layer 10 can be more easily promoted and the turn-on time is shorter than that of the element having the conventional structure. A thyristor capable of controlling a large current can be realized.

When turning off the MOS gate thyristor 100, the gate electrode 30 is turned off to turn off the n ⁺ type floating emitter region 22.
Is cut off from the cathode electrode 50 in terms of potential, and the thyristor operation stops.

(Manufacturing Method) Next, with reference to FIGS. 3 to 9, the MOS gate thyristor 10 shown in FIGS. 1 and 2.
An example of the manufacturing method of 0 will be described. Optimum conditions for the film thickness, size, impurity concentration, etc. of each semiconductor layer are selected depending on the application of the device, design matters, and the like.

First, as shown in FIG. 3, an n ⁺ type buffer layer 12 and an n ⁻ type base region 14 are epitaxially grown on a p ⁺ type silicon substrate 10.

Then, as shown in FIG. 4, a p ^-- type impurity diffusion layer (p well) 16a is formed by diffusing or ion-implanting a p-type impurity into the n ^-- type base region 14. Further, in the p ⁻ type impurity diffusion layer 16a,
An n-type impurity such as arsenic is ion-implanted into a predetermined region by the mask M to form an n ⁺ -type impurity diffusion layer 22a.

Then, as shown in FIG. 5, an n ^-- type base region 14b is formed by epitaxial growth. Then,
As shown in FIG. 6, by performing the annealing treatment, n ⁺
The n ⁺ type floating emitter region 22 is formed by thermally diffusing the type impurity diffusion layer 22a.

Then, as shown in FIG. 7, a p ^-- type impurity diffusion layer 16b is formed by diffusing or ion-implanting a p-type impurity into the n ^-- type base region 14b to form the p ^-- type base region 16. . Furthermore, p ⁻ type base region 1
The n ⁺ -type impurity diffusion layer 18 is formed by selectively ion-implanting n-type impurities into the surface portion of 6.

Further, as shown in FIG. 8, a mask (not shown) is formed, the wafer is selectively removed by dry etching such as RIE, and the n ⁺ -type impurity diffusion layer 18,
p ⁻ type base region 16, n ⁺ type floating emitter region 22, p ⁻ type base region 16 and n ⁻ type base region 1
A trench reaching part of 4 is formed. Then, after removing the mask, an insulating film 32 made of a silicon oxide film is formed on the entire surface of the wafer including the inner wall of the trench, and a conductive layer 34 made of doped polysilicon is formed so as to fill the inside of the trench. The unnecessary insulating film and conductive layer on the upper surface of the layer are removed to form the gate electrode 30 having a trench structure.

Then, as shown in FIG. 9, at least n
^A cathode electrode 50, which is one main electrode, is formed so as to extend over the ⁺ type impurity diffusion layer 18a and the p ⁻ type base region 16, and the anode electrode 60, which is the other main electrode, is formed on the lower surface of the p ⁺ type silicon substrate 10. To form.

The above-described manufacturing method is an example, and other manufacturing methods may be adopted. For example, a method of recrystallizing amorphous silicon into single crystal silicon by performing annealing treatment after forming amorphous silicon film instead of epitaxial growth can be adopted. The manufacturing method described above can basically be applied to semiconductor devices according to other embodiments.

(Second Embodiment) FIG. 10 is a sectional view schematically showing a thyristor (MOS gate thyristor) 200 controlled by a MOS gate, to which the present invention is applied.

(Constitution) This MOS gate thyristor 20
0, the n ⁺ type buffer layer 12 is formed on one main surface of the p ⁺ type silicon substrate (first semiconductor layer) 10 functioning as an emitter layer, and the surface of the buffer layer 12 serves as a drift region. A functional n ⁻ type base region (second semiconductor layer) 14 is formed. A p ⁻ -type base region (third semiconductor layer) 16 is formed on the surface of the n ⁻ -type base region 14, and an n ⁺ -type that functions as a source region of a MOS device is formed on the surface of the base region 16. Impurity diffusion layers (fourth semiconductor layers) 18a and 18b are selectively formed. Further, an n ⁺ type floating emitter region (fifth semiconductor layer) 22 is selectively formed inside the p ⁻ type base region 16 at a position apart from the n ⁺ type impurity diffusion layers 18a and 18b. There is.

Then, in the p ^- type base region 16,
A first gate electrode 30 having a trench structure is formed. The gate electrode 30 is the n ⁺ -type impurity diffusion layer 1
8a, 18b and the p ⁻ -type base region 16 and penetrates through the n ⁺ -type floating emitter region 22.
Is formed by forming a conductive layer 34 made of, for example, doped polysilicon through the insulating film 32 in the trench reaching the. A second gate electrode 40 is formed on a part of the n ⁺ type impurity diffusion region 18b and the surface of the p ⁻ type base region 16 with an insulating film 42 interposed therebetween.

Further, the n ⁺ type impurity diffusion region 18 is formed.
A cathode electrode 50 serving as a first main electrode is formed on the surfaces of a, 18b and p ⁻ type base region 16. The gate electrode 30 and the cathode electrode 50 are electrically separated by the insulating layer 70. An anode electrode 60, which is a second main electrode, is formed on the other main surface of the p ⁺ type emitter layer 10.

In this thyristor 200, the n ⁺ type floating emitter region 22 and the p ⁻ type base region 1 are provided.
6, n ⁻ type base region 14, n ⁺ type buffer layer 12 and p ⁺ type emitter layer 10 constitute an npnp thyristor.

The n ⁺ type impurity diffusion regions (source regions) 18a and 18b, the n ⁺ type floating emitter region (drain region) 22, the trench gate electrode 30 and the first channel region 20a form a MOSFET. The first channel region 20 is formed between the n ⁺ -type impurity diffusion layers 18 a and 18 b and the floating emitter region 22 adjacent to the gate insulating film 32 of the gate electrode 30. And this MOSF
Electrons are supplied to the floating emitter region 22 forming the npnp thyristor by ET.

Further, one of the n ⁺ type impurity diffusion regions 18
b, second channel region 20b, n ⁻ type base region 1
4, the n ⁺ type buffer layer 12 and the p ⁺ type emitter layer 10 form an IGBT.

(Operation) Next, the MO according to the present embodiment
The operation of the S gate thyristor 200 will be described.

In this MOS gate thyristor 200, apart from the first gate electrode 30 having the trench structure,
By having the IGBT using the second gate electrode 40 having the planar structure, the first gate electrode 30 and the second gate electrode 40 can be independently driven.

First, when turning on the MOS gate thyristor 200, the second gate electrode 40 is turned on and the IGBT is turned on. In this state, injection of holes from the p ⁺ type emitter layer 10 can be promoted.
At the same time, the first gate electrode 30 is turned on, and the holes are injected from the p ⁺ -type emitter layer 10, and the n ⁺ -type impurity diffusion layers 18a and 18b are connected to the first channel region 20.
Electrons are injected into the n ⁺ type floating emitter region 22 functioning as a drain region via a. Since the potential of the floating emitter region 22 is not fixed, the potential of the floating emitter region 22 increases due to the increase of the anode voltage, and the MOSFE
Operates as the drain of T. And this MOSFE
Electrons are injected into the floating emitter region 22 by the operation of T, and holes from the p ⁺ type emitter layer 10 are injected by the IGBT operation, so that the potential barrier of the p ⁻ type base region 16 directly below the floating emitter region 22 is injected. Becomes low, and the majority carriers in the floating emitter region 22 and the p ⁻ type base region 16 start the thyristor operation. During the operation of the thyristor, since the floating emitter region 22 is formed in a state of extending in the direction of the main surface of the silicon substrate 10, it is possible to widen the electron injection path, so that the current easily flows and the on-voltage is reduced. it can.

As described above, since the thyristor operation can be easily caused by first turning on the IGBT, the turn-on time of the element can be shortened. Further, when turning off the MOS gate thyristor 200, the operation inside the element can be shifted from the thyristor operating state to the IGBT operating state by first turning off the first gate electrode 30.
After that, by turning off the second gate electrode 40,
The carrier inside the element can be surely turned off in a short time.

(Third Embodiment) FIG. 11 is a sectional view schematically showing a thyristor 300 to which the present invention is applied and which is controlled by a MOS gate. In this embodiment, the thyristor 10 of the first embodiment shown in FIG. 1 is used.
Portions substantially the same as 0 are assigned the same reference numerals and detailed description thereof will be omitted.

This embodiment differs from the first embodiment in that the floating emitter region is made of Schottky metal instead of the n ⁺ -type impurity diffusion layer. As a metal capable of making a Schottky junction with the p ⁻ type base region 16, for example, nickel or the like can be used.
Thus, by forming the floating emitter region 24 made of a metal forming a Schottky junction in the p ⁻ type base region 16, it is possible to form a Schottky junction having better forward characteristics than the pn junction. it can.
As a result, the turn-on time of the element can be shortened and the on-voltage of the element can be lowered, so that the thyristor characteristic is improved.

(Fourth Embodiment) FIG. 12 is a sectional view schematically showing a thyristor 400 controlled by a MOS gate to which the present invention is applied. In FIG.
Portions substantially the same as those of the thyristor 100 according to the first embodiment shown in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

A characteristic of this embodiment is that n
^{This is because} the bottom of the p ⁻ type base region 16 located immediately below the ⁺ type floating emitter region 22 is formed in a wavy shape. By the waveform bottom of the mold base region 16, p ^{- -} Thus p type diffusion depth of the base region 16 is partially shallower, thyristor operation is likely to occur in the shallow diffusion depth, the whole As a result, there is an advantage that the ON voltage of the element is lowered.

As a method of corrugating the bottom of the p ^- type base region 16, for example, when ion-implanting p-type impurities, ion implantation is performed at a portion where the diffusion depth is made deeper than the portion where the diffusion depth is made shallow. It can be formed by increasing the amount and then performing heat treatment.

(Fifth Embodiment) FIG. 13 is a perspective view showing a modification of the gate electrode 30 having a trench structure. The gate electrode 30 of this example has a cross shape in a plan view. As described above, by forming the gate electrode 30 in a cross-shaped planar shape, the channel region is relatively increased and the resistance of the MOSFET can be reduced as compared with the gate electrode having the stripe structure shown in FIG. . As a result, the on-voltage can be lowered.

The modification of the gate electrode 30 shown in FIG. 13 is an example, and other modes can be adopted as long as the increase of the channel region can be achieved.

The third to fifth embodiments described above can be applied not only to the first embodiment but also to the second embodiment, and the same operational effect Can be obtained. Further, in the above-described embodiment, the p-type semiconductor device is used as the first conductivity type and the n-type semiconductor device is used as the second conductivity type. However, the conductivity type may be reversed.

[0048]

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a thyristor according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a planar structure of the thyristor shown in FIG.

FIG. 3 is a sectional view schematically showing a manufacturing process of the thyristor shown in FIGS. 1 and 2.

FIG. 4 is a cross-sectional view showing a step performed after the manufacturing step shown in FIG.

FIG. 5 is a cross-sectional view showing a step performed after the manufacturing step shown in FIG.

FIG. 6 is a cross-sectional view showing a step performed after the manufacturing step shown in FIG.

FIG. 7 is a cross-sectional view showing a step performed after the manufacturing step shown in FIG.

FIG. 8 is a cross-sectional view showing a step performed after the manufacturing step shown in FIG.

FIG. 9 is a cross-sectional view showing a step performed after the manufacturing step shown in FIG.

FIG. 10 is a sectional view schematically showing a thyristor according to a second embodiment of the present invention.

FIG. 11 is a sectional view schematically showing a thyristor according to a third embodiment of the present invention.

FIG. 12 is a sectional view schematically showing a thyristor according to a fourth embodiment of the present invention.

FIG. 13 is a perspective view schematically showing a part of a thyristor according to a fifth embodiment of the present invention.

[Explanation of symbols]

10 p ⁺ type silicon substrate 12 n ⁺ type buffer layer 14 n ⁻ type base region 16 p ⁻ type base region 18, 18a, 18b n ⁺ type impurity diffusion layer 20a first channel region 20b second channel region 22, 24 Floating emitter region 30, 40 Gate electrode 32, 42 Insulating film 34 Conductive layer 50 Cathode electrode 60 Anode electrode 100, 200, 300, 400 Thyristor

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tsutomu Uesugi 1 Nagatote, Nagakute-cho, Aichi-gun, Aichi Prefecture 1 No. 41 Yokomichi Toyota Central Research Institute Co., Ltd. (56) Reference JP-A-7-111324 (JP, A) JP-A-6-275818 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/74

Claims (4)

(57) [Claims] 1. A first-conductivity-type first semiconductor layer, a second-conductivity-type second semiconductor layer formed on one main surface side of the first semiconductor layer, and containing a low-concentration impurity; A third semiconductor layer of a first conductivity type selectively formed on a surface portion of the semiconductor layer; a fourth semiconductor layer of a second conductivity type selectively formed on a surface portion of the third semiconductor layer; A second conductive type fifth semiconductor layer selectively formed inside the semiconductor layer so as to be separated from the fourth semiconductor layer, the fourth semiconductor layer, the third semiconductor layer, the fifth semiconductor layer, and the fifth semiconductor layer. A gate electrode formed through an insulating film in a trench penetrating the third semiconductor layer and further reaching the inside of the second semiconductor layer, and commonly on both surfaces of the third semiconductor layer and the fourth semiconductor layer. The first main electrode formed and the other main surface side of the first semiconductor layer are formed. Second main electrode, seen including, said fifth semiconductor layer, only one end the third semiconductor
In contact with the gate electrode through the insulating film inside the layer
And extends in the main surface direction of the first semiconductor layer.
A semiconductor device formed in a state . 2. A first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, which is formed on one main surface side of the first semiconductor layer and contains a low concentration of impurities, and the second semiconductor layer. A third semiconductor layer of a first conductivity type selectively formed on a surface portion of the semiconductor layer; a fourth semiconductor layer of a second conductivity type selectively formed on a surface portion of the third semiconductor layer; A fifth conductive type fifth semiconductor layer that is selectively formed inside the semiconductor layer while being separated from the fourth semiconductor layer, penetrates the fourth semiconductor layer and the third semiconductor layer, and at least the fifth semiconductor. A first gate electrode formed through an insulating film in the trench reaching the layer; and an insulating film on the surface of the third semiconductor layer of the first conductivity type adjacent to the fourth semiconductor layer of the second conductivity type. A second gate electrode formed through the second gate electrode, the third gate electrode and the fourth gate layer. A first main electrode formed in common on the surface of, and a second main electrode formed on the other main surface side of the first semiconductor layer, a semiconductor device including a. 3. A first semiconductor layer of a first conductivity type , a low concentration formed on one main surface side of the first semiconductor layer.
Second-conductivity-type second semiconductor layer containing impurities, and the first conductive layer selectively formed on the surface of the second semiconductor layer.
Electroconductive third semiconductor layer, a second conductive layer selectively formed on the surface of the third semiconductor layer.
An electrically conductive fourth semiconductor layer, inside the third semiconductor layer and spaced apart from the fourth semiconductor layer.
The selectively formed second-conductivity-type fifth semiconductor layer, the fourth semiconductor layer, the third semiconductor layer, and the fifth semiconductor
A layer and the third semiconductor layer, and further through the second half
Formed via an insulating film in the trench that reaches the inside of the conductor layer.
Surfaces of both the formed gate electrode, the third semiconductor layer and the fourth semiconductor layer
And a second main electrode formed on the other main surface side of the first semiconductor layer.
Electrodes, wherein the said third semiconductor layer located immediately below the fifth semiconductor layer
A semiconductor device having a corrugated bottom. 4. The semiconductor device according to claim 1, wherein a metal layer forming a Schottky junction with the third semiconductor layer is formed instead of the fifth semiconductor layer.