JP4761011B2 - Semiconductor device having thyristor and method for manufacturing the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a thyristor in which an element for passing a trigger current of the thyristor is, for example, an IGBT, and a manufacturing method thereof.
[0002]
[Background]
FIG. 19 is a cross-sectional view of a semiconductor device having a thyristor disclosed in Japanese Patent Laid-Open No. 5-82775. This semiconductor device is used, for example, to control a large current under a high breakdown voltage. The semiconductor device 200 is p ⁺ Type anode layer 204, n type buffer layer 206, n ^- A silicon substrate 202 on which a mold base layer 208 is stacked is provided. P of silicon substrate 202 ⁺ A metal anode electrode 210 is formed on the mold anode layer 204 side.
[0003]
n ^- A p-type first base layer 212 is formed from the surface of the mold base layer 208 toward the inside. An n-type floating emitter layer 214 is formed from the surface of the p-type first base layer 212 toward the inside. A p-type second base layer 216 is formed from the surface of the n-type floating emitter layer 214 toward the inside. From the surface of the p-type second base layer 216 to the inside, n ⁺ The mold cathode layers 218 and 220 are formed with a space therebetween.
[0004]
The cathode electrode 222 is n ⁺ On the surface of the p-type cathode layer 218, on the surface of the p-type second base layer 216, and n ⁺ It is formed over the surface of the mold cathode layer 220. The gate electrode 224 covered with the insulating layer is n ^- On the surface of the p-type base layer 208, on the surface of the p-type first base layer 212, on the surface of the n-type floating emitter layer 214, on the surface of the p-type second base layer 216, and n ⁺ It is formed over the surface of the mold cathode layer 218. The gate electrode 226 covered with the insulating layer is n ^- On the surface of the p-type base layer 208, on the surface of the p-type first base layer 212, on the surface of the n-type floating emitter layer 214, on the surface of the p-type second base layer 216, and n ⁺ It is formed over the surface of the mold cathode layer 220.
[0005]
n-type floating emitter layer 214, p-type first base layer 212, n ^- Type base layer 208, n-type buffer layer 206, p ⁺ A thyristor is constituted by the mold anode layer 204.
[0006]
Next, the operation of the thyristor of the semiconductor device 200 will be described. First, the turn-on operation will be described. The cathode electrode 222 is grounded, and a positive voltage is applied to the gate electrodes 224 and 226 and the anode electrode 210, respectively. When a positive voltage is applied to the gate electrodes 224 and 226, channel regions are formed in the p-type first base layer 212 and the p-type second base layer 216 below the gate electrodes 224 and 226. As a result, n ⁺ The electrons of the type cathode layers 218 and 220 pass through the channel region formed in the p-type second base layer 216, the channel region formed in the n-type floating emitter layer 214 and the p-type first base layer 212, and n ^- It flows into the mold base layer 208. On the other hand, since a positive voltage is also applied to the anode electrode 210, p ⁺ Type anode layer 204 has n holes ^- Implanted into the mold base layer 208. n ^- The IGBT is turned on by these electrons and holes injected into the mold base layer 208.
[0007]
n ^- Holes reaching the p-type first base layer 212 from the p-type base layer 208 are n-type floating emitter layer 214, p-type first base layer 212, n ^- The base current of the NPN transistor formed by the mold base layer 208 becomes the ON current of the NPN transistor. That is, electrons are transferred from the n-type floating emitter layer 214 to the p-type first base layer 212 and the n-type floating emitter layer 214. ^- By being injected into the mold base layer 208, the thyristor is turned on.
[0008]
Next, the turn-off operation will be described. When a negative voltage or 0 V is applied to the gate electrodes 224 and 226, the channel regions formed in the p-type first base layer 212 and the p-type second base layer 216 below the gate electrodes 224 and 226 disappear. As a result, n ⁺ Since the supply of electrons from the type source layers 218 and 220 to the n type floating emitter layer 214 is stopped, the thyristor is turned off.
[0009]
[Problems to be solved by the invention]
The thyristor is required to reduce the turn-on voltage in order to reduce power consumption. Increasing the area of the thyristor can meet this requirement.
[0010]
However, if the area of the thyristor is increased, the amount of carriers stored in the thyristor is increased, which adversely affects the turn-off performance of the thyristor (short turn-off time and reliable turn-off). In other words, if it takes time to turn off, high-speed switching of the thyristor is hindered. Failure to turn off reliably will lead to destruction of the thyristor.
[0011]
In the semiconductor device 200 shown in FIG. 19, the potential of the n-type floating emitter layer 214 tends to rise transiently during the turn-off operation. Due to this increase, a high voltage in the reverse direction is applied to the pn junction between the n-type floating emitter layer 214 and the p-type second base 216, and this pn junction may break down. When this breakdown occurs, the thyristor cannot be turned off.
[0012]
In the semiconductor device 200 shown in FIG. 19, it is difficult to reduce the turn-on voltage even if the area of the thyristor is simply increased. That is, in the semiconductor device 200, a channel region is formed in the p-type second base layer 216 below the gate electrodes 224 and 226. The electron current of the thyristor is n ⁺ It flows between the type cathode layers 218, 220 -channel region-n type floating emitter layer 214. However, the gate electrodes 224 and 226 are formed on the surface of the silicon substrate 202. For this reason, even if the area of the n-type floating emitter layer 214 is increased in order to cause the thyristor operation in a wide range, the electron current flowing into the n-type floating emitter layer 214 is limited by the amount flowing through the channel region. This is a hindrance to lowering the turn-on voltage of the thyristor.
[0013]
An object of the present invention is to provide a semiconductor device capable of improving the turn-off performance of a thyristor and a manufacturing method thereof.
[0014]
Another object of the present invention is to provide a semiconductor device capable of improving the turn-off performance of a thyristor and reducing the turn-on voltage, and a method for manufacturing the same.
[0015]
[Means for Solving the Problems]
(1) A semiconductor device according to the present invention is a semiconductor device having a thyristor, and includes first and second field effect transistors, and the thyristor includes a first conductive type first semiconductor layer and a second conductive type base. A first conductivity type first base layer and a second conductivity type floating emitter layer, the first field effect transistor comprising: a second conductivity type second semiconductor layer; a first conductivity type second base layer; The first conductivity type first base layer and the first conductivity type second base layer include a second conductivity type floating emitter layer and a buried first gate electrode. The second conductivity type floating emitter layer and the second conductivity type second semiconductor layer are separated from each other by the first conductivity type second base layer, and the second field effect transistor is Conductive type Low computing emitter layer, first base layer of a first conductivity type, comprises a base layer and a second gate electrode of the second conductivity type, elements having a second field effect transistor flows a trigger current to operate the thyristor.
[0016]
Since the semiconductor device according to the present invention includes the field effect transistor including the embedded first gate electrode, the turn-on voltage of the thyristor can be reduced. That is, the channel region is formed in the second base layer of the first conductivity type by the field effect transistor. The current of the thyristor flows between the second conductivity type second semiconductor layer (for example, the cathode layer), the channel region, and the second conductivity type floating emitter layer. The first gate electrode is a buried type. For this reason, since the said path | route can be shortened, the turn-on voltage of a thyristor can be lowered | hung. Note that when a plurality of first gate electrodes are provided, the area of the channel region can be increased. This is a factor that can reduce the turn-on voltage of the thyristor.
[0017]
In the semiconductor device according to the present invention, since the first gate electrode is a buried type, the first gate electrode can be positioned on the body portion (a portion other than the end portion) of the second conductivity type floating emitter layer. Therefore, the potential of the second conductivity type floating emitter layer can be brought close to the potential of the first gate electrode. Therefore, when the thyristor is turned off, it is possible to prevent a reverse high voltage from being applied to the junction between the second conductivity type floating emitter layer and the first conductivity type second base layer.
Therefore, since the possibility that this junction breaks down can be reduced, the thyristor can be turned off more reliably.
[0018]
As an element including the second field effect transistor, for example, an IGBT having a planar gate structure, an IGBT having a trench gate structure, or an IEGT (Injection)
Enhanced insulated Gate bipolar
Transistor, MCT (MOS Controlled)
Transistor, MOS gate thyristor,
CSTBT (Carrier Stored Trench-Gate
bipolar transistor), EST (emitter)
Switched Transistor) and the like. The second field effect transistor that appears below also has this meaning.
[0019]
In the semiconductor device according to the present invention, the second gate electrode includes a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, a floating emitter layer of the second conductivity type, and a first first of the first conductivity type. It is preferable that the base layer and the base layer of the second conductivity type are formed on the exposed surface via an insulating film. In this structure, the channel region during operation of the element including the second field effect transistor is formed in a plane, and can be manufactured separately from the channel region for thyristor operation. For this reason, the channel concentration for operating the element including the second field effect transistor (which determines the threshold voltage of the element) can be arbitrarily determined.
[0020]
In the semiconductor device according to the present invention, the second gate electrode includes a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, a floating emitter layer of the second conductivity type, and a first first of the first conductivity type. It is preferably embedded in a layer including a base layer and a base layer of the second conductivity type. With this structure, the channel regions formed in the first conductive type first base layer and the first conductive type second base layer are in the vertical direction. Compared to a structure in which the channel region is formed in the lateral direction, the area of the semiconductor device can be reduced.
[0021]
In the semiconductor device according to the present invention, the first gate electrode is embedded in a layer including a second conductivity type second semiconductor layer, a first conductivity type second base layer, and a second conductivity type floating emitter layer. The one gate electrode preferably does not reach the first base layer of the first conductivity type. According to this structure, the junction area between the second conductivity type floating emitter layer and the first conductivity type first base layer can be formed in a wide range. This large area leads to a large area operating as a thyristor, and the thyristor operation occurs over a wide range, so that the on-voltage of the element can be lowered.
[0022]
In the semiconductor device according to the present invention, the first gate electrode includes the second conductive type second semiconductor layer, the first conductive type second base layer, the second conductive type floating emitter layer, and the first conductive type first. It is preferably embedded in a layer including a base layer. When the thyristor is turned on, an accumulation region is formed in the second conductivity type floating emitter layer in the vicinity of the first gate electrode. According to this structure, the area of the accumulation region can be increased compared to a structure in which the first gate electrode does not reach the first base layer of the first conductivity type. For this reason, the turn-on voltage of the thyristor can be lowered.
[0023]
The accumulation region is a region where carriers of the first conductivity type are accumulated in the semiconductor layer of the first conductivity type. For example, when the semiconductor layer is n-type, the accumulation region is n-type. When the semiconductor layer is p-type, the accumulation region is p-type.
[0024]
(2) A semiconductor device according to the present invention is a semiconductor device having a thyristor, and includes first, second, and third field effect transistors, and the thyristor includes a first semiconductor layer of a first conductivity type, a second conductor A first conductivity type first base layer and a second conductivity type floating emitter layer. The first field effect transistor includes a second conductivity type second semiconductor layer, a first conductivity type second emitter layer. A base layer, a second conductivity type floating emitter layer, and a first gate electrode, wherein the first conductivity type first base layer and the first conductivity type second base layer are formed by a second conductivity type floating emitter layer; The second conductivity type floating emitter layer and the second conductivity type second semiconductor layer are separated from each other by the first conductivity type second base layer, and the second field effect transistor is Conductive flow A device including a first emitter layer, a first conductivity type first base layer, a second conductivity type base layer, and a second gate electrode, and an element including the second field effect transistor applies a trigger current for operating the thyristor; The field effect transistor includes a third gate electrode and a third semiconductor layer of the first conductivity type. When the first and second field effect transistors are off, the third field effect transistor is on, and carriers in the thyristor are third. A semiconductor device having a thyristor that is discharged out of the thyristor through a field effect transistor.
[0025]
The semiconductor device according to the present invention includes a third field effect transistor. The third field effect transistor is turned on when the first and second field effect transistors are turned off. For this reason, when the thyristor is turned off, the carriers accumulated in the vicinity of the third field effect transistor are surely discharged out of the thyristor through the third field effect transistor. Therefore, the turn-off characteristics of the thyristor can be improved.
[0026]
The semiconductor device according to the present invention can be configured as follows. That is,
The first gate electrode is embedded in a trench formed in a layer including a second conductive type second semiconductor layer, a first conductive type second base layer, and a second conductive type floating emitter layer,
The second gate electrode includes a second conductivity type second semiconductor layer, a first conductivity type second base layer, a second conductivity type floating emitter layer, a first conductivity type first base layer, and a second conductivity type. Embedded in the trench formed in the layer including the base layer,
The third gate electrode is embedded in the same trench as the second gate electrode,
The third semiconductor layer of the first conductivity type is in the second semiconductor layer of the second conductivity type.
[0027]
In this configuration, the third gate electrode is embedded in the same trench as the second gate electrode. Therefore, the integration degree of the semiconductor device can be improved as compared with the case where the third gate electrode and the second gate electrode are embedded in different trenches.
[0028]
The semiconductor device according to the present invention can be configured as follows. That is, the first gate electrode is embedded in a trench formed in a layer including a second conductive type second semiconductor layer, a first conductive type second base layer, and a second conductive type floating emitter layer,
The second gate electrode includes a second conductivity type second semiconductor layer, a first conductivity type second base layer, a second conductivity type floating emitter layer, a first conductivity type first base layer, and a second conductivity type. Embedded in the trench formed in the layer including the base layer,
The third gate electrode is embedded in the same trench as the second gate electrode,
The third semiconductor layer of the first conductivity type is between the trench in which the third gate electrode is embedded and the trench located next to the trench.
The third semiconductor layer of the first conductivity type reaches the base layer of the second conductivity type.
[0029]
In this configuration, the first conductivity type third semiconductor layer reaches the second conductivity type base layer. Accordingly, the third field effect transistor can be positioned inside the semiconductor device as compared with the case where the first conductivity type third semiconductor layer is in the second conductivity type second semiconductor layer. The accumulated carrier can be discharged out of the thyristor more smoothly. As a result, the turn-off characteristics of the thyristor can be improved.
It becomes possible.
[0030]
Further, since the third semiconductor layer of the first conductivity type is located between the trench in which the third gate electrode is embedded and the trench located adjacent thereto, the plane area of the third semiconductor layer of the first conductivity type Can be prevented from spreading. That is, in order for the third field effect transistor to operate, the third semiconductor layer of the first conductivity type must have a relatively high concentration. Therefore, when the first conductive type third semiconductor layer reaches the second conductive type base layer at a relatively deep position, the amount of the first conductive type third semiconductor layer diffused in the lateral direction is large. Therefore, the plane area of the first conductivity type third semiconductor layer is increased. This hinders high integration of semiconductor devices. In this configuration, since the first conductive type third semiconductor layer is sandwiched between the trenches, it is possible to prevent an increase in the plane area of the first conductive type third semiconductor layer.
[0031]
(3) A method of manufacturing a semiconductor device according to the present invention includes a first conductivity type base layer of a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type base layer. Introducing impurities to form a first conductivity type first base layer, and introducing a second conductivity type impurity into the first conductivity type first base layer to form a second conductivity type floating emitter layer Forming a first conductivity type second base layer by introducing a first conductivity type impurity into the second conductivity type floating emitter layer; and forming the first conductivity type second base layer into the second conductivity type floating emitter layer. , Introducing a second conductivity type impurity to form a second conductivity type second semiconductor layer; a second conductivity type second semiconductor layer; a first conductivity type second base layer; a second conductivity type Forming a first gate electrode embedded in a layer including the floating emitter layer of The exposed surface of the second conductive type semiconductor layer, the first conductive type second base layer, the second conductive type floating emitter layer, the first conductive type first base layer, and the second conductive type base layer. And a step of forming a second gate electrode through an insulating film thereon.
[0032]
The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a structure in which the second gate electrode is formed on the surface of the semiconductor substrate via an insulating film. Examples of techniques for introducing impurities include ion implantation and impurity diffusion.
[0033]
The method for manufacturing a semiconductor device according to the present invention introduces a first conductivity type impurity into a second conductivity type base layer of a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type base layer. Forming a first conductivity type first base layer, and introducing a second conductivity type impurity into the first conductivity type first base layer to form a second conductivity type floating emitter layer. A step of introducing a first conductivity type impurity into the second conductivity type floating emitter layer to form a first conductivity type second base layer; a second conductivity type second base layer; A step of forming a second conductive type second semiconductor layer by introducing a conductive type impurity; a second conductive type second semiconductor layer; a first conductive type second base layer; and a second conductive type floating emitter. Forming a first gate electrode embedded in a layer including a layer, and a second conductivity type A second semiconductor layer, a second conductivity type second base layer, a second conductivity type floating emitter layer, a first conductivity type first base layer, and a second layer embedded in a layer including a second conductivity type base layer; Forming a gate electrode.
[0034]
The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a structure in which the second gate electrode is buried. Note that the first gate electrode and the second gate electrode may be formed at the same time, the first gate electrode may be formed first, or the second gate electrode may be formed first. Examples of techniques for introducing impurities include ion implantation and impurity diffusion.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
{Description of structure}
FIG. 1 is a cross-sectional view of a first embodiment of a semiconductor device according to the present invention. The semiconductor device 10 includes an anode electrode 20, p ⁺ Type anode layer 14, n ⁺ Type buffer layer 16, n ^- A mold base layer 18 is provided, which are laminated in order. The material of the anode electrode 210 is a metal. p ⁺ Type anode layer 14, n ⁺ Type buffer layer 16 and n ^- The material of the mold base layer 18 is a silicon single crystal. p ⁺ The type anode layer 14 is an example of a first semiconductor layer of a first conductivity type.
[0036]
n ^- P from the surface of the mold base layer 18 toward the inside ^- A mold first base layer 22 is formed. p ^- From the surface of the mold first base layer 22 to the inside, n ⁺ A type floating emitter layer 24 is formed. n ⁺ P from the surface of the floating emitter layer 24 to the inside ^- A mold second base layer 26 is formed. p ^- From the surface of the mold second base layer 26 to the inside, n ⁺ The mold cathode layers 28, 30, and 32 are formed at intervals. n ⁺ The type cathode layers 28, 30, and 32 are examples of the second conductivity type second semiconductor layer.
[0037]
n ⁺ Type cathode layer 28, p ^- Penetrates the mold second base layer 26 and n ⁺ There is a trench 34 that reaches the mold floating emitter layer 24. A gate electrode 40 made of polycrystalline silicon is embedded in the trench 34. The gate electrode 40 is a buried gate electrode. A silicon oxide film 46 is formed between the side surface of the trench 34 and the gate electrode 40 and between the bottom surface of the trench 34 and the gate electrode 40. n ⁺ Type cathode layer 28, p ^- Mold second base layer 26, n ⁺ A field effect transistor is constituted by the type floating emitter layer 24 and the gate electrode 40.
[0038]
n ⁺ Type cathode layer 30, p ^- Penetrates the mold second base layer 26 and n ⁺ There is a trench 36 that reaches the mold floating emitter layer 24. A gate electrode 42 made of polycrystalline silicon is buried in the trench 36. The gate electrode 42 is a buried gate electrode. A silicon oxide film 48 is formed between the side surface of the trench 36 and the gate electrode 42 and between the bottom surface of the trench 36 and the gate electrode 42. n ⁺ Type cathode layer 30, p ^- Mold second base layer 26, n ⁺ A field effect transistor is constituted by the type floating emitter layer 24 and the gate electrode 42.
[0039]
n ⁺ Type cathode layer 32, p ^- Penetrates the mold second base layer 26 and n ⁺ There is a trench 38 that reaches the mold floating emitter layer 24. A gate electrode 44 made of polycrystalline silicon is buried in the trench 38. The gate electrode 44 is a buried gate electrode. A silicon oxide film 50 is formed between the side surface of the trench 38 and the gate electrode 44 and between the bottom surface of the trench 38 and the gate electrode 44. n ⁺ Type cathode layer 32, p ^- Mold second base layer 26, n ⁺ A field effect transistor is constituted by the type floating emitter layer 24 and the gate electrode 44.
[0040]
The gate electrode 52 is n through the gate oxide film 54. ^- P on the surface of the mold base layer 18 ^- On the surface of the mold first base layer 22, n ⁺ P on the surface of the type floating emitter layer 24 ^- On the surface of the mold second base layer 26 and n ⁺ It is formed on the surface of the mold cathode layer 32.
[0041]
Cathode electrode 56 is p ^- On the surface of the mold first base layer 22, p ^- On the surface of the mold second base layer 26, n ⁺ It is formed on the surface of the mold cathode layer 28, 30, 32. n ^- N on the surface of the mold base layer 18 ⁺ A silicon oxide film 58 is formed on the surface of the mold floating emitter layer 24 and on the surfaces of the gate electrodes 40, 42, 44, 52. These are electrically insulated from the cathode electrode 56 by the silicon oxide film 58.
[0042]
n ⁺ Type floating emitter layer 24, p ^- Mold first base layer 22, n ^- Mold base layer 18, n ⁺ Type buffer layer 16, p ⁺ A thyristor is constituted by the mold anode layer 14. N ⁺ Type cathode layer 32, p ^- Mold first base layer 22, n ^- Mold base layer 18, n ⁺ Type buffer layer 16, p ⁺ The type anode layer 14 constitutes an IGBT.
[0043]
{Description of operation}
Next, the operation of the thyristor of the semiconductor device 10 will be described. First, the turn-on operation will be described. The cathode electrode 56 is grounded, and a positive voltage is applied to the surface type gate electrode 52, the buried type gate electrodes 40, 42 and 44, and the anode electrode 20. When a positive voltage is applied to the surface-type gate electrode 52, p under the gate electrode 52 is applied. ^- Mold first base layer 22, p ^- Channel regions 60 and 62 are formed in the mold second base layer 26, respectively, and n regions under the gate electrode 52 are formed. ⁺ An accumulation region 64 is formed in the mold floating emitter layer 24. As a result, n ⁺ The electrons of the type cathode layer 32 pass through the channel region 62, the accumulation region 64, and the channel region 60, and n ^- It flows into the mold base layer 18. On the other hand, since a positive voltage is also applied to the anode electrode 20, p ⁺ Type anode layer 14 has n holes ^- Implanted into the mold base layer 18 and p ^- The mold flows into the first base layer 22. n ^- The IGBT is turned on by these electrons and holes injected into the mold base layer 18.
[0044]
p ^- The holes flowing into the mold first base layer 22 are n ⁺ Type floating emitter layer 24, p ^- Mold first base layer 22, n ^- The base current of the NPN transistor formed by the mold base layer 18 becomes the ON current of the NPN transistor. That is, n ⁺ Type floating emitter layer 24, p ^- Mold first base layer 22, n ^- Mold base layer 18, n ⁺ Type buffer layer 16, p ⁺ The thyristor composed of the type anode layer 14 is in a latch-up state. As a result, the thyristor is turned on.
[0045]
When the thyristor is turned on, the hole is p ⁺ Type anode layer 14 to p ^- It is supplied to the mold first base layer 22. Electron is n ⁺ Type cathode layers 28, 30, 32 to n ⁺ Supplied to the type floating emitter layer 24. That is, a positive voltage is applied to the buried gate electrodes 40, 42, and 44, respectively. Therefore, p ^- A channel region (for example, a channel region 66) is formed in a region of the mold second base layer 26 in the vicinity of the gate electrodes 40, 42, and 44. As a result, electrons are n ⁺ N-type cathode layers 28, 30, and 32 through these channel regions ⁺ Supplied to the type floating emitter layer 24. With these electrons and these holes, the thyristor can continue to turn on.
[0046]
Next, the turn-off operation will be described. When the potentials of the surface type gate electrode 52 and the buried type gate electrodes 40, 42, 44 are set to 0 V or a negative potential, the channel regions 60, 62 under the gate electrode 52 and the p in the vicinity of the gate electrodes 40, 42, 44 are provided. ^- The channel region of the mold second base layer 26 disappears. As a result, n ⁺ Type cathode layers 28, 30, 32 to n ⁺ The supply of electrons to the mold floating emitter layer 24 is stopped. On the other hand, p ⁺ Type anode layer 14 to p ^- The holes supplied to the mold first base layer 22 are p. ^- It flows through the mold first base layer 22 and is absorbed by the cathode electrode 56. As a result, the thyristor is turned off.
[0047]
{Description of manufacturing method}
An example of a method for manufacturing the semiconductor device 10 shown in FIG. 1 will be described. As shown in FIG. ⁺ A silicon substrate to be the mold anode layer 14 is prepared. The p-type impurity is boron. The concentration of the p-type impurity is 1 × 10 ¹⁸ cm ^-3 ~ 1x10 ¹⁹ cm ^-3 It is. The thickness of the anode layer 14 is 200 μm to 300 μm. p ⁺ N on the anode layer 14 by epitaxial growth ⁺ A mold buffer layer 16 is formed. The n-type impurity is phosphorus. The concentration of n-type impurities is 1 × 10 ¹⁶ cm ^-3 ~ 1x10 ¹⁷ cm ^-3 It is. The buffer layer 16 has a thickness of 10 μm to 15 μm. n ⁺ N on the buffer layer 16 by epitaxial growth. ^- A mold base layer 18 is formed. The n-type impurity is phosphorus. The concentration of n-type impurities is 1 × 10 ¹⁴ cm ^-3 ~ 2x10 ¹⁴ cm ^-3 It is. n ^- The mold base layer 18 has a thickness of 60 μm to 70 μm.
[0048]
As shown in FIG. 3, n is implanted by ion implantation. ^- P from the surface of the mold base layer 18 toward the inside ^- The mold first base layer 22 is formed. p ^- The depth of the mold first base layer 22 is 2.5 μm to 3.0 μm. The p-type impurity is boron. The concentration of the p-type impurity is 1 × 10 ¹⁷ cm ^-3 ~ 2x10 ¹⁷ cm ^-3 It is. Next, p by ion implantation. ^- From the surface of the mold first base layer 22 to the inside, n ⁺ A type floating emitter layer 24 is formed. n ⁺ The depth of the type floating emitter layer 24 is 2 μm. The n-type impurity is phosphorus. The concentration of n-type impurities is 1 × 10 ¹⁸ cm ^-3 It is. And n by ion implantation ⁺ P from the surface of the floating emitter layer 24 to the inside ^- A mold second base layer 26 is formed. p ^- The depth of the mold second base layer 26 is 1 μm. The p-type impurity is boron. The concentration of the p-type impurity is 1 × 10 ¹⁶ cm ^-3 It is. And p by ion implantation ^- From the surface of the mold second base layer 26 to the inside, n ⁺ The mold cathode layers 28, 30, and 32 are formed. n ⁺ The depth of the mold cathode layers 28, 30 and 32 is 0.5 μm. The n-type impurity is arsenic. The concentration of n-type impurities is 1 × 10 ²⁰ cm ^-3 It is.
[0049]
As shown in FIG. 4, n is obtained by photolithography technique and etching technique. ⁺ Type cathode layer 28, p ^- Penetrates the mold second base layer 26 and n ⁺ Trench 34, n reaching the type floating emitter layer 24 ⁺ Type cathode layer 30, p ^- Penetrates the mold second base layer 26 and n ⁺ Trench 36, n reaching the type floating emitter layer 24 ⁺ Type cathode layer 32, p ^- Penetrates the mold second base layer 26 and n ⁺ A trench 38 reaching the mold floating emitter layer 24 is formed. The depth of the trenches 34, 36 and 38 is 1.5 μm.
[0050]
As shown in FIG. 5, silicon oxide films 46, 48 and 50 having a thickness of 50 nm are formed on the side and bottom surfaces of the trench by thermal oxidation. Next, a polycrystalline silicon film having a thickness of 1 μm is buried in the trenches 34, 36, and 38 by CVD. Then, this polycrystalline silicon film is cut by an etching technique to form buried gate electrodes 40, 42, 44 in the trenches 34, 36, 38.
[0051]
As shown in FIG. ^- A silicon oxide film is formed by thermal oxidation so as to cover the mold base layer 18. The silicon oxide film becomes a gate oxide film and has a thickness of 50 nm. A polycrystalline silicon film is formed on the silicon oxide film by CVD. This polycrystalline silicon film serves as a gate electrode, and its thickness is 0.4 μm. The polycrystalline silicon film and the silicon oxide film are patterned by photolithography technique and etching technique. As a result, n ^- P on the surface of the mold base layer 18 ^- On the surface of the mold first base layer 22, n ⁺ P on the surface of the type floating emitter layer 24 ^- On the surface of the mold second base layer 26 and n ⁺ A gate electrode 52 is formed on the surface of the mold cathode layer 32 via a gate oxide film 54.
[0052]
As shown in FIG. ^- A silicon oxide film 58 having a thickness of 0.1 μm is formed by CVD so as to cover the mold base layer 18. The silicon oxide film 58 is patterned by a photolithography technique and an etching technique. As a result, n ^- N on the surface of the mold base layer 18 ⁺ A silicon oxide film 58 is left on the surface of the mold floating emitter layer 24 and on the surfaces of the gate electrodes 40, 42, 44, 52.
[0053]
As shown in FIG. 1, Al which becomes the cathode electrode 56 is formed by sputtering. ^- The mold base layer 18 is formed so as to cover it. The thickness of this film is 5 μm. The film is patterned by photolithography and etching techniques. As a result, p ^- On the surface of the mold first base layer 22, p ^- On the surface of the mold second base layer 26, n ⁺ A cathode electrode 56 is formed on the surface of the mold cathode layers 28, 30, 32. And p ⁺ An anode electrode 20 is formed on the surface of the mold anode layer 14 by vapor deposition. Thus, the semiconductor device 10 is completed.
[0054]
{Description of effect}
(Effect 1)
Since the semiconductor device 10 shown in FIG. 1 includes the field effect transistor including the buried gate electrodes 40, 42, and 44, the turn-on voltage of the thyristor can be lowered for the following two reasons. Explain the first reason. These field effect transistors allow p ^- A channel region is formed in the mold second base layer 26. The current flowing through the thyristor is n ⁺ Type floating emitter layer 24-channel region-n ⁺ It flows through the path of the mold cathode layer 28, 30, 32. The gate electrodes 40, 42 and 44 are embedded. For this reason, the said path | route can be shortened. Explain the second reason. There are a plurality of buried gate electrodes 40, 42, 44. For this reason, the area of the channel region can be increased.
[0055]
(Effect 2)
In the semiconductor device 10 shown in FIG. 1, since the gate electrodes 40, 42, and 44 are embedded, n ⁺ The gate electrodes 40, 42, 44 can be positioned on the body portion (portions other than the end portions) of the mold floating emitter layer 24. Therefore, when the potential of the gate electrodes 40, 42, 44 is set to 0V or a negative potential for turning off the thyristor, n ⁺ The potential of the type floating emitter layer 24 can be brought close to 0 V or a negative potential. Therefore, when the thyristor is turned off, n ⁺ Type floating emitter layer 24 and p ^- It is possible to prevent a high voltage in the reverse direction from being applied to the junction with the mold second base layer 26. Therefore, since the possibility that this junction breaks down can be reduced, the thyristor can be turned off more reliably.
[0056]
(Effect 3)
In the semiconductor device 10 shown in FIG. ^- P on the surface of the mold base layer 18 ^- On the surface of the mold first base layer 22, n ⁺ P on the surface of the type floating emitter layer 24 ^- On the surface of the mold second base layer 26 and n ⁺ A gate oxide film 54 is formed on the surface of the mold cathode layer 32. Therefore, the channel concentration at the time of the IGBT operation can be individually set at the same time that the fabrication is easy. That is, there is a merit that the threshold voltage setting of this element is not limited.
[0057]
(Effect 4)
The semiconductor device 10 shown in FIG. ⁺ Type cathode layers 28, 30, 32 are n ⁺ Surrounded by a type floating emitter layer 24. For this reason, p ^- Mold first base layer 22 and n ⁺ The type cathode layers 28, 30, 32 are n ⁺ It is separated by a type floating emitter layer 24. Therefore, at turn-off, p ⁺ Type anode layer 14 to p ^- The holes injected into the mold first base layer 22 are n ⁺ It can prevent flowing into the mold cathode layers 28, 30 and 32. This is because this element is n ⁺ This indicates that there is no parasitic thyristor including the cathode layer, and that the problem that the turn-off is impossible due to the ON operation of the parasitic thyristor does not occur.
[0058]
[Second Embodiment]
{Description of structure}
FIG. 8 is a cross-sectional view of a second embodiment of a semiconductor device according to the present invention. The same parts as those of the first embodiment are denoted by the same reference numerals and the description thereof is omitted. The difference from the first embodiment is the depth of the trenches 34, 36, and 38. The depth values of the trenches 34, 36, and 38 in the second embodiment are larger than the depth values of the trenches 34, 36, and 38 in the first embodiment. That is, the trench 34 is n ⁺ Type cathode layer 28, p ^- Mold second base layer 26, n ⁺ P-type floating emitter layer 24 and p ^- The mold first base layer 22 is reached. The trench 36 is n ⁺ Type cathode layer 30, p ^- Mold second base layer 26, n ⁺ P-type floating emitter layer 24 and p ^- The mold first base layer 22 is reached. Trench 38 is n ⁺ Type cathode layer 32, p ^- Mold second base layer 26, n ⁺ P-type floating emitter layer 24 and p ^- The mold first base layer 22 is reached. Gate electrodes 40, 42, 44 are p ^- The mold first base layer 22 is reached.
[0059]
{Description of operation}
The operation of the semiconductor device 10 shown in FIG. 8 is the same as the operation of the semiconductor device 10 of the first embodiment shown in FIG.
[0060]
{Description of manufacturing method}
The manufacturing method of the semiconductor device 10 shown in FIG. 8 is different from the manufacturing method of the semiconductor device 10 of the first embodiment shown in FIG. 1 in that the trenches 34, 36, and 38 are formed in the step shown in FIG. ^- The point is that the first base layer 22 is formed to reach the mold. The other points are the same.
[0061]
{Description of effect}
The semiconductor device 10 shown in FIG. 8 produces the same effects as (Effect 1) to (Effect 4) of the semiconductor device 10 of the first embodiment shown in FIG. In addition to these, the following effects occur.
[0062]
(Effect 1)
The semiconductor device 10 shown in FIG. 8 and the semiconductor device 10 of the first embodiment shown in FIG. ⁺ An accumulation region 68 is formed in a region in the vicinity of the gate electrodes 40, 42, 44 in the type floating emitter layer 24. The accumulation region 68 has a low resistance because carriers are accumulated. In the semiconductor device 10 according to the second embodiment, the area of the accumulation region 68 is larger than that of the semiconductor device 10 according to the first embodiment. From this point, the semiconductor device 10 of the second embodiment can reduce the turn-on voltage of the thyristor.
[0063]
[Third Embodiment]
{Description of structure}
FIG. 9 is a sectional view of a semiconductor device according to a third embodiment of the present invention. The same parts as those of the first embodiment are denoted by the same reference numerals and the description thereof is omitted. The difference from the first embodiment is the depth of the trench 38. That is, the trench 38 is n ⁺ Type cathode layer 32, p ^- Mold second base layer 26, n ⁺ Type floating emitter layer 24, p ^- Penetrates the mold first base layer 22 and n ^- The mold base layer 18 is reached. The gate electrode 44 of the trench 38 also serves as the gate electrode 52 of the semiconductor device 10 of the first embodiment. Therefore, the semiconductor device 10 of the third embodiment does not have the surface type gate electrode 52.
[0064]
{Description of operation}
The operation of the thyristor of the semiconductor device 10 shown in FIG. 9 will be described. First, the turn-on operation will be described. The cathode electrode 56 is grounded, and a positive voltage is applied to the buried gate electrodes 40, 42, 44 and the anode electrode 20. When a positive voltage is applied to the gate electrode 44, p near the gate electrode 44 is ^- Mold first base layer 22, p ^- Channel regions 70 and 72 are formed in the second mold base layer 26, respectively, and n regions near the gate electrode 44 are formed. ⁺ An accumulation region 74 is formed in the mold floating emitter layer 24. As a result, n ⁺ The electrons of the type cathode layer 32 pass through the channel region 72, the accumulation region 74, and the channel region 70, and n ^- Implanted into the mold base layer 18. On the other hand, since a positive voltage is also applied to the anode electrode 20, p ⁺ Type anode layer 14 has n holes ^- P is injected into the mold base layer 18 ^- The mold flows into the first base layer 22. n ^- The IGBT is turned on by these electrons and holes injected into the mold base layer 18.
[0065]
p ^- The holes flowing into the mold first base layer 22 are n ⁺ Type floating emitter layer 24, p ^- Mold first base layer 22, n ^- The base current of the NPN transistor formed by the mold base layer 18 becomes the ON current of the NPN transistor. That is, n ⁺ Type floating emitter layer 24, p ^- Mold first base layer 22, n ^- Mold base layer 18, n ⁺ Type buffer layer 16, p ⁺ The thyristor composed of the type anode layer 14 is in a latch-up state. As a result, the thyristor is turned on.
[0066]
When the thyristor is turned on, the hole is p ⁺ Type anode layer 14 to p ^- It is supplied to the mold first base layer 22. Electron is n ⁺ Type cathode layers 28, 30, 32 to n ⁺ Supplied to the type floating emitter layer 24. That is, a positive voltage is applied to the buried gate electrodes 40, 42, and 44, respectively. Therefore, p ^- A channel region (for example, a channel region 72) is formed in a region of the mold second base layer 26 in the vicinity of the gate electrodes 40, 42, and 44. As a result, electrons are n ⁺ N-type cathode layers 28, 30, and 32 through these channel regions ⁺ Supplied to the type floating emitter layer 24. With these electrons and these holes, the thyristor can continue to turn on.
[0067]
Next, the turn-off operation will be described. When the potentials of the buried gate electrodes 40, 42, 44 are set to 0V or a negative potential, p in the vicinity of the gate electrodes 40, 42, 44 is obtained. ^- The channel region of the mold second base layer 26 disappears. As a result, n ⁺ Type cathode layers 28, 30, 32 to n ⁺ The supply of electrons to the mold floating emitter layer 24 is stopped. On the other hand, p ⁺ Type anode layer 14 to p ^- The holes supplied to the mold first base layer 22 are p. ^- It flows through the mold first base layer 22 and is absorbed by the cathode electrode 56. As a result, the thyristor is turned off.
[0068]
{Description of manufacturing method}
The manufacturing method of the semiconductor device 10 of the third embodiment shown in FIG. 9 proceeds to the step shown in FIG. 10 after the steps shown in FIGS. 2 and 3 of the manufacturing method of the semiconductor device 10 of the first embodiment.
[0069]
As shown in FIG. 10, n is applied by photolithography and etching. ⁺ Type cathode layer 28, p ^- Penetrates the mold second base layer 26 and n ⁺ Trench 34 and n reaching the type floating emitter layer 24 ⁺ Type cathode layer 30, p ^- Penetrates the mold second base layer 26 and n ⁺ A trench 36 reaching the mold floating emitter layer 24 is formed. The depth of the trenches 34 and 36 is the same as the depth of the trenches 34 and 36 in the first embodiment. Next, by photolithography technology and etching technology, n ⁺ Type cathode layer 32, p ^- Mold second base layer 26, n ⁺ Type floating emitter layer 24, p ^- Penetrates the mold first base layer 22 and n ^- A trench 38 reaching the mold base layer 18 is formed. The depth of the trench 38 is 5 μm. The trench 38 may be formed first, and the trenches 34 and 36 may be formed later.
[0070]
As shown in FIG. 11, silicon oxide films 46, 48 and 50 are formed on the side and bottom surfaces of the trench by thermal oxidation. The thicknesses of the silicon oxide films 46, 48 and 50 are the same as those in the first embodiment. Next, a polycrystalline silicon film is buried in the trenches 34, 36, and 38 by CVD. Then, this polycrystalline silicon film is cut by an etching technique to form buried gate electrodes 40, 42, 44 in the trenches 34, 36, 38. The thickness of the polycrystalline silicon film is the same as in the first embodiment.
[0071]
As shown in FIG. ^- A silicon oxide film 58 is formed by CVD so as to cover the mold base layer 18. The thickness of the silicon oxide film 58 is the same as that of the first embodiment. The silicon oxide film 58 is patterned by a photolithography technique and an etching technique. As a result, n ^- N on the surface of the mold base layer 18 ⁺ A silicon oxide film 58 is left on the surface of the mold floating emitter layer 24 and on the surfaces of the gate electrodes 40, 42 and 44.
[0072]
As shown in FIG. 9, using the same method as in the first embodiment, p ^- On the surface of the mold first base layer 22, p ^- On the surface of the mold second base layer 26, n ⁺ A cathode electrode 56 is formed on the surface of the mold cathode layers 28, 30, 32. And p ⁺ An anode electrode 20 is formed on the surface of the mold anode layer 14. Thus, the semiconductor device 10 is completed.
[0073]
{Description of effect}
The semiconductor device 10 of the third embodiment shown in FIG. 9 produces the same effects as (Effect 1), (Effect 2), and (Effect 4) of the semiconductor device 10 of the first embodiment shown in FIG. In addition to these, the following effects are produced.
[0074]
(Effect 1)
In the semiconductor device 10 shown in FIG. 9, the gate electrode 44 that is a component of the IGBT is n ⁺ Type cathode layer 32, p ^- Mold second base layer 26, n ⁺ Type floating emitter layer 24, p ^- Mold first base layer 22, n ^- It is embedded in a layer including the mold base layer 18. With this structure, the channel regions 70 and 72 are in the vertical direction. Therefore, the area of the semiconductor device can be reduced as compared with the structure in which the channel region is formed in the lateral direction.
[0075]
[Fourth Embodiment]
{Description of structure}
FIG. 13 is a cross-sectional view of a fourth embodiment of a semiconductor device according to the present invention. The same parts as those of the third embodiment shown in FIG. The difference from the third embodiment is the depth of the trenches 34 and 36. The depth value of the trenches 34 and 36 in the fourth embodiment is larger than the depth value of the trenches 34 and 36 in the third embodiment. That is, the trench 34 is n ⁺ Type cathode layer 28, p ^- Mold second base layer 26, n ⁺ P-type floating emitter layer 24 and p ^- The mold first base layer 22 is reached. The trench 36 is n ⁺ Type cathode layer 30, p ^- Mold second base layer 26, n ⁺ P-type floating emitter layer 24 and p ^- The mold first base layer 22 is reached. The gate electrodes 40 and 42 are p ^- The mold first base layer 22 is reached.
[0076]
{Description of operation}
The operation of the semiconductor device 10 shown in FIG. 13 is the same as the operation of the semiconductor device 10 of the third embodiment shown in FIG.
[0077]
{Description of manufacturing method}
The manufacturing method of the semiconductor device 10 shown in FIG. 13 is different from the manufacturing method of the semiconductor device 10 of the third embodiment in that the trenches 34 and 36 are formed in the step shown in FIG. ^- The point is that the first base layer 22 is formed to reach the mold. The other points are the same.
[0078]
{Description of effect}
The semiconductor device 10 shown in FIG. 13 produces the same effect as the semiconductor device 10 of the third embodiment. Further, the semiconductor device 10 shown in FIG. 13 produces the same effect as (Effect 1) of the semiconductor device 10 of the second embodiment.
[0079]
[Fifth Embodiment]
{Description of structure}
FIG. 14 is a sectional view of a fifth embodiment of a semiconductor device according to the present invention. The same parts as those of the third embodiment shown in FIG. The difference from the third embodiment is that n is in contact with the trench 38. ⁺ P on the surface of the cathode layer 32 ⁺ That is, the type drain layer 80 is formed. Thereby, the gate electrode 44, p ⁺ Type drain layer 80, n ⁺ Type cathode layer 32 and p ^- The type second base layer 26 constitutes a pMOS field effect transistor.
[0080]
{Description of operation}
The turn-on operation of the semiconductor device 10 shown in FIG. 14 is the same as the turn-on operation of the semiconductor device 10 of the third embodiment shown in FIG. The turn-off operation of the semiconductor device 10 shown in FIG. 14 is different from the turn-off operation of the semiconductor device 10 of the third embodiment shown in FIG. 9 because of the pMOS field effect transistor. This will be described with reference to FIG. FIG. 15 is a cross-sectional view of the fifth embodiment.
[0081]
As shown in FIG. 15, during the turn-off operation of the semiconductor device 10, as in the semiconductor device 10 of the third embodiment shown in FIG. ^- Flowing through the mold first base layer 22, p ^- It passes through the connecting portion 82 between the first mold base layer 22 and the cathode electrode 56 and is absorbed by the cathode electrode 56.
[0082]
In addition, the semiconductor device 10 shown in FIG. 15 is absorbed by the cathode electrode 56 through the pMOS field effect transistor. That is, when the potential of the embedded gate electrode 44 is set to 0 V or a negative potential, n ⁺ Type cathode layer 32 and n ⁺ A channel is formed in the mold floating emitter layer 24. As a result, the pMOS field effect transistor is turned on, so that the holes accumulated in the vicinity of the gate electrode 44 are n ⁺ Channel formed in the floating emitter layer 24, p ^- Mold second base layer 26, n ⁺ Channel formed in the cathode layer 32 and p ⁺ It is absorbed by the cathode electrode 56 through the mold drain layer 80.
[0083]
{Description of manufacturing method}
The manufacturing method of the semiconductor device 10 shown in FIG. 14 is different from the manufacturing method of the semiconductor device 10 of the third embodiment shown in FIG. ⁺ After forming the cathode layer 32, n is in contact with the trench 38. ⁺ P on the surface of the cathode layer 32 ⁺ Forming a type drain layer 80; The other points are the same.
[0084]
{Description of effect}
The semiconductor device 10 shown in FIG. 14 produces the same effect as the semiconductor device 10 of the third embodiment shown in FIG. In addition, the following effects are produced.
[0085]
(Effect 1)
14 includes a pMOS field effect transistor (a pMOS field effect transistor includes a gate electrode 44, p ⁺ Type drain layer 80, n ⁺ Type cathode layer 32 and p ^- Mold second base layer 26). The pMOS field effect transistor is turned on when the thyristor is turned off. For this reason, when the thyristor is turned off, holes accumulated in the vicinity of the gate electrode 44 are reliably discharged out of the thyristor via the pMOS field effect transistor. Therefore, the turn-off characteristics of the thyristor can be improved.
[0086]
That is, also in the semiconductor device 10 shown in FIG. 14, when the area of the thyristor is increased in order to reduce the turn-on voltage, the amount of holes stored in the thyristor increases. Because of this, all holes are replaced by p ^- In the structure of flowing directly from the first base layer 22 to the cathode electrode 56, p ^- It takes time for holes accumulated at a position away from the connection portion 82 between the mold first base layer 22 and the cathode electrode 56 (for example, holes near the gate electrode 44) to be discharged to the outside of the thyristor. , May not be discharged. This leads to deterioration of turn-off characteristics.
[0087]
In the semiconductor device 10 shown in FIG. 14, when the thyristor is turned off, holes accumulated in the vicinity of the gate electrode 44 are reliably discharged out of the thyristor through the pMOS field effect transistor. Therefore, the turn-off characteristics of the thyristor can be improved.
[0088]
(Effect 2)
In the semiconductor device 10 shown in FIG. 14, the gate electrode 44 of the pMOS field effect transistor and the gate electrode 44 of the IGBT are buried in the same trench (trench 38). Therefore, the integration degree of the semiconductor device can be improved as compared with the case where the gate electrode of the pMOS field effect transistor and the gate electrode of the IGBT are embedded in different trenches.
[0089]
[Sixth Embodiment]
{Description of structure}
FIG. 16 is a sectional view of a sixth embodiment of a semiconductor device according to the present invention. The same parts as those of the fifth embodiment shown in FIG. The difference from the fifth embodiment is p ⁺ Instead of the type drain layer 80, p ⁺ The type drain layer 84 is provided.
[0090]
{Description of operation}
The turn-on operation of the semiconductor device 10 shown in FIG. 16 is the same as the turn-on operation of the semiconductor device 10 of the fifth embodiment shown in FIG. The turn-off operation of the semiconductor device 10 shown in FIG. 16 is different from the turn-off operation of the semiconductor device 10 of the fifth embodiment shown in FIG.
[0091]
That is, during the turn-off operation of the semiconductor device 10 shown in FIG. ^- In addition to being absorbed by the cathode electrode 56 through the connecting portion 82 and flowing through the first base layer 22, n ^- P formed on the mold base layer 18 ⁺ It is absorbed by the cathode electrode 56 through the mold drain layer 84. In turn-off operation, p ⁺ The potential of the type drain layer 84 is 0 V or a negative voltage.
[0092]
{Description of manufacturing method}
The manufacturing method of the semiconductor device 10 shown in FIG. 16 is substantially the same as the manufacturing method of the semiconductor device 10 of the third embodiment shown in FIG. The difference is that between the trench 38 and the trench 86, p ⁺ A step of forming the mold drain layer 84 is added. p ⁺ The type drain layer 84 can be formed by, for example, ion-implanting impurities such as boron and applying heat treatment.
[0093]
{Description of effect}
The semiconductor device 10 shown in FIG. 16 produces the same effect as the semiconductor device 10 of the third embodiment shown in FIG. In addition, the following effects are produced.
[0094]
(Effect 1)
In the semiconductor device 10 shown in FIG. ⁺ The type drain layer 84 has n ^- The mold base layer 18 is reached. Therefore, the carriers accumulated in the thyristor can be discharged out of the thyristor more smoothly. As a result, the turn-off characteristics of the thyristor can be improved.
[0095]
(Effect 2)
In the semiconductor device 10 shown in FIG. ⁺ The type drain layer 84 can be deepened with a narrow plane area. That is, p ⁺ The type drain layer 84 has a large diffusion depth. Usually, when a deep diffusion layer is formed, the lateral spread increases, and the plane area of the diffusion layer increases. p ⁺ Since the type drain layer 84 is formed between the trench 38 and the trench 86 located adjacent thereto, p ⁺ This can prevent the flat area of the mold drain layer 84 from expanding.
[0096]
[Seventh Embodiment]
{Description of structure}
FIG. 17 is a sectional view of a seventh embodiment of the semiconductor device according to the present invention. The same parts as those of the fifth embodiment shown in FIG. The difference from the fifth embodiment is first that n located between the trenches. ⁺ The type cathode layer is connected. That is, n ⁺ The type cathode layer 88 is formed from the side surface of the trench 34 to the side surface of the trench 36. n ⁺ The mold cathode layer 90 is formed from the side surface of the trench 36 to the side surface of the trench 98. n ⁺ The mold cathode layer 92 is formed from the side surface of the trench 98 to the side surface of the trench 38.
[0097]
In addition, n in contact with the trench 38 ⁺ P on the surface of the cathode layer 92 ⁺ A type drain layer 96 is formed. Thereby, the gate electrode 44, p ⁺ Type drain layer 96, n ⁺ Type cathode layer 92 and p ^- The type second base layer 26 constitutes a pMOS field effect transistor.
[0098]
N ⁺ The p type cathode layers 88, 90, 92 are respectively under p. ^- The mold second base layer 26 is located. These p ^- The mold second base layer 26 may be floating, or may be connected to the cathode electrode 56 in the depth direction of the semiconductor device 10.
[0099]
A trench 98 is formed between the trench 38 and the trench 36. The trench 98 is n ⁺ The type floating emitter layer 24 is reached. A gate electrode 94 is embedded in the trench 98 via a silicon oxide film. The function of the gate electrode 94 is the same as that of the gate electrodes 40 and 42.
[0100]
{Description of operation}
The operation of the semiconductor device 10 shown in FIG. 17 is the same as the operation of the semiconductor device 10 of the fifth embodiment shown in FIG.
[0101]
{Description of manufacturing method}
The manufacturing method of the semiconductor device 10 shown in FIG. 17 is different from the manufacturing method of the semiconductor device 10 according to the embodiment so far. ⁺ It is a formation process of a type | mold cathode layer. That is, in the embodiments so far, for example, as shown in FIG. ⁺ N so as to be separated into mold cathode layers 28, 30, 32 ⁺ A mold cathode layer is formed. In contrast, in the method of manufacturing the semiconductor device 10 shown in FIG. ⁺ When forming the cathode layer, n ⁺ The mold cathode layer is not separated.
[0102]
{Description of effect}
The semiconductor device 10 shown in FIG. 17 produces the same effect as the semiconductor device 10 of the fifth embodiment shown in FIG. In addition, the following effects are produced.
[0103]
In the method for manufacturing the semiconductor device 10 shown in FIG. ⁺ When forming the cathode layer, n ⁺ The mold cathode layer is not separated. For this reason, n ⁺ Compared to the case where the type cathode layer is formed separately, n ⁺ The mold cathode layer can be miniaturized. As a result, the semiconductor device can be highly integrated.
[0104]
[Eighth Embodiment]
{Description of structure}
FIG. 18 is a sectional view of an eighth embodiment of a semiconductor device according to the present invention. The eighth embodiment is p ⁺ A pMOS field effect transistor including a type drain layer 128 is provided. The role of this pMOS field effect transistor is the same as that of the pMOS field effect transistor described in the fifth to seventh embodiments. Hereinafter, the structure of the eighth embodiment will be described.
[0105]
The semiconductor device 100 includes a silicon substrate 102, surface type gate electrodes 124, 126 and p. ⁺ A type drain layer 128 is provided.
[0106]
The silicon substrate 102 is p ⁺ Type anode layer 104, n ⁺ Type buffer layer 106, n ^- The mold base layer 108 is laminated. P of silicon substrate 102 ⁺ A metal anode electrode 110 is formed on the mold anode layer 104 side.
[0107]
n ^- From the surface of the mold base layer 108 to the inside, p ^- A mold first base layer 112 is formed. p ^- From the surface of the mold first base layer 112 to the inside, n ^- A type floating emitter layer 114 is formed. n ^- P-type floating emitter layer 114 from the surface to the inside, p ^- A mold second base layer 116 is formed. p ^- From the surface of the mold second base layer 116 to the inside, n ⁺ The mold cathode layers 118 and 120 are formed at intervals.
[0108]
The gate electrode 124 covered with the insulating layer is n ^- P on the surface of the mold base layer 108 ^- On the surface of the mold first base layer 112, n ^- P on the surface of the floating emitter layer 114 ^- On the surface of the mold second base layer 116 and n ⁺ It is formed over the surface of the mold cathode layer 118. The gate electrode 126 covered with the insulating layer is n ^- P on the surface of the mold base layer 108 ^- On the surface of the mold first base layer 112, n ^- P on the surface of the floating emitter layer 114 ^- On the surface of the mold second base layer 116 and n ⁺ It is formed over the surface of the mold cathode layer 120. Further, the cathode electrode 122 is between the gate electrode 124 and the gate electrode 126 and n ⁺ P on the surface of the cathode layer 118 ^- On the surface of the mold second base layer 116 and n ⁺ It is formed on the surface of the mold cathode layer 120.
[0109]
p ⁺ The type drain layer 128 has n ^- It is formed on the mold base layer 108. p ⁺ The type drain layer 128 is p ^- The mold first base layer 112 is spaced apart from the mold first base layer 112. p ⁺ Type drain layer 128 and p ^- N between the mold first base layer 112 ^- A gate electrode 126 is positioned on the mold base layer 108. Gate electrode 126, p ⁺ Type drain layer 128, n ^- Mold base layer 108 and p ^- A pMOS field effect transistor is configured by the first base layer 112.
[0110]
n ^- Type floating emitter layer 114, p ^- Mold first base layer 112, n ^- Mold base layer 108, n ⁺ Type buffer layer 106, p ⁺ A thyristor is constituted by the mold anode layer 104.
[0111]
{Description of operation}
Next, the operation of the semiconductor device 100 will be described. Since the semiconductor device 100 is characterized by a turn-off operation, only the turn-off operation will be described. When a negative voltage or 0 V is applied to the gate electrodes 124 and 126, the p below the gate electrodes 124 and 126 is applied. ^- Mold first base layer 112, p ^- The channel region formed in the mold second base layer 116 disappears. As a result, n ⁺ Type cathode layers 118, 120 to n ^- The supply of electrons to the type floating emitter layer 114 is stopped. On the other hand, holes in thyristors are p ^- Since the mold first base layer 112 is connected to the cathode electrode 122 in the depth direction of the semiconductor device 100, p ^- It flows through the mold first base layer 112 and is absorbed by the cathode electrode 122. Also, the holes in the thyristor are n n because the pMOS field effect transistor is turned on. ^- Channel formed in the mold base layer 108, p ⁺ It is discharged to the outside of the thyristor through the mold drain layer 128.
[0112]
{Description of effect}
In the semiconductor device 100 shown in FIG. 18, when the thyristor is turned off, holes accumulated in the vicinity of the gate electrode 126 are reliably discharged out of the thyristor through the pMOS field effect transistor. Therefore, the turn-off characteristics of the thyristor can be improved.
[0113]
[Modification]
In the first to seventh embodiments, the number of embedded gate electrodes is plural. However, the present invention is not limited to this, and the number of embedded gate electrodes may be one. However, if the number of buried gate electrodes is made plural, the channel area increases, so that the turn-on voltage of the thyristor can be further reduced.
[0114]
In the first to seventh embodiments, a buried gate electrode is formed by forming a trench and embedding a conductive layer in the trench. However, the present invention is not limited to this. For example, a buried gate electrode may be formed by the following method. A conductive layer is formed on the silicon substrate via an insulating film. The conductive layer is patterned to form a gate electrode that becomes a buried gate electrode. A single crystal layer is formed around the gate electrode by solid layer epitaxial growth.
[0115]
In the first to seventh embodiments, p ^- Mold first base layer 22, n ⁺ The type cathode layer 32 (92) is used as a component of the IGBT. However, the present invention is not limited to this. p ^- Mold first base layer 22, n ⁺ P separate from the cathode layer 32 (92) ^- Type conductive layer, n ⁺ It is good also as providing the type | mold conductive layer and making these into the component of IGBT. Even with such a structure, the effects of the present invention can be obtained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a first embodiment of a semiconductor device according to the invention.
FIG. 2 is a cross-sectional view of a substrate showing a first step of the manufacturing method of the first embodiment of the semiconductor device according to the invention.
FIG. 3 is a cross-sectional view of a substrate showing a second step of the manufacturing method of the first embodiment of the semiconductor device according to the invention.
FIG. 4 is a cross-sectional view of a substrate showing a third step of the manufacturing method of the first embodiment of the semiconductor device according to the invention.
FIG. 5 is a cross-sectional view of a substrate showing a fourth step of the manufacturing method of the first embodiment of the semiconductor device according to the present invention.
FIG. 6 is a cross-sectional view of a substrate showing a fifth step of the manufacturing method of the first embodiment of the semiconductor device according to the invention.
FIG. 7 is a cross-sectional view of a substrate showing a sixth step of the manufacturing method of the first embodiment of the semiconductor device according to the invention.
FIG. 8 is a cross-sectional view of a second embodiment of a semiconductor device according to the present invention.
FIG. 9 is a cross-sectional view of a third embodiment of a semiconductor device according to the present invention.
FIG. 10 is a cross-sectional view of a substrate showing a first step of a manufacturing method of the third embodiment of the semiconductor device according to the invention.
FIG. 11 is a cross-sectional view of a substrate showing a second step of the manufacturing method of the third embodiment of the semiconductor device according to the invention.
FIG. 12 is a cross-sectional view of a substrate showing a third step of the method of manufacturing the semiconductor device according to the third embodiment of the present invention.
FIG. 13 is a cross-sectional view of a fourth embodiment of a semiconductor device according to the present invention.
FIG. 14 is a cross-sectional view of a fifth embodiment of a semiconductor device according to the present invention.
FIG. 15 is a diagram used for explaining the operation of the fifth embodiment of the semiconductor device according to the invention;
FIG. 16 is a cross-sectional view of a sixth embodiment of a semiconductor device according to the present invention.
FIG. 17 is a cross-sectional view of a seventh embodiment of a semiconductor device according to the present invention.
FIG. 18 is a cross-sectional view of an eighth embodiment of a semiconductor device according to the present invention.
FIG. 19 is a cross-sectional view of a semiconductor device having a thyristor disclosed in Japanese Patent Laid-Open No. 5-82775.
[Explanation of symbols]
10 Semiconductor devices
14 p ⁺ Type anode layer
16 n ⁺ Type buffer layer
18 n ^- Mold base layer
20 Anode electrode
22 p ^- Mold first base layer
24 n ⁺ Type floating emitter layer
26 p ^- Mold second base layer
28, 30, 32 n ⁺ Type cathode layer
34, 36, 38 trench
40, 42, 44 Gate electrode
46, 48, 50 Silicon oxide film
52 Gate electrode
54 Gate oxide film
56 Cathode electrode
58 Silicon oxide film
60, 62 channel region
64 Accumulation area
66 channel region
68 Accumulation area
70, 72 channel region
74 Accumulation area
80 p ⁺ Type drain layer
82 connections
84 p ⁺ Type drain layer
86 trench
88, 90, 92 n ⁺ Type cathode layer
94 Gate electrode
96p ⁺ Type drain layer
98 trench
100 Semiconductor device
104 p ⁺ Type anode layer
108 n ^- Mold base layer
112 p ^- Mold first base layer
114 n ^- Type floating emitter layer
116 p ^- Mold second base layer
118, 120 n ⁺ Type cathode layer
124, 126 Gate electrode
128 p ⁺ Type drain layer

Claims (11)

A semiconductor device having a thyristor,
A first semiconductor layer of a first conductivity type;
A second conductivity type base layer stacked above the first conductivity type first semiconductor layer;
A first conductivity type first base layer formed in the second conductivity type base layer and separated from the first conductivity type semiconductor layer by the second conductivity type base layer;
A second conductivity type floating emitter layer formed in the first conductivity type first base layer and separated from the second conductivity type base layer by the first conductivity type first base layer;
A first conductivity type second base layer formed in the second conductivity type floating emitter layer and separated from the first conductivity type first base layer by the second conductivity type floating emitter layer;
A second conductive type second semiconductor layer formed in the first conductive type second base layer and separated from the second conductive type floating emitter layer by the first conductive type second base layer;
A buried type first gate buried so as to be in contact with at least the second conductivity type second semiconductor layer, the first conductivity type second base layer, and the second conductivity type floating emitter layer via an insulating film Electrodes,
The second conductivity type base layer, the first conductivity type first base layer, the second conductivity type floating emitter layer, the first conductivity type second base layer, and the second conductivity type second semiconductor. A second gate electrode formed so as to be in contact with the layer through an insulating film,
The thyristor, the first conductive type first semiconductor layer of, makes the second conductivity type base layer, comprising a floating emitter layer of the first base layer and the second conductivity type of said first conductivity type,
A trigger current for operating a thyristor by a field effect transistor including the second conductivity type base layer, the first conductivity type first base layer, the second conductivity type floating emitter layer, and the second gate electrode. A semiconductor device having a thyristor. In claim 1,
The second gate electrode includes a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, a floating emitter layer of the second conductivity type, a first base layer of the first conductivity type, and A semiconductor device having a thyristor formed on an exposed surface of a base layer of the second conductivity type via an insulating film. In claim 1,
The second gate electrode includes a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, a floating emitter layer of the second conductivity type, a first base layer of the first conductivity type, and A semiconductor device having a thyristor embedded so as to be in contact with a layer including a base layer of the second conductivity type through an insulating film . In any one of Claims 1-3,
The first gate electrode is in contact with a layer including the second conductive type second semiconductor layer, the first conductive type second base layer, and the second conductive type floating emitter layer via an insulating film. Embedded,
The semiconductor device having a thyristor, wherein the first gate electrode does not reach the first base layer of the first conductivity type. In any one of Claims 1-3,
The first gate electrode includes a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, a floating emitter layer of the second conductivity type, and a first base layer of the first conductivity type. A semiconductor device having a thyristor embedded so as to be in contact with an included layer through an insulating film . A semiconductor device having a thyristor,
A first semiconductor layer of a first conductivity type;
A second conductivity type base layer stacked above the first conductivity type first semiconductor layer;
A first conductivity type first base layer formed in the second conductivity type base layer and separated from the first conductivity type semiconductor layer by the second conductivity type base layer;
A second conductivity type floating emitter layer formed in the first conductivity type first base layer and separated from the second conductivity type base layer by the first conductivity type first base layer;
A first conductivity type second base layer formed in the second conductivity type floating emitter layer and separated from the first conductivity type first base layer by the second conductivity type floating emitter layer;
A second conductive type second semiconductor layer formed in the first conductive type second base layer and separated from the second conductive type floating emitter layer by the first conductive type second base layer;
A first conductive third semiconductor layer formed in the second conductive second semiconductor layer and separated from the first conductive second base layer by the second conductive second semiconductor layer; ,
A buried type first gate buried so as to be in contact with at least the second conductivity type second semiconductor layer, the first conductivity type second base layer, and the second conductivity type floating emitter layer via an insulating film Electrodes,
The second conductivity type base layer, the first conductivity type first base layer, the second conductivity type floating emitter layer, the first conductivity type second base layer, and the second conductivity type second semiconductor. A second gate electrode formed so as to be in contact with the layer through an insulating film;
A second base layer of the first conductivity type, a second semiconductor layer of the second conductivity type, and a third gate electrode formed through an insulating film and the third semiconductor layer of the first conductivity type;
The thyristor, the first conductive type first semiconductor layer of, makes the second conductivity type base layer, comprising a floating emitter layer of the first base layer and the second conductivity type of said first conductivity type,
The first field effect transistor, a second semiconductor layer of the second conductivity type, becomes the first conductivity type second base layer of, including the floating emitter layer and the first gate electrode of the second conductivity type,
The second field effect transistor, said second conductivity type floating emitter layer, first base layer of the first conductivity type, comprises a base layer and the second gate electrode of the second conductivity type,
The third field effect transistor includes the first conductive type second base layer, the second conductive type second semiconductor layer, the first conductive type third semiconductor layer, and the third gate electrode.
The second field effect transistor causes a trigger current to operate the thyristor;
When the first and second field effect transistors are turned off, the third field effect transistor is turned on, and carriers in the thyristor are discharged out of the thyristor through the third field effect transistor. Semiconductor device. In claim 6,
The first gate electrode is embedded in a trench formed in a layer including the second conductive type second semiconductor layer, the first conductive type second base layer, and the second conductive type floating emitter layer,
The second gate electrode includes a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, a floating emitter layer of the second conductivity type, a first base layer of the first conductivity type, and Embedded in a trench formed in a layer including a base layer of the second conductivity type,
The semiconductor device having a thyristor, wherein the third gate electrode is embedded in the same trench as the second gate electrode.   A semiconductor device having a thyristor,
  A first semiconductor layer of a first conductivity type;
  A second conductivity type base layer stacked above the first conductivity type first semiconductor layer;
  A first conductivity type first base layer formed in the second conductivity type base layer and separated from the first conductivity type semiconductor layer by the second conductivity type base layer;
  A second conductivity type floating emitter layer formed in the first conductivity type first base layer and separated from the second conductivity type base layer by the first conductivity type first base layer;
  A first conductivity type second base layer formed in the second conductivity type floating emitter layer and separated from the first conductivity type first base layer by the second conductivity type floating emitter layer;
  A second conductive type second semiconductor layer formed in the first conductive type second base layer and separated from the second conductive type floating emitter layer by the first conductive type second base layer;
  A third semiconductor layer of a first conductivity type formed in the base layer of the second conductivity type and separated from the first base layer of the first conductivity type by the base layer of the second conductivity type;
  A buried type first gate buried so as to be in contact with at least the second conductivity type second semiconductor layer, the first conductivity type second base layer, and the second conductivity type floating emitter layer via an insulating film Electrodes,
  The second conductivity type base layer, the first conductivity type first base layer, the second conductivity type floating emitter layer, the first conductivity type second base layer, and the second conductivity type second semiconductor. A second gate electrode formed through the layer and the insulating film;
  A third gate electrode formed to be in contact with the first conductive type first base layer, the second conductive type base layer, and the first conductive type third semiconductor layer via an insulating film; ,
  The thyristor includes a first semiconductor layer of the first conductivity type, a base layer of the second conductivity type, a first base layer of the first conductivity type, and a floating emitter layer of the second conductivity type.
  The first field effect transistor includes the second conductive type second semiconductor layer, the first conductive type second base layer, the second conductive type floating emitter layer, and the first gate electrode.
  The second field effect transistor includes the second conductivity type floating emitter layer, the first conductivity type first base layer, the second conductivity type base layer, and the second gate electrode.
  A third field effect transistor including the first conductivity type first base layer, the second conductivity type base layer, the first conductivity type third semiconductor layer, and the third gate electrode;
  The second field effect transistor causes a trigger current to operate the thyristor;
  When the first and second field effect transistors are turned off, the third field effect transistor is turned on, and carriers in the thyristor are discharged out of the thyristor through the third field effect transistor. Semiconductor device. In claim 8 ,
The first gate electrode has an insulating film in a trench formed in a layer including the second conductive type second semiconductor layer, the first conductive type second base layer, and the second conductive type floating emitter layer. Embedded to touch through ,
The second gate electrode includes a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, a floating emitter layer of the second conductivity type, a first base layer of the first conductivity type, and Embedded so as to be in contact with a trench formed in a layer including the base layer of the second conductivity type via an insulating film ;
The third gate electrode is embedded to be in contact with the same trench as the second gate electrode through an insulating film ,
The third semiconductor layer of the first conductivity type is between a trench in which the third gate electrode is embedded and a trench located adjacent thereto,
The semiconductor device having a thyristor, wherein the third semiconductor layer of the first conductivity type reaches the base layer of the second conductivity type. A first conductivity type first base is formed by introducing a first conductivity type impurity into the second conductivity type base layer of a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type base layer. Forming a layer;
Introducing a second conductivity type impurity into the first conductivity type first base layer to form a second conductivity type floating emitter layer;
Introducing a first conductivity type impurity into the second conductivity type floating emitter layer to form a first conductivity type second base layer;
Introducing a second conductivity type impurity into the first conductivity type second base layer to form a second conductivity type second semiconductor layer;
A first gate electrode buried in contact with a layer including the second conductive type second semiconductor layer, the first conductive type second base layer, and the second conductive type floating emitter layer via an insulating film; Forming a step;
A second semiconductor layer of the second conductivity type; a second base layer of the first conductivity type; a floating emitter layer of the second conductivity type; a first base layer of the first conductivity type; and a base of the second conductivity type. Forming a second gate electrode on the surface from which the layer is exposed via an insulating film;
A method of manufacturing a semiconductor device having a thyristor comprising: A first conductivity type first base is formed by introducing a first conductivity type impurity into the second conductivity type base layer of a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type base layer. Forming a layer;
Introducing a second conductivity type impurity into the first conductivity type first base layer to form a second conductivity type floating emitter layer;
Introducing a first conductivity type impurity into the second conductivity type floating emitter layer to form a first conductivity type second base layer;
Introducing a second conductivity type impurity into the first conductivity type second base layer to form a second conductivity type second semiconductor layer;
A first gate electrode buried in contact with a layer including the second conductive type second semiconductor layer, the first conductive type second base layer, and the second conductive type floating emitter layer via an insulating film; Forming a step;
A second semiconductor layer of the second conductivity type; a second base layer of the first conductivity type; a floating emitter layer of the second conductivity type; a first base layer of the first conductivity type; and a base of the second conductivity type. Forming a second gate electrode embedded so as to be in contact with a layer including the layer through an insulating film ;
A method of manufacturing a semiconductor device having a thyristor comprising:

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