JP2001044415A - Semiconductor device comprising thyristor and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device where the turn-on voltage of a thyrisor is lowered, while turning-off is assured. SOLUTION: A semiconductor device 10 comprising a thyristor, where an IGBT is to be a trigger, comprises embedded gate electrodes 40, 42, and 44. An n+ type floating emitter layer 24, p- type first base layer 22, n- type baser layer 18, n+ type buffer layer 16, and p+ type anode layer 14 constitute the thyristor. An n+ type cathode layer 32, p- type first base layer 22, n- type base layer 18, n+ type buffer layer 16, and p+ type anode layer 14 constitute an IGBT. At turn-on of the thyristor, a channel region is formed at a p- type second base layer 26 near the gate electrodes 40, 42, and 44. The current in the thyristor flows a path: a n+ type floating emitter layer 24-channel region-n+ type cathode layers 28, 30, and 32.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a thyristor in which a thyristor trigger current flows, for example, an IGBT, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 19 is a sectional view of a semiconductor device having a thyristor disclosed in Japanese Patent Application Laid-Open No. 5-82775. This semiconductor device is used, for example, for controlling a large current under a high withstand voltage. The semiconductor device 200 has a silicon substrate 202 on which a p ⁺ type anode layer 204, an n type buffer layer 206, and an n ⁻ type base layer 208 are stacked.
On the p ⁺ type anode layer 204 side of the silicon substrate 202, a metal anode electrode 210 is formed.

[0003] A p-type first base layer 212 is formed from the surface of the n ^- type base layer 208 to the inside. An n-type floating emitter layer 214 is formed from the surface of the p-type first base layer 212 to the inside. A p-type second base layer 216 is formed from the surface of the n-type floating emitter layer 214 toward the inside. From the surface of p-type second base layer 216 toward the inside, n ⁺ -type cathode layer 21
8, 220 are formed at intervals from each other.

The cathode electrode 222 is formed of the n ⁺ type cathode layer 2
18 surface, the surface of the p-type second base layer 216 and n ⁺
It is formed over the surface of the mold cathode layer 220.
The gate electrode 224 covered with the insulating layer is the n ⁻ -type base layer 2
08, the surface of the p-type first base layer 212, the surface of the n-type floating emitter layer 214, the surface of the p-type second base layer 216, and the surface of the n ⁺ -type cathode layer 218. The gate electrode 226 covered with the insulating layer is formed on the surface of the n ⁻ -type base layer 208, on the surface of the p-type first base layer 212, on the surface of the n-type floating emitter layer 214, It is formed over the surface and over the surface of the n ⁺ type cathode layer 220.

[0005] The n-type floating emitter layer 214, p
A thyristor is constituted by the first type base layer 212, the n ⁻ type base layer 208, the n type buffer layer 206, and the p ⁺ type anode layer 204.

Next, the operation of the thyristor of the semiconductor device 200 will be described. First, the turn-on operation will be described. The cathode electrode 222 is grounded, and a positive voltage is applied to each of the gate electrodes 224, 226 and the anode electrode 210. When a positive voltage is applied to the gate electrodes 224 and 226, the p-type first
A channel region is formed in the base layer 212 and the p-type second base layer 216. Thereby, the n ⁺ type cathode layer 21
The electrons 8 and 220 are supplied to the channel region formed in the p-type second base layer 216 and the n-type floating emitter layer 21.
4, flows into the n ⁻ -type base layer 208 through the channel region formed in the p-type first base layer 212. On the other hand, since a positive voltage is also applied to the anode electrode 210, p ⁺
The holes of the type anode layer 204 are injected into the n ⁻ type base layer 208. The IGBT is turned on by these electrons and holes injected into the n ⁻ -type base layer 208.

[0007] n ^- holes that reach from the mold base layer 208 to the p-type first base layer 212, n-type floating emitter layer 214 and the p-type first base layer 212 and the n ^- is formed by the mold base layer 208 The current becomes the base current of the NPN transistor, and the NPN transistor turns on.
That is, electrons from the n-type floating emitter layer 214 are transferred to the p-type first base layer 212 and the n ⁻ -type base layer 208.
The thyristor is turned on by being injected into the thyristor.

Next, the turn-off operation will be described.
When a negative voltage or 0 V is applied to the gate electrodes 224 and 226, the channel regions formed in the p-type first base layer 212 and the p-type second base layer 216 below the gate electrodes 224 and 226 disappear. Thereby, the n ⁺ type source layer 21
Since the supply of electrons from 8, 220 to the n-type floating emitter layer 214 stops, the thyristor is turned off.

[0009]

A thyristor is required to have a low turn-on voltage in order to reduce power consumption. Increasing the area of the thyristor can answer this demand.

However, when the area of the thyristor is increased, the amount of carriers stored in the thyristor increases, which adversely affects the turn-off performance of the thyristor (short turn-off time and reliable turn-off). That is, if the turn-off takes time, the thyristor is prevented from switching at a high speed.
Failure to turn off reliably will destroy the thyristor.

In the semiconductor device 200 shown in FIG. 19, the potential of the n-type floating emitter layer 214 tends to rise transiently during the turn-off operation. Due to this rise, a high voltage in the opposite direction is applied to the pn junction between the n-type floating emitter layer 214 and the p-type second base 216, and this pn junction may break down. When this breakdown occurs, the thyristor cannot be turned off.

In the semiconductor device 200 shown in FIG. 19, it is difficult to lower the turn-on voltage even if the area of the thyristor is simply increased. That is, in the semiconductor device 200, a channel region is formed in the p-type second base layer 216 below the gate electrodes 224 and 226. The electron current of the thyristor is the n ⁺ type cathode layer 21.
8, 220—the channel region—the n-type floating emitter layer 214. However, the gate electrodes 224, 2
26 is formed on the surface of the silicon substrate 202. For this reason, even if the area of the n-type floating emitter layer 214 is increased in order to cause a thyristor operation in a wide range, the amount of electron current flowing into the n-type floating emitter layer 214 is limited by the amount flowing through the channel region. This hinders the reduction of the thyristor turn-on voltage.

An object of the present invention is to provide a semiconductor device capable of improving the turn-off performance of a thyristor and a method for manufacturing the same.

Another object of the present invention is to provide a semiconductor device capable of improving the turn-off performance of a thyristor and reducing the turn-on voltage, and a method of manufacturing the same.

[0015]

(1) A semiconductor device according to the present invention is a semiconductor device having a thyristor, comprising first and second field effect transistors, wherein the thyristor is a first conductive type first transistor. A semiconductor layer, a second conductivity type base layer, a first conductivity type first base layer, and a second conductivity type floating emitter layer, wherein the first field-effect transistor has a second conductivity type second semiconductor layer; A first base layer of the first conductivity type and a second base layer of the first conductivity type include a second base layer of one conductivity type, a floating emitter layer of the second conductivity type, and a buried first gate electrode. A second conductive type floating emitter layer, the second conductive type floating emitter layer and a second conductive type second semiconductor layer separated by a first conductive type second base layer; Second field effect Transistor is floating emitter layer of the second conductivity type, a first base layer of a first conductivity type,
A second conductive type base layer and a second gate electrode;
An element having a field-effect transistor causes a trigger current for operating the thyristor to flow.

Since the semiconductor device according to the present invention includes the field effect transistor including the buried first gate electrode, the turn-on voltage of the thyristor can be reduced. That is, a channel region is formed in the second base layer of the first conductivity type by the field effect transistor. The current of the thyristor is equal to the second semiconductor layer of the second conductivity type (for example,
It flows between the (cathode layer), the channel region, and the floating emitter layer of the second conductivity type. The first gate electrode is a buried type. Therefore, the path can be shortened, and the turn-on voltage of the thyristor can be reduced. Note that when a plurality of first gate electrodes are provided, the area of the channel region can be increased. This is a factor that can reduce the turn-on voltage of the thyristor.

Further, in the semiconductor device according to the present invention,
Since the first gate electrode is a buried type, the first gate electrode can be located at the body (other than the end) of the floating emitter layer of the second conductivity type. For this reason, the potential of the floating emitter layer of the second conductivity type can be made closer to the potential of the first gate electrode. Therefore, when the thyristor is turned off, it is possible to prevent a reverse high voltage from being applied to the junction between the second conductivity type floating emitter layer and the first conductivity type second base layer. Therefore, the possibility of this junction breaking down can be reduced, and the thyristor can be more reliably turned off.

Examples of the device having the second field-effect transistor include an IGBT having a planar gate structure, an IGBT having a trench gate structure, and an IEGT (Injection E).
enhanced insulated Gate bi
polarTransistor), MCT (MOS
Controlled Transistor), MOS
Gate thyristor, CSTBT (Carrier St)
ored Trench-Gatebipolar T
ransistor), EST (EmitterSwi)
tched Transistor). The second field effect transistor described below also has this meaning.

In the semiconductor device according to the present invention, the second gate electrode includes a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, a floating emitter layer of the second conductivity type, and a first conductivity type. It is preferable that the first base layer and the second conductivity type base layer are formed on an exposed surface via an insulating film. In this structure, a channel region for operating the device including the second field-effect transistor is formed on a plane, and can be manufactured separately from a channel region for thyristor operation. Therefore, it is possible to arbitrarily determine the channel concentration for operating the device including the second field-effect transistor (this determines the threshold voltage of the device).

In the semiconductor device according to the present invention, the second gate electrode includes a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, a floating emitter layer of the second conductivity type, and a first conductivity type. Embedded in a layer including the first base layer and the second conductive type base layer. With this structure, the first base layer of the first conductivity type and the second base layer of the first conductivity type
The channel region formed in the base layer extends in the vertical direction. The area of the semiconductor device can be reduced as compared with a structure in which the channel region is formed in the lateral direction.

In the semiconductor device according to the present invention, the first gate electrode is embedded in a layer including a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, and a floating emitter layer of the second conductivity type. It is preferable that the first gate electrode does not reach the first base layer of the first conductivity type. According to this structure, the junction area between the second conductive type floating emitter layer and the first conductive type first base layer can be formed in a wide range. The large area leads to a large area for operating as a thyristor, and the thyristor operation occurs in a wide range, so that the on-voltage of the element can be reduced.

In the semiconductor device according to the present invention, the first gate electrode includes a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, a floating emitter layer of the second conductivity type, and a first conductivity type. Embedded in the layer including the first base layer. When the thyristor is turned on,
An accumulation region is formed in the second conductivity type floating emitter layer near the first gate electrode. According to this structure, the area of the achimation region can be made larger than in a structure in which the first gate electrode does not reach the first base layer of the first conductivity type. Therefore, the turn-on voltage of the thyristor can be reduced.

It is to be noted that the accumulation area is the first
A region in which carriers of the first conductivity type are accumulated in the semiconductor layer of the conductivity type. For example, if the semiconductor layer is n-type, the accumulation region is n-type. When the semiconductor layer is p-type, the accumulation region is p-type.

(2) The semiconductor device according to the present invention is a semiconductor device having a thyristor, and includes first, second and third thyristors.
A thyristor comprising a first semiconductor layer of a first conductivity type, a base layer of a second conductivity type, a first base layer of the first conductivity type, and a floating emitter layer of the second conductivity type; The field effect transistor includes a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, a floating emitter layer of the second conductivity type, and a first gate electrode, and a first base layer of the first conductivity type. And the second base layer of the first conductivity type are separated by a floating emitter layer of the second conductivity type, and the floating emitter layer of the second conductivity type and the second semiconductor layer of the second conductivity type are separated from each other by the first conductivity type. The second field effect transistor is separated by a conductive type second base layer, and the second field effect transistor is a second conductive type floating emitter layer, a first conductive type first base layer, a second conductive type base layer, and a second gate. Including electrodes Flowing a trigger current device having a second field effect transistor operates the thyristor, a third field effect transistor, the third gate electrode and the first
A third semiconductor layer of a conductivity type; when the first and second field effect transistors are off, the third field effect transistor is turned on, and carriers in the thyristor are discharged out of the thyristor via the third field effect transistor. , A semiconductor device having a thyristor.

The semiconductor device according to the present invention includes a third field effect transistor. The third field effect transistor is
It turns on when the first and second field effect transistors are off. Therefore, when the thyristor is turned off, the carriers accumulated near the third field-effect transistor become the third field-effect transistor.
It is reliably discharged out of the thyristor via the field effect transistor. Therefore, it is possible to improve the turn-off characteristics of the thyristor.

The semiconductor device according to the present invention can have the following configuration. That is, the first gate electrode includes a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type,
The second gate electrode is buried in a trench formed in a layer including a conductive type floating emitter layer, and the second gate electrode includes a second conductive type second semiconductor layer, a first conductive type second base layer, and a second conductive type floating layer. The third gate electrode is buried in the same trench as the second gate electrode, and is buried in a trench formed in the layer including the emitter layer, the first base layer of the first conductivity type, and the base layer of the second conductivity type. The third semiconductor layer of the first conductivity type is in the second semiconductor layer of the second conductivity type.

In this configuration, the third gate electrode is buried in the same trench as the second gate electrode. Therefore, the degree of integration of the semiconductor device can be improved as compared with the case where the third gate electrode and the second gate electrode are buried in different trenches.

The semiconductor device according to the present invention can have the following configuration. That is, the first gate electrode
The second gate electrode is embedded in a trench formed in a layer including a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, and a floating emitter layer of the second conductivity type.
The second conductive type second semiconductor layer, the first conductive type second base layer, the second conductive type floating emitter layer, the first conductive type first base layer, and the layer including the second conductive type base layer The third gate electrode is embedded in the formed trench,
Embedded in the same trench as the second gate electrode,
The third semiconductor layer of the first conductivity type is between a trench in which the third gate electrode is buried and a trench located adjacent thereto, and the third semiconductor layer of the first conductivity type is formed of the second conductivity type. Has reached the base layer.

In this configuration, the third semiconductor layer of the first conductivity type reaches the base layer of the second conductivity type. Therefore, the third semiconductor layer of the first conductivity type is the second semiconductor layer of the second conductivity type.
Since the third field-effect transistor can be located inside the semiconductor device as compared with the case where it is in the semiconductor layer,
The carriers accumulated in the thyristor can be more smoothly discharged out of the thyristor. As a result, it is possible to improve the turn-off characteristics of the thyristor.

Further, the third semiconductor layer of the first conductivity type is
Since it is between the trench in which the gate electrode is buried and the trench located next to it, the third conductive type third
It is possible to prevent the plane area of the semiconductor layer from expanding. That is, in order for the third field effect transistor to operate,
The third semiconductor layer of the first conductivity type must have a relatively high concentration. Therefore, when the third semiconductor layer of the first conductivity type is made to reach the base layer of the second conductivity type at a relatively deep position, the amount of the third semiconductor layer of the first conductivity type diffused in the lateral direction is large. Therefore, the plane area of the third semiconductor layer of the first conductivity type is increased. This hinders high integration of the semiconductor device. In this configuration, since the third semiconductor layer of the first conductivity type is sandwiched between the trenches, it is possible to prevent the plane area of the third semiconductor layer of the first conductivity type from increasing.

(3) The method of manufacturing a semiconductor device according to the present invention is characterized in that the first conductive type first semiconductor layer and the second conductive type base layer are formed on the second conductive type base layer of the semiconductor substrate including the first conductive type base layer. A step of forming a first base layer of a first conductivity type by introducing impurities of a conductivity type; and a step of introducing a second conductivity type impurity into a first base layer of a first conductivity type to form a second base type floating layer. Forming an emitter layer, introducing a first conductivity type impurity into the second conductivity type floating emitter layer to form a second base layer of the first conductivity type, and forming a second base layer of the first conductivity type.
A step of introducing a second conductivity type impurity into the base layer to form a second conductivity type second semiconductor layer; a step of forming the second conductivity type second semiconductor layer, the first conductivity type second base layer, Forming a first gate electrode embedded in a layer including a two-conductivity-type floating emitter layer; and a second-conductivity-type second semiconductor layer.
A second base layer of the first conductivity type, a floating emitter layer of the second conductivity type, a first base layer of the first conductivity type, and a second base layer of the second conductivity type are exposed via an insulating film on the exposed surface. Forming two gate electrodes.

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a structure in which a second gate electrode is formed on a surface of a semiconductor substrate via an insulating film. As a technique for introducing impurities, for example, there are ion implantation and impurity diffusion.

According to the method of manufacturing a semiconductor device of the present invention, the first conductive type base layer is formed on the semiconductor substrate including the first conductive type first semiconductor layer and the second conductive type base layer. A step of forming a first base layer of the first conductivity type by introducing an impurity, and a step of forming a floating emitter layer of the second conductivity type by introducing an impurity of the second conductivity type into the first base layer of the first conductivity type. Forming a first conductive type second base layer by introducing a first conductive type impurity into the second conductive type floating emitter layer; and forming a first conductive type second base layer on the second conductive type floating base layer. , A second conductivity type impurity is introduced to introduce a second conductivity type second impurity.
Forming a semiconductor layer, and forming a first gate electrode embedded in a layer including a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, and a floating emitter layer of the second conductivity type. Process, a second semiconductor layer of the second conductivity type, the first
Forming a second gate electrode embedded in a layer including a conductive type second base layer, a second conductive type floating emitter layer, a first conductive type first base layer, and a second conductive type base layer; , Is provided.

The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a structure in which the second gate electrode is embedded. Note that the first gate electrode and the second gate electrode may be formed at the same time, the first gate electrode may be formed first,
The second gate electrode may be formed first. Techniques for introducing impurities include, for example, ion implantation and impurity diffusion.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] {Description of Structure} FIG. 1 is a sectional view of a first embodiment of a semiconductor device according to the present invention. The semiconductor device 10 includes an anode electrode 20, a p ⁺ -type anode layer 14, an n ⁺ -type buffer layer 16,
An n ⁻ -type base layer 18 is provided, and these are sequentially stacked. The material of the anode electrode 210 is a metal. The material of the p ⁺ type anode layer 14, the n ⁺ type buffer layer 16 and the n ⁻ type base layer 18 is a single crystal of silicon. The p ⁺ type anode layer 14 is an example of a first conductivity type first semiconductor layer.

A p ^- type first base layer 22 is formed from the surface of the n ^- type base layer 18 to the inside. p ^- type first
An n ⁺ -type floating emitter layer 24 is formed from the surface of the base layer 22 to the inside. A p ⁻ -type second base layer 26 is formed from the surface of the n ⁺ -type floating emitter layer 24 toward the inside. From the surface of the p ⁻ -type second base layer 26 toward the inside, the n ⁺ -type cathode layers 28, 3
0 and 32 are formed at an interval from each other. The n ⁺ -type cathode layers 28, 30, and 32 are an example of a second semiconductor layer of the second conductivity type.

N⁺Type cathode layer 28, p^-Mold second base layer
26, n⁺Type floating emitter layer 24
There is a trench 34 to reach. Polycrystalline trench 34
A gate electrode 40 made of silicon is embedded.
The gate electrode 40 is a buried type gate electrode. Tren
Between the side surface of the gate 34 and the gate electrode 40 and the trench 34
A silicon oxide film 46 is provided between the bottom of
Are formed. n ⁺Type cathode layer 28, p^-Mold No. 2
Layer 26, n⁺Type floating emitter layer 24 and
The gate electrode 40 forms a field effect transistor
ing.

N⁺Type cathode layer 30, p^-Mold second base layer
26, n⁺Type floating emitter layer 24
There is a trench 36 to reach. Polycrystalline trench 36
A gate electrode 42 made of silicon is embedded.
The gate electrode 42 is a buried gate electrode. Tren
Between the side surface of the gate 36 and the gate electrode 42 and the trench 36
A silicon oxide film 48 is formed between the bottom of
Are formed. n ⁺Type cathode layer 30, p^-Mold No. 2
Layer 26, n⁺Type floating emitter layer 24 and
The gate electrode 42 forms a field effect transistor.
ing.

N⁺Type cathode layer 32, p^-Mold second base layer
26, n⁺Type floating emitter layer 24
There is a trench 38 to reach. Polycrystalline trench 38
A gate electrode 44 made of silicon is embedded.
The gate electrode 44 is a buried gate electrode. Tren
Between the side surface of the gate 38 and the gate electrode 44 and the trench 38
A silicon oxide film 50 is provided between the bottom of
Are formed. n ⁺Type cathode layer 32, p^-Mold No. 2
Layer 26, n⁺Type floating emitter layer 24 and
The gate electrode 44 constitutes a field effect transistor
ing.

A gate electrode 52 is formed on the surface of the n ⁻ type base layer 18 via the gate oxide film 54, and the p ⁻ type first base layer 2
2, on the surface of the n ⁺ type floating emitter layer 24, on the surface of the p ⁻ type second base layer 26, and on the surface of the n ⁺ type cathode layer 32.

The cathode electrode 56 is made of the p ⁻ type first base layer 2
2, on the surface of the p ⁻ type second base layer 26, and on the surface of the n ⁺ type cathode layers 28, 30, 32.
On the surface of the n ⁻ type base layer 18, on the surface of the n ⁺ type floating emitter layer 24, and on the gate electrodes 40, 42, 44, 5
2, a silicon oxide film 58 is formed.
These and the cathode electrode 56 are formed by the silicon oxide film 58.
Are electrically insulated.

[0042] n ⁺ -type floating emitter layer 24, p ^-
A thyristor is constituted by the first type base layer 22, the n ⁻ type base layer 18, the n ⁺ type buffer layer 16 and the p ⁺ type anode layer 14. The n ⁺ type cathode layer 32 and the p ⁻ type first
Base layer 22, n ⁻ type base layer 18, n ⁺ type buffer layer 1
6. An IGBT is constituted by the p ⁺ type anode layer 14.

{Description of Operation} Next, the semiconductor device 10
The operation of the thyristor will be described. First, the turn-on operation will be described. The cathode electrode 56 is grounded, and a positive voltage is applied to the surface type gate electrode 52, the buried type gate electrodes 40, 42, 44, and the anode electrode 20, respectively. When a positive voltage is applied to the surface type gate electrode 52, the p ⁻ type first base layer 2 under the gate electrode 52
Channel regions 60 and 62 are formed in the second and p ⁻ -type second base layers 26, respectively, and an accumulation region 64 is formed in the n ⁺ -type floating emitter layer 24 below the gate electrode 52. Thereby, the n ⁺ type cathode layer 32
Electrons flow into the n ⁻ -type base layer 18 through the channel region 62, the accumulation region 64, and the channel region 60. On the other hand, since a positive voltage is also applied to the anode electrode 20, holes of the p ⁺ -type anode layer 14 are injected into the n ⁻ -type base layer 18 and flow into the p ⁻ -type first base layer 22. The IGBT is turned on by these electrons and holes injected into the n ⁻ -type base layer 18.

The holes flowing into the p ⁻ -type first base layer 22 form the n ⁺ -type floating emitter layer 24 and the p ⁻ -type first
The base current of the NPN transistor formed by the base layer 22 and the n ⁻ -type base layer 18 is used.
The transistor turns on. That is, the n ⁺ type floating emitter layer 24, the p ⁻ type first base layer 22, and the n ⁻
The thyristor composed of the mold base layer 18, the n ⁺ buffer layer 16, and the p ⁺ anode layer 14 enters a latch-up state. This turns on the thyristor.

When the thyristor is turned on, holes are p
^The p ^- type first base layer 22 is supplied from the ⁺ -type anode layer 14. Electrons from n ⁺ -type cathode layer 28, 30, 32 n ⁺
Is supplied to the floating emitter layer 24. That is, a positive voltage is applied to each of the embedded gate electrodes 40, 42, and 44. Accordingly, a channel region (for example, a channel region 66) is formed in a region of the p ⁻ -type second base layer 26 near the gate electrodes 40, 42, and 44. As a result, electrons are transferred to the n ⁺ type cathode layer 2.
8, 30, and 32 are supplied to the n ⁺ -type floating emitter layer 24 through these channel regions. These electrons and these holes allow the thyristor to continue its turn-on operation.

Next, the turn-off operation will be described.
Surface type gate electrode 52, embedded type gate electrode 4
When the potentials of 0, 42, and 44 are set to 0 V or a negative potential,
Channel regions 60 and 62 below gate electrode 52 and gate
P near the electrodes 40, 42, 44 ^-Of the mold second base layer 26
The channel region disappears. This gives n⁺Type cathode
Layers 28, 30, 32 to n⁺Type floating emitter
The supply of electrons to the layer 24 stops. On the other hand, p⁺Type anode
Layer 14 to p^-Holes supplied to the mold first base layer 22
Is p^-Flows through the first base layer 22 of the mold to the cathode electrode 56.
Absorbed. As a result, the thyristor turns off.
You.

{Description of Manufacturing Method} An example of a method of manufacturing the semiconductor device 10 shown in FIG. 1 will be described. As shown in FIG. 2, a silicon substrate to be the p ⁺ type anode layer 14 is prepared. The p-type impurity is boron. The concentration of the p-type impurity is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . The thickness of the anode layer 14 is 200 μm to 300 μm. p
^An n ⁺ type buffer layer 16 is formed on the ⁺ type anode layer 14 by epitaxial growth. The n-type impurity is phosphorus. The concentration of the n-type impurity is 1 × 10 ¹⁶ cm ⁻³ to 1 × 10
¹⁷ cm ^-3 . The thickness of the buffer layer 16 is 10 μm to 1
5 μm. An n ⁻ -type base layer 18 is formed on the n ⁺ -type buffer layer 16 by epitaxial growth. The n-type impurity is phosphorus. The concentration of the n-type impurity is 1 × 10 ¹⁴ c
m ^{−3 to} 2 × 10 ¹⁴ cm ⁻³ . The thickness of n ⁻ type base layer 18 is 60 μm to 70 μm.

[0048] As shown in FIG. 3, n by ion implantation ^-
A p ⁻ -type first base layer 22 is formed from the surface of the mold base layer 18 toward the inside. The depth of the p ⁻ -type first base layer 22 is 2.5 μm to 3.0 μm. The p-type impurity is boron. The concentration of the p-type impurity is 1 × 10 ¹⁷ cm ⁻³ to 2 × 1
0 ¹⁷ cm ^-3 . Next, p ^- type first
An n ⁺ -type floating emitter layer 24 is formed from the surface of the base layer 22 to the inside. The depth of n ⁺ type floating emitter layer 24 is 2 μm. The n-type impurity is phosphorus. The concentration of the n-type impurity is 1 × 10 ¹⁸ cm ⁻³ . Then, the p ⁻ -type second base layer 26 is formed from the surface of the n ⁺ -type floating emitter layer 24 to the inside by ion implantation. The depth of the p ⁻ -type second base layer 26 is 1 μm. The p-type impurity is boron. The concentration of the p-type impurity is 1 × 10 ¹⁶ cm ⁻³ . Then, n ⁺ -type cathode layers 28, 30, and 32 are formed from the surface of the p ⁻ -type second base layer 26 to the inside by ion implantation. n ⁺
The depth of the mold cathode layers 28, 30, 32 is 0.5 μm. The n-type impurity is arsenic. The concentration of the n-type impurity is 1 × 10 ²⁰ cm ⁻³ .

As shown in FIG. 4, the n ⁺ -type cathode layer 28,
The trench 34, which penetrates the p ⁻ type second base layer 26 and reaches the n ⁺ type floating emitter layer 24, the n ⁺ type cathode layer 30, the p ⁻ type second base layer 26, and the n ⁺ type floating emitter layer Trench 36, n reaching 24
Through the ⁺ -type cathode layer 32 and the p ⁻ -type second base layer 26,
A trench 38 reaching the n ⁺ type floating emitter layer 24 is formed. The depth of the trenches 34, 36, 38 is 1.5 μm.

As shown in FIG. 5, a 50 nm thick silicon oxide film 46, 4 is formed on the side and bottom surfaces of the trench by thermal oxidation.
8 and 50 are formed. Next, a polycrystalline silicon film having a thickness of 1 μm is buried in the trenches 34, 36, 38 by CVD. Then, this polycrystalline silicon film is shaved by an etching technique to form buried gate electrodes 40, 42 and 44 in the trenches 34, 36 and 38.

As shown in FIG. 6, a silicon oxide film is formed by thermal oxidation so as to cover n ⁻ type base layer 18.
The silicon oxide film becomes a gate oxide film and has a thickness of 50
nm. A polycrystalline silicon film is formed on the silicon oxide film by CVD. This polycrystalline silicon film becomes a gate electrode, and its thickness is 0.4 μm. The polycrystalline silicon film and the silicon oxide film are patterned by the photolithography technology and the etching technology. Thereby, on the surface of the n ⁻ type base layer 18, on the surface of the p ⁻ type first base layer 22, on the surface of the n ⁺ type floating emitter layer 24, on the surface of the p ⁻ type second base layer 26, and on the n ⁺ type A gate electrode 52 is formed on the surface of the cathode layer 32 with a gate oxide film 54 interposed therebetween.

As shown in FIG. 7, a silicon oxide film 58 having a thickness of 0.1 μm is formed so as to cover n ⁻ type base layer 18.
It is formed by VD. The silicon oxide film 58 is patterned by a photolithography technique and an etching technique. Thereby, on the surface of the n ⁻ type base layer 18, n ⁺
A silicon oxide film 58 on the surface of the gate type floating emitter layer 24 and on the surfaces of the gate electrodes 40, 42, 44, 52.
Leave.

As shown in FIG. 1, Al serving as the cathode electrode 56 is formed by sputtering so as to cover the n ⁻ type base layer 18. The thickness of this film is 5 μm. This film is patterned by a photolithography technique and an etching technique. As a result, the cathode electrode 56 is formed on the surface of the p ⁻ type first base layer 22, on the surface of the p ⁻ type second base layer 26, and on the surface of the n ⁺ type cathode layers 28, 30, and 32.
To form Then, an anode electrode 20 is formed on the surface of the p ⁺ type anode layer 14 by a vapor deposition method. Thus, the semiconductor device 10 is completed.

{Explanation of Effect} (Effect 1) Since the semiconductor device 10 shown in FIG. 1 includes the field-effect transistor including the buried-type gate electrodes 40, 42, and 44, the turn-on voltage of the thyristor for the following two reasons. Can be lowered. The first reason is explained. With these field effect transistors, a channel region is formed in the p ⁻ type second base layer 26. The current flowing through the thyristor is n ⁺ type floating emitter layer 24-channel region-n ⁺ type cathode layer 28, 30,
It flows through 32 paths. The gate electrodes 40, 42 and 44 are of a buried type. Therefore, the path can be shortened. I will explain the second reason. There are a plurality of buried gate electrodes 40, 42, 44. Therefore, the area of the channel region can be increased.

(Effect 2) The semiconductor device 10 shown in FIG.
Since the gate electrodes 40, 42, and 44 are buried, n ⁺
Gate electrodes 40, 42, 44 can be located in the body (parts other than the ends) of the floating emitter layer 24. Because of this, to turn off the thyristor,
When the potentials of the gate electrodes 40, 42, and 44 are set to 0 V or a negative potential, the potential of the n ⁺ -type floating emitter layer 24 can be made close to 0 V or a negative potential. Therefore, when the thyristor is turned off, it is possible to prevent a reverse high voltage from being applied to the junction between the n ⁺ -type floating emitter layer 24 and the p ⁻ -type second base layer 26. Therefore, the possibility of this junction breaking down can be reduced, and the thyristor can be more reliably turned off.

(Effect 3) The semiconductor device 10 shown in FIG.
The gate electrode 52 is formed on the surface of the n ⁻ type base layer 18, on the surface of the p ⁻ type first base layer 22, on the surface of the n ⁺ type floating emitter layer 24, on the surface of the p ⁻ type second base layer 26, and ^{On the} surface of the ⁺ type cathode layer 32, a gate oxide film 54 is formed. Therefore, the channel concentration during the IGBT operation can be set individually while the fabrication is easy. That is, there is an advantage that there is no limitation on the threshold voltage setting of the present element.

(Effect 4) The semiconductor device 10 shown in FIG.
The n ⁺ -type cathode layers, 30 and 32 are surrounded by the n ⁺ -type floating emitter layer. For this reason, p ^-
-Type first base layer 22 and n ⁺ -type cathode layers 28, 30, 3
2 are separated from each other by an n ⁺ type floating emitter layer 24. Therefore, at the time of turn-off, holes injected from the p ⁺ -type anode layer 14 into the p ⁻ -type first base layer 22 can be prevented from flowing into the n ⁺ -type cathode layers 28, 30, 32. This indicates that the present device has a structure in which no parasitic thyristor including the n ⁺ -type cathode layer exists, and does not cause a problem that the parasitic thyristor cannot be turned off by the ON operation.

[Second Embodiment] {Description of Structure} FIG. 8 is a sectional view of a semiconductor device according to a second embodiment of the present invention.
The same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The difference from the first embodiment is the depth of the trenches 34, 36, 38. The value of the depth of the trenches 34, 36, 38 of the second embodiment is larger than the value of the depth of the trenches 34, 36, 38 of the first embodiment. That is, the trench 34 includes the n ⁺ -type cathode layer 28, the p ⁻ -type second base layer 26, and the n ⁺ -type floating emitter layer 24.
To reach the p ⁻ -type first base layer 22. The trench 36 penetrates the n ⁺ type cathode layer 30, the p ⁻ type second base layer 26, and the n ⁺ type floating emitter layer 24,
The p ^- type first base layer 22 is reached. Trench 38
Denotes an n ⁺ type cathode layer 32, ap ⁻ type second base layer 26, and n ⁺
Through type floating emitter layer 24, p ^- -type first
The base layer 22 has been reached. Gate electrodes 40, 42,
44 has reached the p ⁻ type first base layer 22.

{Description of Operation} Semiconductor device 10 shown in FIG.
Is similar to the operation of the semiconductor device 10 of the first embodiment shown in FIG.

{Description of Manufacturing Method} The difference between the method of manufacturing the semiconductor device 10 shown in FIG. 8 and the method of manufacturing the semiconductor device 10 of the first embodiment shown in FIG. 1 is that, in the process shown in FIG. , 36, and 38 are p ^- type first base layers 2
2 is formed. The other points are the same.

<< Explanation of Effect >> Semiconductor device 10 shown in FIG.
Produces the same effects as (Effect 1) to (Effect 4) of the semiconductor device 10 of the first embodiment shown in FIG. In addition to these,
The following effects occur.

(Effect 1) In the semiconductor device 10 shown in FIG. 8 and the semiconductor device 10 of the first embodiment shown in FIG. 1, when the thyristor is turned on, the gate electrodes 40 and 42 of the n ⁺ type floating emitter layer 24 are formed. , 44 are formed with an accumulation area 68. The resistance of the accumulation region 68 is low because carriers are accumulated. The semiconductor device 10 according to the second embodiment has a first
As compared with the semiconductor device 10 of the embodiment, the area of the achievable region 68 is larger. The semiconductor device 10 of the second embodiment can reduce the turn-on voltage of the thyristor from this point.

[Third Embodiment] {Description of Structure} FIG. 9 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The difference from the first embodiment is the depth of the trench 38. That is, the trench 38 includes the n ⁺ -type cathode layer 32 and the p ^-- type second
Base layer 26, n ⁺ type floating emitter layer 24,
It penetrates the p ⁻ type first base layer 22 and reaches the n ⁻ type base layer 18. The gate electrode 44 of the trench 38 is
It also functions as the gate electrode 52 of the semiconductor device 10 of the embodiment. Therefore, the semiconductor device 10 of the third embodiment does not have the surface type gate electrode 52.

{Description of Operation} Semiconductor device 10 shown in FIG.
The operation of the thyristor will be described. First, turn
The operation will be described. The cathode electrode 56 is grounded
Embedded gate electrodes 40, 42, 44,
A positive voltage is applied to each of the gate electrodes 20. Gate electrode
When a positive voltage is applied to the gate electrode 44, p
^-Mold first base layer 22, p^-The mold second base layer 26 has
Channel regions 70 and 72 are formed, respectively, and gate electrode 4 is formed.
N near 4⁺Type floating emitter layer 24
A simulation area 74 is formed. This gives n
⁺Electrons of the mold cathode layer 32 are supplied to the channel region 72 and the
After passing through the simulation region 74 and the channel region 70, n
^-It is injected into the mold base layer 18. On the other hand, the anode electrode 2
Since a positive voltage is also applied to 0, p⁺Type anode layer
14 holes are n^-Injected into the mold base layer 18^-Mold No. 1
Flows into the source layer 22. n^-Injected into the mold base layer 18
The IGBT is turned on by these electrons and holes.

The holes flowing into the p ⁻ -type first base layer 22 form the n ⁺ -type floating emitter layer 24 and the p ⁻ -type first
The base current of the NPN transistor formed by the base layer 22 and the n ⁻ -type base layer 18 is used.
The transistor turns on. That is, the n ⁺ type floating emitter layer 24, the p ⁻ type first base layer 22, and the n ⁻
The thyristor composed of the mold base layer 18, the n ⁺ buffer layer 16, and the p ⁺ anode layer 14 enters a latch-up state. This turns on the thyristor.

When the thyristor is turned on, holes are p
^The p ^- type first base layer 22 is supplied from the ⁺ -type anode layer 14. Electrons from n ⁺ -type cathode layer 28, 30, 32 n ⁺
Is supplied to the floating emitter layer 24. That is, a positive voltage is applied to each of the embedded gate electrodes 40, 42, and 44. Therefore, a channel region (for example, a channel region 72) is formed in a region near the gate electrodes 40, 42, and 44 in the p ⁻ -type second base layer 26. As a result, electrons are transferred to the n ⁺ type cathode layer 2.
8, 30, and 32 are supplied to the n ⁺ -type floating emitter layer 24 through these channel regions. These electrons and these holes allow the thyristor to continue its turn-on operation.

Next, the turn-off operation will be described.
The potential of the embedded gate electrodes 40, 42, 44 is 0V
Alternatively, when the potential is set to a negative potential, the gate electrodes 40, 42, 44
The channel region of the p ^- type second base layer 26 in the vicinity disappears. As a result, supply of electrons from the n ⁺ -type cathode layers 28, 30, and 32 to the n ⁺ -type floating emitter layer 24 is stopped. On the other hand, p from p ⁺ -type anode layer 14 ^- -type hole which is supplied to the first base layer 22, p ^- -type first base layer 2
2 and is absorbed by the cathode electrode 56. From the above,
Thyristor turns off.

<< Description of Manufacturing Method >> The method of manufacturing the semiconductor device 10 of the third embodiment shown in FIG. 9 is similar to that of the method of manufacturing the semiconductor device 10 of the first embodiment shown in FIGS. Move to the step indicated by.

As shown in FIG. 10, photolithography
Technology and etching technology ⁺Type cathode layer 2
8, p^-Penetrating the mold second base layer 26, and n⁺Type floaty
Trenches 34 and n reaching the emitter layer 24⁺Type
Cathode layer 30, p^-Penetrating the mold second base layer 26, and n⁺
3 reaching type floating emitter layer 24
6 is formed. The depth of the trenches 34 and 36 is the first embodiment
The same as the depth of the trenches 34 and 36 in the state. Next,
With photolithography technology and etching technology, n⁺
Type cathode layer 32, p^-Mold second base layer 26, n⁺Mold flow
The emitter layer 24, p^-Mold first base layer 22
Penetrate, n^-Trench 38 reaching the mold base layer 18
Form. The depth of the trench 38 is 5 μm. In addition,
The trench 38 is formed first, and the trenches 34 and 36 are formed later.
It may be formed.

As shown in FIG. 11, silicon oxide films 46, 48 and 50 are formed on the side and bottom surfaces of the trench by thermal oxidation. The thickness of the silicon oxide films 46, 48, 50 is the first
This is the same as the embodiment. Next, a polycrystalline silicon film is buried in the trenches 34, 36, 38 by CVD. Then, this polycrystalline silicon film is shaved by an etching technique to form buried gate electrodes 40, 42 and 44 in the trenches 34, 36 and 38. The thickness of the polycrystalline silicon film is the same as in the first embodiment.

As shown in FIG. 12, n ⁻ type base layer 18
A silicon oxide film 58 is formed by CVD so as to cover. The thickness of the silicon oxide film 58 is the same as in the first embodiment. The silicon oxide film 58 is patterned by a photolithography technique and an etching technique. Thereby, on the surface of the n ⁻ type base layer 18, on the surface of the n ⁺ type floating emitter layer 24, the gate electrodes 40, 42,
The silicon oxide film 58 is left on the surface of the substrate.

[0072] As shown in FIG. 9, using the same method as the first embodiment, p ^- -type first base layer 22 on the surface, p ^- -type second
On the surface of the base layer 26, n ⁺ -type cathode layers 28, 30,
32, a cathode electrode 56 is formed. And p
^An anode electrode 20 is formed on the surface of the positive type anode layer 14. Thus, the semiconductor device 10 is completed.

{Explanation of Effects} The semiconductor device 10 of the third embodiment shown in FIG. 9 is different from the semiconductor device 10 of the first embodiment shown in FIG. 1 in (effect 1), (effect 2), and (effect 4). A similar effect is produced. In addition to these, the following effects are produced.

(Effect 1) In the semiconductor device 10 shown in FIG. 9, the gate electrode 44 which is a component of the IGBT has n
⁺ Type cathode layer 32, p ⁻ type second base layer 26, n ⁺ type floating emitter layer 24, p ⁻ type first base layer 2
2, embedded in the layer including the n ⁻ -type base layer 18.
With this structure, the channel regions 70 and 72 are in the vertical direction.
Therefore, the area of the semiconductor device can be reduced as compared with a structure in which the channel region is formed in the lateral direction.

Fourth Embodiment {Description of Structure} FIG. 13 shows a fourth embodiment of the semiconductor device according to the present invention.
It is a sectional view of an embodiment. The same parts as those in the third embodiment shown in FIG. The difference from the third embodiment is that the trenches 34 and 36
Of depth. The value of the depth of the trenches 34 and 36 of the fourth embodiment is larger than the value of the depth of the trenches 34 and 36 of the third embodiment. That is, the trench 34 penetrates the n ⁺ -type cathode layer 28, the p ^-- type second base layer 26, and the n ⁺ -type floating emitter layer 24, and reaches the p ^-- type first base layer 22. The trench 36 is an n ⁺ type cathode layer 30,
It penetrates through the p ⁻ type second base layer 26 and the n ⁺ type floating emitter layer 24 and reaches the p ⁻ type first base layer 22. Gate electrodes 40 and 42 reach p ⁻ type first base layer 22.

{Description of Operation} Semiconductor device 1 shown in FIG.
0 corresponds to the operation of the semiconductor device 10 of the third embodiment shown in FIG.
The operation is the same as that described above.

{Description of Manufacturing Method} The difference between the method of manufacturing the semiconductor device 10 shown in FIG. 13 and the method of manufacturing the semiconductor device 10 of the third embodiment is that in the process shown in FIG. ^- is that formed so as to reach the mold first base layer 22. The other points are the same.

<< Explanation of Effect >> Semiconductor device 1 shown in FIG.
0 has the same effect as the semiconductor device 10 of the third embodiment. The semiconductor device 10 shown in FIG. 13 has the same effect as (effect 1) of the semiconductor device 10 of the second embodiment.

[Fifth Embodiment] {Description of Structure} FIG. 14 shows a fifth embodiment of the semiconductor device according to the present invention.
It is a sectional view of an embodiment. The same parts as those in the third embodiment shown in FIG. The difference from the third embodiment is that the p ⁺ -type drain layer 80 is formed on the surface of the n ⁺ -type cathode layer 32 in contact with the trench 38.
Is formed. Thereby, the gate electrode 44,
p ⁺ type drain layer 80, n ⁺ type cathode layer 32 and p ⁻
The pMOS field-effect transistor is constituted by the type second base layer 26.

<< Description of Operation >> Semiconductor device 1 shown in FIG.
The turn-on operation of 0 is the same as the turn-on operation of the semiconductor device 10 of the third embodiment shown in FIG. The turn-off operation of the semiconductor device 10 shown in FIG. 14 differs from the turn-off operation of the semiconductor device 10 of the third embodiment shown in FIG. 9 because of the presence of the pMOS field-effect transistor. This will be described with reference to FIG. FIG. 15 is a cross-sectional view of the fifth embodiment.

[0081] As shown in FIG. 15, at the turn-off operation of the semiconductor device 10, similarly to the semiconductor device 10 of the third embodiment shown in FIG. 9, holes, p ^- flow type first base layer 22, p ^It passes through the connecting portion 82 between the first base layer 22 and the cathode electrode 56 and is absorbed by the cathode electrode 56.

In the semiconductor device 10 shown in FIG. 15, the light is absorbed by the cathode electrode 56 via the pMOS field effect transistor. That is, when the potential of the embedded gate electrode 44 is set to 0 V or a negative potential, n ⁺
A channel is formed in the type cathode layer 32 and the n ⁺ type floating emitter layer 24. Thereby, the above pM
Since the OS field-effect transistor is turned on, holes accumulated near the gate electrode 44 are transferred to the channel formed in the n ⁺ -type floating emitter layer 24, the p ⁻ -type second base layer 26, and the n ⁺ -type cathode layer 32. Through the formed channel and the p ⁺ -type drain layer 80, the cathode electrode 56
It is absorbed by.

[0083] The point of the method of manufacturing the semiconductor device 10 shown in {manufacturing description of the method} Fig 14 differs from the manufacturing method of the semiconductor device 10 of the third embodiment shown in FIG. 9, n ⁺ -type cathode layer 3
2 after formation, n ⁺ -type cathode layer 32 in contact with trench 38
That is, the p ⁺ type drain layer 80 is formed on the surface.
The other points are the same.

<< Explanation of Effect >> Semiconductor device 1 shown in FIG.
0 produces the same effect as the semiconductor device 10 of the third embodiment shown in FIG. In addition, the following effects are produced.

(Effect 1) The semiconductor device 10 shown in FIG.
Is a pMOS field-effect transistor (the pMOS field-effect transistor has a gate electrode 44, a p ⁺ type drain layer 8
0, n ⁺ -type cathode layer 32 and p ^-- type second base layer 26
). The pMOS field effect transistor is turned on when the thyristor is turned off. Therefore, when the thyristor is turned off, the holes accumulated near the gate electrode 44 are reliably discharged out of the thyristor via the pMOS field effect transistor. Therefore, it is possible to improve the turn-off characteristics of the thyristor.

That is, also in the semiconductor device 10 shown in FIG. 14, when the area of the thyristor is increased in order to reduce the turn-on voltage, the amount of holes stored in the thyristor increases. For this reason, all holes are p
^{In the} structure in which the p ^- type first base layer 22 flows directly from the first base layer 22 to the cathode electrode 56, the p ^- type first base layer 22 and the cathode 5
There is a possibility that it takes a long time to discharge holes (for example, holes near the gate electrode 44) accumulated at a position distant from the connection portion 82 to the thyristor, or the holes may not be discharged. is there. This leads to deterioration of the turn-off characteristic.

In the semiconductor device 10 shown in FIG. 14, when the thyristor is turned off, holes accumulated near the gate electrode 44 are reliably discharged out of the thyristor via the pMOS field effect transistor. Therefore, it is possible to improve the turn-off characteristics of the thyristor.

(Effect 2) In the semiconductor device 10 shown in FIG. 14, the gate electrode 4 of the pMOS field effect transistor
4. The gate electrode 44 of the IGBT is buried in the same trench (trench 38). Therefore, the degree of integration of the semiconductor device can be improved as compared with the case where the gate electrode of the pMOS field effect transistor and the gate electrode of the IGBT are buried in different trenches.

Sixth Embodiment {Description of Structure} FIG. 16 shows a semiconductor device according to a sixth embodiment of the present invention.
It is a sectional view of an embodiment. The same parts as those in the fifth embodiment shown in FIG. The difference between the fifth embodiment, in place of the p ⁺ -type drain layer 80, is the provision of the p ⁺ -type drain layer 84.

{Description of Operation} Semiconductor device 1 shown in FIG.
The turn-on operation of 0 is similar to the turn-on operation of the semiconductor device 10 of the fifth embodiment shown in FIG. The turn-off operation of the semiconductor device 10 shown in FIG. 16 is different from the turn-off operation of the semiconductor device 10 of the fifth embodiment shown in FIG.

That is, during the turn-off operation of the semiconductor device 10 shown in FIG. 16, holes flow through the p ⁻ type first base layer 22, pass through the connection portion 82, are absorbed by the cathode electrode 56, and are n ⁻ type. The light is absorbed by the cathode electrode 56 via the p ⁺ -type drain layer 84 formed on the base layer 18. During the turn-off operation, the potential of the p ⁺ -type drain layer 84 is 0 V or a negative voltage.

{Description of Manufacturing Method} The method of manufacturing the semiconductor device 10 shown in FIG. 16 is substantially the same as the method of manufacturing the semiconductor device 10 of the third embodiment shown in FIG. The difference is that
The point is that a step of forming the p ⁺ -type drain layer 84 between the trench 38 and the trench 86 is added. The p ⁺ -type drain layer 84 can be formed, for example, by ion-implanting an impurity such as boron and applying heat treatment.

{Explanation of Effect} Semiconductor device 1 shown in FIG.
0 produces the same effect as the semiconductor device 10 of the third embodiment shown in FIG. In addition, the following effects are produced.

(Effect 1) In the semiconductor device 10 shown in FIG. 16, the p ⁺ type drain layer 84 has reached the n ⁻ type base layer 18. Therefore, the carrier accumulated in the thyristor can be more smoothly discharged out of the thyristor. As a result, it is possible to improve the turn-off characteristics of the thyristor.

(Effect 2) In the semiconductor device 10 shown in FIG. 16, the p ⁺ -type drain layer 84 can have a small plane area and a large depth. That is, the p ⁺ type drain layer 8
No. 4 has a large diffusion depth. Normally, when a deep diffusion layer is formed, the spread in the lateral direction is large, and the plane area of the diffusion layer is large. The p ⁺ -type drain layer 84 includes the trench 38 and
Since it is formed between the adjacent trenches 86, it is possible to prevent the plane area of the p ⁺ -type drain layer 84 from expanding.

Seventh Embodiment {Description of Structure} FIG. 17 shows a seventh embodiment of the semiconductor device according to the present invention.
It is a sectional view of an embodiment. The same parts as those in the fifth embodiment shown in FIG. The difference from the fifth embodiment is that first, the n ⁺ -type cathode layer located between the trenches is connected. That is, the n ⁺ type cathode layer 88 is
4 to the side surface of the trench 36. The n ⁺ -type cathode layer 90 is formed from the side surface of the trench 36 to the side surface of the trench 98. n ⁺
The mold cathode layer 92 is formed from the side of the trench 98 to the side of the trench 38.

A p ⁺ -type drain layer 96 is formed on the surface of the n ⁺ -type cathode layer 92 in contact with the trench 38. Thereby, the gate electrode 44 and the p ⁺ -type drain layer 9
6, n ⁺ -type cathode layer 92 and p ^-- type second base layer 26
Thereby, a pMOS field effect transistor is configured.

The n ⁺ type cathode layers 88, 90, 92
Below the p ^- type second base layer 26 are located, respectively. These p ⁻ -type second base layers 26 may be floating, or may be connected to the cathode electrode 56 in the depth direction of the semiconductor device 10.

Further, a trench 98 is formed between the trench 38 and the trench 36. The trench 98 has n
^{The +} type floating emitter layer 24 has been reached. A gate electrode 94 is buried in the trench 98 via a silicon oxide film. The function of the gate electrode 94 is the same as the function of the gate electrodes 40 and 42.

{Description of Operation} Semiconductor device 1 shown in FIG.
0 corresponds to the semiconductor device 1 of the fifth embodiment shown in FIG.
0 is the same as the operation.

<< Description of Manufacturing Method >> The manufacturing method of the semiconductor device 10 shown in FIG. 17 is different from the manufacturing method of the semiconductor device 10 of the above embodiments in the step of forming the n ⁺ -type cathode layer. That is, in the previous embodiments, for example, as shown in FIG. 3, n ⁺ -type cathode layer 2
An n ⁺ -type cathode layer is formed so as to be separated into 8, 30, and 32. On the other hand, the semiconductor device 1 shown in FIG.
The 0 manufacturing method of, when the n ⁺ -type cathode layer formed, n ⁺ -type cathode layer is not separated.

{Explanation of Effect} Semiconductor device 1 shown in FIG.
0 produces the same effect as the semiconductor device 10 of the fifth embodiment shown in FIG. In addition, the following effects are produced.

[0103] In the manufacturing method of the semiconductor device 10 shown in FIG. 17, when the n ⁺ -type cathode layer formed, n ⁺ -type cathode layer is not separated. Therefore, the n ⁺ -type cathode layer can be miniaturized as compared with the case where the n ⁺ -type cathode layer is formed separately. Thus, high integration of the semiconductor device can be achieved.

[Eighth Embodiment] {Description of Structure} FIG. 18 is a sectional view of an eighth embodiment of a semiconductor device according to the present invention. The eighth embodiment includes a pMOS field-effect transistor including a p ⁺ -type drain layer 128. The role of the pMOS field effect transistor is the same as the role of the pMOS field effect transistor described in the fifth to seventh embodiments. Hereinafter, the structure of the eighth embodiment will be described.

The semiconductor device 100 includes a silicon substrate 10
2. It has surface type gate electrodes 124 and 126 and a p ⁺ type drain layer 128.

The silicon substrate 102 is made of p⁺Type anode layer
104, n⁺Type buffer layer 106, n ^-Mold base layer 108
Are laminated structures. P of silicon substrate 102⁺Type
On the anode layer 104 side, a metal anode electrode 110 is formed.
Are formed.

A first p ^- type base layer 112 is formed from the surface of n ^- type base layer 108 toward the inside. p ^-
An n ⁻ -type floating emitter layer 114 is formed from the surface of the first type base layer 112 to the inside. n
^A p ⁻ type second base layer 116 is formed from the surface of the ⁻ type floating emitter layer 114 toward the inside.
From the surface of the p ⁻ type second base layer 116 toward the inside, n ⁺
The mold cathode layers 118 and 120 are formed at intervals from each other.

The gate electrode 124 covered with the insulating layer has n
^On the surface of the -type base layer 108, the p ^- type first base layer 112
On the surface, on the surface of the n ⁻ -type floating emitter layer 114, on the surface of the p ⁻ -type second base layer 116, and on the surface of the n ⁺ -type cathode layer 118. Further, the gate electrode 126 covered with the insulating layer is formed of the n ⁻ type base layer 1.
08, on the surface of the p ⁻ type first base layer 112, on the surface of the n ⁻ type floating emitter layer 114, on the surface of the p ⁻ type
It is formed over the surface of the base layer 116 and over the surface of the n ⁺ -type cathode layer 120. Further, the cathode electrode 122 is between the gate electrode 124 and the gate electrode 126 and on the surface of the n ⁺ -type cathode layer 118, on the surface of the p ⁻ -type second base layer 116, and on the n ⁺ -type cathode layer 120.
Formed on the surface.

The p ⁺ type drain layer 128 is formed on the n ⁻ type base layer. The p ⁺ type drain layer 128
The p ^- type first base layer 112 is formed at a distance therefrom. P ⁺ type drain layer 128 and p ⁻ type first base layer 112
The gate electrode 126 is located on the n ⁻ -type base layer 108 between them. The gate electrode 126, the p ⁺ -type drain layer 128, the n ^-- type base layer 108, and the p ^-- type first base layer 112 form a pMOS field-effect transistor.

N ⁻ type floating emitter layer 114,
p ⁻ type first base layer 112, n ⁻ type base layer 108, n ⁺
A thyristor is constituted by the type buffer layer 106 and the p ⁺ type anode layer 104.

{Description of Operation} Next, the operation of the semiconductor device 100 will be described. Since the semiconductor device 100 is characterized by a turn-off operation, only the turn-off operation will be described. A negative voltage or 0 V is applied to the gate electrodes 124 and 126
Is applied, the channel regions formed in the p ⁻ -type first base layer 112 and the p ⁻ -type second base layer 116 under the gate electrodes 124 and 126 disappear. This gives n ⁺
The supply of electrons from the cathode layers 118 and 120 to the n ⁻ -type floating emitter layer 114 is stopped. On the other hand, a hole in the thyristor, p ^- the type first base layer 112 is the depth direction of the semiconductor device 100, since it is connected to the cathode electrode 122, p ^- flow type first base layer 112, a cathode electrode 122 Is absorbed by In addition, holes in the thyristor cause the channel formed in the n ⁻ -type base layer 108 and the p ⁺
It is discharged out of the thyristor via the mold drain layer 128.

{Explanation of Effect} Semiconductor device 1 shown in FIG.
00, when the thyristor is turned off, the gate electrode 12
The holes accumulated near 6 are surely discharged out of the thyristor via the pMOS field effect transistor. Therefore, it is possible to improve the turn-off characteristics of the thyristor.

[Modification] In the first to seventh embodiments, the number of buried gate electrodes is plural. However,
The present invention is not limited to this, and the number of embedded gate electrodes may be one. However, if the number of buried gate electrodes is plural, the area of the channel becomes large, so that the turn-on voltage of the thyristor can be further reduced.

In the first to seventh embodiments, a buried gate electrode is formed by forming a trench and burying a conductive layer in the trench. However, the present invention is not limited to this. For example, a buried gate electrode may be formed by the following method. A conductive layer is formed over a silicon substrate via an insulating film. This conductive layer is patterned to form a gate electrode serving as a buried gate electrode. A single crystal layer is formed around the gate electrode by solid layer epitaxial growth.

In the first to seventh embodiments, the p ⁻ type first base layer 22 and the n ⁺ type cathode layer 32 (92) are
And the components. However, the present invention is not limited to this. p ⁻ type first base layer 22, n ⁺
P ⁻ type conductive layer, n ⁺ separately from the type cathode layer 32 (92)
It is also possible to provide a conductive layer of a mold and use these as constituent elements of the IGBT. Even with such a structure, the effects of the present invention can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view of the substrate showing a first step in a method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of the substrate showing a second step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of the substrate showing a third step in the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view of the substrate, showing a fourth step in the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a sectional view of the substrate, showing a fifth step in the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view of the substrate showing a sixth step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view of a second embodiment of the semiconductor device according to the present invention.

FIG. 9 is a sectional view of a third embodiment of the semiconductor device according to the present invention.

FIG. 10 is a sectional view of a substrate showing a first step in a method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 11 is a cross-sectional view of a substrate showing a second step of the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 12 is a cross-sectional view of a substrate showing a third step of the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 13 is a sectional view of a fourth embodiment of the semiconductor device according to the present invention.

FIG. 14 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 15 is a view used to explain the operation of the fifth embodiment of the semiconductor device according to the present invention.

FIG. 16 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 17 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 18 is a sectional view of an eighth embodiment of a semiconductor device according to the present invention.

FIG. 19 is a sectional view of a semiconductor device having a thyristor disclosed in Japanese Patent Application Laid-Open No. 5-82775.

[Explanation of symbols]

Reference Signs List 10 semiconductor device 14 p ⁺ type anode layer 16 n ⁺ type buffer layer 18 n ⁻ type base layer 20 anode electrode 22 p ⁻ type first base layer 24 n ⁺ type floating emitter layer 26 p ⁻ type second base layer 28, 30 , 32 n ⁺ type cathode layer 34, 36, 38 Trench 40, 42, 44 Gate electrode 46, 48, 50 Silicon oxide film 52 Gate electrode 54 Gate oxide film 56 Cathode electrode 58 Silicon oxide film 60, 62 Channel region 64 Channel region 68 Channel region 68 Accumulation region 70, 72 Channel region 74 Accumulation region 80 P ⁺ type drain layer 82 Connection part 84 P ⁺ type drain layer 86 Trench 88, 90, 92 n ⁺ type cathode layer 94 Gate electrode 96 p ⁺ -type drain layer 98 trench 100 semiconductor Location 104 p ⁺ -type anode layer 108 n ^- -type base layer 112 p ^- -type first base layer 114 n ^- -type floating emitter layer 116 p ^- -type second base layer 118, 120 n ⁺ -type cathode layer 124, 126, the gate electrode 128 p ⁺ type drain layer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masayasu Ishiko 41-cho, Yokomichi, Nagakute-cho, Aichi-gun, Aichi F-1 term in Toyota Central R & D Laboratories Co., Ltd. 5F005 AA01 AA03 AB03 AC02 AE01 AE07 AF01 AF02 AH02 AH03 AH04 BA02 BB02 GA01

Claims (10)

[Claims] 1. A semiconductor device having a thyristor, comprising a first and a second field effect transistor, wherein the thyristor has a first conductive type first semiconductor layer, a second conductive type base layer, and a first conductive type. A first base layer of a second conductivity type and a floating emitter layer of a second conductivity type, wherein the first field-effect transistor has a second semiconductor layer of a second conductivity type, a second base layer of a first conductivity type, and a second conductivity type. A floating-type emitter layer and a buried first gate electrode, the first base layer of the first conductivity type and the second base layer of the first conductivity type.
The base layer is separated from the second conductive type floating emitter layer by the second conductive type floating emitter layer.
The conductive type second semiconductor layer is separated from the conductive type second semiconductor layer by the first conductive type second base layer. The second field effect transistor includes the second conductive type floating emitter layer and the first conductive type A semiconductor device including a thyristor including a first base layer, the second conductivity type base layer, and a second gate electrode, wherein an element including the second field effect transistor flows a trigger current for operating the thyristor. 2. The semiconductor device according to claim 1, wherein the second gate electrode comprises: a second semiconductor layer of the second conductivity type; a second base layer of the first conductivity type; a floating emitter layer of the second conductivity type; A semiconductor device having a thyristor formed on an exposed surface of a first base layer of a first conductivity type and a base layer of the second conductivity type via an insulating film. 3. The semiconductor device according to claim 1, wherein the second gate electrode comprises: a second semiconductor layer of the second conductivity type; a second base layer of the first conductivity type; a floating emitter layer of the second conductivity type; A semiconductor device having a thyristor embedded in a layer including a first base layer of a first conductivity type and a base layer of the second conductivity type. 4. The semiconductor device according to claim 1, wherein the first gate electrode comprises a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, and a second base layer of the second conductivity type. A semiconductor device having a thyristor embedded in a layer including a floating emitter layer, wherein the first gate electrode does not reach the first base layer of the first conductivity type. 5. The semiconductor device according to claim 1, wherein the first gate electrode comprises a second semiconductor layer of the second conductivity type, a second base layer of the first conductivity type, and a second base layer of the second conductivity type. A semiconductor device having a thyristor embedded in a layer including a floating emitter layer and a first base layer of the first conductivity type. 6. A semiconductor device having a thyristor, comprising: a first, a second, and a third field effect transistor, wherein the thyristor has a first semiconductor layer of a first conductivity type, a base layer of a second conductivity type, A first base layer of a first conductivity type and a floating emitter layer of a second conductivity type, wherein the first field-effect transistor has a second semiconductor layer of a second conductivity type, a second base layer of the first conductivity type, A first conductive type floating emitter layer and a first gate electrode, the first conductive type first base layer and the first conductive type second base layer;
The base layer is separated from the second conductive type floating emitter layer by the second conductive type floating emitter layer.
The conductive type second semiconductor layer is separated from the conductive type second semiconductor layer by the first conductive type second base layer. The second field effect transistor includes the second conductive type floating emitter layer and the first conductive type An element including a first base layer, the second conductivity type base layer, and a second gate electrode, wherein an element including the second field effect transistor flows a trigger current for operating the thyristor; A third semiconductor layer of a first conductivity type, the third field effect transistor being on when the first and second field effect transistors are off, and carriers in the thyristor being the third semiconductor layer. A semiconductor device having a thyristor discharged to the outside of the thyristor via a field effect transistor. 7. The device according to claim 6, wherein the first gate electrode includes the second conductive type second semiconductor layer, the first conductive type second base layer, and the second conductive type floating emitter layer. Embedded in a trench formed in a layer, the second gate electrode includes: a second semiconductor layer of the second conductivity type; a second base layer of the first conductivity type; a floating emitter layer of the second conductivity type; The third gate electrode is buried in a trench formed in a layer including a first base layer of the first conductivity type and the base layer of the second conductivity type, and the third gate electrode is buried in the same trench as the second gate electrode. A semiconductor device having a thyristor, wherein the third semiconductor layer of the first conductivity type is in the second semiconductor layer of the second conductivity type. 8. The semiconductor device according to claim 6, wherein the first gate electrode includes the second conductive type second semiconductor layer, the first conductive type second base layer, and the second conductive type floating emitter layer. Embedded in a trench formed in a layer, the second gate electrode includes: a second semiconductor layer of the second conductivity type; a second base layer of the first conductivity type; a floating emitter layer of the second conductivity type; The third gate electrode is buried in a trench formed in a layer including a first base layer of the first conductivity type and the base layer of the second conductivity type, and the third gate electrode is buried in the same trench as the second gate electrode. The third semiconductor layer of the first conductivity type is located between a trench in which the third gate electrode is buried and a trench located adjacent thereto, and the third semiconductor layer of the first conductivity type is , The second conductive type It has reached the scan layer, a semiconductor device having a thyristor. 9. A first conductive type impurity is introduced into the second conductive type base layer of a semiconductor substrate including a first conductive type first semiconductor layer and a second conductive type base layer. Forming a first base layer of a first conductivity type; introducing a second conductivity type impurity into the first base layer of the first conductivity type to form a floating emitter layer of a second conductivity type; Forming a second base layer of the first conductivity type by introducing an impurity of the first conductivity type into the floating emitter layer of the two conductivity type; and forming a second conductivity type on the second base layer of the first conductivity type. Forming a second semiconductor layer of a second conductivity type by introducing an impurity of the second conductivity type; a second semiconductor layer of the second conductivity type; a second semiconductor layer of the first conductivity type;
Forming a first gate electrode embedded in a layer including the base layer and the floating emitter layer of the second conductivity type; a second semiconductor layer of the second conductivity type;
A second layer is formed on an exposed surface of the base layer, the floating emitter layer of the second conductivity type, the first base layer of the first conductivity type, and the base layer of the second conductivity type via an insulating film.
Forming a gate electrode; and a method for manufacturing a semiconductor device having a thyristor comprising: 10. A first conductive type impurity is introduced into a second conductive type base layer of a semiconductor substrate including a first conductive type first semiconductor layer and a second conductive type base layer. Forming a first base layer of a first conductivity type; introducing a second conductivity type impurity into the first base layer of the first conductivity type to form a floating emitter layer of a second conductivity type; Forming a second base layer of the first conductivity type by introducing an impurity of the first conductivity type into the floating emitter layer of the two conductivity type; and forming a second conductivity type on the second base layer of the first conductivity type. Forming a second semiconductor layer of a second conductivity type by introducing an impurity of the second conductivity type; a second semiconductor layer of the second conductivity type; a second semiconductor layer of the first conductivity type;
Forming a first gate electrode embedded in a layer including the base layer and the floating emitter layer of the second conductivity type; a second semiconductor layer of the second conductivity type;
Forming a second gate electrode embedded in a layer including a base layer, the second conductive type floating emitter layer, the first conductive type first base layer, and the second conductive type base layer. Of manufacturing a semiconductor device having a thyristor provided.