JPH06163908A - Double gate mos device - Google Patents

Abstract

PURPOSE:To restrain latch up due to function of parasitic thyristor by employing first and second gate electrodes of trench structure thereby reducing the amount of current to be discharged per unit cell at the time of turn OFF and preventing the discharge current from concentrating immediately below the emitter region. CONSTITUTION:Gate oxide 8 is formed on the inner surface of a groove 13 penetrating through a p-base region 4, an n-base region 5 formed on the surface thereof, and a p-emitter region 6 formed on the surface thereof, and then the groove 13 is filled with poly-Si thus providing a first gate electrode 11. A second gate electrode 12 is formed between an exposed part of the p-base region 4 and the emitter region 6 through the gate oxide 8. This structure prevents a depletion layer, extending from p-n junction of the p-base region 4 and an n- layer 3 to the n- layer 3, from spreading beneath the first gate electrode 11 thus allowing free injection of electrons from an n-base region 5 when the first gate electrode 11 is turned OFF and decreasing negative resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor switching element used in a power supply device or the like, and more particularly to a double gate MOS device used as a voltage driving switching element.

[0002]

2. Description of the Related Art A semiconductor element for switching is ideally low in both steady loss and switching loss, and various semiconductor elements have been proposed for this purpose. However, in general, the steady loss and the switching loss have a trade-off relationship, and there is a problem that the switching loss increases when trying to reduce the steady loss. In order to reduce the steady loss, it is necessary to perform thyristor operation using conductivity modulation, but in the case of thyristor operation, it takes time for minority carriers to disappear, increasing turn-off time, that is, This causes an increase in switching loss. If a lifetime killer is introduced to promote the recombination of the minority carriers and reduce the switching loss, the conductivity modulation is reduced and the on-voltage, that is, the steady loss is increased. On the other hand, a double-gate MOS device in which the thyristor operation that was conventionally driven by current to reduce the on-voltage is driven by voltage that drastically reduces the input loss was proposed by Sakurai et al.
ngs of 1992 International Symposium on Power Semico
nductor Devices & ICs, Tokyo, pp28-33.

FIG. 2 shows a vertical double gate MOS device.
The basic structure is shown. This vertical type double gate MOS device
Where p⁺N on the surface of the collector layer 1⁺buffer
N through layer 2^-Layer 3 is formed, n^-Layer surface layer
The p base region 4 is selectively formed on the surface layer by n layers.
Base regions 5 are formed respectively. In addition, n base region
P emitter regions 6 are selectively formed in the surface layer of the region 5,
Emitter ends on the surfaces of the p emitter region 6 and the n base region 5
The emitter electrodes 7 connected to the child E are in common contact
It The first gate electrode 11 is formed on the n-base region 5.
of the portion sandwiched between the p base region 4 and the p emitter region 6
N from the top^-A gate oxide film 8 is formed over the exposed portion of layer 3.
Provided through the insulating film 9 and is covered with the first gate terminal G.
₁It is connected to the. The second gate electrode 12 is a p base region.
From the exposed part of the region 4 to the p emitter region of the n base region 5
6 through the gate oxide film 8
And the second gate terminal G covered with the insulating film 9.₂
It is connected to the. Also p⁺Collector layer 1
Such a double gate MOS device in contact with the electrode 10
In the vice, the first and second gate electrodes 11, 12 are shown in FIG.
Voltage is applied in the form shown in. G₁Above the threshold on the terminal
When a voltage is applied, the p base region 4 under the gate electrode 11
An inversion layer is formed on the surface of the. Electrons passing through this inversion layer
By n^-Layer 3 and n⁺An electron current flows through the buffer layer 2.
To enter. No positive voltage is applied to the collector electrode 10.
, N^-Layer 3 and n⁺Electron current flowing into buffer layer 2
Is the built-in p⁺Layers 1 and n⁺Buffer area 2 and
And n ^-A pnp transistor formed by the layer 3 and the p base region 4.
It becomes the base current of the transistor, n^-Conductivity modulation in layer 3
Is turned on. In addition, the conductivity modulation
The hole current generated by^-Layer 3 and
n⁺Buffer layer 2, p base region 4, and n base region 5
It becomes the base current of the npn transistor formed by
Drive this transistor and finally p⁺Layers 1 and n⁺
Buffer layers 2 and n^-Layer 3, p base region 4 and n base
Since the thyristor formed with the area 5 operates,
₁It can be turned on by the terminal. This device
The turn-off of the gate is applied to the gate electrodes 11 and 12.
Turn off the gate-emitter voltage by shifting it as shown in Fig. 3.
By doing. At this time, t₁At time to GND
The dropped voltage of the gate electrode 12 becomes the voltage of the gate electrode 11.
On the other hand, the surface area of the n region 5 under the gate electrode 12 becomes negative with respect to
Then, an inversion layer is generated in the p-channel MOSFET to turn on.
When this MOSFET turns on, the p base region 4 and the n base
The base area 5 is electrically short-circuited, and the basic structure is
Structure is equivalent to IGBT. Therefore, in normal operation,
Without the gate electrode 11, the thyristor operates and the
Sometimes first t ₁At this time, the gate electrode 12 is paired with the gate electrode 11.
And turn it negative to turn on the IGBT from the thyristor operation.
Change to the state. And after the IGBT operation,
T after 3 to 4 μsec₂Voltage applied to the gate electrode 11
Turn off to stop the supply of electrons and turn on this device.
You can

[0004]

In such a double gate MOS device, a depletion layer extending from the pn junction between the p base region 4 and the n ⁻ layer 3 to the n ⁻ layer 3 is formed under the gate oxide film 8. Also extends and narrows the gap with the depletion layer extending from the adjacent pn junction base region side.
^- limit the electron current flowing into the layer 3, p ⁺ layer 1, n ⁺ layer 2 and the n ^- layer 3, p region 4, time consuming thyristor structure formed by the n region 5 to turn on, Figure 4
A negative resistance component as shown by the line 41 in FIG. This leads to an increase in steady loss, which is a problem when driving at high frequencies.

Further, as shown in FIG. 3, the timings of the G1 and G2 voltages are shifted, the G2 voltage is turned off, and the above-mentioned pnp is applied.
The n4 layer thyristor structure is used for p ⁺ layer 1, n ⁺ layer 2 and n ^−.
When converted to a pnp three-layer transistor structure composed of the layer 3 and the p base region 4, the voltage drop generated when the current swept out by the depletion layer passes directly under the p region 6 is a built-in voltage between the p region and the n region. By exceeding the potential difference, n
^- layer 3, p region 4, n region 5, p region parasitic thyristor operates of 6, the latch-up occurs which can not be turned off devices off the G1 voltage, safe operating area at turn-off is narrower There is a problem.

The object of the present invention is to solve these problems,
It is an object of the present invention to provide a double-gate MOS device having a low steady loss, a wide safe operating area at turn-off, a high-speed turn- _{off, and} a small turn-off loss E _off .

[0007]

To achieve the above object, a double-gate MOS device of the present invention comprises a second conductivity type layer having a second conductivity type collector layer contacting one side with a second conductivity type second layer on the other side. A base layer of a conductivity type is in contact, a base region of a first conductivity type is selectively formed on a surface layer of the second conductivity type base layer, and a second layer is selectively formed on a surface layer of the base region of the first conductivity type. A conductive type emitter region is formed, the emitter electrode commonly contacts the emitter region surface and the exposed surface of the first conductive type base region, the collector electrode contacts the surface of the collector layer, the first gate electrode causes the emitter region, The second gate electrode is provided on the exposed surface of the second conductivity type base layer in a groove penetrating the first conductivity type base region and the second conductivity type base layer and reaching the first conductivity type layer, with an insulating film interposed. From the exposed surface of the first conductivity type base area Toward emitter regions on the surface and those provided via the insulating film. Alternatively, a second-conductivity-type base layer and a first-conductivity-type base layer are sequentially stacked on the other side of the first-conductivity-type layer that is in contact with the second-conductivity-type collector layer on one side, and the first-conductivity-type base layer is formed. A plurality of second-conductivity-type emitter regions are selectively formed on the surface layer of the collector electrode, the emitter electrode commonly contacts the emitter-region surface and the exposed surface of the first-conductivity-type base layer, and the collector electrode contacts the collector layer. A first gate electrode is provided in a groove penetrating the emitter region, the first conductivity type base layer and the second conductivity type base layer to reach the first conductivity type layer via an insulating film, and the second gate electrode is It is assumed that it is provided through an insulating film in a groove that penetrates the emitter region and the base layer of the first conductivity type and reaches the base layer of the second conductivity type. Then, in this case, it is effective that the insulator is filled between the first gate electrode and the second gate electrode and the opening surface of the groove.

[0008]

The effect of limiting the injection current by the depletion layer formed by forming the first gate electrode between the trench structure, the base region of the second conductivity type and the first conductivity type layer is eliminated. In addition, by making the first and second gate electrodes have a trench structure, the cell density can be increased, the amount of the sweep current per cell at turn-off can be reduced, and the sweep can be performed uniformly. Since the concentration of the sweep current immediately below is dispersed, latchup due to the operation of the parasitic thyristor is suppressed.
Further, due to the increase in cell density, the ratio of the current injected from the opposite side to the current injected from the first conductivity type base layer by the gate voltage application increases, and the collector layer of the second conductivity type, the first conductivity type layer, It means that the base current of the bipolar transistor consisting of the second conductivity type base layer is increased.
The current amplification factor increases, the ratio of the current due to carriers injected from the collector layer, for example, the proportion of hole current, decreases, and the current can be swept out to the collector electrode at high speed at turn-off, and the turn-off can be speeded up. In addition, the saturation voltage decreases as the cell density increases, and the trade-off relationship between the saturation voltage and E _off is improved, so E _off can be reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings including the same parts in FIG.
In the embodiment shown in FIG. 1, the first gate electrode has a trench structure. That is, the p base region 4, the n base region 5 formed in the surface layer, and the p formed in the surface layer
The inner surface of the trench 13 dug through the emitter region 6 is covered with the gate oxide film 8, and the polycrystalline silicon filling the inside is used as the first gate electrode 11. Second gate electrode
Similar to the conventional structure of FIG. 2, 12 is provided from above the exposed portion of p base region 4 to above the portion sandwiched by emitter region 6 via gate oxide film 8. The emitter electrode 7 is formed on the entire surface of the semiconductor substrate, and the gate electrode
It is insulated by 11 and the insulating film 14. This structure allows
From the pn junction between the p base region 4 and the n ⁻ layer 3 to the n ⁻ layer 3
It is possible to prevent the depletion layer that spreads over the first gate electrode 11 from extending below the first gate electrode 11. Therefore, when the depletion layer is turned off by applying a voltage above the threshold value to the first gate electrode 11, The effect of suppressing the generated electron current is lost, and the negative resistance can be reduced as in the V _CE -I _C characteristic shown by the solid line 42 in FIG.

In the embodiment shown in FIG. 5, the second gate electrode
12 also has a trench structure provided in a groove 15 penetrating the emitter region 6 and the n base region 5 and reaching the p base region. The emitter electrode 7 and the groove 15 are insulated by the insulating film 14 that closes the opening. As a result, the cell density in the semiconductor substrate can be increased as compared with the case of FIG. 1, and the ratio of the electron current injected from the n base region 5 when a voltage is applied to G1 and G2 as shown in FIG. 3 increases. To do. This is, p ⁺ layer 1, n ⁺ buffer region 2 and the n ^- because the layer 3, p base is formed by the area 4 will be the base current of the pnp transistor increases the current amplification factor increases, p ⁺ layer The ratio of the hole current injected from 1 can be made smaller than that in the case of FIG. As a result, the amount of holes accumulated in the n ⁻ layer 3 is reduced, and when turned off, the holes can be swept out to the collector electrode 10 at a high speed. In addition, since the saturation voltage decreases as the cell density increases, as shown in FIG. 6, the trade-off relationship between the saturation voltage V _{CE (sat)} and the turn-off loss E _off is the dotted line in FIG.
It is improved to solid line 62 from 61. Further, as shown in FIG.
When the G1 voltage is first turned off to convert the thyristor structure to the IGBT structure and then the G2 voltage is turned off, the hole current distributed to each cell based on the holes swept out by the depletion layer is more uniform due to the increase in cell density. Therefore, the concentration right under the p emitter region 6 is avoided, and the voltage drop in this portion is reduced, so that latch-up is suppressed. As a result, the turn-off tolerance is improved, and the safe operation area is wider in the range shown by the solid line 72 than in the conventional range shown by the dotted line 71 in FIG.

In the embodiment shown in FIG. 8, the first gate electrode 11
The second gate electrode 12 and the insulating film 14 that insulates the emitter electrode 7 are completely embedded in the trenches 13 and 15. Thereby, the emitter electrode 7 can be formed on a perfect plane, the manufacturing process can be simplified, and the cost can be reduced.

[0012]

According to the present invention, by exposing the first gate electrode or both the first and second gate electrodes of the double gate MOS device to the trench structure, the surface exposed portion of the high resistivity layer is eliminated, and that portion is eliminated. Since the current limiting effect due to the expansion of the depletion layer into the gate is eliminated, the negative resistance component in the current / voltage output characteristics can be eliminated, and the cell density can be increased. We were able to improve the trade-off relationship between losses and expand the safe operating area.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a double gate MOS device according to an embodiment of the present invention.

FIG. 2 is a sectional view of a conventional double gate MOS device.

FIG. 3 is a gate voltage waveform diagram of a double gate MOS device.

FIG. 4 is a voltage / current output characteristic diagram of a double gate MOS device according to an embodiment and a conventional example.

FIG. 5 is a cross-sectional view of a double gate MOS device according to another embodiment of the present invention.

FIG. 6 is a saturation voltage / turn-off loss diagram of the double-gate MOS device of the example and the conventional example.

FIG. 7 is a turn-off tolerance diagram of the double-gate MOS device of the example and the conventional example.

FIG. 8 is a double gate MO according to still another embodiment of the present invention.
Cross section of S device

[Explanation of symbols]

1 p ⁺ collector layer 2 n ⁺ buffer layer 3 n ⁻ layer 4 p base region 5 n base region 6 p emitter region 7 emitter electrode 8 gate oxide film 9 insulating film 10 collector electrode 11 first gate electrode 12 second gate electrode 13 Groove 14 Insulating film 15 Groove

Claims (3)

[Claims] 1. A first conductivity type layer is in contact with one side of the second conductivity type collector layer, and a second conductivity type base layer is in contact with the other side of the first conductivity type layer, and a surface layer of the second conductivity type base layer is selectively formed. A first conductivity type base region is formed, and a second conductivity type emitter region is selectively formed on a surface layer of the first conductivity type base region,
The emitter electrode is in common contact with the emitter region surface and the exposed surface of the first conductivity type base region, the collector electrode is in contact with the surface of the collector layer, the first gate electrode is in the emitter region,
The second gate electrode is provided on the exposed surface of the second conductivity type base layer in a groove penetrating the first conductivity type base region and the second conductivity type base layer and reaching the first conductivity type layer, with an insulating film interposed. To the exposed surface of the first conductivity type base region to the surface of the emitter region via an insulating film. 2. A second conductivity type base layer and a first conductivity type base layer are sequentially laminated on the other side of the first conductivity type layer which is in contact with one side of the second conductivity type collector layer. A plurality of second conductivity type emitter regions are selectively formed on the surface layer of the base layer, the emitter electrode commonly contacts the emitter region surface and the exposed surface of the first conductivity type base layer, and the collector electrode functions as the collector layer. Contact, the first gate electrode is the emitter region,
The second gate electrode is provided in the groove penetrating the first conductivity type base layer and the second conductivity type base layer to reach the first conductivity type layer, and the second gate electrode is provided with the emitter region and the first conductivity type base layer. A double-gate MOS device, wherein the double-gate MOS device is provided through an insulating film in a groove penetrating through to reach the second conductivity type base layer. 3. The double-gate MOS device according to claim 2, wherein an insulator is filled between the upper surfaces of the first and second gate electrodes and the opening surface of the groove.