JPH05206469A - Insulated gate bipolar transistor - Google Patents

Insulated gate bipolar transistor

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Publication number
JPH05206469A
JPH05206469A JP1405292A JP1405292A JPH05206469A JP H05206469 A JPH05206469 A JP H05206469A JP 1405292 A JP1405292 A JP 1405292A JP 1405292 A JP1405292 A JP 1405292A JP H05206469 A JPH05206469 A JP H05206469A
Authority
JP
Japan
Prior art keywords
emitter
region
type
semiconductor
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1405292A
Other languages
Japanese (ja)
Inventor
Toshiki Kurosu
Masahito Miura
雅人 三浦
俊樹 黒須
Original Assignee
Hitachi Haramachi Semiconductor Ltd
Hitachi Ltd
日立原町電子工業株式会社
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Haramachi Semiconductor Ltd, Hitachi Ltd, 日立原町電子工業株式会社, 株式会社日立製作所 filed Critical Hitachi Haramachi Semiconductor Ltd
Priority to JP1405292A priority Critical patent/JPH05206469A/en
Publication of JPH05206469A publication Critical patent/JPH05206469A/en
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Abstract

PURPOSE:To improve the short-circuit resistance and the latch-up resistance in an IGPT which has intermittent emitter structure. CONSTITUTION:In the plan view showing the embodiment, a plurality of N-type emitters 5 are provided intermittently selectively inside a P-type base 4. The gate electrode 7 made in the upper layer between an emitter 5 and an N- epitaxial layer 3 is not made in the section where the N-type emitter 5 is not present. Moreover, an emitter electrode 8 may be formed on a P-type base 4, at a specified interval from the gate electrode 7 made as mentioned above. Accordingly, the saturated current at the short-circuit between a collector and an emitter can be reduced, and besides the latch up critical current can be elevated, whereby the short-circuit resistance and the latch-up resistance of IGBT can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor).
er: hereinafter referred to as IGBT), and particularly to an IGBT having high short circuit withstand capability and latch-up withstand capability suitable for use in applications where load short circuit conditions such as inverters are assumed.

[0002]

2. Description of the Related Art Generally, an IGBT is a DSA (Diffusio).
A conductive type layer opposite to the source is provided in the drain region of the power MOSFET element in which the source and base regions are diffused and formed by the n Self Align method, so that conductivity modulation is caused in the drain region to cause on-resistance. Although the power switching element is reduced, a parasitic layer thyristor is formed by the newly provided conductive type layer, and when the parasitic thyristor turns on, it cannot be controlled by the voltage from the gate electrode.

This phenomenon is called so-called latch-up, and an IGBT of this type is thermally destroyed by an overcurrent once latch-up occurs. Therefore, it is important to increase the latch-up withstanding capability. ..

A conventional IGBT having a high latch-up resistance will be described below with reference to the drawings.

FIG. 5 is a plan view showing the structure of the prior art, and FIG.
FIG. 6 is a sectional view taken along line CC of FIG. 5 and 6, 1
Is a P-type collector layer, 2 is an N-type buffer layer, 3 is an N-type epitaxial layer, 4 is a P-type base region 4, 5 is an N-type emitter region, 6 is a gate insulating film, 7 is a gate electrode, 8 is an emitter electrode , 9 are collector electrodes.

An IGBT according to the prior art generally has an intermittent emitter structure, that is, a structure in which a plurality of IGBT elements such as a polygonal structure such as a square and a stripe structure are connected in parallel. The emitter is further divided into a plurality of structures. 5 and 6
The prior art shown in (1) shows, as an example thereof, an IGBT having a striped structure and an intermittent emitter structure.

That is, the conventional IG shown in FIG.
The BT is configured by forming N-type emitter layers 5 at predetermined intervals in a P-type base region 4 formed in a stripe shape on the surface of a semiconductor substrate so as to be separated.

As shown in FIG. 6, in the conventional IGBT, the N-type buffer layer 2 and the N-type epitaxial layer 3 are sequentially formed on the P-type collector layer 1, and the surface of the N-type epitaxial layer 3 is formed. The P-type base region 4 is selectively formed in a stripe shape, and an N-type emitter region 5 is selectively formed on the surface of the P-type base region 4 so as to be intermittently formed.

The vicinity of the surface of the N type epitaxial layer 3 and the surface of the P type base region 4 sandwiched by the surfaces of the N type emitter regions 5 is defined as a channel region. A gate electrode 7 made of polysilicon is formed on the channel region via a gate insulating film 6. Further, an emitter electrode 8 is formed so as to be electrically connected to both the P-type base region 4 and the N-type emitter region 5, and a collector electrode 9 is formed so as to be electrically connected to the P-type collector layer 1. ing.

The example of the IGBT shown in FIG. 5 has a stripe structure as described above, and the gate electrode 7 and the emitter electrode 8 are usually integrated with all the IGBT cells in the same pellet. Also, the collector electrode 9
A PNPN thyristor structure is parasitic between the emitter electrode 8 and the emitter electrode 8, and having this thyristor structure causes latch-up.

The mechanism of latch-up generation is as described below. Now, when a hole current flows just below the N-type emitter region 5, a voltage drop occurs due to the lateral resistance RB existing in the P-type base region 4. When this voltage drop becomes higher than the built-in potential of the PN junction formed by the P-type base region 4 and the N-type emitter region 5, the PN junction is forward biased and the N-type emitter region 5 is formed.
Electron injection into the P-type base region 4 occurs. And
This electron injection serves as a trigger to turn on the thyristor of the PNPN and cause latch-up.

As the main current ICE of the IGBT increases, the hole current flowing directly under the N-type emitter region 5 also increases and latch-up easily occurs. Therefore, the IGBT is generally designed so that Ilat> ICE (sat) MAX. To be done. Here, Ilat is the limit main current that can avoid latch-up, and ICE (sat) MAX is the saturation current at the maximum gate voltage in actual use.

IGBT with an intermittent emitter structure shown in FIG.
Of the N-type emitter region 5 is formed in the P-type base region 4 so as to be separated into a plurality of portions at a predetermined interval. It is divided into a region immediately below and a region between the emitter regions. Therefore, the lateral resistance of the P-type base region 4 in the region between the emitter regions can be made lower than that immediately below the emitter because the emitter region on the surface is removed.

Thus, the IGBT according to this prior art is
Can increase Ilat and suppress the occurrence of latch-up. Further, in this conventional technique, the effective channel width can be slightly reduced and ICE (sat) MAX can be reduced as compared with the case where the emitters are continuously formed. It is also effective for improvement.

As a conventional technique relating to this type of IGBT, for example, a technique disclosed in Japanese Patent Laid-Open No. 61-164263 is known.

[0016]

The IGBT according to the prior art described above can improve the short-circuit withstand capability and the latch-up withstand capability by having the above-mentioned configuration. However, there is a problem that sufficient short-circuit withstand capability and latch-up withstand capability cannot be obtained for practical use in the expected field.

An object of the present invention is to solve the above-mentioned problems of the prior art and provide an IGBT having a high short-circuit withstand capability and a latch-up withstand capability capable of enduring actual use in a field where an inverter device or the like is assumed to have a load short circuit. Especially.

[0018]

According to the present invention, the above-mentioned object is to provide a gate in a portion where an emitter region is not formed between emitter regions which are selectively intermittently formed in an IGBT having a discontinuous emitter structure. This is achieved by avoiding the formation of electrodes. Further, the purpose is
This is achieved by forming an emitter electrode on the base region with a certain distance from the gate electrode.

That is, the IGBT according to the present invention is the first
A first conductive type first semiconductor layer having a second main surface, a second conductive type second semiconductor layer formed on the first main surface of the first semiconductor layer, and the second semiconductor layer. A first conductive type first semiconductor region selectively formed on the surface, and a plurality of second semiconductor regions selectively formed on the surface of the first semiconductor region.
A conductive type second semiconductor region, a control electrode formed on the first semiconductor region sandwiched between the surface of the second semiconductor layer and the surface of the second semiconductor region via an insulating film, and A first main electrode formed on the first and second semiconductor regions, and a second main electrode formed on the second main surface of the first semiconductor layer, and formed separately. The control electrode is not formed in a portion where the second semiconductor region is not formed between the second semiconductor regions of the second conductivity type.

The IGBT according to the present invention has a first conductive type first semiconductor layer having first and second main surfaces, and a second conductive layer formed on the first main surface of the first semiconductor layer. Type 2
A semiconductor layer, a first conductive type first semiconductor region selectively formed on the surface of the second semiconductor layer, and a plurality of second semiconductor layers selectively formed on the surface of the first semiconductor region. A conductive type second semiconductor region, a control electrode formed on the first semiconductor region sandwiched between the surface of the second semiconductor layer and the surface of the second semiconductor region via an insulating film, and A first main electrode formed on the first and second semiconductor regions, and a second main electrode formed on the second main surface of the first semiconductor layer, and formed separately. The control electrode is not formed in a portion where the second semiconductor region is not formed between the plurality of second conductivity type second semiconductor regions, and the first main electrode is kept at a predetermined distance from the control electrode. , Has a structure formed on the first semiconductor region.

[0021]

The present invention provides an I having a conventional interrupted emitter structure.
Since the gate electrode between the emitter region and the emitter region of the GBT is removed, the channel width can be effectively reduced, and thus ICE (sat) MAX can be reliably and effectively reduced.

Further, in the present invention, contrary to the gate electrode to be removed, the emitter electrode is provided so as to project to the portion where the gate electrode is removed. By flowing between the regions, the resistance can be reduced in the lateral direction of the base region, and thus Ilat can be increased.

According to the present invention, it is possible to provide an IGBT having a high short circuit withstand capability and a high latch up withstand capability as described above.

[0024]

Embodiments of the insulated gate bipolar transistor according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a plan view showing the structure of the first embodiment of the present invention, and FIG. 2 is a sectional view taken along line BB in FIG. 1 and 2 are the same as those in FIGS. 5 and 6.

Illustrated IGBT according to a first embodiment of the present invention
Has a structure in which a plurality of N-channel type IGBT cells having a stripe structure are connected in parallel. As shown in FIG. 2, the cross section is a structure in which an N-type buffer layer 2 and an N-type epitaxial layer 3 (second semiconductor layer) are sequentially formed on a P-type collector layer 1 (first semiconductor layer). have. A P-type base region 4 is selectively formed on the surface of the N-type epitaxial layer 3, and an N-type emitter region 5 (first semiconductor region) is selectively formed on the surface of the P-type base region 4 (first semiconductor region). 2 semiconductor regions) are formed.

The vicinity of the surface of the N type epitaxial layer 3 and the surface of the P type base region 4 sandwiched by the surfaces of the N type emitter regions 5 is defined as a channel region. A gate electrode 7 made of polysilicon is formed on the channel region via a gate insulating film 6. Further, an emitter electrode 8 is formed so as to be electrically connected to both the P-type base region 4 and the N-type emitter region 5, and a collector electrode 9 is formed so as to be electrically connected to the P-type collector layer 1. ing. Then, the gate electrode 7 and the emitter electrode 8
Are integrated for all cells in the same pellet.

The first embodiment of the present invention is an N type in which the gate electrode 7 is separated at a predetermined interval as shown by hatching in the plan view of FIG. The plane pattern is not formed in the upper layer between the emitter regions where the emitter regions 5 are not formed.

In the first embodiment of the present invention configured as described above, the gate electrode 7 is now applied with a positive voltage applied to the collector electrode 9 and a negative voltage applied to the emitter electrode 8.
It is assumed that a positive voltage is applied to. In this case, an inversion layer is formed on the surface of the P-type base region 4 below the gate electrode 7, and a channel of the N-type MOSFET is formed, and an electron current flows from the N-type emitter region 5 to the N-type epitaxial layer 3 through this channel. Injected.

In the first embodiment of the present invention, as shown in FIG. 1, the gate electrode 7 between the emitter and the emitter between the N-type emitter regions 5 which are separated by a predetermined distance is formed. Since it is deleted, no channel is formed on the surface 11 of the P-type base region 4 in this portion. Therefore, when a voltage is applied to each electrode as described above, the width of the channel formed in the P-type base region 4 is
The channel width becomes almost equal to the width of the N-type emitter region 5, and the flow of electron current can be limited only to the surface 10 of the P-type base region 4 defined as the channel region.

Therefore, in the above-described first embodiment of the present invention, the saturation current ICE (sat) MAX at the maximum gate voltage in actual use is used.
Can be reduced, and the short-circuit withstand capability and the latch-up withstand capability can be improved.

This is because the conventional technique described with reference to FIGS. 5 and 6 has a gate electrode between the emitters and the emitters between the N-type emitter regions 5 which are separated from each other with a predetermined distance. Therefore, the electron current flows with a horizontal lateral spread through the channel region generated on the surface 11 of the P-type base region 4 in the meantime, and the emitter-emitter distance is substantially larger than the channel length. Electron current cannot be reduced, and therefore I
This is clear when one considers that CE (sat) MAX could not be effectively reduced.

FIG. 3 is a plan view showing the structure of the second embodiment of the present invention, FIG. 4 is a sectional view taken along the line A--A of FIG. 4, and the reference numerals in the drawing are the same as those in FIGS. ..

The second embodiment of the present invention is also an IGBT having a stripe structure similarly to the first embodiment, and its sectional structure is substantially the same as that of the first embodiment.

That is, as shown in FIG. 4, its cross section has a structure in which an N type buffer layer 2 and an N type epitaxial layer 3 are sequentially formed on a P type collector layer 1. A P-type base region 4 is selectively formed on the surface of the N-type epitaxial layer 3, and an N-type emitter region 5 is selectively formed on the surface of the P-type base region 4.

The surface vicinity 10 of the P-type base region 4 sandwiched between the surface of the N-type epitaxial layer 3 and the surface of the N-type emitter region 5 is defined as a channel region. A gate electrode 7 made of polysilicon is formed on the channel region via a gate insulating film 6. Further, an emitter electrode 8 is formed so as to be electrically connected to both the P-type base region 4 and the N-type emitter region 5, and a collector electrode 9 is formed so as to be electrically connected to the P-type collector layer 1. ing. Then, the gate electrode 7 and the emitter electrode 8
Are integrated for all cells in the same pellet.

In the second embodiment of the present invention, as in the case of FIG. 1, the gate electrode 7 is separated at a predetermined interval as shown by hatching in the plan view of FIG. The N-type emitter region 5 configured as described above is configured so as to have a planar pattern that is not formed between the emitter and the emitter where it is not formed.

Therefore, the second embodiment of the present invention shown in FIGS.
The embodiment can reduce ICE (sat) MAX as in the case of FIG.

In addition, in the second embodiment of the present invention, in addition to the structure of the first embodiment, the plane pattern of the emitter electrode 8 is devised to limit the main current Ila that can avoid latch-up.
This is intended to improve the latch-up resistance of the IGBT by increasing t.

That is, as described in the mechanism of latch-up generation described above, it is important to reduce the lateral resistance RB in the P-type base region 4 through which the hole current flows in order to improve the latch-up resistance. The intermittent emitter structure allows a part of the hole current to flow by bypassing between the emitter and the emitter to reduce the RB, but in this case as well, the lateral resistance RB is equal to the emitter region-emitter. It was restricted by the inter-region distance and the sheet resistance of the base region.

Therefore, according to the second embodiment of the present invention, as shown in FIG. 3, the emitter electrode 8 is kept at a predetermined distance required for insulation between the gate electrode 7 and the electrode, while the P-type base region 4 is kept. It is provided on the top and configured. As a result, the second embodiment of the present invention can effectively pass the hole current by bypassing between the emitter region and the emitter region without being restricted by the sheet resistance of the base region. It is possible to reduce the lateral resistance of the region and increase Ilat.

As an example, the emitter width W and the distance D between the emitters are set to 1: 1 and the depth of the base region = 6 μm, the sheet resistance of the base region = 200 Ω / □, the depth of the emitter layer = 1 μm, and Sheet resistance of base area = 5
00Ω / □, the extension length of the emitter electrode is L1, its width is L4, the distance between the emitter electrode and the emitter end is L2,
The distance between the emitter electrode and the tip of the base region is L3,
W = D = L1 = L2 = 10 μm, L3 = 15 μm, L4
As for the IGBT formed with a width of 6 μm, the equivalent lateral resistance RB of the base region is about 200 Ω in the case of the conventional technique in which the emitter electrode is not provided with a protrusion, whereas the emitter electrode is provided with a protrusion. In the case of the second embodiment of the invention, the equivalent lateral resistance RB of the base region could be about 60Ω.

That is, in the second embodiment of the present invention, RB can be increased to 1/3 or less and Ilat can be increased to 3 times or more as compared with the prior art.

In the above-described second embodiment of the present invention, the gate electrode 7 is formed between the emitter region and the emitter region in which the N-type emitter region 5 formed by being separated at a predetermined interval is not formed. However, the emitter electrode 8 is formed up to this portion, but instead of the emitter electrode 8 in the P-type base region 4 between the emitter region and the emitter region,
A high-concentration P-type region can be provided, and the same effect can be obtained.

The above-described first and second embodiments of the present invention have been described by taking the N-channel type IGBT as an example.
The present invention can be similarly applied to a P-channel IGBT. Further, although the above-described first and second embodiments of the present invention have been described assuming that the IGBT cell structure is a stripe structure, the present invention is also applicable to the case where the IGBT cell structure is a polygonal structure. Can be applied.

Next, an example of a semiconductor circuit using the IGBT according to the embodiment of the present invention configured as described above will be described.

FIG. 7 is a diagram showing an example of a semiconductor circuit in which the IGBT according to the present invention is applied to a separately excited inverter. Figure 7
, E is a DC power supply, L is a DC reactor, VR,
VS and VT are three-phase AC voltages, T1, T3 and T5 are upper arm switch groups, T2, T4 and T6 are lower arm switch groups, and 100 is an IGBT according to the present invention.

The separately excited inverter shown in FIG. 7 is constructed by using one IGBT 100 or a plurality of IGBTs connected in series as each switch. In this inverter, the switch of the IGBT of the present invention is a circuit of a three-phase bridge structure, so that the DC power source E is a three-phase AC voltage V
It can be converted into R, VS, and VT.

In the above description, an example in which an inverter is constructed using the IGBT of the present invention has been described.
The BT is not limited to this and can be used in various power conversion devices.

[0050]

As described above, according to the present invention, in the IGBT having the intermittent emitter structure, the gate electrode on the base region where the emitter-emitter and the epitaxial layer face each other is eliminated, so that the channel is effectively formed. The width can be reduced, and the saturation current ICE (sat) MAX at the maximum gate voltage in actual use can be reliably and effectively reduced, which can improve short-circuit withstand capability and latch-up withstand capability. ..

Further, according to the present invention, the hole current can be effectively bypassed between the emitter and the emitter by the emitter electrode projecting in the opposite direction to the removed gate electrode, and the base region can be made to flow. The lateral resistance can be reduced, and the main current Ilat, which is the limit at which latch-up can be avoided, can be increased. Therefore, the short-circuit withstand capability and the latch-up withstand capability can be improved.

[Brief description of drawings]

FIG. 1 is a plan view showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a sectional view taken along line BB in FIG.

FIG. 3 is a plan view showing a configuration of a second exemplary embodiment of the present invention.

4 is a cross-sectional view taken along the line AA of FIG.

FIG. 5 is a plan view showing a configuration of a conventional technique.

6 is a cross-sectional view taken along line CC of FIG.

FIG. 7 is a diagram showing an example of a semiconductor circuit using an IGBT according to the present invention.

[Explanation of symbols]

 1 P-type collector layer 2 N-type buffer layer 3 N-type epitaxial layer 4 P-type base region 5 N-type emitter region 6 Gate insulating film 7 Gate electrode 8 Emitter electrode 9 Collector electrode

Claims (7)

[Claims]
1. In an insulated gate bipolar transistor having a discontinuous emitter structure, a gate electrode is not formed in a region in which no emitter region is formed between emitter regions that are selectively intermittently formed. Characteristic insulated gate bipolar transistor.
2. The insulated gate bipolar transistor according to claim 1, wherein an emitter electrode is formed on the base region with a constant distance from the gate electrode.
3. In an insulated gate bipolar transistor having a discontinuous emitter structure, a region where no emitter region is formed between the selectively discontinuously formed emitter regions does not operate as a channel of the transistor. Insulated gate bipolar transistor.
4. A first-conductivity-type first semiconductor layer having first and second principal surfaces, and a second-conductivity-type second semiconductor layer formed on the first principal surface of the first semiconductor layer. A first semiconductor region of the first conductivity type selectively formed on the surface of the second semiconductor layer, and a plurality of second conductivity type first selectively formed on the surface of the first semiconductor region. A second semiconductor region, a control electrode formed via an insulating film on the first semiconductor region sandwiched between the surface of the second semiconductor layer and the surface of the second semiconductor region, and the first and the second control electrodes. 2 In the insulated gate bipolar transistor including a first main electrode formed on a semiconductor region and a second main electrode formed on a second main surface of the first semiconductor layer, the selective isolation A second semiconductor region is formed between the plurality of second conductivity type second semiconductor regions formed by The insulated gate bipolar transistor, wherein the control electrode is not formed in a non-existing portion.
5. The insulated gate type according to claim 4, wherein a high concentration region having the same conductivity type as that of the first semiconductor region is formed on a surface of the first semiconductor region in a portion where the control electrode is not formed. Bipolar transistor.
6. A first-conductivity-type first semiconductor layer having first and second principal surfaces, and a second-conductivity-type second semiconductor layer formed on the first principal surface of the first semiconductor layer. A first semiconductor region of the first conductivity type selectively formed on the surface of the second semiconductor layer, and a plurality of second conductivity type first selectively formed on the surface of the first semiconductor region. A second semiconductor region, a control electrode formed via an insulating film on the first semiconductor region sandwiched between the surface of the second semiconductor layer and the surface of the second semiconductor region, and the first and the second control electrodes. 2 In the insulated gate bipolar transistor including a first main electrode formed on a semiconductor region and a second main electrode formed on a second main surface of the first semiconductor layer, the selective isolation A second semiconductor region is formed between the plurality of second conductivity type second semiconductor regions formed by The insulated gate bipolar transistor, wherein the control electrode is not formed in a non-existing portion, and the first main electrode is formed on the first semiconductor region with a predetermined distance from the control electrode.
7. A power conversion device comprising the insulated gate bipolar transistor according to claim 1 or 2.
JP1405292A 1992-01-29 1992-01-29 Insulated gate bipolar transistor Granted JPH05206469A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1405292A JPH05206469A (en) 1992-01-29 1992-01-29 Insulated gate bipolar transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1405292A JPH05206469A (en) 1992-01-29 1992-01-29 Insulated gate bipolar transistor
DE19934301947 DE4301947A1 (en) 1992-01-29 1993-01-25 Insulated gate bipolar transistor - has high short-circuit resistance and latch-up resistance

Publications (1)

Publication Number Publication Date
JPH05206469A true JPH05206469A (en) 1993-08-13

Family

ID=11850324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1405292A Granted JPH05206469A (en) 1992-01-29 1992-01-29 Insulated gate bipolar transistor

Country Status (2)

Country Link
JP (1) JPH05206469A (en)
DE (1) DE4301947A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0817274B1 (en) * 1996-07-05 2004-02-11 SGS-THOMSON MICROELECTRONICS S.r.l. Asymmetric MOS technology power device
DE19654113A1 (en) * 1996-12-23 1998-06-25 Asea Brown Boveri Method for producing a MOS-controlled power semiconductor component
JP2002505525A (en) 1998-02-27 2002-02-19 アーベーベー (シュヴァイツ) アクチェンゲゼルシャフト Insulated gate bipolar transistor
DE19808154A1 (en) * 1998-02-27 1999-09-02 Asea Brown Boveri Bipolar transistor with insulated gate (IGBT)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4963951A (en) * 1985-11-29 1990-10-16 General Electric Company Lateral insulated gate bipolar transistors with improved latch-up immunity
US4779123A (en) * 1985-12-13 1988-10-18 Siliconix Incorporated Insulated gate transistor array
JPH02312280A (en) * 1989-05-26 1990-12-27 Mitsubishi Electric Corp Insulated gate bipolar transistor
DE69029180T2 (en) * 1989-08-30 1997-05-22 Siliconix Inc Transistor with voltage limiting arrangement
JP2650519B2 (en) * 1991-07-25 1997-09-03 株式会社日立製作所 Horizontal insulated gate transistor

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