JP3257186B2 - Insulated gate thyristor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate thyristor used as a voltage-driven switching element in a power supply device or the like.

[0002]

2. Description of the Related Art Ideally, a switching semiconductor element has a small steady-state loss and a small switching loss, and various semiconductor elements have been proposed for this purpose. However, in general, the steady loss and the switching loss are in a trade-off relationship, and there is a problem that an attempt to reduce the steady loss increases the switching loss. This requires that a thyristor operation using conductivity modulation be performed to reduce the steady-state loss.However, when the thyristor operation is performed, it takes time until the minority carrier disappears, and the turn-off time increases, that is, This causes an increase in switching loss. When a lifetime killer is introduced to promote the recombination of the minority carriers and reduce the switching loss, the conductivity modulation decreases and the on-voltage, that is, the steady loss increases. On the other hand, the insulated gate thyristor, which used a voltage drive to significantly reduce input loss, instead of a current drive thyristor to reduce the on-voltage, was developed by Sakurai et al. In Proceedings.
of 1992 International Symposium on Power Semicondu
ctor Devices, ICS, Tokyo, pp 28-33.

FIG. 2 shows a basic structure of an insulated gate thyristor. In this insulated gate thyristor, p ⁺
N ⁻ on the surface of the collector layer 11 via the n ⁺ buffer layer 10
A base layer 1 is formed, ap base region 2 is selectively formed on a surface layer of n ⁻ base layer 1, and an n ⁺ emitter region 3 is selectively formed on the surface layer. p in the surface layer of the base region 2, in addition to the n ⁺ source region 4 of the n ⁺ emitter region 3 is formed. n exposed between the p base region 2 ^- layer 1 and n ^- the layer 1 and the n ⁺ p base region 2 on the surface exposed between the regions 3, a first gate electrode via a gate oxide film 5 6 Are formed and connected to the G1 terminal. On the surface of n base region 2 exposed between n ⁺ emitter region 3 and n ⁺ source region 4, a gate oxide film 5
, A second gate electrode 7 is formed and connected to the G2 terminal. An emitter electrode 9 is in common contact with a part of the p base region 2 and a part of the n ⁺ emitter region 3 at the opening of the insulating film 8 surrounding the gate electrodes 6 and 7, and is connected to the E terminal. The collector electrode 12 is in contact with the p ⁺ collector layer 11 on the opposite side,
Connected to terminal C.

When a positive voltage is applied to the first and second gate electrodes 6 and 7 from the G1 and G2 terminals while a positive voltage is applied to the collector electrode 12 of such an insulated gate thyristor, the p base region Inversion layers are formed in both the channel region 21 immediately below the first gate electrode 6 and the channel region 22 immediately below the second gate electrode 7, and first, the n ⁺ source region 4 is connected to the n ⁺ emitter region 3 via the channel region 22. , And the n ⁺ source region 4 and the n ⁺ emitter region 3 are short-circuited. At the same time are also caused an inversion layer in the channel region 21, the emitter electrode 9 - for voltage is applied, from the emitter electrode 9 through the n ⁺ source region 4, n ⁺ emitter region 3 n ^- base layer 1 The flow of electrons that reaches to occurs. A positive voltage is applied to the collector electrode 12, and the PNP transistor formed by the p ⁺ collector layer 11, the n ⁺ buffer layer 10, the n ⁻ base layer 1, and the p base region 2 is driven. At this time, holes are injected from the p ⁺ collector region 11,
Conductivity modulation occurs in the n ^- base layer 1. This hole current is the base current of the NPN transistor formed by n ⁻ base layer 1, p base region 2, n ⁺ source region 4 and n ⁺ emitter region 3 that are short-circuited to each other. Since the emitter layer of the NPN transistor composed of the n ⁺ region 3 and the n ⁺ region 4 is long and has a structure that actively drives the NPN transistor, electrons are injected from the n ⁺ region 3 and the n ⁺ region 4. Easy to get offended. By driving the PNP transistor and the NPN transistor in this way, when the sum of the current amplification factors of the respective transistors becomes larger than 1, the p ⁺ collector layer 11, the n ⁻ base layer 1, the p base region 2, the n ⁺ region 3 And 4 are turned on. In order to turn off this element, the voltage applied to the gate electrodes 6 and 7 is set to 0 to stop the injection of electrons from the n ⁺ regions 3 and 4, thereby eliminating the formation of the inversion layers of both the channel regions 21 and 22. It can be done by doing.

[0005]

In this insulated gate thyristor, the on-resistance of the MOSFET formed by the n ⁺ regions 3 and 4 and the second gate electrode 7 increases as a large current flows. Unlike the normal thyristor structure, it has the characteristic that the current capacity is saturated, so the safe operation area is wider than that of the voltage-driven thyristor. However, because of the thyristor structure, it is safer than the insulated gate bipolar transistor (IGBT). The disadvantage is that the area is small. In addition, there is a disadvantage that an injection current is limited by a depletion layer extending from a pn junction between n ⁻ layer 1 and p region 2.

An object of the present invention is to provide an insulated gate thyristor which eliminates these drawbacks and extends a safe operation area.

[0007]

In order to achieve the above-mentioned object, a first insulated gate thyristor of the present invention comprises a base layer of a first conductivity type having a collector layer of a second conductivity type on one side. On the other side, a base layer of the second conductivity type is laminated, and a separation layer reaching the first conductivity type base layer from the surface of the second conductivity type base layer is filled with an insulator, and the second layer in contact with the separation layer is filled with an insulator. An emitter region and a source region of the first conductivity type are selectively formed on the surface layer of the conductivity type base layer from the first conductivity type base layer side, and the first conductivity type base layer and the emitter of the second conductivity type base layer are formed. A first gate electrode is provided in the separation layer facing the portion sandwiched between the regions via a gate insulating film, and a gate insulating film is provided in the separation layer facing the portion sandwiched between the emitter region and the source region. A second gate electrode is provided in the insulator through the film. , The emitter electrode is in contact with the common source region and a second conductivity type base layer, a collector electrode is assumed to contact the collector layer.

A second insulated gate thyristor according to the present invention is characterized in that a second conductivity type base layer is laminated on the other side of a first conductivity type base layer in which a second conductivity type collector layer is provided on one side, As the surface of the second conductivity type base layer in the separation layer to reach the first conductivity type base <br/> scan layer insulator is filled, the surface layer of the second conductivity type base layer in contact with the separation layer anti The emitter region of the first conductivity type reaching the surface on the base layer side of the first conductivity type and the source region of the first conductivity type are selected on the surface layer on the side opposite to the first conductivity type with an interval from the emitter region. The first gate electrode is formed in the insulator via the gate insulating film in the separation layer facing the portion of the second conductivity type base layer between the first conductivity type base layer and the emitter region. ,
A second gate electrode is provided on the surface of the portion sandwiched between the emitter region and the source region via a gate insulating film, and the emitter electrode is in common contact with the source region and the second conductivity type base layer, Assume that the collector electrode contacts the collector layer.

A third insulated gate thyristor of the present invention is characterized in that a base layer of the second conductivity type is laminated on the other side of the base layer of the first conductivity type on one side of which a collector layer of the second conductivity type is provided, As the surface of the second conductivity type base layer in the separation layer to reach the first conductivity type base <br/> scan layer insulator is filled, the surface layer of the second conductivity type base layer anti first conductivity type base On the layer side surface
The first and second emitter regions of the first conductivity type that reach are separated layers.
One side of the separation layer is formed in contact with both side walls of
A source region of the first conductivity type is selectively formed on the surface layer of the base layer of the second conductivity type with an interval from the first emitter region in contact with the wall, and the first conductivity type base layer of the base layer of the second conductivity type A first gate electrode in the insulator via a gate insulating film in a separation layer facing a portion sandwiched between the first and second emitter regions, and a first emitter region and a source region On the surface of the sandwiched portion, second gate electrodes are respectively provided via a gate insulating film, and the emitter electrode is a source region,
It is assumed that the collector layer is in common contact with the second emitter region and the second conductivity type base layer in contact with the other side wall of the separation layer, and the collector electrode is in contact with the collector layer.

A fourth insulated gate thyristor according to the present invention is characterized in that a first second conductivity type base layer is provided on one side of a first first conductivity type base layer on which a second conductivity type collector layer is provided. Layer, a second base layer of the first conductivity type, and a base layer of the second second conductivity type are stacked, and reach the first first conductivity type base layer from the surface of the second second conductivity type base layer. The separation layer is filled with an insulator, and the surface layer of the first second conductivity type base layer that is in contact with the separation layer is selectively provided with an emitter region of the first conductivity type from the first first conductivity type base layer side. And a first source region are formed, the source region is in contact with the second first conductivity type base layer, and a separation layer is formed on a surface layer of the second second conductivity type base layer opposite to the first base layer. A second source region of the second conductivity type in contact is formed, and a first first conductivity type base layer of the first second conductivity type base layer A first gate electrode is provided in the separation layer facing the portion sandwiched between the emitter region and the emitter region and the first source region in a separation layer facing the portion sandwiched between the emitter region and the first source region. In the separation layer facing the portion of the second second conductivity type base layer between the second first conductivity type base layer and the second source region via the gate insulating film. A third gate electrode is provided in the insulator via a gate insulating film, the emitter electrode is in common contact with the second source region and the second second conductivity type base layer, and the collector electrode is connected to the collector layer. Shall be in contact.

[0011]

Since the base layer of the second conductivity type is laminated on the base layer of the first conductivity type, the effect of limiting the injection current due to the spread of the depletion layer therebetween is lost. In addition, by forming the first and second gate electrodes or only the first gate electrode in a trench structure, the cell density can be increased, and the concentration of the sweep current per cell at the time of turn-off is reduced, and the sweep is uniform. Since the concentration of the sweeping current immediately below the emitter region is dispersed, latch-up due to the operation of the parasitic thyristor is suppressed. Furthermore, the ratio of the current injected from the opposite side of the current injected into the first conductivity type base layer by the gate voltage due to the increase in the cell density increases, and the collector layer of the second conductivity type, the first conductivity type base layer, Since the base current of the bipolar transistor composed of the second conductivity type base layer is increased, the current amplification factor is increased, and the current due to minority carriers injected from the collector layer into the first conductivity type base layer, for example, the hole current , The voltage can be quickly swept to the collector electrode at the time of turn-off, and the turn-off can be speeded up. In addition, the saturation voltage decreases as the cell density increases, and the trade-off relationship between the saturation voltage and the turn-off loss is improved, so that the turn-off loss can be reduced.

When only the first gate electrode has a trench structure, the second gate electrode is provided only on one side of the trench isolation layer, and is directly in contact with the emitter electrode on the emitter region on one side of the first gate electrode. Thereby, the IGBT is connected in parallel to the insulated gate thyristor, and the safe operation area can be expanded by utilizing the advantage of the wide safe operation area which is an advantage of the IGBT.

Further, by further laminating a base layer of both conductivity types on the insulated gate thyristor and providing a third gate electrode of a trench structure, a MOSFET is connected in series to the insulated gate thyristor, and Since the minority carriers accumulated in the layer can be extracted by the gate-collector capacitance at the time of turn-off, the cutoff current greatly increases.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a first embodiment of the present invention. The difference from FIG. 2 is that the first gate electrode 6 and the second gate electrode 7 have n ⁻
It has a trench structure provided in the insulator 8 filled in the trench 13 dug from the surface of the p base layer 2 stacked on the layer 1 to reach the n ⁻ layer. The n ⁺ emitter region 3 and the n ⁺ source region 4 are formed in the surface layer of the p base layer 2 which is in contact with the inner surface of the groove 13. As a result, it is possible to increase the number of MOS portions each constituted by the first gate electrode 6 and the second gate electrode 7, thereby increasing the total cell density. As the cell density increases, the electron current flowing into the n ⁻ base layer 1 increases, and the p ⁺ collector layer 11
The ratio of the hole current injected from the substrate increases. Increasing the electron current increases the base current of the PNP transistor formed by the p ⁺ collector layer 11, the n ⁺ buffer layer 10, the n ⁻ layer 1, and the p base layer 2, thereby increasing the current amplification factor. This will result in an increase in hole current.
The hole current, n ^- base layer 1, p base layer 2, are short-circuited to each other by a voltage applied to the gate electrode 7 n ⁺
N formed by emitter region 3 and n ⁺ source region 4
The current becomes the base current of the PN transistor, and the current amplification factor can be increased. Therefore, the driving efficiency of the PNPN thyristor is improved overall, and the saturation voltage can be reduced. In addition, it takes time until the conductivity modulation is performed when a voltage higher than the threshold voltage is applied to the first and second gate electrodes 6 and 7 to turn on the thyristor structure, and a certain transient voltage is generated. This transient voltage can also be reduced by increasing the cell density. By increasing the cell density and decreasing the saturation voltage, the ratio of the electron current to the total current increases, and as a result, the loss at the time of turn-off can be reduced. These reduce the total loss and enable use at high frequencies. Also, by increasing the cell density, the distribution of the hole current at the time of turn-off becomes uniform, and the hole current density per cell decreases, so that the cutoff current can be increased. Further, since the trench structure is used, a hole current flows vertically also in the central region of the p base layer 2, and the hole current flowing immediately below the gate electrode is reduced, so that the cutoff current at the time of turn-off is increased. be able to.

In the second embodiment of the present invention shown in FIG. 3, only the first gate electrode 6 is buried in the insulator 8 of the groove 13, and the second gate electrode 7 is formed on the p base layer as in FIG. 2 is provided on the surface. Therefore, n ⁺ emitter region 3 is in contact with the inner surface of trench 13, and n ⁺ source region 4 is in contact with the surface of p layer 2. As a result, the increase in cell density is inferior to that in the first embodiment shown in FIG. 1, but the effect of reducing the total loss is obtained.
On the other hand, since the gate electrode of the trench structure becomes one layer,
There is an advantage that manufacturing is simplified.

In the third embodiment of the present invention shown in FIG. 4, the first gate electrode 6 has a trench structure as in the second embodiment, and the second gate electrode 7 is formed on the surface of the p base layer 2. , But is provided only on one side of the first gate electrode 6. The first gate electrode 6 is connected to the n ⁻ base layer 1, the p base layer 2 and the n ⁺ regions 31 , 32 and the first M
The second gate electrode 7 is an n ⁺ region 3
1 , the p-layer 2 and the n ⁺ region 4 constitute a second MOSFET. The p ⁺ collector layer 11 and the n base layer 1 (n ⁺
The buffer layer 10) and the p base layer 2 constitute a bipolar transistor. Therefore, in a portion where the second gate electrode 7 is not provided on the surface, an IGBT is constituted by the first MOSFET and the bipolar transistor. Thus, by configuring the IGBT in the bipolar mode on one side,
Since a part of the hole current having conductivity modulation generated in the n ^- base layer 1 can be borne on the IGBT side, the cut-off current at the time of turn-off is smaller than in the case of FIGS. 1 to 3 which is a complete thyristor structure. And the safe operation area is widened.

In a fourth embodiment of the present invention shown in FIG. 5, an n ^- base layer 14 and a p-base layer 15 are laminated on the p-layer 2 having the structure of the first embodiment shown in FIG. The groove 13 is the p layer
It is dug from the surface of 15 until it reaches the n ^- layer 1. p layer
An n ⁺ second source region 16 is formed on the surface layer 15 in contact with the groove 13, and a p ⁺ region between the second source region 16 and the n ⁺ region 4 is formed.
A third gate electrode 17 forming an inversion layer in a channel region 23 in contact with the inner surface of the groove 13 of the layer 15
It is provided in an insulator 8 filling 13. As a result, an N-channel MOSFET having a gate electrode 17 is connected in series to the emitter side of the insulated gate thyristor. When a positive voltage higher than the threshold voltage is applied to the first gate electrode 6, the second gate electrode 7, and the third gate electrode 17 while a positive voltage is applied to the collector electrode 12 of the device, the channel region 21 , 22, and 23 are formed with inversion layers. As a result, the n ⁺ region 16, the n ⁻ layer 14, and the n ⁻ layer 1 are short-circuited, and the element can be turned on. At the time of turning off, when a voltage lower than the threshold voltage is applied to each of the gate electrodes 6, 7, and 17, holes are accumulated in the channel regions 21, 22, and 23, and the collector electrode 12, the p-layer 15, and the source region 16 Is insulated from the emitter electrode 9 that contacts the substrate. At this time, the hole current generated by the conductivity modulation cannot flow through the emitter electrode 7, but can be extracted by the gate and collector capacitances, and can be turned off at high speed. Further, the breaking current can be greatly increased as compared with the first embodiment.

[0018]

According to the present invention, since the insulated gate portion of the insulated gate thyristor has a trench structure, the cell density can be increased, the saturation voltage and the turn-off loss can be reduced, and the cutoff current can be increased. As a result, the safe operation area can be expanded. Furthermore, the trench structure M
The OSFETs can be connected in series, and the cutoff current can be further increased.

[Brief description of the drawings]

FIG. 1 is a sectional view of an insulated gate thyristor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional insulated gate thyristor.

FIG. 3 is a sectional view of an insulated gate thyristor according to a second embodiment of the present invention;

FIG. 4 is a sectional view of an insulated gate thyristor according to a third embodiment of the present invention;

FIG. 5 is a sectional view of a MOSFET series-connected insulated gate thyristor according to a fourth embodiment of the present invention;

[Explanation of symbols]

1, 14 n ⁻ base layer 2, 15 p base layer 3 n ⁺ emitter region 4 n ⁺ source region 5 gate oxide film 6 first gate electrode 7 second gate electrode 8 insulator 9 emitter electrode 10 n ⁺ buffer layer 11 p ⁺ Collector layer 12 collector electrode 13 groove 16 second n ⁺ source region

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/749

Claims (4)

(57) [Claims] 1. A base layer of a second conductivity type, wherein a collector layer of a second conductivity type is provided on one side, and a base layer of a second conductivity type is laminated on the other side of the base layer of the first conductivity type. An insulator is filled in the separation layer reaching the base layer of the first conductivity type, and the surface layer of the base layer of the second conductivity type in contact with the separation layer is selectively filled with the first conductivity type from the base layer side of the first conductivity type. An emitter region and a source region are formed, and a first gate is formed in a separation layer facing a portion of the second conductivity type base layer between the first conductivity type base layer and the emitter region via a gate insulating film. In the separation layer facing the portion between the emitter region and the source region, a second gate electrode is provided in the insulator via a gate insulating film, and the emitter electrode is provided in the source region and the second region. In common contact with the conductive type base layer,
An insulated gate thyristor, wherein a collector electrode contacts a collector layer. 2. A base layer of a second conductivity type, wherein a collector layer of a second conductivity type is provided on one side, and a base layer of a second conductivity type is laminated on the other side of the base layer of the first conductivity type. First guide
An insulator is filled in the separation layer reaching the base layer, and an emitter of the first conductivity type reaching the surface on the side opposite the first conductivity type is provided on the surface layer of the base layer of the second conductivity type in contact with the separation layer. The source region of the first conductivity type is selectively formed in the surface layer on the side opposite to the first conductivity type base layer with an interval between the emitter region and the first conductivity type base layer of the second conductivity type base layer. The first gate electrode is placed in the insulator via the gate insulating film in the separation layer facing the portion sandwiched between the layer and the emitter region, and on the surface of the portion sandwiched between the emitter region and the source region. Is provided with a second gate electrode via a gate insulating film, an emitter electrode is in common contact with the source region and the second conductivity type base layer, and a collector electrode is in contact with the collector layer. Thyristor. 3. A base layer of the second conductivity type is laminated on the other side of the base layer of the first conductivity type, wherein a collector layer of the second conductivity type is provided on one side. First guide
An insulating material is filled in the separation layer reaching the electric conductivity type base layer, and the surface layer of the second conductivity type base layer is opposite to the first conductivity type base layer.
First and second emitter regions of the first conductivity type reaching the surface of
There is formed in contact with each side wall of the separation layer, the source region of the first conductivity type in a surface layer of the second conductivity type base layer through the first emitter region and gap in contact with one side wall of the separating layer The first conductive type base layer of the second conductive type base layer is selectively formed in the separation layer facing the portion between the first and second emitter regions via the gate insulating film. A second gate electrode is provided on a surface of a portion where the gate electrode is interposed between the first emitter region and the source region in the insulator with a gate insulating film interposed therebetween, and the emitter electrode is connected to the source region and the isolation region. An insulated gate thyristor in which the second emitter region and the second conductivity type base layer are in common contact with the other side wall of the layer, and the collector electrode is in contact with the collector layer. 4. A base layer of a first second conductivity type, a base layer of a first second conductivity type, and a base layer of a second first conductivity type on the other side of the first base layer of the first conductivity type provided with a collector layer of the second conductivity type on one side. A base layer, a base layer of the second second conductivity type is laminated, and an insulating material is filled in the separation layer reaching the first first conductivity type base layer from the surface of the second second conductivity type base layer, An emitter region and a first source region of the first conductivity type are selectively formed on the surface layer of the first second conductivity type base layer in contact with the separation layer from the first first conductivity type base layer side. The region is in contact with the second first conductivity type base layer, and the second source region of the second conductivity type is in contact with the separation layer on the surface layer of the second second conductivity type base layer opposite to the first base layer. Is formed, and the portion facing the portion between the first first conductivity type base layer and the emitter region of the first second conductivity type base layer is formed. In the layer, the first gate electrode via the gate insulating film, and in the separation layer facing the portion between the emitter region and the first source region, the second gate electrode via the gate insulating film, A third gate electrode is provided via a gate insulating film in a separation layer facing a portion between the second first conductivity type base layer and the second source region of the second second conductivity type base layer. An insulated gate thyristor provided in an insulator, wherein the emitter electrode is in common contact with the second source region and the second second conductivity type base layer, and the collector electrode is in contact with the collector layer.