CN103199017B - Form buried conductive layer method, material thickness control methods, form transistor method - Google Patents

Form buried conductive layer method, material thickness control methods, form transistor method Download PDF

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Publication number
CN103199017B
CN103199017B CN201310060514.1A CN201310060514A CN103199017B CN 103199017 B CN103199017 B CN 103199017B CN 201310060514 A CN201310060514 A CN 201310060514A CN 103199017 B CN103199017 B CN 103199017B
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groove
layer
grid
trench
electrode
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CN103199017A (en
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阿肖克·沙拉
艾伦·埃尔班霍威
克里斯托弗·B·科康
史蒂文·P·萨普
彼得·H·威尔逊
巴巴克·S·萨尼
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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Abstract

The present invention is provided in forming groove on a semiconductor substrate, form the method for buried conductive layer, for controlling the method for the thickness of epitaxially grown semi-conducting material, for controlling the method for the thickness of epitaxially grown semi-conducting material, for the method forming trench gate type transistor.Method includes: form the first dielectric materials layer on the upper surface of semiconductor substrate and described groove；First dielectric materials layer is formed the first conductive material layer；One patterned the first dielectric materials layer and described first conductive material layer are to form the first conductive electrode, and described first conductive electrode is included in the Part I that the interior longitudinal axis along described groove of described groove extends and the Part II extended on the top of the described substrate of the first end of described groove；Described first conductive material layer forms the second dielectric materials layer；Described second conductive material layer forms the second dielectric materials layer；And the second dielectric materials layer described in one patterned and described second conductive material layer.

Description

Form buried conductive layer method, material thickness control methods, form transistor method
The application is the divisional application of the original bill application of Application No. 201010138629.4, filing date December in 2004 29 days, invention entitled " power semiconductor and manufacture method ".
The application of Application No. 201010138629.4 is the divisional application of the original bill application of Application No. 200480042161.1, filing date December in 2004 29 days, invention entitled " power semiconductor and manufacture method ".
Cross reference to related applications
The application is the part continuity of following commonly assigned U.S. Patent application:
10/155th, No. 554 (the acting on behalf of Reference Number 18865-17-2/17732-7226.001) of Mo et al., entitled " FieldEffectTransistorandMethodsofitsManufacture ", on May 24th, 2002；
The No.10 of Sapp, 209, No. 110 (acting on behalf of Reference Number 18865-98/17732-55270), entitled " DualTrenchPowerMOSFET ", on July 30th, 2002；
The 09/981st of Kocon, No. 583 (acting on behalf of Reference Number 18865-90/17732-51620), entitled " SemiconductorStructurewithImprovedSmallerForwardLossandH igherBlockingCapability ", October 17 calendar year 2001；
The 10/640th of Kocon et al., No. 742 (acting on behalf of Reference Number 90065.000241/17732-66550), entitled " ImprovedMOSGatingMethodforReducedMillerCapacitanceandSwi tchingLosses ", on August 14th, 2003；
09/774th, No. 780 (the acting on behalf of Reference Number 18865-69/17732-26400) of Marchant, entitled " FieldEffectTransistorHavingaLateralDepletionStructure ", January 30 calendar year 2001；
10/200th, No. 056 (the acting on behalf of Reference Number 18865-97/17732-55280) of Sapp et al., entitled " VerticalChangeControlSemiconductorDevicewithLowOutputCap acitance ", on July 18th, 2002；
The 10/288th of Kocon et al., No. 982 (acting on behalf of Reference Number 18865-117/17732-66560), entitled " DriftRegionHigherBlockingLowerForwardVoltageDropSemicond uctorStructure ", on November 5th, 2002；
10/442nd, No. 670 (the acting on behalf of Reference Number 18865-131/17732-66850) of Herrick, entitled " StructureandMethodforFormingaTrenchMOSFETHavingSelf-Alig nedFeatures ", on May 20th, 2003；
The 10/315th of Yedinak, No. 719 (acting on behalf of Reference Number 90065.051802/17732-56400), entitled " MethodofIsolatingtheCurrentSenseonP1anarorTrenchStripePo werDeViceswhileMaintainingaContinuousStripeCell ", on December 10th, 2002；
10/222nd, No. 481 (the acting on behalf of Reference Number 18865-91-1/17732-51430) of Elbanhawy, entitled " MethodsandCircuitforReducingLossesinDC-DCConverters ", on August 16th, 2002；
10/235th, No. 249 (the acting on behalf of Reference Number 18865-71-1/17732-26390-3) of Joshi, entitled " UnmoldedPackageforaSemiconductordevice ", on JIUYUE 4th, 2002；And
10/607th, No. 633 (the acting on behalf of Reference Number 18865-42-1/17732-13420) of Joshi et al. is entitled " FlipChipinLeadedMoldedPackageandMethodofManufactureThere of ", on June 27th, 2003；
And require the priority of the U.S. Patent application of following interim submission:
60/506th, No. 194 (the acting on behalf of Reference Number 18865-135/17732-66940) of Wilson et al., entitled " HighVoltageShieldedTrenchGateLDMOS ", on JIUYUE 26th, 2003；And
60/588th, No. 845 (acting on behalf of Reference Number 18865-164/17732-67010), entitled " AccumulationDevicewithChargeBalanceStructureandMethodofF ormingtheSame ", on July 15th, 2004.
The full content of application listed above is hereby expressly incorporated by reference.
Technical field
On the whole, the present invention relates to semiconductor device, it particularly relates to about the power semiconductor (such as, transistor and diode) improved and manufacture method thereof, including encapsulation and the various embodiments of the circuit being combined with power semiconductor.
Background technology
Critical component in power semiconductor is solid-state switch (solidstateswitch).IGNITION CONTROL to battery-operated consumer electronic devices from automatically application, the power conversion in commercial Application, it is required for meeting most the power switch of application-specific needs.Sustainable development includes that the solid state switch of such as power metal oxide semiconductor field-effect transistor (power MOSFET), insulated gate bipolar transistor (IGBT) and various types of thyratron is to meet this needs.Such as, in the case of power MOSFET, in many other technologies, have been developed for there is the double diffusion structure (DMOS) of lateral channel (lateralchannel) (such as, the U.S. Patent No. 4 of Blanchard et al., 682, No. 405), trench gate (trenchedgate) structure is (such as, the U.S. Patent No. 6 of Mo et al., 429, No. 481), and the various technology of charge balance are (such as in the transistor drift district, the U.S. Patent No. 4 of Temple, 941, No. 026, the 5th of Chen, 216, No. 275, and the 6th of Neilson the, 081, No. 009), with satisfied difference and the demand of often competitive performance.
It is its conducting resistance, breakdown voltage and switching speed for defining some Performance Characteristics of power switch.According to the requirement of special applications, different emphasis be placed on these performance standards each on.Such as, for more than the power application of about 300-400 volt, IGBT demonstrates intrinsic relatively low conducting resistance compared with power MOSFET, but owing to its slower turn-off characteristic makes its switching speed relatively low.Therefore, for the application more than 400 volts with the low switching frequency of requirement low on-resistance, IGBT is preferably to switch, and power MOSFET is often for the device selected by of a relatively high frequency application.If the frequency requirement of given application specifies the switchtype used, then voltage request determines the composition structure of concrete switch.Such as, in the case of power MOSFET, because conducting resistance R of Drain-SourceDSonAnd the proportionate relationship between breakdown voltage so that cause and keep low R while improving transistor voltage performanceDSonDifficulty.Have been developed for the various charge balance structure in transistor drift district difficult to solve this, and obtain success in various degree.
Device parameter performance also can be encapsulated affected by manufacturing process and tube core (die).Make some problem that various effort solves in these problems with the technique and encapsulation technology by developing various improvement.
Either in super portable consumer electronic device in router the most in a communications system and hub, the various application of power switch are along with the expansion of electronics industry and sustainable growth.Therefore, power switch is the semiconductor device with high development potentiality.
Summary of the invention
Present invention provide for the power device of various power electronics applications and manufacture method thereof, encapsulation and be combined with the various embodiments of circuit of power device.Briefly, many charge balance techniques and other technology being used for reducing parasitic capacitance are combined by one aspect of the present invention, to realize having the voltage performance of improvement, compared with high switching speed and compared with the various embodiments of the power device of low on-resistance.Another aspect provides the improvement terminal structure (terminationstructure) for low, medium and high voltage device.According to other aspects of the invention, it is provided that the improved method that power device manufactures.Provide the concrete improvement processing step by various embodiments of the present invention, such as, the formation of groove, the formation of groove inner-dielectric-ayer, the formation of mesa structure (mesastructure), for the technique reducing substrate thickness.According to a further aspect in the invention, temperature and the current sensing elements of such as diode are combined on the same die by the power device of charge balance.Other aspects of the present invention improve equivalent series resistance (ESR) or the resistance of power device, combine adjunct circuit, and provide the improvement of the encapsulation to charge balance power devices on the chip identical with power device.
According to an aspect of the present invention, it is provided that a kind of semiconductor device, including the drift region of the first conduction type；Well region, extends on described drift region, and has second conduction type contrary with described first conduction type；Active groove, extend through described well region and extend into described drift region, sidewall and bottom lined with dielectric material along described active groove, and described active groove is substantially filled with the first screening conductive layer and grid conducting layer, described first screening conductive layer is arranged under described grid conducting layer, and is separated with described grid conducting layer by inter-electrode dielectric；Source area, has described first conduction type, and it is formed in the described well region adjacent with described active groove；And charge control trench, more in depth extend in described drift region than described active groove, and be substantially filled with the material controlled for the vertical electric charge in described drift region.
Preferably, dielectric materials layer is set along described charge control trench, and described charge control trench is substantially filled with conductive material.
Preferably, the described conductive material in described charge control trench is electrically connected to described source area by described source electrode.
Preferably, being provided with multiple conductive layer in described charge control trench, the plurality of conductive layer vertical stacking is the most separated from one another by dielectric material and separate with described trenched side-wall.
Preferably, the plurality of conductive layer being electrically biased in described charge control trench, to provide vertical electric charge balance in described drift region.
Preferably, the plurality of conductive layer in described charge control trench is configured to independent bias.
Preferably, the thickness of the plurality of conductive layer in described charge control trench is different.
Preferably, the thickness of more deep in described charge control trench described first conductive layer is less than the thickness of the second conductive layer being arranged on described first conductive layer.
Preferably, the described first screening conductive layer in described active groove is configured to electrical bias to expectation current potential.
Preferably, described first screening conductive layer and described source area are electrically connected to essentially identical current potential.
Preferably, described active groove also includes being arranged on the secondary shielding conductive layer under described first screening conductive layer.
Preferably, described first screening conductive layer is different with the thickness of secondary shielding conductive layer.
Preferably, described first screening conductive layer and secondary shielding conductive layer are configured to independent bias.
Preferably, described charge control trench is substantially filled with dielectric material.
Preferably, described semiconductor device also includes the lining of the second conductive material extended along the lateral wall of described charge control trench.
Preferably, described semiconductor device also includes Schottky junction structure, and it is formed between described charge control trench and the second adjacent charge control trench.
According to a further aspect in the invention, it is provided that a kind of semiconductor device, including the drift region of the first conduction type；Well region, extends on described drift region, and has second conduction type contrary with described first conduction type；Active groove, extend through described well region and extend into described drift region, the main grid pole being made of an electrically conducting material and the secondary grid being made of an electrically conducting material is formed in described active groove, and it is separated from one another by dielectric materials layer and separate with described trenched side-wall, described main grid pole is on described grid, described active groove also has the first bucking electrode being made of an electrically conducting material, and it is arranged under described grid and is separated with described grid by dielectric material；And source area, there is described first conduction type, it is formed in the described well region adjacent with described active groove.
Preferably, described main grid pole and described grid are configured to independent electrical biasing.
Preferably, described grid biases at the constant potential of the starting voltage of the most described semiconductor device.
Preferably, described grid is more than being applied at the current potential of described source area current potential bias.
Preferably, described grid was connected to the current potential of described starting voltage of the most described semiconductor device before switch motion.
Preferably, described first bucking electrode is configured to independent bias to expectation current potential.
Preferably, described active groove also includes one or more bucking electrode in addition to described first bucking electrode, and it is stacked under described first bucking electrode.
Preferably, described first bucking electrode is different with the size of the one or more additional shield electrodes.
Preferably, described semiconductor device also includes charge control trench, and it extends into described drift region and is substantially filled with the material controlled for described vertical electric charge in drift region.
Preferably, the described conductive material in described charge control trench is electrically connected to described source area by source electrode.
Preferably, multiple conductive layer is set in described charge control trench, the plurality of conductive layer vertical stacking, separated from one another by dielectric material and separate with described trenched side-wall.
Preferably, the plurality of conductive layer in charge control trench described in electrical bias, to provide vertical electric charge to balance in a substrate.
Preferably, the plurality of conductive layer in described charge control trench is configured to independent bias.
Preferably, the size of the plurality of conductive layer in described charge control trench is different.
Preferably, the first conductive layer being more deep in described charge control trench be smaller in size than the size being arranged on the second conductive layer on described first conductive layer.
Preferably, described semiconductor device is additionally included between two adjacent trenches the Schottky junction structure formed.
According to a further aspect in the invention, it is provided that a kind of semiconductor device, including the drift region of the first conduction type；Well region, extends on described drift region, and has second conduction type contrary with described first conduction type；Active groove, extend through described well region and extend into described drift region, the main grid pole being made of an electrically conducting material and the secondary grid being made of an electrically conducting material is formed in described active groove, separated from one another by dielectric materials layer and separate with described trenched side-wall and bottom, described main grid pole is on described grid；Source area, has described first conduction type, and it is formed in the described well region adjacent with described active groove；And charge control trench, more in depth extend in described drift region than described active groove, and be substantially filled with the material controlled for the vertical electric charge in described drift region.
Preferably, described main grid pole and described grid are configured to independent electrical biasing.
Preferably, described grid biases at the constant potential of the starting voltage of the most described semiconductor device.
Preferably, described grid biases at the current potential bigger than the current potential being applied to described source area.
Preferably, described grid was connected to the current potential of described starting voltage of the most described semiconductor device before switch motion.
Preferably, dielectric material is set along described charge control trench, and described charge control trench is substantially filled with conductive material.
Preferably, the described conductive material in described charge control trench is connected to described source area by source electrode.
Preferably, multiple conductive layer is set in described charge control trench, the plurality of conductive layer vertical stacking, separated from one another by dielectric material and separate with described trenched side-wall.
Preferably, the plurality of conductive layer in charge control trench described in electrical bias, to provide vertical electric charge to balance in a substrate.
Preferably, the plurality of conductive layer in described charge control trench is configured to independent bias.
Preferably, the plurality of conductive layer size in described charge control trench is different.
Preferably, be more deep into described charge control trench the first conductive layer be smaller in size than the size being arranged on the second conductive layer on described first conductive layer.
Preferably, described charge control trench is substantially filled with dielectric material.
Preferably, described semiconductor device also includes the lining of the second conductive material, and it extends along the lateral wall of described charge control trench.
Preferably, described semiconductor device also includes Schottky junction structure, and it is formed between described charge control trench and the second adjacent charge control trench.
According to a further aspect in the invention, it is provided that a kind of semiconductor device, including the substrate of the first conduction type；First well region and the second well region, described first well region and the second well region are spaced apart, and have second conduction type contrary with described first conduction type, and extend to first degree of depth of described substrate；First source area and the second source area, having described first conduction type and be respectively formed in described first well region and the second well region, the interval between the outward flange of the outward flange of each source area and its respective well region forms respective first channel region and the second channel region；Main grid pole, it forms on the substrate, and described first source area and described first channel region is horizontal superposes, and is separated with described first source area and described first channel region by thin dielectric layer；Secondary grid, part is formed at described main grid and extremely goes up and be partly formed on described first channel region, and separated with described main grid pole and described first channel region by thin dielectric layer；And first charge control trench and the second charge control trench, it is each passed through described first well region and the second well region extends and extend into described substrate, and be substantially filled with the material controlled for the vertical electric charge in described substrate.
Preferably, dielectric materials layer is set along each charge control trench, and described charge control trench is substantially filled with conductive material.
Preferably, the described conductive material in described charge control trench is electrically connected to described source area by the source electrode formed on the surface of described substrate.
Preferably, multiple conductive layer is set in each charge control trench, the plurality of conductive layer vertical stacking, separated from one another by dielectric material and separate with described trenched side-wall.
Preferably, the plurality of conductive layer in each charge control trench of electrical bias, to provide vertical electric charge balance in described substrate..
Preferably, the plurality of conductive layer in each charge control trench is configured to independent bias.
Preferably, the plurality of conductive layer size in each charge control trench is different.
Preferably, that more gos deep into the first conductive layer in each charge control trench is smaller in size than the size being arranged on the second conductive layer on described first conductive layer.
Preferably, described main grid pole and described grid are configured to independent electrical biasing.
Preferably, described grid biases at the constant potential of the starting voltage of the most described semiconductor device.
Preferably, described grid biases at the current potential bigger than the current potential being applied to described source area.
Preferably, described grid was connected to the current potential of described starting voltage of the most described semiconductor device before switch motion.
According to a further aspect in the invention, it is provided that a kind of semiconductor device, including the drift region of the first conduction type；Well region, extends on described drift region, and has second conduction type contrary with described first conduction type；Active groove, extends in the described drift region being deeper than described well region, and along sidewall and the bottom lined with dielectric material of described active groove, and described active groove is substantially filled with grid conducting layer；Source area, has described first conduction type, is formed in the described well region adjacent with described active groove；Active trench, its be deeper than described well region extend, form described active trench adjacent to described trap and source area thereof, described active trench is substantially filled with conductive material；And layer, there is described second conduction type that concentration increases, be substantially looped around around described body groove.
Preferably, described active trench is substantially filled with the epitaxial material being electrically connected to described source area.
Preferably, described active trench is substantially filled with the DOPOS doped polycrystalline silicon being electrically connected to described source area.
Preferably, form, by injection technology, the layer that described concentration increases.
Preferably, the alloy diffused out by the described conductive material in described active trench forms the layer that described concentration increases.
Preferably, regulate distance L between the sidewall of described active groove and the sidewall of described adjacent active trench, edge gate-capacitance of drain to be minimized.
Preferably, L is approximately equal to or less than 0.3um.
Preferably, the distance between outward flange and the described sidewall of described adjacent active trench of the layer that described concentration increases is regulated, edge gate-capacitance of drain to be minimized.
Preferably, described active trench is deeper than described active groove.
Preferably, described interval L is approximately equal to or less than 0.5um.
Preferably, described active groove also includes the first bucking electrode being made of an electrically conducting material, and it is formed under described grid conducting layer, and described bucking electrode is by dielectric materials layer and described grid conducting layer and described trenched side-wall and bottom insulation.
Preferably, described first bucking electrode in described active groove is configured to electrical bias to expectation current potential.
Preferably, described first bucking electrode and described source area are electrically connected to essentially identical current potential.
Preferably, described active groove also includes the secondary shielding electrode being made of an electrically conducting material, and it is arranged under described first bucking electrode.
Preferably, described first bucking electrode is different with the size of secondary shielding electrode.
Preferably, described first screening conductive layer and secondary shielding conductive layer can be by independent bias.
Preferably, described semiconductor device also includes charge control trench, extends in described substrate and be substantially filled with the material that the vertical electric charge in described substrate balances.
Preferably, dielectric materials layer is set along described charge control trench, and described charge control trench is substantially filled with conductive material.
Preferably, the described conductive material in described charge control trench is electrically connected to described source area by source electrode.
Preferably, multiple conductive layer is set in described charge control trench, the plurality of conductive layer vertical stacking, separated from one another by dielectric material and separate with described trenched side-wall.
Preferably, the plurality of conductive layer in charge control trench described in electrical bias, to provide vertical electric charge balance in described substrate.
Preferably, the plurality of conductive layer in described charge control trench is configured to independent bias.
Preferably, the size of the plurality of conductive layer in described charge control trench is different.
Preferably, the size being smaller in size than the second conductive layer being arranged on described first conductive layer of the first conductive layer being more deep in described charge control trench.
Preferably, described semiconductor device is additionally included between two adjacent trenches the Schottky junction structure formed.
According to a further aspect in the invention, it is provided that a kind of semiconductor device, including the drift region of the first conduction type；Well region, extends on described drift region, and has second conduction type contrary with described first conduction type；Active groove, extends in the described drift region being deeper than described well region, forms the main grid pole being made of an electrically conducting material in described active groove, and described main grid pole is separated with trenched side-wall and bottom by dielectric material；And source area, there is described first conduction type, it is formed in the described well region adjacent with described active groove, wherein, described active groove is filled with the bottom of dielectric material and deeply extends in described drift region, described bottom is by the lining institute cincture of the second conductive material, to provide vertical electric charge control.
Preferably, described semiconductor device also includes multiple locus of discontinuities of the second conduction type, and the lateral wall adjacent to the described active groove in described drift region forms the plurality of locus of discontinuity.
Preferably, described active groove also includes the secondary grid being made of an electrically conducting material, and described time grid is formed under described main grid pole, and by dielectric layer and described main gate insulator.
Preferably, described grid is configured to independent electrical biasing.
Preferably, described grid biases at the constant potential of the starting voltage of the most described semiconductor device.
Preferably, described grid biases at the current potential bigger than the current potential being applied to described source area.
Preferably, described grid was connected to the current potential of described starting voltage of the most described semiconductor device before switch motion.
Preferably, described active groove also includes the first bucking electrode being made of an electrically conducting material, and described first bucking electrode is formed under described main grid pole, and is insulated with described first bucking electrode by dielectric layer.
Preferably, described first bucking electrode is configured to individually be biased to expect current potential.
Preferably, described active groove also includes one or more bucking electrode being made of an electrically conducting material in addition to described first bucking electrode, and the one or more bucking electrode stacks under described first bucking electrode.
Preferably, described first bucking electrode is different with the size of the one or more additional shield electrodes.
According to a further aspect in the invention, it is provided that a kind of semiconductor device, including the drift region of the first conduction type；Well region, extends on described drift region, and has second conduction type contrary with described first conduction type；Active groove, extend through described well region and extend into described drift region, sidewall and bottom lined with dielectric material along described active groove, and described active groove is substantially filled with the first conductive layer and first grid conductive layer, described first conductive layer is arranged under described first grid conductive layer, and by inter-electrode dielectric and described first grid conductive layers apart；Source area, has described first conduction type, and it is formed in the described well region adjacent with described active groove；And first Schottky junction structure, it is formed on the first table top between two adjacent trenches.
Preferably, described first conductive layer is configured to bucking electrode.
Preferably, described first conductive layer is configured to second gate electrode.
Preferably, described active groove also includes the second conductive layer, is arranged on and is configured under described first conductive layer of bucking electrode.
Preferably, described first conductive layer is configured to electrical bias to current potential, and described second conductive layer is configured to electrical bias to current potential.
Preferably, described semiconductor device also includes the second Schottky junction structure, and it is formed on the second table top adjacent to described first table top.
Preferably, in the way of being perpendicular to the longitudinal axis of said two adjacent trenches, described first Schottky junction structure is formed.
According to a further aspect in the invention, it is provided that a kind of semiconductor device, including the drift region of the first conduction type；Well region, extends on described drift region, and has second conduction type contrary with described first conduction type；Active groove, extend through described well region and extend into described drift region, sidewall and bottom lined with dielectric material along described active groove, and described active groove is substantially filled with the first conductive layer forming upper electrode and the second conductive layer forming bottom electrode, described upper electrode is arranged on described bottom electrode and is separated with described bottom electrode by inter-electrode dielectric；Source area, has described first conduction type, is formed in the described well region adjacent with described active groove；And charge control trench, the sidewall along described charge control trench arranges dielectric material, forms one or more diode structure therein.
Preferably, the one or more diode structure includes multiple opposite polarity conductive layer, and the plurality of conductive layer is alternately stacked in described charge control trench, and wherein, of bottommost makes electrical contact with described drift region.
Preferably, described upper electrode is configured to primary gate electrode.
Preferably, described bottom electrode is configured to time gate electrode.
Preferably, described active groove also includes being arranged on the 3rd conductive layer under described second conductive layer, and described 3rd conductive layer is configured to bucking electrode.
Preferably, described bottom electrode is configured to the first bucking electrode.
Preferably, described active groove also includes the 3rd conductive layer, is arranged under described second conductive layer, and described 3rd conductive layer is configured to secondary shielding electrode.
Preferably, described first and second electrodes can be with electrical bias.
Preferably, described semiconductor device also includes Schottky junction structure, and it is formed on the table top between two adjacent charge control trench.
According to a further aspect in the invention, it is provided that a kind of semiconductor device, including the substrate of the first conduction type；First well region and the second well region, described first well region and the second well region are spaced apart, and have second conduction type contrary with described first conduction type, and extend to first degree of depth of described substrate；First source area and the second source area, having described first conduction type and be respectively formed in described first well region and the second well region, the interval between the outward flange of the outward flange of each source area and its respective well region forms respective first channel region and the second channel region；Gate electrode, it is formed on the described substrate superposed with described first channel region and the second channel region, and is separated with described substrate by thin dielectric layer；And first charge control trench and the second charge control trench, it is each passed through described first well region and the second well region extends and extends into described substrate, sidewall along each charge control trench arranges dielectric material, forms one or more diode structure in described charge control trench.
Preferably, the one or more diode structure includes that multiple opposite conductivities layer, the plurality of opposite conductivities layer are alternately stacked in described charge control trench, and of bottommost makes electrical contact with described drift region.
Preferably, described semiconductor device is additionally included on the table top between two adjacent charge control trench the Schottky junction structure formed.
According to a further aspect in the invention, it is provided that a kind of semiconductor device, including the drift region of the first conduction type；Multiple well regions, have second conduction type contrary with described first conduction type, and described well region extends on described drift region；Source area, has described first conduction type, is formed in each well region in the plurality of well region, and limits channel region；Grid structure, it is formed adjacent to described channel region；And multiple floating region, there is the second conduction type, it is arranged in basic described drift region under each of the plurality of well region, wherein, the interval between multiple peak concentrations of the described floating region under each well region increases along with described floating region and the increase of the spacing of each of which well region.
Preferably, described grid structure is substantially planar conductive layer, and it is formed on described channel region.
Preferably, described grid structure is formed on described channel region, and includes the main grid pole of the Part I of channel region described in superposition and be partially formed and the secondary grid of the Part II of channel region described in superposition in described main grid pole.
Preferably, described grid structure includes the groove extending and extending into described drift region through well region, and along sidewall and the bottom lined with dielectric material of described groove, and described groove is substantially filled with conductive material.
Preferably, the described conductive material being substantially filled with described groove includes being formed the top of primary gate electrode and forms the bottom of absolute electrode with described upper isolation.
Preferably, described absolute electrode is configured to time gate electrode.
Preferably, described absolute electrode is configured to bucking electrode.
Preferably, the size of the multiple floating regions under each well region reduces along with described floating region and the increase of the spacing of each of which well region.
Preferably, in the plurality of floating region under each well region, the peak concentration of each reduces along with described floating region and the increase of the spacing of each of which well region.
Preferably, contact each other from those floating regions that described well region is nearest under well region, and under described well region from those floating regions that described well region is farthest be effective floating region.
According to a further aspect in the invention, it is provided that a kind of semiconductor device, including the drift region of the first conduction type；Well region, extends on described drift region, and has second conduction type contrary with described first conduction type；Active groove, extend through described well region and extend into described drift region, sidewall and bottom lined with dielectric material along described active groove, and described active groove is substantially filled with the first conductive layer forming upper electrode and the second conductive layer forming bottom electrode, described upper electrode is arranged on described bottom electrode, and is separated with described bottom electrode by inter-electrode dielectric；Source area, has described first conduction type, and it is formed in the described well region adjacent with described active groove；And first terminal groove, extend under described well region, and be arranged on the outer edge of the active area of described device.
Preferably, the dielectric materials layer thicker than the described dielectric material of the described sidewall along described active groove is set along described first terminal groove, and described first terminal groove is substantially filled with conductive material.
Preferably, the described conductive material in described first terminal groove is electrically connected to source metal.
Preferably, the described conductive material in described first terminal groove is buried under the dielectric material in the bottom of described terminal trenches.
Preferably, described first terminal groove is substantially filled with dielectric material.
Preferably, the width of the table top formed between described first terminal groove and adjacent active groove is different from the width of the table top formed between two active grooves.
Preferably, described first terminal groove is wound on the active region of described device with annular ring.
Preferably, described semiconductor device also includes the second terminal trenches, and it is looped around the described active region of the described device outside described first terminal groove.
Preferably, distance S1 between described first terminal groove and the second terminal trenches is about the twice of distance S2 between described first terminal groove and the end of described active groove.
According to a further aspect in the invention, provide the terminal structure of a kind of outer edge at semiconductor device, described terminal structure includes the multiple concentric annulated column with the first conduction type, it is formed in the termination environment with the second conduction type contrary with described first conduction type, and it is looped around the active region of described device, wherein, each post is connected respectively to conductive field plate.
Preferably, the big field plate that is made of an electrically conducting material cover multiple posts subset and with the subset electric insulation of multiple posts, different conductive field plate is connected in the plurality of post remaining one.
Preferably, described big field plate is connected to ground.
Preferably, the subset of described post is not covered by any conductive field plate.
Preferably, the middle heart septum between the plurality of post changes along with the distance with described active edge.
Preferably, the middle heart septum between the plurality of post increases along with the distance with described active edge.
Preferably, the width of each post changes along with the distance with the edge of described active area.
Preferably, the width of each post reduces along with the distance with the edge of described active area.
Preferably, the width of the plurality of post in described terminal structure keeps essentially identical, and the width of the post of the opposite polarity under the well region in described active area reduces along with the distance with described well region.
According to a further aspect in the invention, it is provided that a kind of method for forming buried conductive layer in forming groove on a semiconductor substrate, described method includes: form the first dielectric materials layer on the upper surface of described semiconductor substrate and described groove；Described first dielectric materials layer forms the first conductive material layer；First dielectric materials layer described in one patterned and described first conductive material layer are to form the first conductive electrode, and described first conductive electrode is included in the Part I that the interior longitudinal axis along described groove of described groove extends and the Part II extended on the top of the described substrate of the first end of described groove；Described first conductive material layer forms the second dielectric materials layer；Described second conductive material layer forms the second dielectric materials layer；And the second dielectric materials layer described in one patterned and described second conductive material layer are to form the second conductive electrode, described second conductive electrode has in described groove and the Part I that extends along the longitudinal axis of described groove and the Part II extended on the top of the described Part II of described first conductive electrode.
Preferably, described method also includes: by the first conductive layer described in the openings contact in described first dielectric layer in the described Part II of described first conductive electrode；And by the second conductive layer described in the openings contact in described second dielectric layer in the described Part II of described second conductive electrode.
According to a further aspect in the invention, it is provided that a kind of method for forming buried conductive layer in forming groove on a semiconductor substrate, described method includes: form the first dielectric materials layer on the upper surface of described semiconductor substrate and described groove；Described first dielectric materials layer forms the first conductive material layer；First dielectric materials layer described in one patterned and described first conductive material layer are to form the first conductive electrode, and described first conductive electrode has the first basic horizontal part extended in described groove and the second substantially vertical part of the described upper surface extending to described substrate along the longitudinal axis of described groove；Described first conductive material layer forms the second dielectric materials layer；Described second conductive material layer forms the second dielectric materials layer；And the second dielectric materials layer described in one patterned and described second conductive material layer are to form the second conductive electrode, described second conductive electrode has the Part I extended in described groove and the Part II of the described upper surface generally perpendicularly extending to described substrate along the longitudinal axis of described groove.
Preferably, described method is additionally included in surface described first conductive electrode of contact and the described Part II of the second conductive electrode of described substrate.
According to a further aspect in the invention, it is provided that the method forming buried conductive layer in multiple grooves in semiconductor substrate, including: along the sidewall of each in the plurality of groove and bottom, the first dielectric materials layer is set；The plurality of groove is substantially filled with the first conductive material layer；Mask layer is applied on a groove selected in the plurality of groove；By recessed to described first conductive material layer in remaining multiple grooves and described first dielectric materials layer；Remove described mask layer；The described upper surface of the described substrate of the described upper surface and sidewall that include described remaining multiple grooves forms the second dielectric materials layer；The top of described remaining multiple grooves is substantially filled with the second conductive material layer；And cover described second conductive material layer with the 3rd dielectric materials layer.
According to a further aspect in the invention, it is provided that a kind of in the multiple grooves in semiconductor substrate formed buried conductive layer method, including: along the sidewall of each in the plurality of groove and bottom, the first dielectric materials layer is set；The plurality of groove is substantially filled with the first conductive material layer；In the groove of each part exposing the first conductive material layer, from the upper surface of described substrate and the described sidewall of the plurality of groove, described first dielectric materials layer is removed to first degree of depth, and the part that described first conductive material layer is exposed forms two grooves in each groove；Apply the described surface of the described exposed portion of the second dielectric materials layer covering described upper surface of described substrate, the described sidewall of each groove and described first conductive material layer；Said two groove in each groove is substantially filled with the second conductive material layer；And cover described second conductive material layer with the 3rd dielectric materials layer.
According to a further aspect in the invention, it is provided that a kind of method of thickness for controlling epitaxially grown semi-conducting material, including: the semiconductor substrate that adulterated by first kind alloy is provided；Forming cushion on described semiconductor substrate, by the alloy of described undoped buffer layer Second Type, the diffusibility of the alloy of described Second Type is less than the diffusibility of described first kind alloy；And on described cushion, form the described epitaxially grown layer of expectation thickness.
Preferably, described undoped buffer layer arsenic.
According to a further aspect in the invention, it is provided that a kind of method of thickness for controlling epitaxially grown semi-conducting material, including: the semiconductor substrate that adulterated by first kind alloy is provided；Forming barrier layer on described semiconductor substrate, described barrier layer has the mixture including carbon；And the epitaxially grown layer of thickness is expected in formation on described cushion, wherein, described barrier layer is for stoping the described alloy of the described first kind to diffuse upward into described epitaxially grown layer from described substrate.
Preferably, the described step forming described barrier layer includes growing silicon carbide layer.
Preferably, the described step forming described barrier layer includes being injected in the surface of described semiconductor substrate carbon doping thing.
According to a further aspect in the invention, it is provided that a kind of method of thickness for controlling epitaxially grown semi-conducting material, including: the semiconductor substrate that adulterated by first kind alloy is provided；Described semiconductor substrate is formed the epitaxially grown layer of expectation thickness；
Forming well region in described epitaxially grown layer, described well region has the alloy of the Second Type of the described alloy opposite conductivities with the described first kind；And at the knot between described epitaxially grown layer and described well region, form diffusion barrier layer, wherein, described barrier layer is for preventing the diffusion of alloy between described well region and described epitaxially grown layer.
Preferably, the described step forming described diffusion barrier layer includes that the window by limiting described well region injects carbon atom.
According to a further aspect in the invention, it is provided that a kind of method for forming trench gate type transistor, including: the substrate of the first conduction type is provided；The drift region of described first conduction type is formed on described substrate；Groove is formed in described drift region；Sidewall and bottom along described groove arrange the first dielectric materials layer；By under-filled first conductive material layer of described groove；Described first conductive material layer is covered with interlayer dielectric material；The optionally epitaxial layer of the second conduction type that growth is contrary with described first conduction type, with groove on forming well region on the upper surface of described drift region and being formed on described interlayer dielectric material；The upper surface and sidewall of described epitaxial layer form the second dielectric materials layer；And described upper groove is substantially filled with the second conductive material layer.
According to a further aspect in the invention, it is provided that a kind of method for forming well region in the semiconductor device, including: the substrate of the first conduction type is provided；The drift region of the first conduction type is formed on described substrate；Groove is formed in described drift region；Form the buried electrodes sealed by dielectric material in the bottom of described groove, expose the sidewall on the top of described groove；Perform the first trap with the alloy of the second conduction type contrary with described first conduction type to inject, be injected in the upper surface of described drift region；And the sidewall exposed by the described top of described groove is performed the second angle trap with the alloy of the second conduction type and injects.
According to a further aspect in the invention, it is provided that a kind of method for forming well region in the semiconductor device, including: the substrate of the first conduction type is provided；The first drift region of the first conduction type is formed on described substrate；Forming dielectric material cylinder on described drift region, the width of each cylinder is substantially equal to the width of the groove formed in later step；Form the second drift region of described first conduction type with described dielectric material pillar on described first drift region；
The optionally epitaxial layer of the second conduction type that growth is contrary with described first conduction type, to form well region on described second drift region with the upper surface of the groove being respectively formed on dielectric material cylinder.
According to a further aspect in the invention, it is provided that a kind of method for thinning wafers of semiconductor material, including: complete the manufacture of device in the top side of described wafer；By the first adhesion process by the described top side temporary adhesive attachment of described wafer to carrier；It is thinned to the dorsal part of described wafer expect thickness；By the second adhesion process, the described dorsal part of the described wafer being thinned is adhered to low resistance substrate；And remove described carrier and clear up the described top side of described wafer.
Preferably, described reduction steps includes grinding technics.
Preferably, described reduction steps includes chemical treatment.
According to a further aspect in the invention, it is provided that a kind of method for thinning silicon substrate, including: the rear side of described silicon substrate is adhered to glass substrate；Heavy sheet glass silicon (SOTG) substrate is formed by adhesion (cleave) described silicon substrate optically；The silicon face of described SOGT substrate is formed epitaxial layer；The described silicon face of described SOGT substrate manufactures active device；By grinding technics, a part for described glass substrate is removed from the dorsal part of described silicon substrate；And processed the remainder of described glass substrate from the described dorsal part removal of described silicon substrate by chemical etching.
According to a further aspect in the invention, it is provided that a kind of method for etching groove in semiconductor substrate, including: performing main first degree of depth that etches into, described main etching uses chemicals based on chlorine so that middle groove has taper and smooth sidewall；And execution time etches into ultimate depth, described etching uses chemicals based on fluorine, and wherein, described secondary etching based on fluorine provides the fillet of described channel bottom and further smoothing of trenched side-wall.
Preferably, described main etch chemistries includes C12/HBr, and described etch chemistries includes SF6.
According to a further aspect in the invention, provide a kind of method for etching groove in semiconductor substrate, including: performing main first degree of depth that etches into, described main etching uses chemicals based on fluorine so that middle groove has substantially straight sidewall and circular bottom；And performing the secondary ultimate depth that etches into, described etching uses chemicals based on chlorine, wherein, etches for described based on fluorine time and provides the fillet of described groove top corner and further smoothing of trenched side-wall.
Preferably, described main etch chemistries includes CF6/O2, and described etch chemistries includes C12.
According to a further aspect in the invention, provide a kind of method for etching groove in semiconductor substrate, including: use to have and add the chemicals based on fluorine of argon and perform main etching, to increase ion bom bardment and to prevent the most recessed tendency in the described top of described groove；And perform time etching, with the sidewall of smooth described groove.
Preferably, described main etch chemistries includes SF6/O2/Ar.
According to a further aspect in the invention, it is provided that a kind of method for etching groove in semiconductor substrate, including: use anaerobic chemicals based on fluorine perform main etching；And use the chemicals based on fluorine of oxidation to perform time etching, wherein, described main etching makes the side etching at described groove top increase, and described etching makes the remainder of described groove produce substantially straight sidewall and circular bottom.
Preferably, described main etch chemistries includes SF6, and described etching includes SF6/O2.
According to a further aspect in the invention, it is provided that a kind of for the method for etching deep groove in semiconductor substrate, including: use the chemicals based on fluorine of oxidation, wherein, introduce oxygen with gradual manner, to control side wall passivation；And progressive power and pressure are to control ion current density and to keep substantially invariable etch-rate.
According to a further aspect in the invention, provide a kind of for the method for etching deep groove in semiconductor substrate, including: use the chemicals based on fluorine that nitrogenous activity is bigger to perform main etching, be then used by the less chemicals SF6 based on fluorine of activity and perform time etching.
Preferably, described main etching includes NF3, and described etching includes SF6/O2.
Preferably, described method also includes repeating described main etching and the step of described etching in an alternating fashion.
According to a further aspect in the invention, it is provided that a kind of method for etching groove in semiconductor substrate, including: the top of described substrate formed pad oxide thin layer；Described cushion oxide layer is formed non-oxidating material layer；Conductive material layer is formed silicon nitride layer；Cushion oxide layer, non-oxidating material layer and silicon nitride layer described in one patterned, to limit the opening for forming described groove；And by groove described in described opening etching, wherein, the described non-oxidating material layer between described pad oxide layer and described silicon nitride layer prevents the growth of the pad oxide during process step subsequently at described slot wedge.
According to a further aspect in the invention, it is provided that a kind of method for etching groove in semiconductor substrate, including: the top of described substrate formed pad oxide thin layer；Described cushion oxide layer is formed silicon nitride layer；Cushion oxide layer described in one patterned and silicon nitride layer, to limit the opening for forming described groove；The surface texture of described substrate is formed non-oxidating material thin layer；Remove described non-oxidating material thin layer from the horizontal surface of described surface texture, leave the non-oxidating material sealing coat of vertical edge along described nitride-pad oxidation structure；And by groove described in described opening etching, wherein, described non-oxidating material sealing coat prevents the growth of the pad oxide during with post-processing step at described slot wedge.
According to a further aspect in the invention, it is provided that a kind of method for forming inter-electrode dielectric layer in groove, including: sidewall and bottom along described groove arrange the first dielectric materials layer；Described groove is substantially filled with the first conductive material layer to form the first electrode；First degree of depth that described first dielectric materials layer and described first conductive material layer are recessed in described groove；Polysilicon material layer is formed on described dielectric material in described groove and the upper surface of conductive material layer；Aoxidize described polysilicon material layer, thus be converted into silicon dioxide layer；And in the groove on described silicon dioxide layer, form the second electrode being made of an electrically conducting material, and separated with trenched side-wall by the second dielectric layer.
According to a further aspect in the invention, it is provided that a kind of method for forming inter-electrode dielectric layer in groove, including: sidewall and bottom along described groove arrange the first dielectric materials layer；Described groove is substantially filled with the first conductive material layer to form the first electrode；Make first degree of depth that described first conductive material layer is recessed in described groove；The remainder of described groove is substantially filled with dielectric fill material；Described first dielectric materials layer and described dielectric fill material layer is made to be recessed into second degree of depth to form inter-electrode dielectric layer；And in the described groove on described inter-electrode dielectric layer, form the second electrode being made of an electrically conducting material, and separated with trenched side-wall by the second dielectric layer.
According to a further aspect in the invention, it is provided that a kind of method for forming inter-electrode dielectric layer in groove, including: sidewall and bottom along described groove arrange the first dielectric materials layer；Described groove is substantially filled with the first conductive material layer, to form the first electrode；First degree of depth being recessed in described groove by described first conductive material layer, makes the top of described recessed conductive material layer higher than the final goal degree of depth by desired depth；By changing the characteristic of described first conductive material layer, increase the oxidation rate on the described top of described the first recessed conductive material layer；Described first dielectric materials layer is removed from remaining trenched side-wall；Performing oxidation step, the top that described first conductive material layer changes is oxidized with the speed faster than described trenched side-wall, forms the inter-electrode dielectric layer thicker than lateral wall insulation lining；And in the described groove on described inter-electrode dielectric layer, form the second electrode being made of an electrically conducting material, and separated with channel insulation lining by described sidewall.
Preferably, the described step of the oxidation rate improving the described top of described the first recessed conductive material layer includes chemically or physically changing described top.
Preferably, the described step of the oxidation rate improving the described top of described the first recessed conductive material layer includes the upper surface essentially perpendicularly implanted dopant with described first conductive material layer.
Preferably, the one during described impurity is argon or fluorine.
According to a further aspect in the invention, it is provided that a kind of method for forming inter-electrode dielectric layer in groove, including: sidewall and bottom along described groove arrange the first dielectric materials layer；Described groove is substantially filled with the first conductive material layer to form the first electrode；Make first degree of depth that described first conductive material layer is recessed in described groove；It is preferably formed as the second dielectric layer, thus on the horizontal surface structure in described groove, forms relatively thick inter-electrode dielectric layer, and the dielectric layer of the sidewall formation relative thin along described groove；Remove the dielectric layer of the described relative thin along described trenched side-wall；And in the described groove on described inter-electrode dielectric layer, form the second electrode being made of an electrically conducting material, and separated with trenched side-wall by side wall dielectric lining.
Preferably, the described step forming the second dielectric layer includes that orientated deposition processes.
Preferably, described orientated deposition processes and includes plasma enhanced chemical vapor deposition.
According to a further aspect in the invention, it is provided that a kind of method for forming inter-electrode dielectric layer in groove, including: sidewall and bottom along described groove arrange the first dielectric materials layer；Described groove is substantially filled with the first conductive material layer to form the first electrode；Make first degree of depth that described first dielectric materials layer and described first conductive material layer are recessed in described groove；Masking oxide thin layer is formed along the vertically and horizontally surface in described groove；Form the silicon nitride layer covering described masking oxide thin layer；Remove described silicon nitride layer from the described bottom of described groove, to expose described horizontal masking oxide thin layer, but leave the described vertical masking oxide thin layer covered by described silicon nitride layer；Described groove is exposed to oxidation environment, to form relatively thick inter-electrode dielectric layer on the horizontal bottom surface of described groove；Described silicon nitride layer is removed from described trenched side-wall；And in the described groove on described inter-electrode dielectric layer, form the second electrode being made of an electrically conducting material, and separated with trenched side-wall by lateral wall insulation lining.
According to a further aspect in the invention, a kind of method forming inter-electrode dielectric layer in providing groove for being formed in semiconductor substrate, including: form the first electrode being made of an electrically conducting material in the bottom of described groove, and separated with trenched side-wall and bottom by the first dielectric liner；Form the thick dielectric materials layer filled described groove and extend on described semiconductor substrate；Described thick dielectric layer is planarized to fully the upper surface of described semiconductor substrate；And perform isotropically wet etching process, make the remainder of described thick dielectric materials layer be recessed into target depth in described groove.
Preferably, the step of described abundant planarization includes performing anisotropic plasma etching process processes.
Preferably, the step of described abundant planarization includes that performing chemical-mechanical planarization processes.
According to a further aspect in the invention, it is provided that a kind of method for forming oxide layer on the semiconductor wafer, including: under the test environment to described semiconductor wafer apply DC bias；The surface with oxide react substantially suppressed under conditions of determine DC bias condition；External bias is applied to described semiconductor wafer during aoxidizing；And utilize described external bias to carry out optimization oxidation rate.
According to a further aspect in the invention, provide a kind of method that channel bottom for being formed in semiconductor substrate forms thick oxide layer, including: form conformal oxide-film by filling the Low-pressure chemical vapor accumulation process of described groove the upper surface that covers described substrate；And in the described upper surface and described groove of described substrate, etch away described oxide-film, to leave the oxide layer of the substantially flat with target thickness at the described bottom of described groove.
Preferably, described method also includes performing Temperature Treatment so that described oxide-film is fine and close.
According to a further aspect in the invention, provide a kind of method that channel bottom for being formed in semiconductor substrate forms thick oxide layer, including: process deposited oxide film by orientation tetraethyl orthosilicate (TEOS), wherein, described TEOS processes and forms thicker oxide-film on the horizontal surface of described bottom including described groove rather than in the vertical surface include trenched side-wall；And it is isotropically etched described oxide-film, until all oxide-films removed on trenched side-wall, and leave oxide layer in the described bottom of the described groove with target thickness.
Preferably, described etching step includes that dry top oxide etches, and is followed by wet buffer oxide etch.
Preferably, described dry top oxide etching include mist etch processes, described mist etch processes with at the rate etch of acceleration compared with the oxide at the described bottom of described groove close to the oxide of the described top of described groove.
According to a further aspect in the invention, provide a kind of method that channel bottom for being formed in semiconductor substrate forms thick oxide layer, including: carry out deposited oxide film by high-density plasma deposition processes, wherein, the oxide layer that described high-density plasma deposition processes is formed at described channel bottom is than the oxidation thickness formed on trenched side-wall；And remove removing oxide layer by wet etching process from trenched side-wall, thus, the section of described groove from groove close to outward-dipping at the top of described groove.
According to a further aspect in the invention, it is provided that a kind of in semiconductor substrate formed channel bottom formed thick oxide layer method, including: form cushion oxide layer on the substrate；Cvd nitride silicon thin layer in described cushion oxide layer；Perform anisotropic etching, to get on silicon nitride layer from horizontal plane, and leave the silicon nitride layer on trenched side-wall；Low-pressure chemical vapor accumulation is used to process deposited oxide layer on the horizontal surface including described channel bottom；And remove the interlayer between oxide layer-nitride layer-oxide layer by etch processes from trenched side-wall.
According to a further aspect in the invention, it is provided that a kind of in semiconductor substrate formed channel bottom formed thick oxide layer method, including: on the substrate including described trenched side-wall and bottom formed liner oxidation thin layer；Form nitride layer at the top of described liner oxidation thin layer, and etch away the nitride layer on horizontal surface, and leave on trenched side-wall the nitration case adjacent to cushion oxide layer；Remove described cushion oxide layer from horizontal surface, expose upper surface and the trench bottom surfaces of described substrate；The horizontal surface that exposed is performed anisotropic etching, to remove semi-conducting material from the described bottom of described groove to the desired degree of depth, thus forms lower trench；In the position growth oxide layer that the nitration case not being included described lower trench covers；And remove described nitride layer and cushion oxide layer, thus, thick bottom oxidization layer extends along the described sidewall of described groove.
According to a further aspect in the invention, it is provided that a kind of power device formed on single semiconductor substrate, including: power transistor, there is charge balance structure, it is formed in groove；Current inductor part, it is formed adjacent to described power transistor, and is separated with described power transistor by insulation layer；And one or more Charge balance trench, it is formed under described current inductor part, wherein, keeps the seriality of charge balance through described semiconductor substrate.
According to a further aspect in the invention, it is provided that a kind of power device formed on single semiconductor substrate, including: power transistor, there is charge balance structure, it is formed in groove；One or more diode structures, it is formed adjacent to described power transistor, and is separated with described power transistor by insulation layer；And one or more Charge balance trench, it is formed under the one or more diode structure, wherein, keeps the seriality of charge balance through described semiconductor substrate.
According to a further aspect in the invention, it is provided that a kind of for forming the method improving power device, including: provide and there is the semiconductor substrate of the first conduction type；Forming the groove extending into described substrate, wherein, the bottom electrode formed in the bottom of described groove is separated with trenched side-wall and bottom by the first dielectric liner；Described bottom electrode is formed inter-electrode dielectric layer；Forming electrode on described inter-electrode dielectric layer in the top of described groove, it is separated with trenched side-wall by the second insulating bushing；The well region with second conduction type contrary with described first conduction type is formed adjacent to described groove；The source area with the first conduction type is formed in described well region；And after forming described well region and source area, silicon is applied to the upper surface of described upper electrode, wherein, described upper electrode includes the gate terminal of described power device, and described silicide reduces the equivalent series resistance of described device.
According to a further aspect in the invention, it is provided that a kind of for forming the method for power device with relatively low equivalent series resistance, including: in multiple parallel grooves, form grid structure；And forming suicide material surface layer, it is basically perpendicular to the plurality of groove and extends, and contacts in the intersection with the plurality of parallel groove.
According to a further aspect in the invention, it is provided that a kind of DC-DC converter circuit, including: high-side switch, it is made up of the dual-gate power transistor with first gate electrode and second gate electrode, source electrode and drain electrode；Low side switch, by having first gate electrode and second gate electrode, the source electrode of described source electrode being connected to described high-side switch and the dual-gate power transistor of drain electrode are made；First drive circuit, is connected to the described first gate electrode of described high-side switch；And second drive circuit, it is connected to the described first gate electrode of described low side switch, wherein, connect the described second gate electrode of described high-side switch and described low side switch to receive the first driving signal and two driving signal respectively, so that the switching speed optimization of each transistor.
Below in conjunction with accompanying drawing, describe these and other aspects of the present invention in detail.
Accompanying drawing explanation
Fig. 1 illustrates the sectional view of a part of exemplary N-shaped groove (trench) power MOSFET；
Fig. 2 A illustrates the exemplary embodiment of double groove power MOSFET；
Fig. 2 B illustrates the exemplary embodiment of planar gate (planargate) MOSFET with source shield groove structure；
Fig. 3 A illustrates a part for the exemplary embodiment of shielded gate trench power MOSFET；
Fig. 3 B illustrates the alternative embodiment of the shielded gate trench power MOSFET of the shielded gate structure combining double groove structures of Fig. 2 A and Fig. 3 A；
Fig. 4 A is the simplification part figure of the exemplary embodiment of bigrid groove power MOSFET；
Fig. 4 B illustrates and combines planar double gate architecture and exemplary power MOSFET of the trench electrode for vertical electric charge control；
The exemplary embodiment of the power MOSFET that bigrid and dhield grid technology are combined in being shown in identical groove by Fig. 4 C；
Fig. 4 D and Fig. 4 E is the sectional view of the alternative embodiment of the power MOSFET with deep body structure (deepbodystructure)；
Fig. 4 F and Fig. 4 G illustrate ditch groove depth body structure in power MOSFET close to gate electrode equipotential line be distributed impact；
Fig. 5 A, Fig. 5 B and Fig. 5 C are the sectional views of the part illustrating exemplary power MOSFET with various vertical electric charge balanced structure；
Fig. 6 illustrates the simplification sectional view of the power MOSFET combining exemplary vertical capacity control structure and shielded gate structure；
Fig. 7 illustrates the simplification sectional view of another power MOSFET combining exemplary vertical capacity control structure and double-grid structure；
Fig. 8 illustrates an example of the dhield grid power MOSFET with vertical electric charge control structure and integrated schottky diode；
Fig. 9 A, Fig. 9 B and Fig. 9 C illustrate the various exemplary embodiments of the power MOSFET with integrated schottky diode；
Fig. 9 D, Fig. 9 E and Fig. 9 F illustrate that the exemplary layout for interspersion Schottky diode unit in the active cell array (activecellarray) of power MOSFET changes；
Figure 10 illustrates the simplification sectional view with the exemplary groove-type power MOSFET burying diode (burieddiode, also known as embedding diode) charge balance structure；
Figure 11 and Figure 12 illustrates respectively by dhield grid and double-grid structure and the exemplary embodiment burying the power MOSFET that diode charge balance is combined；
Figure 13 is the simplification sectional view combining the exemplary planar power MOSFET burying diode charge balance technique and integrated schottky diode；
Figure 14 illustrates the simplification embodiment of exemplary accumulation mode (accumulation-mode) power transistor with the alternating conductive district arranged with current parallel；
Figure 15 is the simplification figure of another accumulation mode device with the trench electrode for electric charge extension；
Figure 16 is the simplification figure of exemplary pair of groove accumulation mode device；
Figure 17 and Figure 18 illustrates other simplification embodiments of the exemplary accumulation mode device of the groove of the filled dielectric material of the outer liner (exteriorliner) with opposite polarity；
Figure 19 is another simplification embodiment using one or more accumulation mode devices burying diode；
Figure 20 is the simplification isometric view of the exemplary accumulation mode transistor including heavy doping opposite polarity district along the surface of silicon；
Figure 21 has the simplified example of super junction (super-junction, also known as super junction) the power MOSFET being alternately opposite doping region in being shown in voltage sustaining layer；
The vertical direction that Figure 22 is shown in voltage sustaining layer has the exemplary embodiment of the super junction power MOSFET on the opposite polarity island that disunity separates；
Figure 23 and Figure 24 is shown respectively the exemplary embodiment of the super junction power MOSFET with bigrid and shielded gate structure；
Figure 25 A illustrates the top view of the active of trench transistor and terminal trenches layout；
Figure 25 B to 25F illustrates the simplified layout diagram of the alternative embodiment of trench termination structure；
Figure 26 A to 26C is the sectional view of exemplary trench termination structure；
Figure 27 illustrates the exemplary means of the terminal trenches with larger radius of curvature；
Figure 28 A to 28D is the sectional view of the termination environment with silicon post (siliconpillar) charge balance structure；
Figure 29 A to 29C is the sectional view of the exemplary embodiment of the supertension device using super junction technology；
Figure 30 A illustrates the example of the EDGE CONTACT (edgecontacting) of trench device；
Figure 30 B to 30F is shown in the exemplary process step of the EDGE CONTACT structure forming trench device；
Figure 31 A is the example of multiple active region contact (activeareacontact) structure burying polysilicon layer (polylayer)；
Figure 31 B to 31M illustrates the exemplary process flow of the active area shielding contact structures for forming groove；
Figure 31 N is the sectional view of the alternative embodiment of active area shielding contact structures；
Figure 32 A and Figure 32 B is the layout of the exemplary trench device with active area shielding contact structures；
Figure 32 C to 32D is intended that the simplified layout diagram of two embodiments touching the groove periphery having in the trench device interrupting groove structure；
Figure 33 A is the alternative embodiment of the plough groove type shielding polysilicon layer in contacting active area；
Figure 33 B to 33M illustrates the example of the technological process of the active area shielding construction for type shown in hookup 33A；
Figure 34 illustrates have sealing coat (spacer) or buffering (potential barrier) layer to reduce the epitaxial layer of extension drift region (epidriftregion) thickness；
Figure 35 illustrates the alternative embodiment of the device with barrier layer；
Figure 36 illustrates to minimize the barrier layer that epitaxy layer thickness is used at deep body-epitaxy junction；
Figure 37 is the simplified example of the trap-drift region knot of the transistor using diffusion barrier layer；
Figure 38 A to 38D illustrates the Simplified flowsheet of the example of the self-Aligned Epitaxial-trap trench device with buried electrodes；
Figure 39 A to 39B illustrates the exemplary process flow that angle trap injects；
Figure 40 A to 40E illustrates the example of self-Aligned Epitaxial trap technique；
Figure 40 R to 40U illustrates the method reducing substrate thickness；
Figure 41 is shown with the chemical technology example as the technological process of last thinning (thinning) step；
Figure 42 A to 42F illustrates the example of the etch process of improvement；
Figure 43 A and Figure 43 B illustrates the embodiment of the groove etching process eliminating beak problem；
Figure 44 A and Figure 44 B illustrates optional etch processes；
Figure 45 A to 45C illustrates and forms the technique of (inter-poly) dielectric layer between the polysilicon layer improved；
Figure 46 A, 46B and 46C illustrate the alternative forming IPD layer；
Figure 47 A and Figure 47 B is the sectional view of the another kind of method forming high-quality polysilicon interlayer dielectric layer；
Figure 48 and Figure 49 A to 49D illustrates other embodiments of the IPD layer for forming improvement；
Figure 50 A illustrates the anisotropic plasma etch process for IPD planarization；
Figure 50 B is shown with the optional IPD method of planarizing of chemical mechanical process；
Figure 51 is the flow chart of the illustrative methods for controlling oxidation rate；
Figure 52 illustrates the improved method forming thick oxide layer for using low pressure chemical vapor deposition to process at channel bottom；
Figure 53 is for using orientation tetraethyl orthosilicate (Tetraethoxyorthsilicate) technique to form the exemplary process diagram of thick oxide layer at channel bottom；
Figure 54 and Figure 55 illustrates another embodiment for forming thick bottom oxidization layer；
Figure 56 to 59 illustrates another technique for forming thick dielectric layer at channel bottom；
Figure 60 is the simplification figure of the MOSFET with current inductor part；
Figure 61 A is the example of the charge balance MOSFET with planar gate and separate current induction structure；
Figure 61 B illustrates example integrated to current inductor part and groove MOSFET；
Figure 62 A to 62C illustrates the alternative embodiment of the MOSFET with serial temperature sense diode；
Figure 63 A and Figure 63 B illustrates the alternative embodiment of the MOSFET with ESD protection；
Figure 64 A to 64D illustrates the example of esd protection circuit；
Figure 65 illustrates the illustrative processes for forming the charge balance power devices with low ESR；
Figure 66 A and Figure 66 B illustrates the topology reducing ESR；
Figure 67 is shown with the DC-DC converter circuit of power switch；
Figure 68 illustrates that another uses the DC-DC converter circuit of power switch；
Figure 69 illustrates the exemplary driver circuits of bigrid MOSFET；
Figure 70 A illustrates the alternative embodiment driving gate electrode with separation；
Figure 70 B illustrates the sequential chart of the circuit operation of explanatory diagram 70A；
Figure 71 is the simplification sectional view of molded package；And
Figure 72 is the simplification sectional view of non-molded package.
Detailed description of the invention
On and off switch can be realized by any one of power MOSFET, IGBT, various types of IGCTs etc..For illustrative purposes, the many new techniques occurred herein are described under conditions of power MOSFET.It should be appreciated, however, that the various embodiments of invention as described herein are not limited to MOSFET, but can apply in many other types of power switch technology, such as, include IGBT, other kinds of double-pole switch, various types of IGCT and diode.Further, for illustrative purposes, it is shown that various embodiments of the present invention include concrete p and n-type area.Those skilled in the art is it should be appreciated that technology herein can be applied equally in the device that the electric conductivity in each district is contrary.
With reference to Fig. 1, it is shown that the partial section view of exemplary N-shaped groove power MOSFET100.Other views as described herein, it is clear that the various elements shown in figure and the relative size of parts and size the most directly reflect actual size, are only for descriptive purpose.The gate electrode that groove MOSFET 100 is formed in being included in groove 102, wherein, groove 102 begins to pass p-type trap from the upper surface of substrate or body region (bodyregion) 104 extends, and terminates in N-shaped drift or epitaxial region 106.Thin dielectric layer 108 is set along groove 102, and groove 102 is filled by conductive material 110 (such as, DOPOS doped polycrystalline silicon) substantially.N-type source district 112 is formed in the body region 104 being adjacent to groove 102.The drain terminal of MOSFET100 is formed on rear side of the substrate being connected to heavy doping n+ substrate zone 114.Structure Fig. 1 shown in is repeated several times, to form transistor array on the common substrate being made up of such as silicon.This array can be configured to various netted (cellular) known in the art or striated structure.When the transistor conducts, between source area 112 and drift region 106, conducting channel is formed along gate trench 102 sidewall.
Due to its vertical gate structure, when compared with planar gate device, MOSFET100 is capable of high packaging density, and higher packaging density can realize relatively low conducting resistance.In order to improve the breakdown voltage property of this transistor, in p-trap 104, form p+ heavy doping body region 118 so that the interface between the trap 104 of the heavily doped body region of p+ 118 and p-forms abrupt junction.The degree of depth by the severity control p+ heavy doping body region 118 relative to gash depth and trap so that the electric field produced when transistor is applied voltage disappears from groove.Which adds the avalanche current disposal ability of transistor.To the change of this improved structure and being described in detail in the U.S. Patent No. 6,429,481 that Mo et al. is total for forming the technique of transistor, especially abrupt junction, entire contents is hereby expressly incorporated by reference.
Although vertical trench MOSFET100 demonstrates the ruggedness of good conducting resistance and improvement, but it has of a relatively high input capacitance.The input capacitance of groove MOSFET 100 includes two parts: gate source capacitance CgsWith gate drain capacitor Cgd.Gate source capacitance CgsProduce by grid conducting material 110 with close to the superposition between the source area 112 at groove top.The electric capacity formed between reverse raceway groove in grid and main body can increase C equallygs, this is because in typical power switch is applied, the main body of transistor is together with source electrode short circuit.Gate drain capacitor CgdProduced by the superposition between grid conducting material 110 and the drift region 106 being connected to drain electrode of each channel bottom.Gate drain capacitor Cgd, or Miller capacitance limit strangle transistor VDSTransit time.Therefore, higher CgsAnd CgdResult in considerable switching loss.These switching losses become increasing along with power management application close to higher switching frequency.
Reduce gate source capacitance CgsA kind of method be reduce transistor channel length.Shorter channel length directly reduces CgsGate-channel component.A short channel length the most just with RDSonProportional, and identical device current amount can be obtained in the case of there is less gate trench.Thus reduce C by reduction gate-to-source and gate-to-drain superposition amount simultaneouslygsAnd Cgd.But, when being deep into body region due to back-biased main body-drain junction and form depletion layer close to source area, shorter channel length makes device fragile and causes break-through (punchthrough).Reduce the doping content of drift region so that maintain broader depletion layer to have increase transistor conduct resistance RDSonLess desirable effect.
Use additional " shielding " groove with gate trench lateral separation that transistor arrangement is improved, not only reduce channel length, and also efficiently solve disadvantages mentioned above.With reference to Fig. 2 A, it is shown that the exemplary embodiment of double groove MOSFETs 200.Term " double groove " refers to the transistor with the two distinct types of groove relative with the sum of similar grooves.In addition to the architectural feature common with the MOSFET100 of Fig. 1, double groove MOSFETs 200 include the shield trenches 220 being interposed between adjacent gate trenches 202.In the exemplary embodiment shown in Fig. 2 A, shield trenches 220 passes p+ district 218 from surface, body region 204 extends into drift region 206, is sufficiently below the degree of depth of gate trench 202.Groove 220 is provided with dielectric material 222, and groove 220 is substantially filled with the conductive material 224 of such as DOPOS doped polycrystalline silicon.Conductive material 224 in groove 220 is electrically connected to n+ source area 212 and heavy doping p+ body region 218 by metal level 216.Therefore, in this embodiment, groove 220 is properly termed as source shield groove.Commonly assigned U.S. Patent Application No. 10/209 at entitled " DualTrenchPowerMOSFET " of StevenSapp, describing the example of such pair of groove MOSFET, manufacturing process and the application of its circuit in No. 110 in detail, entire contents is hereby expressly incorporated by reference.
The impact of deeper source shield groove 220 is so that the depletion layer formed due to back-biased main body-drain junction is more deep in drift region 206.Therefore, wider depletion region is not so that increase electric field.This allows for more heavy doping drift region, and don't can reduce breakdown voltage.More heavily doped drift region reduces the conducting resistance of transistor.Additionally, the electric field reduced near main body-drain junction makes channel length fully reduce, reduce the conducting resistance of transistor further, and fully reduce gate source capacitance Cgs.Additionally, compared with the MOSFET in Fig. 1, double groove MOSFETs make it possible to obtain identical transistor current amount in the case of having less gate trench.So significantly decrease gate-to-source and gate-to-drain overlap capacitance.Noticing, in exemplary embodiment shown in fig. 2, gate trench conductive layer 210 is buried in and eliminates in the groove that interlayer dielectric dome (dome) needs, wherein, above interlayer dielectric dome groove 102 in MOSFET100 shown in Fig. 1.Equally, the use of the source shield groove here as illustrated is not limited to trench gate mosfet, can obtain identical advantage when being horizontally formed in the planar MOSFET of grid on the upper surface of substrate when source shield groove uses.The exemplary embodiment of planar gate MOSFET with source shield groove structure is shown in fig. 2b.
In order to reduce input capacitance further, additional structure improvement can be carried out, it is preferred that emphasis is reduce gate drain capacitor Cgd.As it has been described above, gate drain capacitor CgdIt is to be produced by superposition between grid and the drain region of channel bottom.Reduce the thickness that a kind of method of this electric capacity is to increase the gate dielectric of channel bottom.Referring again to Fig. 2 A, it is shown that with compared with the dielectric layer of gate trench sidewalls, gate trench 202 has thicker dielectric layer 226 there is, with drift region 206 (transistor drain terminal), the channel bottom superposed.Which reduce gate drain capacitor Cgd, the most do not reduce the forward conduction of transistor.Can realize in many ways bottom gate trench, generate thicker dielectric layer.Describing an illustrative processes for generating thicker dielectric layer in the total U.S. Patent No. of Hurst et al. 6,437,386, entire contents is hereby expressly incorporated by reference.Other techniques for forming thick dielectric layer at channel bottom are further described below in conjunction with accompanying drawing 56 to 59.The another kind of method reducing gate drain capacitor is in the second dielectric core (core) centrally disposed in the groove upwardly extending groove of suprabasil dielectric liner.In one embodiment, the second dielectric core can upwardly extend from all directions, with contact trench conductive material 210 dielectric layer above.The example of this embodiment and its change have been described in detail in the total U.S. Patent No. 6,573,560 of Shenoy.
For reducing gate drain capacitor CgdAnother kind of technology be directed to use with one or more bias electrode and carry out dhield grid.According to this embodiment, in gate trench and below the conductive material forming gate electrode, form one or more electrode and grid is come with drift region shielding, thus substantially reduce gate-to-drain overlap capacitance.With reference to Fig. 3 A, it is shown that a part for the exemplary embodiment of shielded gate trench MOSFET300A.In this example, the groove 302 in MOSFET300A includes gate electrode 310 and two supplemantary electrode 311a and 311b below gate electrode 310.Electrode 311a and 311b shield grid electrode 310 so that it is not there is with drift region 306 any substantial superpose, thus almost eliminate gate-to-drain overlap capacitance.Bucking electrode 311a and 311b can be at optimal current potential independent bias.In one embodiment, of bucking electrode 311a with 311b can bias as source terminal at same potential.Similar with double groove structures, the biasing of bucking electrode can aid in equally widens the depletion region formed at main body-drain junction, further reduces Cgd.Should be understood that can be according to switch application, and the voltage request especially applied is to change the number of bucking electrode 311.Similarly, the size of the bucking electrode in given groove can also change.Such as, bucking electrode 311a can be more than bucking electrode 311b.In one embodiment, minimum bucking electrode is closest to channel bottom, and remaining bucking electrode is gradually increased along with moving closer to gate electrode.In groove, the electrode of independent bias can be also used for vertical electric charge control, to improve less forward voltage loss and higher blocking-up (blocking) ability.This aspect of the transistor arrangement further described further in connection with high tension apparatus is also in the commonly assigned U.S. Patent Application No. 09/981 of entitled " SemiconductorStructurewithImprovedSmallerForwardLossandH igherBlockingCapability " of Kocon, being described in detail in No. 583, entire contents is hereby expressly incorporated by reference.
Fig. 3 B illustrates the alternative embodiment of the shielded gate trench MOSFET300B shielded gate structure of the double groove structures in Fig. 2 A and Fig. 3 A combined.In the exemplary embodiment shown in Fig. 3 B, similar with the groove 302 of MOSFET300A, gate trench 301 includes bucking electrode 311 gate electrode 310 above.But, the purpose controlled for vertical electric charge, MOSFET300B includes the non-gate trench 301 that can be deeper than gate trench 302.As shown in Figure 2 A, when charge control trench 301 can have conductive material (such as, the polysilicon) monolayer connecting source metal at groove top, what embodiment in Fig. 3 B used multiple stackings can be with the polysilicon electrode 313 of independent bias.The number of the electrode 313 stacked in the trench can change according to application needs, it is also possible to for the size of the electrode 313 shown in Fig. 3 B.Electrode can be with independent bias or be electrically connected together.The number of the charge control trench in device is similarly dependent on this application.
For improving the another technology of power mosfet switch speed by using double-grid structure to reduce gate drain capacitor Cgd.According to this embodiment, the grid structure in groove is divided into two parts: Part I is for performing to receive the conventional gate function of switching signal, and first grid part is come by Part II with the shielding of drift (drain electrode) district, and can independent bias.Thus significantly decrease the gate drain capacitor of MOSFET.Fig. 4 A is the simplification part figure of the exemplary embodiment of bigrid groove MOSFET 400A.As shown in Figure 4 A, the grid of MOSFET400A has two parts G1 and G2.The bucking electrode (311a and 311b) being different from the MOSFET300A of Fig. 3 A, forms the conductive material of G2 in MOSFET400A and has the district 401 with ditch trace-stacking, accordingly act as gate terminal.But, this time gate terminal G2 biases independent of main gate terminal G1, and does not receive the identical signal driving switching transistor.On the contrary, in an embodiment example, G2 is at the constant potential upper offset of merely greater than MOSFET threshold voltage, to invert the raceway groove in superposition district 401.This will assure that and form continuous raceway groove when being transformed into main grid pole G1 from secondary grid G 2.Additionally, because the current potential at G2 is higher than source potential, so reducing Cgd, and from drift region to secondary grid G 2 electric charge shift also contribute to reduce Cgd.In another embodiment, replacing constant potential, secondary grid G 2 can be biased to the current potential higher than starting voltage only before switch motion.In other embodiments, the current potential at G2 can be changed and carry out optimal adjustment, with by gate drain capacitor CgdAny marginal portion minimize.Double-grid structure can use in having the MOSFET of planar gate and including the other kinds of trench-gate power devices of IGBT etc..To the change of bigrid groove MOS gated device with for manufacturing the technique commonly assigned U.S. Patent Application No. 10/640 at entitled " the ImprovedMOSGatingMethodforReducedMillerCapacitanceandSwi tchingLosses " of Kocon et al. of such device, being described in detail in No. 742, entire contents is hereby expressly incorporated by reference.
Showing another embodiment of the power MOSFET of improvement in figure 4b, wherein, exemplary MOSFET400B combines planar gate and the bucking electrode controlled for vertical electric charge.Main gate terminal G1 and time gate terminal G2 effect in the way of similar with the groove double-grid structure of Fig. 4 A, deep trench 420 arranges electrode in drift region, to extend electric charge and to increase the breakdown voltage of device.In the illustrated embodiment, shielding or secondary grid G 2 are superimposed with the top of main grid pole G1, and extend on p trap 404 and drift region 406.In an alternative embodiment, main grid pole G1 extends on shielding/time grid G 2.
Can be in conjunction with various technology described so far, such as grid cover and the trench electrode for vertical electric charge control, to obtain power device optimized for given performance characteristics (including laterally and vertically MOSFET, IGBT, diode etc.).Such as, the groove double-grid structure shown in Fig. 4 A can combine with the vertical electric charge control groove structure of type shown in Fig. 3 B or 4B easily.Such device includes the active groove with double-grid structure as shown in Figure 4 A, and the deeper charge control trench substantially filled by the conductive electrode (groove 301 as in Fig. 3 B) of conductive material monolayer (groove as in Fig. 4 B) or multiple stacking.The transversal device (that is, electric current horizontal mobility) being positioned at as source terminal in the similar face of substrate for drain terminal, replaces stacking in vertical trench, and charge control electrode horizontally set forms field plate (fieldplate).The orientation of charge control electrode is typically parallel with the direction of electric current flowing in drift region.
In one embodiment, in identical groove, combine bigrid and dhield grid technology, to increase switching speed and blocking voltage.Fig. 4 C illustrates MOSFET400C, and wherein, groove 402C is included in shown single groove main grid pole G1, secondary grid G 2 and the screen layer 411 of stacking.It is the deepest that groove 402C can do, it is possible to includes requiring as many screen layer 411 with application.The same trench for charge balance and bucking electrode is used to be capable of higher density, because which eliminating the needs of two grooves and being bonded to be one.It can also realize more current expansion, and improves the conducting resistance of device.
So far described device uses the combination of dhield grid, bigrid and other technologies to reduce parasitic capacitance.But, due to edge effect, these technology can not be completely by gate drain capacitor CgdMinimize.With reference to Fig. 4 D, it is shown that have the partial section view of the exemplary embodiment of the MOSFET400D of deep body design.According to this embodiment, main body (body) structure is formed by groove 418, wherein, groove 418 is etched by table top (mesa) center formed between gate trench 402, and extends to position that is deep as gate trench 402 or that be deeper than gate trench 402.Active trench 418 fills shown source metal.Source metal can include thin refractory metal on the (not shown) of metal diffusion term face.In this embodiment, agent structure also includes that the basic p+ main body around active trench 418 injects knot 419.P+ injects knot and 419 makes to realize additional mask, to change in device the Potential distribution especially close to gate electrode.In the alternative embodiment shown in Fig. 4 E, such as, active trench 418 uses such as selective epitaxy growth (SEG) deposition to be substantially filled with epitaxial material.Alternatively, active trench 418 is substantially filled with DOPOS doped polycrystalline silicon.In any one of the two embodiment, replace injecting p+ and shield knot 419, but by alloy from the main diffusion filled to silicon in Temperature Treatment subsequently, to form p+ shielding knot 419.Describing many changes for groove agent structure and formation in the commonly assigned U.S. Patent No. 6,437, No. 399 and the 6th, 110, No. 799 of Huang, entire contents is hereby expressly incorporated by reference.
In embodiment shown in Fig. 4 D and 4E, distance L between control gate groove 402 and active trench 418 and the relative depth of two grooves, to minimize edge gate-capacitance of drain.In using the embodiment of active trench of SEG or filling polysilicon, the interval between outward flange and the gate trench wall of layer 419 can be regulated by the doping content of polysilicon in change SEG or active trench 418.Fig. 4 F and 4G illustrate ditch groove depth body in device close to gate electrode equipotential line be distributed impact.For illustrative purposes, Fig. 4 F and 4G uses the MOSFET with shielded gate structure.Fig. 4 F illustrates the equipotential line of the back-biased dhield grid MOSFET400F with ditch groove depth body 418, and Fig. 4 G illustrates the equipotential line of the back-biased dhield grid MOSFET400G with shallow body structure.When reverse biased (such as, blocking state (blockingoff-state)), the equal pitch contour in each device illustrates the Potential distribution in device.White line illustrates that trap is tied, and also defines the bottom of the raceway groove being next to gate electrode.It can be seen that have relatively low current potential and relatively low electric field to be arranged on raceway groove and around the gate electrode of the ditch groove depth body MOSFET400F of Fig. 4 F.This current potential reduced can reduce channel length, thus reduces the gate charge that device is total.Such as, the degree of depth of gate trench 402 can decrease below such as 0.5um, and can accomplish to be shallower than active trench 418, and spacing L is about 0.5um or less.In one exemplary embodiment, spacing L is less than 0.3um.Other advantages of this embodiment are to reduce gate-drain charge QgdWith Miller capacitance Cgd.The value of these parameters is the lowest, and the speed that device can be changed is the fastest.Occurred in by reduction and be next to the current potential of gate electrode and realize these and improve.The structure improved has the lowest current potential that will be changed, and the faradism capacity current in grid is the lowest.Make the most again gate switch faster.
The ditch groove depth body structure described in conjunction with Fig. 4 D and 4E can combine with other charge balance techniques (such as, dhield grid or double-grid structure), improves the switching speed of device, conducting resistance and blocking ability further.
Improved and change the generation reinforcement switch element for the power electronics applications of relatively low voltage by what above-mentioned power device provided.Low-voltage used herein refers to such as, about 30 volts of-40 volts and following voltage range, can according to specifically should be used for change this scope.Require that the application of blocking voltage, substantially on this scope, needs power transistor is carried out some type of structural modification.In general, in order to make device maintain higher voltage during blocking state it is necessary to the doping content reduced in power transistor drift region.But, lightly doped drift region can cause transistor conduct resistance RDSonIncrease.Higher resistivity directly increases the power loss of switch.Along with the new development of the semiconductor manufacturing reducing power device package density further, power loss just becomes more important.
Carry out conducting resistance and the power loss attempting improving device, keep high blocking voltage simultaneously.Many this trials use various vertical electric charges to control technology, produce big plane electric fields with vertical in the semiconductor device.Have been proposed that many such device architectures, it is included in the total U.S. Patent No. 6 of entitled " FieldEffectTransistorHavingaLateralDepletionStructure " of Marchant, 713, the having lateral depletion device disclosed in No. 813, this device is in the total U.S. Patent Application No. 6 of Kocon, being described in 376, No. 878, entire contents is hereby expressly incorporated by reference.
Fig. 5 A illustrates the partial section view of exemplary power MOSFET500A with planar gate.MOSFET500A seems have the structure similar to the plane MOSFET200B of Fig. 2 B, but different from that device at two important aspects.Replacement conductive material fills groove 520, the dielectric material of these trench fill material such as silicon dioxide, and this device also includes the discontinuous floating p-type area 524 separated adjacent to the lateral wall of groove.As described in the double groove MOSFETs combining Fig. 2 A, the conductive material (such as, polysilicon) in source electrode groove 202 helps improve unit breakdown voltage by making depletion region go deep into drift region.From these grooves, remove conductive material will therefore cause reducing breakdown voltage, until using the additive method reducing electric field.Floating region 524 is used for reducing electric field.
With reference to the MOSFET500A shown in Fig. 5 A, owing to when increasing drain voltage, electric field increases so that floating p district 524 obtains the corresponding current potential determined by them at space charge region.The floating potential in these p districts 524 makes electric field more be deep in drift region, causes more uniform field degree of depth of table section between groove 520.As a result, the breakdown voltage of transistor is added.Stride across insulator by the more parts that the advantage of the conductive material in insulant replacement groove is space-charge region and be not probably the drift region of silicon.Because the dielectric constant of insulator is less than the dielectric constant of such as silicon, and because the depletion region in groove reduces, so the fan-out capability of device is substantially reduced.This further enhances the switching characteristic of transistor.The degree of depth of the groove 520 of filled dielectric material depends on voltage request；Groove is the deepest, and blocking voltage is the highest.Vertical electric charge control more advantages of technology be allow transistor unit for heat insulation horizontally set, without increasing electric capacity.In an alternative embodiment, replacing floating p district, the lateral wall along the groove of filled dielectric material arranges p-type layer, to realize similar vertical electric charge balance.Illustrating the partial section view of the simplification of this embodiment in figure 5b, wherein, the lateral wall of groove 520 is covered by p-type layer or lining 526.In figure 5b in exemplary embodiment, grid is the most trench, further improves the mutual conductance of device.Use this technology change improve power device other embodiments Sapp et al. entitled " VerticalChangeControlSemiconductorDevicewithLowOutputCap acitance; " commonly assigned U.S. Patent Application No. 10/200, being described in detail in detail in No. 056 (acting on behalf of Reference Number 18865-0097/17732-55280), entire contents is hereby expressly incorporated by reference.
As it has been described above, the groove MOSFET 500B of Fig. 5 B demonstrates the output capacitance of reduction and the breakdown voltage of improvement.But, because active groove (gate trench 502) is between the charge control trench 520 of filled dielectric material, the channel width of MOSFET500B can not be wide as the channel width of conventional groove MOSFET structure.So may cause higher conducting resistance RDSon.With reference to Fig. 5 C, it is shown that have the alternative embodiment of the groove MOSFET 500C of the vertical electric charge control eliminating time charge control trench.Groove 502C in MOSFET500C includes gate electrode 510 and the bottom of the filled dielectric material extending deep into drift region 506.In one embodiment, groove 502C extends to the degree of depth of about drift region 506 degree of depth half.As it can be seen, p-type lining 526C is wound on around outer wall along the lower loop of each groove.This single groove structure eliminates time charge control trench, is used for increasing channel width and reducing RDSon.In order to reduce output capacitance and gate drain capacitor, maintained the major part of electric field at groove outer wall by the bottom of the deeper groove 502C of p-type lining 526C cincture.In an alternative embodiment, side and bottom p-type lining 526C along groove 502C are made into multiple locus of discontinuity.It is capable of other embodiments, to reduce the parasitic capacitance of device further by combining single groove Charge controlled and above-mentioned dhield grid or dual-gate technologies.
With reference to Fig. 6, it is shown that be suitable for the simplification sectional view that high-voltage applications also requires the power MOSFET600 of very fast switching speed.MOSFET600 combines the vertical electric charge control technology improving breakdown voltage and the shielded gate structure improving switching speed.As shown in Figure 6, between the bucking electrode 611 grid conducting material 610 and channel bottom in gate trench 602.The grid of transistor is come by electrode 611 with the shielding of following drain region (drift region 606) so that significantly reduce the gate drain capacitor of transistor, therefore adds its maximum switching frequency.The groove 620 of the filled dielectric material with p doping lining 626 contributes to vertically producing big plane electric fields, to improve the breakdown voltage of device.Operationally, the groove 620 of filled dielectric material and the combination of p-type lining 626 and shielded gate structure reduce parasitic capacitance, and contribute to exhausting n drift, are disperseed by the electric field focusing on gate electrode marginal portion.Such device may be used for RF amplifier or HF switch application.
Fig. 7 is shown suitable for the alternative embodiment of another power MOSFET of high voltage, upper frequency application.In the simplified example shown in Fig. 7, MOSFET700 combines the vertical electric charge control technology improving breakdown voltage and the double-grid structure improving switching speed.Similar with the device shown in Fig. 6, the groove 720 of filled dielectric material by use with p doping lining 726 realizes vertical electric charge control.By using double-grid structure to realize the reduction of parasitic capacitance, from there through secondary gate electrode G2, primary gate electrode G1 is come with drain electrode (n drift 706) shielding.In order to when break-over of device, the raceway groove being reversed in district 701 guarantees the continuous flowing of the electric current through continuous raceway groove, secondary gate electrode G2 can persistently bias or only bias before switch motion.
In another embodiment, shielding vertical electric charge controls MOSFET and also using the trenched side-wall of filled dielectric material of doping to realize integrated Schottky diode.Fig. 8 shows an example of the dhield grid MOSFET800 according to this embodiment.In this example, gate electrode 810 is come, to reduce gate-drain parasitic electric capacity by the electrode 811 bottom groove 802 with drift region 806 shielding.Lateral wall has the groove 820 of filled dielectric material of p doping lining for vertical electric charge control.Schottky diode 828 is formed between two groove 820A and 820B of mesa structure of width W being formed.This Schottky diode structure spreads all over trench MOSFET cell array, to strengthen the Performance Characteristics of switch mosfet.Forward voltage drop is reduced by the advantage utilizing the low barrier height of Schottky junction structure 828.Additionally, compared with the common PN junction of vertical power MOSFET, the advantage that this diode has intrinsic Reverse recovery speed.By by the wall doping such as boron of the groove 820 of filled dielectric material, eliminating the sidewall leakage passage produced due to phosphorous segregation (phosphorussegregation).The feature that can use trench process carrys out the performance of optimization Schottky diode 828.Such as, in one embodiment, adjustment width w so that the loss being affected by adjacent PN junction and being controlled in the drift region of Schottky diode 828, to increase the reversal voltage ability of Schottky diode 828.Can find the example of single chip integrated groove MOSFET and Schottky diode in the commonly assigned U.S. Patent No. 6,351,018 of Sapp, entire contents is hereby expressly incorporated by reference.
Should be understood that, the Schottky diode formed between the groove of filled dielectric material can carry out integrated with various types of MOSFET, including having the MOSFET of planar gate, at channel bottom with or without the trench-gate MOSFET etc. not having any bucking electrode of thick dielectric substance.Show the exemplary embodiment of the bigrid groove MOSFET with integrated schottky diode in figure 9 a.MOSFET900A includes gate trench 902, wherein, main grid pole G1 formation on secondary grid G 2, to reduce parasitic capacitance and to increase switching frequency.MOSFET900A also includes the groove 920 of filled dielectric material, and wherein, groove 920 has the p doping lining 926 controlled for vertical electric charge formed along its lateral wall, to increase the blocking voltage of device.For the embodiment (such as, shown in Fig. 5 B, 6,7,8 and 9A) of above-mentioned many, a kind of method forming lining is to use plasma doping technique.As it can be seen, form Schottky diode 928A between groove 920A and 920B of two adjacent filled dielectric materials.In another variation instance, form single chip integrated Schottky diode and groove MOSFET, and there is no the groove of filled dielectric material.Fig. 9 B is the sectional view of exemplary means 900B according to this embodiment.
MOSFET900B includes active groove 902B, and each has the electrode 911 buried for 910 times at gate electrode.As it can be seen, form Schottky diode 928B between two groove 902L and 902R.The charge balance effect of bias electrode 911 makes to add the doping content of drift region, and does not affect reverse BV.For this structure, the doping content of higher drift region reduces again forward voltage drop.As the aforementioned groove MOSFET with buried electrodes, the degree of depth of each groove and the number of buried electrodes can change.In shown in Fig. 9 C a variation instance, as it can be seen, groove 902C only has a buried electrodes 911, and the gate electrode 910S in schottky cell 928C is connected to source electrode.Alternatively, the grid of Schottky diode may be coupled to the gate terminal of MOSFET.Fig. 9 D, 9E and 9F show the change of the exemplary layout of the Schottky diode in the active cell array being dispersed in MOSFET.Fig. 9 D and 9E respectively illustrates single table surface Schottky and the layout of dual stage face Schottky, and Fig. 9 F shows the layout of schottky region and MOSFET groove vertical.These and other changes (including the Schottky of optional multiple MOSFET region) of integrated schottky diode can combine with any transistor arrangement as herein described.
In another embodiment, by voltage blocking capability that use one or more series connection, that diode structure that be buried in being provided with the groove of dielectric material and arrange with the current parallel in device drift region strengthens power device.Figure 10 provides the simplification sectional view of the exemplary groove MOSFET 1000 according to this embodiment.Diode groove 1020 is arranged on the both sides of gate trench 1002, extends into drift region 1006 from trap.Diode groove 1020 includes one or more diode structure being made up of opposite conductivity type district 1023 and 1025, and wherein, conductivity type district 1023 and 1025 defines one or more PN junction in groove.In one embodiment, groove 1020 includes having single district opposite polarity with drift region so that forming single PN junction on the interface of drift region.P-type and N-shaped DOPOS doped polycrystalline silicon or silicon may be respectively used for forming district 1023 and 1025.Other kinds of material (such as, carborundum, GaAs, SiGe etc.) can be used for forming district 1023 and 1025.Diode in groove and drift region 1006 are insulated by the thin dielectric layer 1021 extended along the medial wall of groove.As it can be seen, the bottom along groove 1020 does not has dielectric layer, therefore, it is allowed to bottom zone 1027 makes electrical contact with substrate below.In one embodiment, those control gate oxide layers 1008 are designed in the design and the formation that are applied to dielectric layer 1021 with the similar Consideration manufactured.Such as, the thickness of dielectric layer 1021 by such because usually determining, i.e. its need the voltage kept and in drift region the degree (degree e.g., coupled by dielectric layer) of diode groove internal electric field of sensing.
Operationally, when MOSFET1000 is in its blocking state below-center offset, the PN junction in diode groove utilizes the peak electric field reverse bias produced at each diode junction.By dielectric layer 1021, the respective electric field in electric field induction drift region 1006 in diode groove.The electric field sensed occurs in drift region with the form rising spike (up-swingspike), and general increase in the electrical bending of drift region.The increase of this electric field causes the electrical bending in Geng great district, causes again higher breakdown voltage.The change of this embodiment is in the commonly assigned U.S. Patent Application No. 10/288 of entitled " the DriftRegionHigherBlockingLowerForwardVoltageDropSemicond uctorStructure " of Kocon et al., being described in detail in No. 982 (acting on behalf of Reference Number 18865-117/17732-66560), entire contents is hereby expressly incorporated by reference.
Can there be other embodiments of the power device technology (such as, dhield grid or double-grid structure) of the trench diode and reduction parasitic capacitance that are used for charge balance combined.Figure 11 shows an example according to a MOSFET1100 that example is implemented.MOSFET1100 uses bucking electrode 1111 under gate electrode 1110 in active groove 1102, with reduce to such as the gate drain capacitor C of relevant for the MOSFET300A transistor in Fig. 3 Agd.Compared with MOSFET1000, MOSFET1100 employs different number of PN junction.Figure 12 is combined with the sectional view of the MOSFET1200 of dual-gate technologies and trench diode structure.Active groove 1202 in MOSFET1200 includes main grid pole G1 and time grid G 2, and works in the way of identical with the active groove in the bigrid MOSFET that Fig. 4 B describes.Diode groove 1220 provides charge balance, and to increase the blocking voltage of device, and bigrid active groove structure improves the switching speed of device.
Figure 13 shows the another embodiment being combined by trench diode charge balance technique in planar gate MOSFET1300 with integrated schottky diode.Similar advantage can be obtained with the MOSFET combined described in Fig. 8 and 9 by integrated schottky diode 1328.In this embodiment, for illustrative purposes, show planar gate, those skilled in the art should be understood that in the MOSFET of grid structure (including trench-gate, bigrid and dhield grid) that the combination of Schottky diode and trench diode structure can apply to have any other type.As combined the description of MOSFET400D and 400E of Fig. 4 D and Fig. 4 E, any one synthetic example can also combine with groove agent technology, to reduce edge parasitic capacitance further.Can also there be other changes and equivalent.Such as, the number in the opposite conductivity district in diode groove can change along with the degree of depth of diode groove.The polarity in opposite conductivity district can invert along with the polarity of MOSFET.Additionally, if it is desire to by such as each district being extended along the third dimension, until the silicon face that makes electrical contact with can be carried out with them, then any PN district (923,925 or 1023,1025 etc.) all can be with independent bias.Further, multiple diode grooves can serve as the requirement needed by the voltage of device size and application, and the interval of diode groove and configuration can realize with various stripeds or mesh design.
In another embodiment, it is assumed that accumulation mode transistor-like uses various for reducing forward voltage loss and improving the charge balance technique of blocking ability.In general accumulation mode transistor, do not block knot, and carry out pinch-off current by slight reversion near the channel region of gate terminal and make device end.When by application grid bias conducting transistor, form accumulation layer rather than inversion layer at channel region.Owing to being formed without inversion channel, so that channel resistance is minimum.Additionally, there is no PN body diode in accumulation mode transistor so that the loss otherwise produced in particular electrical circuit application (such as, synchronous rectifier) is minimum.It is lightly doped, to provide reverse bias when device is at blocking mode that the shortcoming of tradition accumulation mode device is that drift region has to carry out.More lightly doped drift region causes higher conducting resistance.Embodiment described herein limits by using various charge balance technique to overcome this in accumulation mode device.
With reference to Figure 14, it is shown that have the simplification embodiment of the exemplary accumulation mode transistor 1400 in the alternating conductive district arranged with current parallel.In this embodiment, transistor 1400 is n-channel transistor, including: the gate terminal formed in groove 1402, the n-type channel district 1412, the column N-shaped including opposite polarity and the drift region 1406 of p-type part 1403 and 1405 that are formed between groove and n-type drain district 1414.Being different from enhancement transistor, accumulation mode transistor 1400 does not include blocking (in this example for p-type) trap or the body region of raceway groove formed therein that.On the contrary, form conducting channel when forming accumulation layer in district 1412.The doping type of doping content and gate electrode that transistor 1400 is typically based on district 1412 turn on or by.When n-type area 1412 is completely depleted and slightly inverts, transistor by.The doping content in the district 1403 and 1405 of regulation opposite polarity, to maximize electric charge extension, it is possible to makes the voltage that transistor maintenance is higher.By not allowing the knot away from being formed between district 1412 and 1406 to reduce electric field linearly, the columnar phase reversed polarity district with current parallel is utilized to make Electric Field Distribution become mild.The electric charge expansion effect of this structure allows to use the more heavily doped drift region reducing transistor conduct resistance.The doping content in each district can change, and such as, n-type area 1412 and 1403 can have identical or different doping content.Those skilled in the art is it should be appreciated that the p-channel transistor of improvement can be obtained by the polarity in the various districts of device shown in reversion Figure 14.Other changes later in association with the columnar phase reversed polarity district in supertension device detailed description drift region.
Figure 15 is the simplification figure of another accumulation mode device 1500 with the trench electrode for electric charge extension.All districts 1512,1506 and 1514 have identical conduction type (in this example for N-shaped).For general disconnection device (offdevice), grid polycrystalline silicon 1510 makes p-type.The doping content of regulatory region 1512, to form the blocking-up knot exhausted under not having bias condition.In each groove 1502, under gate electrode 1510, form one or more buried electrodes 1511, by dielectric material 1508 cincture.As described in combine enhancement mode MOSFET300A of Fig. 3 A, buried electrodes 1511 is as field plate, and if necessary, it is possible to be biased to make its optimized current potential of electric charge expanded function.Extend owing to electric charge can be controlled by independent bias buried electrodes 1511, it is possible to increase maximum field significantly.Similar to the buried electrodes used in MOSFET300A, it is possible to achieve the different changes of structure.For example, it is possible to according to applying the degree of depth and the size of buried electrodes and number changing groove 1502.In the way of the groove structure of the MOSFET300B shown in Fig. 3 B is identical, electric charge diffusion electrode can be buried in the groove that the active groove with covering transistor gate electrode separates.Figure 16 shows the example of such embodiment.In the example shown in Figure 16, n-type area 1612 includes the heavy doping n+ source area 1603 that can increase with selectivity.As it can be seen, heavy-doped source polar region 1603 can extend along the top edge of n-type area 1612, or the Liang Ge district (not shown) adjacent to trench wall can be formed as along the top edge of n-type area 1612.In certain embodiments, can suitably block in order to ensure transistor, the alloy in n+ district 1603 can be necessarily less than the doping content of n-type area 1606.This is during selectively heavy-doped source polar region can be used in any one accumulation transistor described herein in an identical manner.
Another embodiment of the accumulation mode transistor improved uses the groove of the filled dielectric material with opposite polarity outer liner.Figure 17 is the simplification sectional view of the accumulation transistor 1700 according to this embodiment.The groove 1720 of filled dielectric material extends downwardly into drift region 1706 from silicon trap surface.Groove 1720 is substantially filled with the dielectric material of such as silicon dioxide.In the exemplified embodiment, transistor 1700 is the n-channel transistor with trench gate structure.As it can be seen, p-type area 1726 is along the outer wall of the groove 1720 of filled dielectric material.Similar with transistor 500A, 500B and 500C of the enhancement mode described respectively in connection with Fig. 5 A, 5B and 5C, groove 1720 reduces the output capacitance of transistor, and p-type lining 1726 provides the charge balance in drift region, to increase the blocking ability of transistor.In the alternative embodiment shown in Figure 18, lining 1826N and 1826P of phase contra-doping is formed at the opposite side of the groove 1820 of filled dielectric material.It is, the groove 1820 of filled dielectric material have along side lateral wall extend p-type lining 1826P, and along same trench opposite side lateral wall extend N-shaped lining 1826N.As combined the description of corresponding enhancement transistor, it is possibility to have have the various changes of the groove contact of accumulation transistor AND gate filled dielectric material.Such as, this includes: device as shown in Figure 5A, has the accumulation transistor of the floating p-type area of plane (as relative with groove) grid structure and replacement p-type lining 1726；Device as shown in Figure 5 B, has and only covers lateral wall and be not covered with the accumulation transistor bottom groove 1726；And device as shown in Figure 5 C, there is the accumulation transistor etc. of the single groove structure of the p-type lining of covering groove bottom.
In another embodiment, accumulation mode transistor uses one or more diode formed of connecting in groove for charge balance.Figure 19 shows the simplification sectional view of the exemplary accumulation mode transistor 1900 according to this embodiment.Diode groove 1920 is arranged on every side of gate trench 1902, extends into drift region 1906 from trap.Gate trench 1902 includes one or more diode structure, and wherein, diode structure is made up of the district 1923 and 1925 of the opposite conductivity type forming one or more PN junction in groove.P-type and N-shaped DOPOS doped polycrystalline silicon or silicon may be used for forming district 1923 and 1925.The thin dielectric layer 1920 extended along the inwall of groove makes the diode in groove and drift region 1906 insulate.As it can be seen, the bottom along groove 1920 does not has dielectric layer, bottom zone 1927 is therefore allowed to make electrical contact with substrate below.Being combined in the description of the corresponding enhancement transistor as shown in Figure 10,11,12 and 13, can there be this other changes accumulation transistor and trench diode combined.
An any of the above described accumulation mode transistor can use heavy doping reversed polarity district in top (source electrode) district.Figure 20 shows the simplification graphics of the exemplary accumulation mode transistor 2000 that this feature combines with other changes.In this embodiment, the charge balance diode in accumulation mode transistor 2000 and grid are formed in identical groove.Groove 2000 includes gate electrode 2010, is presented herein below and forms the N-shaped 2023 of PN junction and p-type 2025 silicon or polysilicon layer.Diode structure is separated by thin dielectric layer 2008 with gate terminal 2002 and drift region 2006.As it can be seen, form heavy doping p+ district 2118 in the interval of the land length formed between the groove in source area 2012.Heavy doping p+ district 2118 reduces the area in n-district 2012, and reduces the leakage of device.The hole current that p+ district 2118 also allows for improving in snowslide contacts with the p+ improving device robustness.Discuss the change to exemplary vertical mos gate pole accumulation transistor, so that the various feature and advantage of this kind of device to be described.Those skilled in the art is it should be appreciated that these can also realize in the other kinds of device including lateral MOS gridistor, diode, bipolar transistor etc..Electric charge expansion electrode can be formed in the groove identical with grid or in the groove separated.Above-mentioned various exemplary accumulation mode transistor has the groove terminated in drift region, but they can also terminate in the heavy doping substrate being connected to drain electrode.Various transistors can be to include that hexagon or the striped of foursquare transistor unit or network structure are formed.Being possible in conjunction with other changes described in some other embodiments and combination, be described further in the U.S. Patent Application No. of some of them previously reference 60/506, No. 194 and the 60/588th, No. 845, entire contents is hereby expressly incorporated by reference.
The another kind of device for power switching designed for extra-high pressure application (such as, 500V-600V and more than) uses the p doping in the epitaxial region between substrate and trap and n doped silicon alternating orthogonal part.With reference to Figure 21, it is shown that use an example of the MOSFET2100 of this kinds of structures.In MOSFET2100, district 2102 sometimes referred to as voltage maintains or blocks district, including n-type area 2104 alternately and p-type area 2106.The effect of this structure is: when device is applied voltage, depletion region is flatly diffused into every side in district 2104 and 2106.The whole vertical thickness of barrier layer 2102 exhausted before horizontal component of electric field sufficiently high generation avalanche breakdown, because the electric charge net quantity in each vertical area 2104,2106 is less than the quantity produced needed for breakdown electric field.After this district is the most completely depleted, continue vertically to set up electric field, until it reaches the snowslide electric field of every micron about 20 to 30 volts.Thus significantly enhance the voltage blocking capability of device, the voltage range of device is expanded to 400 volts or more than.The different changes of such super-junction device are described in detail in the total patent the 6th, 081, No. 009 and the 6th, 066, No. 878 of Nielson, and entire contents is hereby expressly incorporated by reference.
Change to super junction MOSFET2100 uses floating p-type island in N-shaped blocks district.The use on floating p-type island is contrary with column method, reduces R by reducing the thickness of charge balance layersDSon.In one embodiment, replacing being uniformly splitting p-type island, they are separated from one another, in order to maintain the electric field close to critical electric field.Figure 22 is the simplification sectional view of the MOSFET2200 of the example illustrating the device according to this embodiment.In this example, deeper floating p district 2226 is farther with what above separated.It is, distance L3 is more than distance L2, and distance L2 is more than distance L1.By processing the distance between floating knot by this way, minority carrier enters in more short grained mode.The source electrode granule of these carriers is the least, more can realize lower RDSonWith higher breakdown voltage.Those skilled in the art is it should be appreciated that may be made that many changes.Such as, the unlimited number of floating region 2226 in vertical direction is in four shown in figure, and optimal number can change.Additionally, the doping content of each floating region 2226 can also change, such as, in one embodiment, the doping content of each floating region 2226 is gradually reduced close to the degree of substrate 2114 along with district.
Further, as combined described by low-voltage and middle voltage devices, including dhield grid and double-grid structure many for reduce parasitic capacitance to increase switching speed technology can with Figure 21 and 22 described in high tension apparatus and its change be combined.Figure 23 is combined with the change of super-junction structures and the simplification sectional view of the high-voltage MOSFET 2300 of double-grid structure.MOSFET2300 has the planar double gate architecture being made up of gate terminal G1 and G2 being similar to the double gate transistor shown in such as Fig. 4 B.Opposite polarity (for p-type in this example) district 2326 is vertically set in p trap 2308 N-shaped drift region 2306 below.In this example, the size of p-type area 2326 and interval are different, thus as it can be seen, the district 2326 being positioned proximate to trap 2308 contacts with each other, and district 2326 that setting is more on the lower is floating and size is the least.Figure 24 shows the another embodiment for high-voltage MOSFET 2400 of combining super knot technology and shielded gate structure.MOSFET2400 is trench-gate device, has the gate electrode 2410 and bucking electrode 2411 come with drift region 2406 shielding, such as, similar with the MOSFET300A in Fig. 3 A.In MOSFET2400 also includes being arranged on drift region 2406 and the floating region 2426 of opposite polarity of current parallel.
Terminal structure
Above-mentioned various types of discrete device has the cylinder by the depletion region at die edge or the breakdown voltage of spherical form restriction.Owing to such cylinder or spherical breakdown voltage are general all than the parallel plane breakdown voltage BV in device active regionPPMuch lower, so needing to terminate the edge of device, in order to reach the device electric breakdown strength close to active area breakdown voltage.Have been developed for different technology to expand and be unified in the electric field on edge termination width and voltage, to realize close to BVPPBreakdown voltage.These technology include the different combinations of field plate, field ring, knot termination extension (JTE) and these technology.The example including that there is the field terminal structure of the deep knot (being deeper than trap) of the superimposed field oxide layer being looped around around active cell array is described in the total U.S. Patent No. 6,429,481 of Mo et al..Such as, in the case of the n-channel transistor, terminal structure includes forming the PN junction Shen p+ district with N-shaped drift region.
In an alternative embodiment, the one or more ring-shaped grooves being looped around around cell array periphery are for weakening electric field and increasing avalanche breakdown.Figure 25 shows the commonly used trench layouts's figure for trench transistor.Active groove 2502 is by ring terminal groove 2503 cincture.In the structure shown here, faster than what other districts exhausted by the district 2506 shown in imaginary circle shape at table top end, the electric-field enhancing in Shi Gai district so that reduce breakdown voltage under conditions of reverse bias.Therefore, such design is restricted to relatively low voltage devices (e.g., ＜ 30V).Figure 25 B to Figure 25 F illustrates the several alternative embodiments having the trench layouts different from shown in Figure 25 A to reduce the terminal structure of high electric field region.It can be seen that in these embodiments, some or all active grooves separate with terminal trenches.Gap W between active groove end and terminal trenchesGThe electric field set effect observed in structure shown in Figure 25 A for reduction.In one exemplary embodiment, WGMake the half of mesa width between about groove.For higher voltage devices, it is possible to use the multiple terminal trenches shown in Figure 25 F, to reduce the breakdown voltage of device further.More detailed description is to the change of some in these embodiments in the total U.S. Patent No. 6,683,363 of entitled " TrenchStructureforSemiconductorDevices " of Challa, and entire contents is hereby incorporated by.
Figure 26 A to Figure 26 C shows the sectional view of the exemplary trench termination structure for Charge balance trench MOSFET.In the exemplary embodiment shown, MOSFET2600A uses the shielded gate structure with the polycrystalline electrodes 2611 being buried in the shielding below gate electrode 2610 in active groove 2602.In the embodiment shown in Figure 26 A, terminal trenches 2603A is provided with relatively thick dielectric layer (oxide layer) 2605A, and terminal trenches 2603A fills the conductive material of such as electrode 2607A.Interval (such as, the width of last table top) between the thickness of oxide layer 2605A, the degree of depth of terminal trenches 2603A and terminal trenches and neighboring active groove is determined by device reverse BV.In the embodiment shown in Figure 26 A, the groove in surface is wider (T groove structure), and Metal field plate 2609A is used on termination environment.In alternative embodiment (not shown), can be by the electrode 2607A in terminal trenches 2603A being extended on surface and on termination environment, (left end of terminal trenches in Figure 26 A) is formed field plate by polysilicon.Can there be many changes.Touch Gui p+ district (not shown) preferably carry out Ohmic contact for example, it is possible to increase below metal.P-well region 2604 in last table top of adjacent terminals groove 2603A and each contact between them can optionally remove.Floating p-type area also is able to increase to the left side (such as, active area is outer) of terminal trenches 2603A.
In another changes, replacement polysilicon fills terminal trenches 2603, the lower trench being buried in the groove of fill oxide by polysilicon electrode.Figure 26 B shows this embodiment, wherein, the only about half of fill oxide 2605B of terminal trenches 2603B, and lower half has the polysilicon electrode 2607B being buried in oxide.The degree of depth and the height of buried electrodes 2607B changing groove 2603B can be processed based on device.In the another embodiment shown in Figure 26 C, terminal trenches 2603C has been essentially filled with dielectric material, buried conductive material the most wherein.For three embodiments shown in Figure 26 A, B and C, the width of last table top terminal trenches and last active groove separated can be different from the width of the typical table top formed between two active grooves, and can be adjusted the optimal charge balance realizing in termination environment.All changes of the shown structure of above-mentioned combination Figure 26 A may apply in those structures shown in Figure 26 B and 26C.Further, those skilled in the art is it should be appreciated that when terminal structure described herein is used for dhield grid device, similar structure can realize with the termination environment for all above-mentioned various devices based on groove.
For relatively low voltage devices, the corner design of trench termination ring can not be made excessive demands.But, for higher voltage devices, it may be desirable that the fillet (rounding) at end ring turning has bigger radius of curvature.The voltage request of device is the highest, and the radius of curvature at terminal trenches turning is the biggest.The number of end ring can also increase along with the increase of device voltage.Figure 27 illustrates the exemplary means with two relatively large groove 2703-1 and 2703-2 of radius of curvature.Equally based on device voltage request regulates the interval between groove.In this embodiment, distance S1 between terminal trenches 2703-1 and 2703-2 is about the twice of the distance between first terminal groove 2703-1 and active groove end.
Figure 28 A, 28B, 28C and 28D show the example cross section for the various termination environments with silicon post charge balance structure.In the embodiment shown in Figure 28 A, each ring of field plate 2809A contact p-type post 2803A.Thus allow broader table section, this is because the lateral loss produced due to field plate.Breakdown voltage commonly relies on the thickness of field oxide, the number of ring and the degree of depth of terminal pillar 2803A and interval.Many different changes can be had for such terminal structure.Such as, Figure 28 B shows alternative embodiment, and wherein, big field plate 2809B-1 covers all post 2803B of last post except being connected to another field plate 2809B-2.By by big field plate 2809B-1 ground connection, the exhausting quickly of the table section between p-type post, and horizontal pressure drop will not be the most notable so that less than the breakdown voltage of the embodiment shown in Figure 28 A.In another embodiment shown in Figure 28 C, terminal structure does not has field plate on middle post.Because there is no field plate, so being just provided with narrower table section to exhaust fully on middle post.In one embodiment, it is gradually reduced mesa width towards outer shroud and produces optimal performance.Embodiment shown in Figure 28 D is conducive to and the contacting of p-type post by providing wider well region 2808D and the interval that increases between field oxide.
In the case of using the supertension device of various super junction technology of the above-mentioned type, breakdown voltage is much higher than the BV of routinePP.For super-junction device, charge balance or super-junction structures (such as, opposite polarity post or floating region, buried electrodes etc.) can also be with in the termination region.The standard edge terminal structure combining charge balance structure, such as, the field plate of top planes at device edge can also be used.In certain embodiments, the standard edge structure at top can be eliminated by using the quick electric charge that reduces in terminal is tied.For example, it is possible to along with the distance the fewest p-type post formed in termination environment of the most remote electric charge of active area, wherein, active area creates net n-type balancing charge.
In one embodiment, the distance of active area is moved away to change the interval between the inner p-type post of termination environment along with post.Figure 29 A shows the highly simplified sectional view of an exemplary embodiment of the device 2900A according to this embodiment.In the active area of device 2900A, the opposite conductivities post 2926A being such as made up of the p-type spheroid of multiple connections is formed under the p-type trap 2908A in the 2904A of N-shaped drift region.In the edge of device, below termination environment, form p-type terminal pillar TP1 as depicted, TP2 to TPn.Substituting and have unified interval in active area, the interval of the center to center between terminal pillar TP1 to TPn increases along with mobile post and the increase of the interface distance of active area.It is, distance D1 between TP2 and TP3 is less than distance D2 between TP3 and TP4, and distance D2 is less than distance D3 between TP4 and TP5, the like.
This super junction terminal structure can be carried out many changes.Such as, substitute and form p-type terminal pillar TP1 to TPn with different distances in voltage sustaining layer 2904A, but the interval of center to center is kept consistent, but the width of each terminal pillar can be changed.Figure 29 B shows the simplified example of the terminal structure according to this embodiment.In this example, terminal pillar TP1 has the width W1 of the width W2 more than terminal pillar TP2, and W2 is more than the width W3 of terminal pillar TP3 successively, the like.The interval between charge balance district according to the opposite polarity in termination environment, the resultative construction in device 2900B is similar with device 2900A, although the interval of the center to center in device 2900B between groove post can be identical.Simplifying in another exemplary embodiment shown in sectional view at Figure 29 C, the width of each opposite polarity post 2926C in active area reduces from top planes to substrate, and the width of terminal pillar TP1 with TP2 keeps consistent.Less area is so utilized to be achieved that desired breakdown voltage.It should be appreciated by those skilled in the art, above-mentioned various terminal structures can combine in any desired way, such as, the interval of center to center of terminal pillar and/or beam overall including device 2900C shown in Figure 29 C can change in conjunction with the embodiment shown in Figure 29 A and 29B.
Technology
It is described the different components that many has the groove structure of multiple buried electrodes or transistor.In order to bias these trench electrode, these devices need to make electrical contact with each buried regions.There is here disclosed for forming groove structure and the method for carrying out contacting with buried electrodes with the polysilicon layer buried in groove.In one embodiment, the edge at tube core contacts with trench polysilicon silicon layer.Figure 30 A shows an example of the EDGE CONTACT of the trench device 3000 with two polysilicon layers 3010 and 3020.Figure 30 A is showing along the sectional view of the device of trench longitudinal axes.According to this embodiment, groove terminates, for the purpose contacted, the surface of the referred substrate of polysilicon layer 3010 and 3020 in the edge close to tube core.Dielectric (oxidation) layer 3030 allows to contact with the metal of polysilicon layer with 3022 with the opening 3012 in 3040.Figure 30 B to 30F shows each process step of the EDGE CONTACT structure relating to formation Figure 30 A.In Figure 30 B, at top one patterned dielectric (such as, the silicon dioxide) layer 3001 of epitaxial layer 3006, and etch the surface of substrate exposure to form groove 3002.Then, as shown in Figure 30 C, the upper surface crossing the substrate including groove forms the first oxide layer 3003.Then, as shown in fig. 30d, the first conductive material (such as, polysilicon) 3010 is formed on the top in oxide layer 3003.With reference to Figure 30 E, in groove, etch polysilicon layer 3010, and on polysilicon layer 3010, form another oxide layer 3030.Perform similar step, to form the interlayer of second oxide layer-polysilicon layer-oxide layer as shown in Figure 30 F, the top oxide layer 3040 shown in etching, formed respectively for carrying out the opening 3012 and 3022 that metal contacts with polysilicon layer 3010 and 3020.Last step can be repeated to form additional polysilicon layer, and if desired, by superposition metal level, polysilicon layer can be connected together.
In another embodiment, carry out in the active area of device rather than along the edge of tube core with contacting of the multiple polysilicon layers in given groove.Figure 31 A shows an example for multiple active region contact structures burying polysilicon layer.In this example, the sectional view along trench longitudinal axes shows the polysilicon layer 3110 providing gate terminal and polysilicon layer 3111a and 3111b providing two screen layers.When the metal wire 3112,3122 of three separation illustrated contacts with polysilicon layer with 3132, they can be connected together and to the source terminal of device, or use any other combination contacted by the requirement of special applications.Compared with the multilamellar EDGE CONTACT structure shown in Figure 30 A, the advantage of this structure is the plane character of contact.
Figure 31 B to 31M illustrates for for having the example that the groove of two polysilicon layers is formed with the technological process of source region shielding contact structures.Then the etching of the groove 3102 in Figure 31 B is the formation of screen oxide 3108 in Figure 31 C.Then, as fig. 3 id, deposition shield polysilicon 3111, and in making its recessed groove.In Figure 31 E, except being expected at substrate surface carry out the position of shielding contact, bucking electrode 3111 is the most recessed.In Figure 31 E, mask 3109 protects the polysilicon in middle groove in order to avoid being etched further.In one embodiment, this mask is applied at diverse location along different grooves, such as middle groove, and shielding polysilicon is recessed into other parts of groove at third dimension (not shown).In another embodiment, the shielding polysilicon 3111 in the one or more selection grooves in active area is masked along the total length of groove.Then, as shown in Figure 31 F, etch shield oxide layer 3108, then, as shown in Figure 31 G, after removing mask 3109, cross substrate top form the thin layer of grid oxic horizon 3108a.It is followed by the deposition of gate electrode and recessed (Figure 31 H), the injection of p trap and driving (drive) (Figure 31 I), and n+ source electrode injection (Figure 31 J).Figure 31 K, 31L respectively illustrate BPSG deposition, contact etching and the step of p+ heavy doping main body injection with 31M, followed by metallize.Figure 31 N shows the sectional view of the alternative embodiment of active area shielding contact structures, and wherein, the top barrier polysilicon 3111 in screen oxide forms relatively wide platform.So be conducive to contacting bucking electrode, but be the introduction of the configuration (topography) that manufacturing process may be made to complicate further.
There is shown in Figure 32 A the top-down simplified layout diagram of the exemplary trench device of active area shielding contact structures.The mask of restriction bucking electrode groove prevents at bucking electrode position 3211C in active area and the periphery of shield trenches 3213 is recessed.The improvement of this technology uses " dog bone (dogbone) " shape to be used for shielding polysilicon recess mask, is providing broader district to be used for contacting shielding polysilicon with the intersection of each groove 3202.So make the shielding polysilicon in blasnket area also be recessed into, but be the initial surface being recessed into table top, it is thus eliminated that configuration.The top-down layout of alternative embodiment shown in Figure 32 B, wherein, active area groove is connected to peripheral groove.In this embodiment, contacting for the active area shield trenches with source metal, it is recessed along the length of selected groove (this example show middle groove) that shielding polysilicon recess mask prevents shielding polysilicon.Figure 32 C with 32D is to illustrate the simplified layout diagram for two the different embodiments carrying out contacting in having the trench device disconnecting groove structure with peripheral groove.In these figures, for illustrative purposes, active groove 3202 and peripheral groove 3213 are represented by single line.In Figure 32 C, the extension of peripheral gates polysilicon bearing 3210 or finger (finger) are relative to peripheral shield polysilicon finger cross arrangement, to be separated with peripheral groove by peripheral contacts.Source electrode also contacts with active area inner shield polysilicon with shielding contact area 3215 at shown position 3211C.Embodiment shown in Figure 32 D eliminates the side-play amount between active and peripheral groove, to avoid the possible restriction caused by groove tilt requirements.In this embodiment, alignment the active groove 3202 and horizontal extension of peripheral groove 3213, the window 3217 in grid polycrystalline silicon bearing 3210 for by with contacting that the shielding polysilicon around peripheral groove is carried out.Active region contact is carried out at such as the position 3211C of preceding embodiment.
For contacting the alternative embodiment of the trench mask polysilicon in active area shown in Figure 33 A.In this embodiment, substitute recessed shielding polysilicon, but vertically it is extended to silicon face from the above of active groove entity part.With reference to Figure 33 A, along with shielding the polysilicon 3311 high perpendicular extension along groove 3302, grid polycrystalline silicon 3310 is divided into two parts.Two grid polycrystalline silicon part correct positions in groove are in the third dimension or connect together when they enter groove.One advantage of this embodiment is to utilize by carrying out the district of source polysilicon contact in active groove instead of using the silica space contacted for trench polisilicon.Figure 33 B to 33M shows an example of the technological process of the active shielding contact structures for forming Figure 33 A shown type.In Figure 33 B, etch groove 3302, be the formation of the screen oxide 3308 shown in Figure 33 C afterwards.Then, as shown in Figure 33 D, shielding polysilicon 3311 is deposited in groove.As shown in Figure 33 E, etch shield polysilicon 3311, and in making its recessed groove.Then, as shown in Figure 33 F, etch shield oxide skin(coating) 3308, leave the part that the shielding polysilicon 3311 forming two grooves in groove inner shield polysilicon 3311 side exposes.Then, as shown in Figure 33 G, cross the lamellar grid oxic horizon 3308a of the flute profile in the top of substrate, trenched side-wall and groove.It is followed by the deposition of grid polycrystalline silicon and recessed (Figure 33 H), the injection of p trap and driving (Figure 33 I), and n+ source electrode injection (Figure 33 J).Figure 33 K, 33L are shown respectively BPSG deposition, contact etching and the step of p+ heavy doping main body injection with 33M, are followed by metallization.This technological process can be changed.Such as, by rearranging some processing steps, the processing step forming grid polycrystalline silicon 3310 can be before forming the step of shielding polysilicon 3311.
It is all well-known for performing the concrete processing method of many steps of above-mentioned technological process and parameter and change thereof.For given application, special process method, chemistry and material type can well be adjusted, to strengthen manufacturability and the performance of device.Improvement can be proceeded by, it is, be formed on the substrate of extension drift region from raw material.In most of power are applied, it is desirable to reduce conducting resistance R of transistorDSon.The preferable conducting resistance of power transistor is the function that critical field (criticalfield) is stronger, and wherein, critical field is defined as the maximum field under breakdown condition in device.Assume to keep rational mobility, if device is higher than the material manufacture of the critical field of silicon by critical field, can significantly reduce the conducting resistance of transistor.Owing to the characteristic (including structure and technique) of many power devices described so far is described in the content of silicon substrate, it is possible to use be different from other embodiments of the baseplate material of silicon.According to an embodiment, the power device described herein substrate manufacture being made up of wide bandgap materials (including such as, carborundum (SiC), gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP), diamond etc.).These wide bandgap materials demonstrate the critical field of the critical field more than silicon, may be used for being substantially reduced the conducting resistance of transistor.
What another mainly helped reduction transistor conduct resistance is thickness and the doping content of drift region.Drift region is usually and is formed by epitaxially grown silicon.In order to reduce RDSon, it is desirable to by the minimizing thickness of this extension drift region.The thickness of epitaxial layer is controlled by the type portions of initial substrate.Such as, for discrete-semiconductor device, the substrate of doping red phosphorus is the material of initial substrate general type.But, the characteristic of phosphorus atoms is that they promptly spread in silicon.Accordingly, it is determined that the thickness of the epitaxial region formed at substrate top, the phosphorus atoms diffused up from following heavy doping substrate with regulation.
In order to the thickness making epitaxial layer is minimum, according to shown in Figure 34 a embodiment, phosphorio plate 3414 forms extension spacer or buffering (potential barrier) layer 3415 of the alloy (such as, arsenic) with relatively small diffusibility.The substrate of Doping Phosphorus of combination and the cushion of arsenic doped provide basis for subsequently forming extension drift region 3406.Require to determine the arsenic doping concn of layer 3415 by the breakdown voltage of device, and determined the thickness of arsenic epitaxial layer 3415 by concrete heat budget (thermalbudget).It is then possible at the uniform epitaxial layer of deposited atop 3406 of arsenic epitaxial layer, its thickness is determined by requirement on devices.The diffusibility that arsenic is the lowest allows to reduce the gross thickness of extension drift region so that reduce the conducting resistance of transistor.
In an alternative embodiment, in order to calculate dopant species diffusing up from heavy doping substrate to epitaxial layer, diffusion barrier layer is used between the two layers.According to shown in Figure 35 a exemplary embodiment, by such as carborundum SixC1-xThe barrier layer 3515 of composition is epitaxially deposited on the substrate 3514 of boron or phosphorus.Then, epitaxial layer 3506 is deposited on above barrier layer 3515.Heat budget according to Technology can change thickness and carbon compound.Alternatively, carbon doping thing can be first poured in substrate 3514, then carries out heat treatment and activates carbon atom, to form Si on the surface of substrate 3514xC1-xCompound.
Another aspect limiting the specific trench transistor technology reducing epitaxy layer thickness ability is the knot formed between deep body and epitaxial layer, and this knot is sometimes used in active area, is sometimes used in termination environment.The formation in this Shen Ti district relates generally to the implantation step in technique early stage.Owing to requiring that heat budget subsequently, the knot between deep body and drift region are divided into big scope by the formation of field oxide and grid oxic horizon.In order to avoid early puncturing at the edge of tube core, need the thickest drift region, which results in higher conducting resistance.For the minimizing thickness by required epitaxial layer, the use of diffusion barrier layer can also use at deep body-epitaxial layer knot.According to the exemplary embodiment shown in Figure 36, by deep body window, performing injection carbon doping thing before deep body injects.Thermal process subsequently activates carbon atom, forms Si with the border in Shen Ti district 3630xC1-xCompound 3615.Silicon carbide layer 3615 is used as to stop the diffusion barrier layer of boron diffusion.The deep body knot ultimately formed is the shallow-layer allowing to reduce epitaxial layer 3606 thickness.Another knot in the representative groove transistor benefiting from barrier layer is trap-drift region knot.Figure 37 illustrates the simplified example of the embodiment using this barrier layer.In the exemplary process flow for Figure 31 M structure, between two shown in Figure 31 H and 31I step, form p trap.Before injecting trap alloy (being p-type in this exemplary n-channel embodiment), it is initially injected carbon.Thermal process subsequently activates carbon atom, to form Si at p trap epitaxy junctionxC1-xLayer 3715.Layer 3715 is used as diffusion barrier layer and prevents boron from spreading so that can keep the degree of depth of p trap 3704.So contribute to reducing the channel length of transistor, and do not increase break-through current potential.When loss border of advancing is along with when the increase of dram-source voltage arrives source junction, break-through occurring.By as diffusion barrier layer, layer 3715 is also prevented from break-through.
As discussed above, it is desired to reduce the channel length of transistor, because it causes the reduction of conducting resistance.In another embodiment, by using epitaxially grown silicon formation well region to make transistor channel length minimum.It is, replace forming the traditional method about the trap injecting drift epitaxial layer before diffusing step, form well region at the top of extension drift layer.Except shorter channel length can be obtained from the formation of extension-trap, also have other advantages.Such as, in shielded gate trench transistor, the distance that gate electrode extends in the bottom of the trap of contact trench (grid is to the overlapping portion of drain electrode) is for determining gate charge QgdCritically important.Gate charge QgdDirectly affect the switching speed of transistor.It is therefore desirable to be able to accurately minimize and control this distance.But, such as, inject at the trap shown in above-mentioned Figure 31 I and be diffused in the manufacturing process of shown epitaxial layer, it is difficult to controlling this distance.
In order to preferably control corner's grid at trap to the superposition of drain electrode, it is proposed that the various methods of trench devices for forming the traps with self-aligned.In one embodiment, the depositing operation flow process relating to epitaxial layer-trap enables to bottom and the gate bottom self-aligned of body junction.With reference to Figure 38 A to 38D, it is shown that have the simplification of flowsheet of an example of the extension-trap trench device of the self-aligned of buried electrodes (or dhield grid).Groove 3802 is etched into the first epitaxial layer 3806 formed at the top of substrate 3814.For n-channel transistor, substrate 3814 and the first epitaxial layer 3806 are n-type material.
Figure 38 A shows shield dielectric layer 3808S of the grown on top at the epitaxial layer 3806 including internal groove 3802.Then, as shown in fig. 38b, in groove 3802, deposit conductive material 3811 (such as, polysilicon), and deeply etch below epitaxial mesa.The dielectric material 3809S that deposition is added is to cover shielding polysilicon 3811.As shown in Figure 38 C, after deep etching dielectric layer clears up table top, optionally grow the second epitaxial layer 3804 at the top of the first epitaxial layer 3806.The table top formed by epitaxial layer 3804 is on the groove top generated above of shown original groove 3802.This second epitaxial layer 3804 has the opposite polarity alloy (such as, p-type) with the first epitaxial layer 3806.The doping content of the second epitaxial layer 3804 is set to the aspiration level of transistor well region.After the selective epitaxy of cambium layer 3804 grows (SEG) step, on end face and along trenched side-wall, form gate dielectric 3808G.Then, as shown in Figure 38 D, deposit grid conducting material, fill the remainder of groove 3802, then perform planarization.Such as, the technological process shown in Figure 31 J to 31M is continued, to complete transistor arrangement.
As shown in Figure 38 D, this technique forms the grid polycrystalline silicon 3810 with trap epitaxial layer 3804 self-aligned.In order to make the bottom of grid polycrystalline silicon 3810 reduce under extension trap 3804, slightly the upper surface of the polysilicon interlayer dielectric layer 3809S shown in Figure 38 C can be etched into the desired locations in groove 3802.Therefore, the distance between gate electrode and the turning of trap is provided and accurately controls by this technique.It should be appreciated by those skilled in the art, SEG trap formation process is not limited to shielded gate trench transistor, it is possible to use in other trench-gate transistor structures many, wherein, many is described the most in this article.The additive method forming SEG mesa structure is described in the 6th, 373, No. 098 of Brush et al. in the U.S. Patent No. 6,391,699 of commonly assigned Madson et al., and entire contents is hereby expressly incorporated by reference.
The formation of SEG trap it is independent of for controlling the alternative at the turning of the trap of self-aligned, but instead of using relating to the technique that angle trap injects.Figure 39 A and 39B illustrates the exemplary process flow of this embodiment.In this embodiment, replace shown in trench fill (such as, in Figure 31 H and 31I) grid polycrystalline silicon after formed trap, but in the dielectric layer 3908 in groove 3902 embed shielding polysilicon after, fill groove remainder before, given part perform first trap inject 3905.Then, as shown in Figure 39 B, perform second by the sidewall of groove 3902 but the injection of the trap of angulation.Then, complete drive cycle, to obtain the desired trap profile to drift epitaxial interface at trench corner.According to the structural requirement of device, injection rate (implantdoes), energy and the details of drive cycle will be changed.This technology can use in the type of device that many is different.In an alternative embodiment, regulation groove tilts and angle is injected so that when angle injects diffusion, and its district with adjacent unit combines and forms continuous trap, eliminates the needs that the first trap injects.
In conjunction with accompanying drawing 40A to 40E, another embodiment being used for forming the extension trap technique of the self-aligned of trench device is described.As it has been described above, in order to reduce gate drain capacitor, some trench gate type transistors use gate dielectric, and wherein, the bottom thickness of gate dielectric groove below grid polycrystalline silicon is more than the thickness of the dielectric layer along interior vertical sidewall.According to the illustrative processes embodiment shown in Figure 40 A to 40E, as shown in fig. 40, dielectric layer 4008B is first formed at the top of extension drift layer 4006.Forming the dielectric layer 4008B with expectation thickness, then, as shown in Figure 40 B, etching dielectric layer 4008B makes the dielectric post of the remaining groove same widths having and subsequently form.It follows that in Figure 40 C, perform selective epitaxial growth step, to form the second extension drift layer 4006-1 around dielectric post 4008B.Second extension drift layer 4006-1 and the first extension drift layer 4006 have identical conduction type and can be identical material.Alternatively, the second extension drift layer 4006-1 can also use other kinds of material.In one exemplary embodiment, by using SiGe (SixGe1-x) the SEG step of alloy forms the second extension drift layer 4006-1.SiGe alloy improves the carrier mobility of the accumulation area bottom adjacent trenches.This improves the switching speed of transistor, and reduce RDSon.Other compounds, such as, GaAs or GaN can also be used.
As Figure 40 D and 40E is respectively shown in, being formed on an upper and cover extension well layer 4004, then, etching extension well layer 4004 forms groove 4002.It is followed by the formation of grid oxic horizon and the deposition (not shown) of grid polycrystalline silicon.Final structure is the trench-gate of the extension trap with self-aligned.Traditional treatment technology can be used to complete remaining processing step.It should be appreciated by those skilled in the art there is change.Such as, replacing being formed and cover extension well layer 4004 and then etch groove 4002, extension trap 4004 can only top at the second drift epitaxial layer 4006-1 optionally grow, along with its growth formation groove 4002.
Above-mentioned various treatment technology strengthens device performance, to reduce channel length and R by paying close attention to the formation of well regionDson.By improving other aspects of technological process, it is also possible to realize similar performance enhancement.Such as, by reducing substrate thickness, the impedance of device can be reduced further.Therefore to reduce the thickness of substrate, generally perform wafer grinding and process.Typically perform wafer grinding by mechanical lapping and tape handling (tapeprocess).Grind and tape handling is mechanical force to be applied on wafer, cause the damage of wafer surface, which results in a manufacture difficult problem.
In the embodiment being described below, the wafer grinding of improvement processes and significantly decreases substrate impedance.A kind of method for reducing substrate thickness is shown in Figure 40 R, Figure 40 S, Figure 40 T and Figure 40 U.After completing the making of expectation circuit on wafer, the top of the wafer making circuit is temporarily adhered to carrier.The wafer 4001 that Figure 40 R has illustrated adheres to carrier 4005 by adhesion material 4003.Then, such as grinding, chemical etching etc. are used to process the polished backside of the wafer completed to expecting thickness.Figure 40 S illustrates the sandwich similar with shown in Figure 40 R, has thinning wafer 4001.After the back side of polishing wafer 4001, as shown in Figure 40 T, the back side of wafer adheres to Low ESR (such as, metal) wafer 4009.Traditional method can be used to complete these steps, such as, use the shallow layer of solder 4007 that metal wafer 4009 adheres to thinning wafer 4001 at temperature and pressure.Then, before further processing, remove carrier 4005 and clear up the upper surface of thinning wafer 4001.The metal basal board 4009 of high connductivity contributes to heat radiation, reduces impedance and provide mechanical strength for thinning wafer.
By using chemical treatment to perform last reduction processing, alternative embodiment achieves the thinner wafer not having traditional mechanical to process shortcoming.According to this embodiment, the silicon layer of heavy sheet glass silicon (silicon-on-thick-glass, referred to as SOTG) substrate forms active device.In the stage of grinding, can be by chemically the glass etching of SOTG substrate back being fallen wafer grinding.Figure 41 illustrates the exemplary process flow according to this embodiment.From the beginning of silicon substrate, first in step 4110, such as He or H2Alloy be injected into silicon substrate.Then, 4112, silicon substrate is adhered to glass substrate.Different adhesion process can be used.In an example, silicon wafer and chip glass make sandwich-like, are heated approximately to 400 DEG C and bond two substrates.Glass can be silicon dioxide etc., and can have the thickness of the most about 600um.Then, in step 4114, optionally adhesive silicone substrate, and form heavy sheet glass silicon (silicon-on-thick-glass) SOGT substrate.In order to protective substrate, from stress, can repeat adhesion process in processing and processing procedure subsequently, form SOGT substrate (step 4116) with the opposite side at substrate.It follows that on the silicon face of substrate deposit epitaxial layers (step 4118).Except front side, it is also possible to perform at rear side.Preferably, the doping content on rear side of epitaxial layer is similar with the doping content of rear side silicon, and front side epitaxial layer is along with the doped in concentrations profiled of requirement on devices.Then, substrate carries out each step of the manufacturing process for forming active device on the silicon layer of front side.
In one embodiment, being processed the intensity of the stress that step introduces by front side in order to further enhance substrate opposing, backside substrate can carry out pattern and turn to the reverse geometry of tube core framework on front side of approximation.By this way, glass substrate etching network access grid, to help thin substrate to support the stress in wafer.After milling, first pass through traditional grinding technics, from rear side, silicon layer is removed (step 4120).It is followed by another grinding steps 4122, removes a part (such as, half) for glass substrate.Then, by using the chemical etching of Fluohydric acid. such as to process the removal of remaining for glass substrate part.The etching of rear glass substrate can be performed, and active silicon layer does not corrode or causes the risk of mechanical damage.Thus eliminating the band needs around (tape) wafer, eliminate band and operate relevant process risk around the needs of (re-tape) equipment with each around with band again.Therefore, such technique makes to be minimized by substrate thickness further to strengthen device performance.Should be understood that the change that can have many this improvement wafer thinning process.Such as, according to the expectation thickness of final substrate, reduction steps can relate to grinding or be not related to grind, because chemical etching is enough.Additionally, the wafer thinning process improved is not limited to the process of discrete device, it is also possible to apply in the process of other types device.Other wafer thinning process, in the commonly assigned U.S. Patent No. 6 of Pritchett, is described in 500,764, and entire contents is hereby incorporated by.
There is other structures of many power transistors and process aspect and can other active devices of their performance of appreciable impact.The shape of groove is an example.In order to reduce the potential destructive electric field being prone to around the turning of groove concentrate, it is desirable to avoid sharp corners, but form the groove with radiused corners.In order to improve reliability, also it is desirable to realize the trenched side-wall with smooth surface.Different etch chemistries provides balance in different results (such as, silicon etch rate, the selectivity of mask layer, etching section (side wall angle), top corner fillet, the degree of roughness of sidewall and the fillet of channel bottom).Fluoride (such as, SF6) high silicon etch rate (more than 1.5um/min), round channel bottom and straight side are provided.Fluoride shortcoming is coarse sidewall and the difficulty (can be recessed) of groove top control.Chloride (such as, Cl2) provide more smooth sidewall, and etching section and groove top preferably control.Muriatic shortcoming is to have relatively low silicon etch rate (less than 1.0um/min), and the fillet that channel bottom is less.
Additional gas can be added in etch chemistries, to contribute to being passivated sidewall during etching.Side wall passivation, for being minimized by side etching, etches into desired gash depth.Additional process step can be used to make trenched side-wall smooth, and realize the rounding of groove top corner and bottom.The surface quality of trenched side-wall is critically important, because it has influence on the quality of the oxide layer that can grow on trenched side-wall.The chemicals no matter used, generally used before main etching step and penetrate (breakthrough) step.The purpose of penetration step is to remove any native oxide that can shelter silicon etching during main etching step on silicon face.Typical break-through-etch chemicals are CF4Or Cl2。
For improving an embodiment use main silicon trench etch based on chlorine of etch process shown in Figure 42 A, it is followed by etching step based on fluorine.One example of this technique uses Cl2The main etching step of/HBr, is followed by SF6Etching step.Chlorinating step for etching into the part of desired depth by main line.So produce and there is a certain degree of tapering and there is the groove side surface of smooth side wall.Fluorination step subsequently is for the residue of etched trench groove depth, rounding channel bottom and the further smoothing of the silicon conjugate providing any suspension sticked on trenched side-wall.Preferably, fluorination etching step relatively low fluorine flowing, low pressure and lower powered under the conditions of perform, to control smoothing and rounding.Due to the difference of etch-rate between two kinds of etch chemistries, the time of two steps can be balanced, to realize the technique with the relatively reliable and manufacturability of acceptable total etching period, and keep desired groove side surface, sidewall roughness and channel bottom fillet.
In another embodiment shown in Figure 42 B, the improved method for silicon etching includes main etching step based on fluorine, is followed by the second etching step based on chlorine.One example of this technique uses SF6/O2Main etching step, is followed by Cl2Etching step.Fluorination step is for etching the most of degree of depth in main line.The step for generate the groove of channel bottom with straight sidewall and rounding.The step for of it is optionally possible to oxygen is added to, to provide side wall passivation, and contribute to by reducing the sidewall that side etching keeps straight.The top corner of follow-up chlorinating step rounding groove also reduces the roughness of sidewall.The high silicon etch rate of fluorination step increases the manufacturability of technique by increasing the throughput of etch system.
In another embodiment shown in Figure 42 C, by argon is added to obtain in chemicals based on fluorine the silicon etch process of improvement.The example for the chemicals of main etching step according to this embodiment is SF6/O2/Ar.The argon increasing to etching step adds ion bom bardment, hence in so that etching is more physico.So contribute to controlling the top of groove, and eliminate the tendency that groove top is the most recessed.Additional argon can also increase the fillet of channel bottom.Additional etch processes may be used for the smoothing of sidewall.
As shown in Figure 42 D, the alternative embodiment of the silicon etch process for improving uses chemicals based on fluorine, starts to remove oxygen from main etching step.One example of this technique uses SF6Step, is followed by SF6/O2Step.In the first stage of etching, owing to there is not O2, lack side wall passivation.Such result is the increase of the side etching amount at groove top.Then, the second etching step, SF6/O2, continue to etch remaining gash depth so that there is straight side and circular channel bottom.So cause top in groove structure wider, be sometimes referred to as T groove.Use T groove structure device example Herrick entitled " StructureandMethodforFormingaTrenchMOSFETHavingSelf-Alig nedFeatures; " commonly assigned U.S. Patent Application No. 10/442, being described in detail in No. 670 (acting on behalf of Reference Number 18865-131/17732-66850), entire contents is hereby expressly incorporated by reference.The cycle for two main etching steps can be adjusted, to realize the expectation thickness of the every part of T groove (top T part, the part of bottom smooth side wall).Additional treatments can be used to come the top corner cavetto of T groove, and make trenched side-wall polish.These additional treatments can include, such as: (1) step based on fluorine at the end of trench etch method, or the etching based on fluorination (2) separated in separating etch system, or (3) sacrifical oxide, or any other combination.Chemical-mechanical planarization (CMP) step can be used, to remove the top recessed portion again of groove side surface.H can also be used2Annealing (anneal) helps rounding and forms favourable valley gutter side.
Deeper high-voltage applications is tended to for groove, there is the item being additionally required consideration.Such as, due to deeper groove, so silicon etch rate is critically important for producing the technique that can manufacture.Etch chemistries for this application is generally fluorochemical thing, because the etching chemistry reaction of chlorination is the slowest.It is also expected to straight line is to the trench profile of taper, there is smooth sidewall.Due to the degree of depth of groove, etch process also needs to have selectivity good to mask layer.If selectivity is very poor, then be accomplished by thicker mask layer, total aspect ratio will be increased.Side wall passivation is also strict, and needs to realize balancing accurately.The point that undue side wall passivation will make channel bottom close to it narrows, and side wall passivation very little will cause increasing side etching.
In one embodiment, it is provided that optimally balance the deep trench etch process of all these requirement.According to this embodiment, shown in Figure 42 E, etch process includes having gradual change (ramped) O2, progressive power and/or the chemicals based on fluorine of gradual change pressure.One example embodiments uses SF in the way of the silicon etch rate keeping etching section and run through etching6/O2Etching step.By gradual change O2, can control to run through the side wall passivation amount of etching, to avoid the side etching (in the case of passivation very little) or the pinch off channel bottom (in the case of excess passivation) that increase.Use the example U.S. Patent No. 6 at total for Grebs et al. entitled " IntegratedCircuitTrenchEtchwithIncrementalOxygenFlow " of the etching based on fluorine with gradual change oxygen stream, 680, being described in detail in No. 232, it is hereby expressly incorporated by reference.The gradual change of power and pressure contributes to controlling ion current density and keeping silicon etch rate.If silicon etch rate significantly reduces along with groove is etched deeper during etching, then total etching period will increase.Which results in the low wafer processing capabilities of etcher.Additionally, gradual change O2Can aid in the selection controlled mask material.The exemplary process of the groove for being deeper than such as 10um according to this embodiment can have the O of per minute 3 to 5sccm2Turnover rate, the power level of 10-20 watt per minute and the pressure stage of 2-3mT per minute.
The alternative embodiment of deep trench etch process uses stronger chemicals (such as, NF based on fluorine3).For silicon is etched, NF3Compare SF6Function more easily as reaction, use NF3Technique can realize the silicon etch rate increased.Need to increase extra gas for side wall passivation and profile control.
In another embodiment, NF3It is SF after etching step6/O2Process.According to this embodiment, NF3Step is for the major part with high silicon etch rate etched trench groove depth.Then, SF6/O2Etching step is used for being passivated existing trenched side-wall, and the remainder of etched trench groove depth.In the change of this embodiment shown in Figure 42 F, perform NF in an alternating fashion3And SF6/O2Etching step.This creates the terminal and have than direct SF6/O2The technique of the higher silicon etch rate of technique.Thus at fast etch-rate step (NF3) and generate the step (SF of side wall passivation for profile control6/O2Balance is achieved between).The balance of step controls the roughness of sidewall.SF for etching6/O2Part, in addition it is also necessary to gradual change O2, power and pressure, to keep silicon etch rate, and generate enough side wall passivations and contribute to controlling etching section.It should be appreciated by those skilled in the art, each processing step described in conjunction with above-described embodiment can combine, in a different manner to realize optimal trench etch process.Should be understood that any groove in any power device that these groove etching process may be used for being described herein as, and the groove of any other type that use is in other kinds of integrated circuit.
Before groove etching process, form trench etch mask at silicon face, and carry out one patterned and will carry out trench district to expose.As shown in Figure 43 A, in general device, trench etch, before etching silicon substrate, etches first through nitride layer 4305 and liner (pad) thin oxide layer 4303.After forming groove during oxide layer in forming the trenches, cushion oxide layer 4303 can also be in edge's growth of the groove of the nitride layer promoting superposition.This creates the terminal the structure 4307 of commonly referred to as " beak ", i.e. cushion oxide layer growing partly at the slot wedge under nitride layer 4305.Will will shoal near groove at the source area being adjacent to be formed at the slot wedge having under the cushion oxide layer of beak structure subsequently.This is the most undesirable.In order to eliminate beak effect, in one embodiment, shown in Figure 43 B, non-oxidating material (such as, polysilicon) layer 4309 is clipped between nitride layer 4305 and cushion oxide layer 4303.Polysilicon layer 4309 protects cushion oxide layer 4303, in case being further oxided during groove subsequently aoxidizes and formed.In another embodiment, shown in Figure 44 A, after being etched through the nitride layer 4405 and cushion oxide layer 4403 limiting groove opening, board structure forms the thin layer 4405-1 of the non-oxidating material of such as nitride.Then, as shown in Figure 44 B, remove protective layer 4405-1, the sealing coat of the remaining vertical edge along nitride-liner oxidation Rotating fields from horizontal surface.Nitride spacer protection cushion oxide layer 4403, in case being further oxided in a subsequent step, reduces beak effect.In an alternative embodiment, in order to reduce the degree that any beak is formed, the embodiment shown in Figure 43 B and 44B can be combined in.It is, except from combining the sealing coat generated in the technique that Figure 44 A and 44B describes, it is also possible to polysilicon layer is interposed between cushion oxide layer and the nitride layer of superposition.Can there is other change, such as, increase another layer (such as, oxide layer) at the top of nitride layer, to contribute to the selectivity of nitride when etching silicon trench.
The transistors with shielded gate structure as various in above-mentioned combination, bucking electrode is come by dielectric materials layer with grid electrode insulating.This inter-electrode dielectric layer sometimes referred to as polysilicon interlayer dielectric layer or IPD must be formed with firm and reliable way so that it can withstand the potential difference existed between bucking electrode and gate electrode gate electrode.Referring again to Figure 31 E, 31F and 31G, it is shown that for the simple flow of associated process steps.After shielding polysilicon 3111 in deep etching groove (Figure 31 E), shield dielectric layer 3108 is etched into the degree (Figure 31 F) as shielding polysilicon 3111 deeply.Then, as shown in Figure 31 G, the upper surface of silicon forms gate dielectric 3108a.It is the step forming IPD layer.The artefact of shielding dielectric groove etching is to form shallow slot on the upper surface of the shield dielectric layer of the either side residual of bucking electrode.This is shown in Figure 45 A.The structure finally with uneven configuration can cause consistency problem, filling step the most subsequently.In order to eliminate such problem, it is proposed that the various improved methods for forming IPD.
According to an embodiment, after shielding dielectric groove etching, as shown in Figure 45 B, such as low-pressure chemical vapor phase deposition (LPCVD) is used to process deposit polycrystalline silicon lining 4508P.Alternatively, polysilicon lining 4508P can only be formed on shielding polysilicon and shield dielectric layer, is sputtered by the polysilicon using the growth selection of polysilicon to process or be directed at so that trenched side-wall does not has polysilicon substantially.Polysilicon lining 4508P is the most oxidized is converted to silicon dioxide.This can be performed by traditional thermal oxidation.Being formed without on trenched side-wall in the embodiment of polysilicon, this oxidation processes also forms gate dielectric 4508G.It addition, as shown in Figure 45 C, after trenched side-wall etching oxidation polysilicon, form gate dielectric thin layer 4508G, remaining groove cavity fills gate electrode 4510.The advantage of this process is that polysilicon deposits in the way of the most conformal.So make space and other shortcomings minimum, and once polysilicon, at shield dielectric layer and the deposited atop of bucking electrode, will form more smooth surface.Result is to obtain firmer and reliable improvement IPD layer.By arranging polysilicon along trenched side-wall and vicinal silicon surface district before the oxidation, oxidation step subsequently will make less table top be lost, and widened by less desirable groove and minimize.
In an alternative embodiment, the sectional view simplified shown in Figure 46 A, 46B and 46C, the cavity produced by shielding polysilicon recess etch in groove is filled dielectric fill material 4608F, and wherein, dielectric fill material 4608F has the etch-rate identical with shield dielectric layer 4608S.The step for that any one of high-density plasma (HDP) oxide deposition, chemical vapor deposition (CVD) or spin-coating glass (SOG) process perform can be used, it is followed by planarization steps, to obtain the plane at groove top.Then, as shown in Figure 46 B, dielectric fill material 4608F and shielding dielectric material 4608S unification are etched deeply so that the insulation material layer with necessary thickness is stayed on bucking electrode 4611.Then, as shown in Figure 46 C, after arranging grid dielectric material along trenched side-wall, remaining groove cavity fills gate electrode.Result is that of avoiding the IPD layer of the inconsistent high conformal of configuration.
Simplifying shown in sectional view for forming the exemplary embodiment of the another kind of method of high-quality IPD in Figure 47 A and 47B.In shield dielectric layer 4708S formed in groove with after filling cavity with shielding polysilicon, performing the shielding deep etching step of polysilicon, being recessed at groove so that shielding polysilicon.In this embodiment, shielding polysilicon recess etch leaves more polysilicon in groove so that the upper surface of recessed shielding polysilicon is higher than final target depth.The thickness of the extra polysilicon on surface is designed to about identical with Target IP D thickness on the shield polysilicon.Then, the top of bucking electrode is physically or chemically changed, to further enhance its oxidation rate.Can be by impurity (such as, fluorine or argon ion) ion implanting be entered the method that polysilicon performs chemically or physically to change electrode, to strengthen the oxidation rate of bucking electrode respectively.Preferably, as shown in Figure 47 A, this is infused under zero degree execution, it is, vertical with bucking electrode, in order to will not physically or chemically change trenched side-wall.Then, dielectric layer is removed by etch shield dielectric layer 4708S from trenched side-wall.This shielding dielectric groove etching remaining neighbouring bucking electrode 4711 shield dielectric layer in produce slight recessed (being similar to shown in Figure 45 A).It is followed by traditional oxidation step, thus the top that bucking electrode 4711 changes is oxidized with the speed being faster than trenched side-wall.This results on bucking electrode rather than form the thickest insulating barrier 4708T along the sidewall on groove silicon surface.Thicker insulating barrier 4708T on bucking electrode forms IPD.The polysilicon lateral oxidation changed compensates some grooves formed at the upper surface of shield dielectric layer due to shielding dielectric groove etching.Then, perform traditional step, to form gate electrode in the trench, generate the structure shown in Figure 47 B.In one embodiment, bucking electrode is changed to obtain the thickness ratio of IPD and grid oxic horizon that scope is 2: 1 to 5: 1.Such as, if selected for the ratio of 4: 1, for the IPD of formed on the shield electrode about 2000 angstroms, form the gate oxide of 500 angstroms along the big appointment of trenched side-wall.
In an alternative embodiment, after shielding dielectric groove etching, perform physically or chemically to change step.It is, etch shield oxide layer 4708S, so that oxide is removed from trenched side-wall.So disclose the top of above-mentioned bucking electrode and method that silicon is physically or chemically changed.Owing to exposing trenched side-wall, so changing step to be only limited to horizontal surface, it is, only silicon mesa and bucking electrode.Change method (such as, the ion implanting of alloy) will perform at zero degree (being perpendicular to bucking electrode), in order to avoids physically or chemically changing trenched side-wall.Then, perform traditional method, to form gate electrode in the trench, on bucking electrode, therefore produce thicker dielectric layer.
Figure 48 illustrates the another method of IPD layer for forming improvement.According to this embodiment, form, on recessed screen oxide 4808S and bucking electrode 4811, thick dielectric layer 4808T being made up of such as oxide.Preferably, the craft of orientated deposition techniques of the plasma chemical vapor deposition (PECVD) using such as high-density plasma (HDP) to deposit or to strengthen forms thick dielectric layer 4808T (it is, " be inverted and fill (bottmupfill) ").As shown in figure 48, orientated deposition makes along horizontal plane (it is, on bucking electrode and screen oxide) rather than forms sufficiently thick insulating barrier along vertical (it is, along trenched side-wall).Then, perform etching step, to get on deoxygenation compound from sidewall, and leave enough oxides on the shield polysilicon.Then, perform traditional step, to form gate electrode in the trench.Except obtaining conformal IPD, the advantage of this embodiment is to prevent table top loss and groove to widen, because IPD is formed by deposition processes rather than oxidation processes.The another advantage of this technology is to obtain fillet at the upper turning of groove.
In another embodiment, after shield dielectric layer or shielding polysilicon are recessed, in groove, thin oxide layer 4908P is sheltered in growth.Then, as shown in Figure 49 A, deposited silicon nitride layer 4903 is to cover oxidation masking layer 4908P.Then, uneven etches both silicon nitride layer 4903 so that it is do not remove from trenched side-wall from the bottom surface (it is, on bucking electrode) of groove.Final structure shown in Figure 49 B.Then, as shown in Figure 49 C, wafer is exposed to oxidation environment so that form thick oxide layer 4908T on shielding polysilicon surface.Owing to nitride layer 4903 can be not oxidized, along trenched side-wall, significant oxidation growth would not occur.Then, by wet etching, use such as strong phosphoric acid to remove nitride layer 4903.As shown in Figure 49 D, the most traditional processing step, to form grid oxic horizon and gate dielectric.
In certain embodiments, the formation of IPD layer relates to etch processes.Such as, the embodiment that IPD film is deposited on configuration, can the first thick a lot of thin layer of the desired final IPD thickness of deposition rate.Do so is obtained in that planar lamina, to be minimized in groove by the groove of initiation layer.Then, etching can be filled up completely with groove and the thicker thin layer extended on a silicon surface, so that its thickness to be reduced to Target IP D layer thickness.According to an embodiment, this IPD etch process performs with minimum two etching steps.First step is by layer planesization to silicon face.In this step, the uniformity of etching is very important.Second step is to make the recessed desired depth of IPD layer (and thickness) in groove.In this second step, the etching selectivity of IPD layer to silicon is critically important.During groove etching step, expose silicon mesa, and silicon trench sidewall is the same with IPD layer is recessed in groove.Any loss on table top all can affect the gash depth of reality, and if comprise T groove, also can affect the degree of depth of T groove.
In an exemplary embodiment shown in Figure 50 A, anisotropic plasma etch step 5002 is used for IPD planarizing layers until silicon face.Exemplary etch-rate for plasma etching can be 5000A/min.It is followed by isotropic wet etch step 5004, with by recessed for IPD groove.Preferably, the solution using controlled silicon to select performs deep etching, in order to will not corrode sidewall silicon when exposing, and provide repeatably etching to obtain accurate depth of groove.Exemplary chemical agents for wet etching can be the buffer oxide etch (BOE) of 6: 1, produces the etch-rate of about 1100A/min at 25 DEG C.Providing the details for the example plasma and wet etch process being suitable for this technique in the commonly assigned U.S. Patent No. 6,465,325 of RodneyRisley, entire contents is hereby expressly incorporated by reference.For planarization the first plasma etch step compared with wet etching, the IPD layer on groove has less groove.For the second wet etch step of groove etching compared with plasma etching, produce more preferable silicon selectivity and the infringement less to silicon.In the alternative embodiment shown in Figure 50 B, chemical-mechanical planarization (CMP) processes and is used for IPD layer planesization until silicon face.It is followed by wet etching, with by recessed for IPD groove.CMP process makes the IPD layer on groove produce less groove.For the wet etch step of groove etching compared with CMP, produce more preferable silicon selectivity and the infringement less to silicon.These other combinations processed also are possible.
Except IPD, desirably form high-quality insulating barrier in the structure, including groove and plane gate dielectric, interlayer dielectric layer etc..The dielectric material commonly used most is silicon dioxide.There is the parameter of several definition oxide film of high quality.Mainly uniform thickness, good integrity (low interface trap density), high electric field breakdown strengths and low drain level.The factor affecting the many character in these character is the speed of oxide growth.It is desirable to accurately control the growth rate of oxide.During thermal oxide, the charged particle in wafer surface produces gas phase reaction.In one embodiment, complete by affecting charged particle for controlling the method for oxidation rate, typically silicon and oxygen, by wafer is applied external voltage, so that oxidation rate is decreased or increased.This is different from plasma enhanced oxidation, is formed without plasma (active component) on wafer.Additionally, according to this embodiment, gas does not accelerate towards surface, is only prevented from it and reacts with surface.In the exemplary embodiment, reactive ion etch (RIE) room with high temperature capabilities can be used to adjust for required energy value.RIE room is not used to etching, but is used for applying DC bias and controls required energy, to slow down and to stop oxidation.Figure 51 is the flow chart for the illustrative methods according to this embodiment.First, RIE room is for applying DC bias (5100) to wafer under the test environment.After determining the potential energy (5110) needed for the reaction of suppression surface, apply sufficiently large external bias, to prevent to aoxidize (5120).Then, by controlling external bias (such as, impulse modulation or additive method), the oxidation rate (5130) when average very high-temperature can be controlled.This method is obtained in that the advantage (flowing of more preferable oxide, relatively low stress, eliminate the differential growth etc. of various crystal orientation) of high-temperature oxydation, and not have quick the and shortcoming of heterogeneous growth.
Although such as those described above combines the quality that the technology of Figure 51 can improve the oxide layer of generation, but has especially left over the integrity problem of oxide in trench-gate device.One of them main deterioration problem be due to trench corner at high electric field, wherein, electric field is produced by the local reduction of the gate oxide at these points.This results in high grid leakage current and low gate oxide breakdown voltage.This impact is proportionally reduced conducting resistance further along with trench device and becomes more violent, and along with the grid voltage requirement reduced, result in thinner gate oxide.
In one embodiment, by use, there is the dielectric material of the dielectric constant (high-k dielectrics) more than silicon dioxide and solve the integrity problem of gate oxide.So allow the starting voltage equal with the thickest electrolyte and mutual conductance.According to this embodiment, high-k dielectrics reduces grid leakage current, and adds the breakdown voltage of gate-dielectric, without reducing conducting resistance or the drain breakdown voltage of device.The hafnium of the required heat stability of display and applicable interface state density (includes A12O3、HfO2、AlxHfyOz、TiO2、ZrO2Deng) will carry out in trench gate and other power devices integrated.
As it has been described above, for the switching speed improving groove power MOSFET, it is desirable to by transistor gate-capacitance of drain CgdMinimize.Compared with trenched side-wall, thicker dielectric layer is used to be above-mentioned for reducing C at channel bottomgdOne of several methods.Relate to forming masking oxide thin layer along sidewall and the bottom of groove for forming a kind of method of the bottom oxidization layer of thickness.Then, thin oxide layer is covered by oxidation inhibiting material (such as, nitride) layer.Then, it is etched anisotropically through nitride layer so that from the horizontal bottom all of nitride of removal of groove, but the nitride layer that trenched side-wall remains coated with.After removing nitride from channel bottom, form the oxide layer with expectation thickness in the bottom of groove.Hereafter, after removing nitride layer and masking oxide from trenched side-wall, relatively thin raceway groove oxide layer is formed.This method for forming thick bottom oxidization layer and amendment thereof have carried out more detailed description in U.S. Patent No. 6,437,386 commonly assigned for Hurst et al., and entire contents is hereby incorporated by.Other relates to selective oxidation deposition and is described in the commonly assigned U.S. Patent No. 6,444,528 of Murphy for the method forming thick oxide layer at channel bottom, and entire contents is hereby incorporated by.
In one embodiment, improved method use low pressure chemical vapour deposition (SACVD) process of thick oxide layer is formed at channel bottom.According to the method, figure 52 illustrates exemplary process diagram, after etching groove (5210), SACVD for depositing the oxide layer (5220) of high conformal, such as, uses tetraethyl orthosilicate (TEOS) not have the filling groove in space in the oxide.Can from 100 torr to the low pressure of 700 torr scopes, and under conditions of the exemplary temperature scope of about 450 DEG C to about 600 DEG C perform SACVD step.Such as, TEOS (in units of mg/min) and Ozone is (with cm3/ min is unit) ratio can be arranged in the range of 2 to 3, it is therefore preferable to about 2.4.Use this technique, it is possible to formed and there is thickness about 2000 angstroms of oxide layers to 10, between 000 angstrom.Should be understood that these data for illustrative purposes only, can require according to concrete technology and other factors (such as, manufacturing the air pressure in equipment place) change.Optimum temperature can be obtained by the quality of oxide layer of balance sedimentation rate and formation.At a higher temperature, sedimentation rate slows down, and can reduce the contraction of thin layer.Such lamina shrink is so that form gap in the oxide layer of the slight crack heart in the trench.
After deposited oxide layer, deeply etch from silicon face with in groove, to form the relatively flat oxide layer (5240) with expectation thickness at channel bottom.Such as use the HF of dilution, this etching can be performed by the combination of wet etching process or wet etching and dry ecthing.Because the oxide that SACVD is formed is prone to infiltration, so it absorbs the dampness of surrounding after deposition.In a preferred embodiment, then deep etching performs compacting step 5250, to improve this effect.For example, it is possible to perform compacting step by Temperature Treatment at such as 1000 DEG C under conditions of about 20 minutes.
The method other advantages is that the ability of shield terminal groove (step 5230) during the deep etching step of SACVD oxidation, leave the terminal trenches of fill oxide.It is, for the various embodiments of above-mentioned terminal structure (including the groove of filled dielectric material), identical SACVD step may be used for terminal trenches fill oxide.Additionally, by sheltering a termination environment during deep etching, identical SACVD processes step so that form field oxide in termination environment, eliminates the most required processing step to form Thermal field oxidation layer.Additionally, process provides other motility, because owing to silicon is not over thermal oxidation loss but in the case of being arranged on two positions during SAVCD deposits and too etching, it allows the reprocessing that terminal dielectric layer is complete with thick bottom oxidization layer.
In another embodiment, for forming the another kind of method use orientation TEOS process of thick oxide layer at channel bottom.According to this embodiment, figure 53 illustrates exemplary process diagram, the conformal nature of TEOS is combined with the directional characteristic of plasma-reinforced chemical vapor deposition (PECVD), with optionally deposition oxide (5310).This combination can have more higher deposition velocity than vertical surface at horizontal surface.Such as, use the thickness that the oxide layer of this process deposits can have 2500 angstroms at channel bottom, and there is on trenched side-wall the average thickness of about 800 angstroms.Then, being isotropically etched oxide, until removing all of oxide from sidewall, retaining oxide layer at channel bottom.Etch process can include that dry top oxide etches (drytopoxideetch) step 5320, is followed by wet buffer oxide etch (BOE) step 5340.For exemplary embodiment as described herein, after the etching, retain the oxide layer with such as 1250 angstroms of thickness at channel bottom, and remove all of side wall oxide.
In a particular embodiment, the upper surface concentrating on structure uses intervention portion oxide etching, the oxide of the speed etching top area to accelerate, and to reduce the oxide of a lot of speed etched trench trench bottoms.The etching type of this referred to herein as " mist etching (fogetch) " includes that balanced etching condition and etch chemistries are to produce desired selectivity carefully.In an example, the plasma etcher (such as, LAM4400) with top power supply is used to perform this etch process under relatively low power and pressure.The example value of power and pressure can be respectively between 200-500 watt and 250-500 millitorr in the range of.Different etch chemistries can be used.In one embodiment, combination fluoride (such as, C2F6) and chlorine, best ratio the most about 5: 1 (such as, C2F6 be 190sccm, C1 be 40sccm) under mix, produce desired selectivity.Use chlorine as partial oxidation etch chemistries the most common, because chlorine is used more generally to etch metal or polysilicon, and the etching of its general inhibited oxidation thing.But, for such purpose selecting etching, this work in combination fine, because the strongest etching of C2F6 is close to the oxide of upper surface, higher energy makes C2F6 overcome the impact of chlorine, and simultaneously close to channel bottom, chlorine has slowed down etching speed.After the dry etching steps 5320 that this is main, prior to BOE etching 5340 is to remove etching 5330.Should be understood that according to this embodiment, optimal selectivity can be realized according to pressure, energy and the etch chemistries that plasma etcher changes by regulation minutely.
If it is desire to obtain the bottom oxidization layer with target thickness, can be repeated one or more times according to the PECVD/ etch process of this embodiment.This technique also makes to be formed on the level table between groove thick oxide layer.Can deposit polycrystalline silicon be etched this oxide layer after deep etching from the teeth outwards in the trench so that the oxide of protection channel bottom is from the impact of etching step subsequently.
Can have for the additive method at the selectively formed thick oxide layer of channel bottom.Figure 54 illustrates the flow chart of an illustrative methods, uses high-density plasma (HDP) deposition to prevent from being formed oxide layer (5410) on trenched side-wall.The characteristic of HDP deposition is it along with deposition etch, compared with orientation TEOS method, is formed relative to the less oxide of the oxide of channel bottom on trenched side-wall.Then, use wet etching (step 5420), to remove some on sidewall or to remove oxide, and the thick oxide layer being retained on channel bottom.As shown in fig. 55, the advantage of this technique is away from groove 5500 on the slope, side 5510 at groove top so that is more prone to realize atresia polysilicon and fills.Before polysilicon fills (step 5440), it is possible to use some oxides are etched away by above-mentioned " mist etching " (step 5430) from top so that after the polysilicon etch, less oxide needs to etch away from top.HDP deposition processes can be used for deposition oxide between two polysilicon layers in the groove (such as, having the groove MOSFET of shielded gate structure) with buried electrodes.
According to the another method shown in Figure 56, the SACVD of selection processes for forming thick oxide layer on channel bottom.The method utilizes SACVD to become selective ability at relatively low TEOS:Ozone ratio.Oxide has the slowest deposition velocity in silicon nitride, but can quickly deposit in silicon.The ratio of TEOS with Ozone is the lowest, and deposition just becomes more selective.According to the method, after etching groove (5610), the silicon face of groove array grows cushion oxide layer (5620).Then, cvd nitride thing thin layer (5630) in cushion oxide layer.It is followed by being etched anisotropically through, to denitrogenate compound layer up from horizontal plane, and retained nitrogen compound layer (5640) on trenched side-wall.Then, such as about 0.6 TEOS:Ozone ratio, under conditions of about 405 DEG C, the horizontal plane include channel bottom deposits the SACVD oxide (5650) of selection.Then, by Temperature Treatment selectively by SACVD oxide compacting (5660).Then, oxide-nitrogen-oxide etching is performed, to remove the nitride on trenched side-wall and oxide (5670).
As it has been described above, be the Q reducing and improving switching speed in the reason using thicker oxide layer bottom gate trench compared with trenched side-wallgdOr gate-drain charge.The degree of depth of identical reason appointment groove is about identical, groove superposition to be minimized in drift region with the degree of depth of trap knot.In one embodiment, thickness dielectric layer is extended to channel side by the method being used for being formed thick dielectric layer at channel bottom.This makes the thickness of bottom oxidization layer unrelated with gash depth and trap junction depth, and makes the polysilicon in groove and groove be deeper than trap knot, without increasing Qgd。
Figure 57 to Figure 59 illustrates the exemplary embodiment forming thick bottom dielectric layer according to this method.Figure 57 A is shown in it and has been etched only after covering groove sidewall, simplification that liner oxidation thin layer 5710 and nitride layer 5720 are arranged along groove and partial section view.As shown in Figure 57 B, so it is capable of the etching of cushion oxide layer 5710, the upper surface of silicon and tube core to expose channel bottom.Being followed by the anisotropic etching of exposed silicon, result is the structure as shown in Figure 58 A, and wherein, the silicon of top silicon and channel bottom all has been removed by the desired degree of depth.In an alternative embodiment, the silicon of upper surface can be sheltered so that during silicon etches, only etched trench trench bottom.It follows that execution oxidation step, to grow thick oxide layer 5730 on the position not covered by nitride layer 5720, result is the structure shown in Figure 58 B.Such as, the thickness of oxide layer can be about 1200 angstroms to 2000 angstroms.Then, remove nitride layer 5720, and etch away cushion oxide layer 5710.The etching of cushion oxide layer will cause some of thick oxide layer 5730 thinning.Remaining technique can use the flow process of standard, and to form gate electrode, trap and source junction, result is example arrangement as shown in Figure 59.
As shown in Figure 59, final grid oxic horizon includes the bottom thick-layer 5730 on the trap knot that trenched side-wall extends in district 5740.In certain embodiments, wherein, the channel doping in the well region on groove side has less alloy at drain side 5740, and this district, with compared with the district of source electrode, typically has relatively low starting voltage.Channel side along the raceway groove being added in district 5740 extends thicker oxide layer will not increase the starting voltage of device.It is, this embodiment makes optimization trap junction depth and side wall oxide optimal, with by QgdMinimize, without affecting the conducting resistance of device.Those skilled in the art should be understood that the method at channel bottom formation thick oxide layer can be applied in above-mentioned various devices, the bigrid including dhield grid, combining various charge balance structure and other trench-gate device.
Those skilled in the art is it should also be understood that any of above for forming thick oxide layer at channel bottom and can use in the technique for forming any ditch gate transistor as herein described for the technique of IPD.These techniques can be carried out other change.Such as, as combined the technique described in Figure 47 A and Figure 47 B, the chemically or physically change of silicon can strengthen its oxidation rate.According to such embodiment, halogen ionic species (such as, fluorine, bromine etc.) is injected in the silicon of channel bottom with zero degree.This injection can occur in the example energy of about 15KeV or less, more than 1E14(such as, 1E15To 5E17) Exemplary amounts and 900 DEG C to 1150 DEG C between exemplary temperature under.In the halogen injection region of channel bottom, oxide layer is with the growth rate of acceleration compared with trenched side-wall.
For the purpose of charge balance, above-mentioned multiple trench device includes that trenched side-wall adulterates.Such as, all embodiments shown in Fig. 5 B and Fig. 5 C and Fig. 6 to Fig. 9 A have trenched side-wall doped structure.There is the restriction produced due to the vertical sidewall of physical constraint restriction, deep trench and/or groove in wall doping technology.Source of the gas or angle are injected and be may be used for forming trenched side-wall doped region.In one embodiment, the trenched side-wall doping techniques of improvement uses plasma doping or pulse plasma doping techniques.The utilization of this technology is applied to the pulse voltage of the wafer being included in the plasma of dopant ion.The voltage applied accelerates ion and injects the speed of wafer from cathode sheath.The voltage applied is by impulse action, and continuous action is until realizing desired result.This technology can make many such trench devices realize conformal doping techniques.Additionally, the high-throughput of this technique reduces the total cost of manufacturing process.
It is to be appreciated that those skilled in the art that plasma doping or pulse plasma doping techniques are not limited to groove charge balance structure, it is also possible to be applied to other structures, connect including trench termination structure and groove drain electrode, source electrode or main body.Such as, the method may be used for the trenched side-wall of doping shield trenches structure (such as, those combine the structure described by Fig. 4 D, 4E, 5B, 5C, 6,7,8 and 9A).Additionally, this technology may be used for being formed the channel region of Uniform Doped.Depletion region when reverse bias power device controls to the charge concentration penetrated through on these knot both sides of channel region (p trap knot).When the doping content of epitaxial layer is the highest, the infiltration to this knot can allow break-through, to limit breakdown voltage or requirement is longer than the raceway groove of desired length to keep low conducting resistance.In order to the infiltration of raceway groove be minimized, may require that higher channel dopant concentration, so that reduce threshold value.Due to this threshold value be by source electrode in groove MOSFET below peak concentration (peakconcentration) determine, the uniform doping concentration in raceway groove can provide between channel length and breakdown voltage and preferably balance.
Additive method can be used to obtain and to obtain more uniform channel concentration, form channel junction, use multiple kinds of energy injection including use epitaxy technique and other are for forming the technology of projection knot.Another kind of technology uses the initial wafer with lightly doped protective layer.By this way, compensation is minimized, and diffuses up the channel dopant profile that may be used for being formed evenly.
Trench device can utilize threshold value be by along trenched side-wall the fact that channel dopant concentration is arranged.Allow high-dopant concentration away from groove, keep the technique of Low threshold can help prevent break-through mechanism simultaneously.There is provided the doping of p trap to make to separate trap n-type impurity (such as, boron) before gate oxidation process and enter trench oxide layer, to reduce the concentration in raceway groove, therefore reduce threshold value.This technique and above-mentioned technology are combined the raceway groove that can provide shorter without break-through.
The application of some power requires to measure the magnitude of current flowing through power transistor.Typically via isolation with measure the part of total device current, it is subsequently used for inferring that the total current flowing through device completes.Total device current of isolated part flows through electric current sensing or detection device, generates the signal representing isolation size of current, and then it is for determining total device current.This set is known mirror current source.Current sense transistor generally entirety is fabricated to two devices and shares common substrate (drain electrode) and the power device of grid.Figure 60 is the simplification figure of the MOSFET6000 with current inductor part 6002.The electric current flowing through main MOSFET6000 is divided into active area each other between main transistor and electric current induction part 6002 in proportion.Therefore, being flow through the electric current of sensing device by measurement, the ratio that then faradic current is multiplied by active area calculates the electric current flowing through main MOSFET6000.
For isolating the various methods total U.S. Patent Application No. 10/315 at entitled " the MethodofIsolatingtheCurrentSenseonPlanarorTrenchStripePo werDeviceswhileMaintainingaContinuousStripeCell " of Yedinak et al. of current inductor part from main device, being described in 719, entire contents is hereby expressly incorporated by reference.Explained below for by embodiment integrated with various power devices for sensing device, there is the device of charge balance structure including those.According to an embodiment, in the power transistor of current inductor part with charge balance structure and over all Integration, it is preferable that electric current induction zone is formed has identical continuous N OSFET structure and charge balance structure.In charge balance structure, do not keep seriality, it will owing to charge mismatch makes breakdown voltage reduce, cause voltage provide district will not be completely depleted.Figure 61 A illustrates the exemplary embodiment of the charge balance MOSFET6100 of an electric current induction structure 6115 with planar gate and isolation.In this embodiment, opposite conductivities (for p-type in this example) post 6126 formed in charge balance structure is included in drift region (N-shaped) 6104.Such as, p-type post 6126 can fill groove formation with DOPOS doped polycrystalline silicon or extension.As shown in Figure 61 A, charge balance structure keeps seriality 6115 times at electric current induction structure.The induction liner metal 6113 covering current response device 6115 surface district is separated with source metal 6116 electronically by dielectric regime 6117.Should be understood that the current inductor part with analog structure can carry out integrated with any any other power device described herein.Such as, Figure 61 B shows how current inductor part carries out integrated example with the groove MOSFET with dhield grid, can obtain charge balance by the shielding polysilicon in regulation gash depth and biasing groove.
There is the power application that diode and power transistor are integrated in same die by many expectations.Such application includes the protection of temperature sense, static discharge (ESD), source clamper and voltage division therein.Such as, for temperature sense, the diode of one or more series connection is integrally integrated with power transistor, and anode and the cathode terminal of diode is used for separating bond pad (bondpad) whereby, or uses conductive interconnection to be connected to overall control circuit parts.Temperature sensor is carried out by the change of the forward voltage (Vf) of diode.Such as, with the gate terminal of power transistor, there is suitable being connected with each other, owing to the Vf of diode is along with temperature reduction so that grid voltage is pulled low, to reduce the electric current flowing through device, until it reaches desired temperature.
Figure 62 A illustrates the exemplary embodiment of the MOSFET6200A with serial temperature sense diode.MOSFET6200A includes diode structure 6215, and wherein, the DOPOS doped polycrystalline silicon with alternating conductivity forms the temperature sense diode of three series connection.In this exemplary embodiment, the MOSFET part of device 6200A uses the Charge balance trench that the p-type extension forming opposite conductivities district in N-shaped extension drift region 6204 is filled.As shown, it is preferred that charge balance structure holding seriality below temperature sense diode structure 6215.Diode structure is formed on the top of field dielectric (oxidation) layer 6219 on silicon face top.P-type junction isolation district 6221 can be at random in 6219 times diffusions of dielectric layer.The device 6200B that this p-type is tied is not had shown in Figure 62 B.In order to confirm to obtain the diode of forward-, series biasing, use short circuit metallic 6223 with by back-biased P/N+ knot short circuit.In one embodiment, perform p+ through this knot and inject and diffusion, to form N+/P/P+/N+ structure, wherein, p+ occurs to obtain the Ohmic contact of improvement for 6223 times at short circuit metallic.For can also be through the opposite polarity N+ of N/P+ knot diffusion, to form P+/N/N+/P+ structure.Equally, it should be appreciated by those skilled in the art, such temperature sense diode can use in any one combines the various power devices of other features of many described herein.Such as, Figure 62 C illustrates the MOSFET6200C with shield trenches grid structure, and wherein, bucking electrode may be used for charge balance.
In another embodiment, by use with for isolation technology similar shown in the device 6200 of temperature sense diode, it is achieved that asymmetric ESD protection.For the purpose of ESD protection, one end of diode structure is electrically connected to source terminal, and the other end is connected to the gate terminal of device.Alternatively, as shown in Figure 63 A and 63B, connect N+/P/N+ knot by the most short-circuit any back of the body and obtain symmetrical ESD protection.Exemplary MOSFET6300A shown in Figure 63 A uses planar gate, and uses the opposite conductivities post for charge balance, and the exemplary MOSFET6300B shown in Figure 63 B is the trench-gate device with shielded gate structure.Uneven in order to prevent in charge balance, charge balance structure gate bonding pad metal and any other control extension below element bond pad.
Figure 64 A to Figure 64 D shows exemplary esd protection circuit, wherein, can be to use any charge balance or any one power device described herein of other technologies by above-mentioned diode structure protection main device, grid.Figure 64 A illustrates the simplification figure of the polysilicon diode ESD protection of symmetrical isolation, and Figure 64 B shows that the standard back of the body connects the polysilicon diode esd protection circuit of isolation.Esd protection circuit shown in Figure 64 C uses for BVcerThe fast NPN transistor recovered.BVcerIn subscript " cer " represent back-biased colelctor electrode-emitter stage bipolar transistor knot, wherein, the connection to base stage uses resistance to control base current.Low ESR makes major part emitter current be migrated by base stage, prevents EB junction from turning on, it is, inject a small amount of carrier to return colelctor electrode.Turn-on condition can be set by resistance value.When carrier is injected into return colelctor electrode, the holding voltage between emitter and collector reduces-is referred to as " recovering soon " phenomenon.Can be by adjusting base collector electrode resistance RBEValue BV is setcerRecover the electric current being triggered soon.Figure 64 D shows use thyristor or SCR and the esd protection circuit of shown diode.By using gate-cathode short-circuit structure, trigger current can be controlled.Diode breakdown voltage may be used for biasing SCR latch voltage.The diode structure of above-mentioned entirety can use in these or other any esd protection circuit.
In some power is applied, the important Performance Characteristics of device for power switching is its equivalent series resistance or measures switch terminal or the ESR of grid impedance.Such as, in the synchronous buck converter using power MOSFET, relatively low ESR contributes to reducing switching loss.In the case of trench gate mosfet, its grid ESR is largely determined by the size of the groove filling polysilicon.Such as, the length of gate trench can be limited by encapsulation restriction (such as, minimum wire bond bond pad size).It is known that polysilicon application silicide film can be reduced resistance.But, use silicide film that a lot of problem occurs in groove MOSFET.In the discrete MOS structure of typical plane, after knot has been injected into and be driven into the respective degree of depth, grid polycrystalline silicon can be silicified.The trench-gate device being recessed into for grid polycrystalline silicon, application silicide becomes more complicated.The use of conventional salicide limits maximum temperature, and wafer can stand approximately be less than the quick silicidation of 900 DEG C.When forming diffusion region (such as, source electrode, drain electrode and trap), this is provided with the biggest restriction to process for making.Most typical metal for silication is titanium.The metal of other such as tungsten, tantalum, cobalt and platinum can be used for the quick silicidation of higher heat budget, it is provided that bigger process range.Grid ESR can also be reduced by various designing techniques.
The various embodiment for forming the charge balance power switching device with lower ESR is described below.In shown in Figure 65 a embodiment, process 6500 include being formed have for shielding and/or charge balance purpose form the groove (step 6502) of relatively low electrode at lower trench.It is followed by deposition and etching IPD layer (step 6504).IPD layer can be formed by known technique.Alternatively, the technique of any of the above described a kind of combination Figure 45 to 50 may be used for forming IPD layer.It follows that in step 6506, use processes well known to deposit and etch upper electrode or grid polycrystalline silicon.It is followed by injecting and driving trap and source area (step 6508).In the step 6510 after step 6508, silicide is applied to grid polycrystalline silicon.Then, in step 6512, deposit and planarize dielectric layer.In the change of this technique, deposition and the step 6512 of planarization dielectric layer are first carried out, then after forming silicide contacts, open contact hole to arrive source/body and grid.The two embodiment relies on the heavy doping body implant area by activating less than the process annealing of silicide film transition point.
In another embodiment, polysilicon gate is replaced by metal gates.According to this embodiment, the source electrode being directed at by use is deposited such as Ti and forms metal gates, to improve the filling capacity in groove structure.After applied metal grid, once having been injected into and drive knot, dielectric selects to include HDP and TEOS, keeps apart to be contacted with source/body by grid.In an alternative embodiment, have various metal from aluminum to copper select ripple and dual damascene approach for forming gate terminal.
The layout of grid conductor can also affect the main switch speed of grid ESR and device.In another embodiment shown in Figure 66 A and 66B, vertical siliconized surfaces polysilicon stripes (stripe) and recessed trench polisilicon are combined and reduce grid ESR by topology.With reference to Figure 66 A, it is shown that highly simplified device architecture 6600, wherein, the polysilicon lines 6604 of silicide coating extends along the silicon face being perpendicular to groove strip 6602.Figure 66 B is showing along the simplification sectional view of the device 6600 of AA ' axle.Silicification polysilicon line 6604 contacts grid polycrystalline silicon at the infall with groove.Multiple silication polycrystalline lines 6604 can extend at the end face of silicon face, to reduce the resistivity of gate electrode.Such as, by having the process of two or more interconnection layers, this and other topologies are possibly realized, may be used for improving the grid ESR in any trench-gate device described herein.
Circuit is applied
Such as, due to being substantially reduced by the device on-resistance of various devices described herein and Technology offer, the chip region taken by power device can be reduced.As a result, the over all Integration of these high tension apparatus with low voltage logic and control circuit becomes more feasible.In typical circuit is applied, the various types of functions can being integrated in same die with power device include power control, sense, protect and interface circuit.Major issue in power device with other circuit over all Integrations is for by high voltage power device and low voltage logic or the technology of control circuit electric isolution.There is many known methods to realize, including junction isolation, dielectric isolation, insulator silicon (silicon-on-insulator) etc..
Below, by describe many be used for power switch electric currents application, wherein, various galvanic elements can integrated on the same chip.Figure 67 illustrates the synchronous buck converter (dc-dc) requiring lower voltage devices.In the circuit, n-channel MOSFETQ1 (being commonly called " high-side switch ") is designed as having the low on-resistance of appropriateness but has fast switching speed, with by minimum power losses.MOSFETQ2 (commonly referred to " low side switch ") is designed as having low-down conducting resistance and the high switching speed of appropriateness.Figure 68 illustrates that another arrives the dc-dc of high tension apparatus in being particularly suited for.In the circuit, main switching device Qa demonstrates fast switching speed and high blocking voltage.Because this circuit uses transformator, so less electric current flows through transistor Qa so that it has suitable conducting resistance.For synchronous rectifier Qs, it is possible to use have the MOSFET of electric capacity between low-down conducting resistance, fast switching speed, low-down QRR and low electrode.Other embodiments and this dc-dc is improved the commonly assigned U.S. Patent Application No. 10/222 of entitled " MethodsandCircuitforReducingLossesinDC-DCConverters " at Elbanhawy, being described in detail in No. 481 (acting on behalf of Reference Number 18865-91-1/17732-51430), entire contents is hereby expressly incorporated by reference.
Any one of above-mentioned various power device may be used for the MOSFET in the converter circuit of Figure 67 and 68.Such as, the bigrid MOSFET type shown in Fig. 4 A is the type providing specific advantages when being used in and realizing synchronous buck converter.In one embodiment, special driving arranges and utilizes all features provided by bigrid MOSFET.The example of this embodiment shown in Figure 69, wherein, the current potential of the first grid terminal G2 of high side MOSFETQ1 is determined by the circuit being made up of diode D1, resistance R1 and R2 and electric capacity C1.Fixed potential at the gate terminal G2 of Q1 can be adjusted to best Qgd, with the switch time of optimization transistor.The second grid terminal G1 of high side MOSFETQ1 receives normal gate from pulsewidth modulation (PWM) controller/driver (not shown) and drives signal.As it can be seen, the two of lower switching transistor Q2 gate electrodes are driven like.
In an alternative embodiment, an example shown in Figure 70 A, two gate electrodes of high-side switch are driven respectively, to make circuit performance optimum further.According to this embodiment, gate terminal G1 and G2 of different drive waveform high-side switch Q1, the conducting resistance that device is best during realizing the best switching speed of transition period and rest period.In a shown example, carry low-down Q at the transition period voltage of about 5 volts to the grid of high-side switch Q1gd, cause high switching speed, but before and after transition period td1 and td2, RDSonNot at its minimum.But, due at transition period RDSonIt not the significant side of loss, so the operation of circuit can't be had adverse effect on by this.In order to guarantee minimum R during remaining pulse persistanceDSon, current potential V at gate terminal G2g2Bring up to the second voltage Vb, wherein, the time t shown in the sequential chart of Figure 70 BpPeriod the second voltage Vb is higher than Va.This efficiency driving design to achieve optimum.To this driving design change in the U.S. Patent Application No. 10/686 of the usual registration of entitled " DriverforDualGateMOSFETs " of Elbanhawy, having carried out more detailed description in No. 859 (acting on behalf of Reference Number 17732-66930), entire contents is hereby expressly incorporated by reference.
Encapsulation technology
Major issue for all of power semiconductor is shell or the encapsulation for device is connected to circuit.Semiconductor element generally uses metallic bond coat (such as, welding) or the epoxy adhesive of filler metal is connected to metal pad.Wire typically adheres to the top of chip, then, make that projection by the main body of molding.Then, this assembling is arranged on circuit board.Shell provides the electrically and thermally connection between semiconductor chip and electronic system and surrounding thereof.Low dead resistance, electric capacity and inductance are for being capable of the desired electrical characteristics of shell being more preferably connected with chip.
The improvement of the encapsulation technology having been proposed that is concentrated mainly on the resistance and inductance reduced in encapsulation.In specific encapsulation technology, soldered ball or copper button are distributed on the metal surface of relatively thin (such as, 2-5 μm) of chip.Connecting by being distributed metal in the large area of metal surface, it is shorter that the current path in metal does, and reduces metallic resistance.As the convex side of fruit chip is connected to copper conductor frame or the copper cash being connected on printed circuit board, compared with wire bonding method, reduce the resistance of power device.
Figure 71 and 72 is shown respectively molding and the simplification sectional view of non-molding encapsulation, uses soldered ball or the copper button of the metal surface that lead frame is connected to chip.Molded package 7100 as shown in Figure 71 includes lead frame (leadframe) 7106, and it is connected to the first side of tube core 7102 by soldered ball or copper button 7104.The second side away from the tube core 7102 of lead frame 7106 is exposed by molding material.In typical Vertical power transistors, the second side of tube core forms drain terminal.Second side of tube core can form the direct electrical connection of pad on circuit boards, therefore provides low-impedance heat and power path for tube core.Such encapsulation and change thereof are in the commonly assigned U.S. Patent Application No. 10/607 of entitled " FlipChipinLeadedMoldedPackageandMethodofManufactureThere of " of Joshi et al., having carried out more detailed description in No. 633 (acting on behalf of Reference Number 18865-42-1/17732-1342), entire contents is hereby expressly incorporated by reference.
Figure 72 illustrates the non-molding embodiment of encapsulation 7200.In the exemplary embodiment shown in Figure 72, encapsulation 7200 has multilager base plate 7212, and it includes basic unit 7220 (such as, being made up of) and the metal level 7221 separated by dielectric layer 7222 metal.Welding Structure 7213 (such as, soldered ball) is connected to substrate 7212.Tube core 7211 is connected to substrate 7212, and Welding Structure 7213 is arranged on around tube core.Tube core 7211 can pass through tube core connecting material (such as, solder 7230) and be connected to substrate 7212.After encapsulation shown in being formed, it is squeezed and is arranged on circuit board (not shown) or other circuit substrates.In the embodiment that Vertical power transistors manufactures on tube core 7211, soldered ball 7230 forms drain terminal and connects, and chip surface forms source terminal.Reversion can also be realized by the connection of reversion tube core 7211 to substrate 7212 to connect.As it can be seen, encapsulation 7200 the thinnest and non-molding, so need not mould material.The commonly assigned U.S. Patent Application No. 10/235 of entitled " UnmoldedPackageforaSemiconductordevice " of Joshi it is encapsulated in for such non-molding, having carried out more detailed description in No. 249 (acting on behalf of Reference Number 18865-007110/17732-26390.003), entire contents is hereby incorporated by.
The upper surface having been proposed for chip is directly connected to the alternative of copper by solder or conductive epoxy resin.Because the stress caused between copper and silicon increases along with chip region, so the method that is directly connected to may be limited, because solder or epoxy resin interface only can be pressed that degree before destroying.On the other hand, raised pad makes to realize more replacement before destroying, and has shown that together with the biggest chip and work.
In encapsulation design, another important problem is heat radiation.The improvement of power semiconductor performance typically results in less chip region.As the power attenuation in fruit chip does not increase, then the centralized heat energy on smaller area can produce higher temperature and reliably decline.The method increasing the heat conversion ratio outside encapsulation includes reducing the quantity at hot interface, uses the material with more high-termal conductivity and the thickness reducing layer (such as, silicon, solder, tube core are fixed and tube core anchor pad).RajeevJoshi entitled " SemiconductorDiePackageWithImprovedThermalandElectricalP erformance; " commonly assigned U.S. Patent No. 6,566, No. 749 discuss the solution of heat dissipation problem, especially with respect to the tube core of the vertical power MOSFET included for RF application.For improving the other technologies commonly assigned U.S. Patent No. 6 at RajeevJoshi of total encapsulation performance, 133, No. 634 and the 6th, 469, No. 384, and the U.S. Patent Application No. 10/271,654 (acting on behalf of Reference Number 18865-99-1/17732.53440) number of entitled " ThinThermallyEnhancedFlipChipinaLeadedMoldedPackage " of Joshi et al. has been described in detail.Should be understood that any one of various power device described herein can be contained in any encapsulation described herein or any other suitable encapsulation.
Use more shell area for heat radiation also to increase shell and keep the ability of lower temperature, such as, cover top portion and the hot interface of bottom.The surface area of the increase that the air-flow around these surfaces is combined adds rate of heat dispation.Enclosure designs can also be connected with external heat sink easily.Owing to conduction of heat and Infrared Radiation Technology are commonsense methods, so the application being alternately cooled method is possible.Such as, commonly assigned U.S. Patent Application No. 10/408 at entitled " PowerCircuitryWithAThermionicCoolingSystem " of RenoRossetti, being described thermionic emission in 471 (acting on behalf of Reference Number 17732-6672) number and can be used for cooling down a kind of method of power device heat radiation, entire contents is hereby expressly incorporated by reference.
Include that the integrated of logic circuit of power output and control function brings other problems in a single package.One, shell needs more pin to be connected with other electric function.Encapsulation is specifically contemplated that being connected with each other of high current power and being connected with each other of low current signal in encapsulation.The various encapsulation technologies that can solve these problems include: chip to chip (chip-to-chip) wire bonding, to eliminate special connection pad；Stacked die (chip-on-chip), to save the space in shell；And multi-chip module, different silicon technologies is attached in Single Electron function by its permission.nullThe various embodiments of multi-chip package technology are in the commonly assigned U.S. Patent Application No. 09/730 of entitled " StackedPackageUsingFlipinLeadedMoldedPackageTechnology " of RajeevJoshi,No. 932 (acting on behalf of Reference Number 18865-50/17732-19450)，And be equally RajeevJoshi entitled " MultichipModuleIncludingSubstratewithanArrayofInterconne ctStructures " the 10/330th,No. 741 (acting on behalf of Reference Number 18865-121/17732-66650.08) are described，Entire contents is hereby expressly incorporated by reference.
Although the complete explanation to the preferred embodiment of the present invention provided above, but many to replace, revise and be equal to be all feasible.Such as, in this article, many charge balance techniques are at MOSFET, are described in the case of especially trench gate MOSFET.It is to be appreciated that those skilled in the art that in other kinds of device and transversal device that identical technology can be applied to include IGBT, thyristor, diode and plane MOSFET.Therefore, for these and other reasons, above description is not intended to limit the scope of the invention defined by the claims.

Claims (12)

1. for forming a device for buried conductive layer in forming groove on a semiconductor substrate, including:
Active groove；
First grid polysilicon segment, is arranged in described active groove；
Second grid polysilicon segment, is arranged in described active groove；And
Bucking electrode, is arranged in described active groove, and described bucking electrode is arranged between described first grid polysilicon segment and described second grid polysilicon segment；
Wherein, described first grid polysilicon segment and described second grid polysilicon segment cover dielectric materials layer；
Described bucking electrode is shielding polysilicon, by etching screen oxide, forms the first groove and form the second groove on the second side of described shielding polysilicon on the first side of described shielding polysilicon；
Described first groove and the sidewall of the second groove and diapire are formed grid oxic horizon；
Described first grid polysilicon segment and described second grid polysilicon segment is formed in described first groove being formed with described grid oxic horizon and described second groove.
Device the most according to claim 1, wherein, described bucking electrode extends vertically on a part for described active groove until a silicon face.
Device the most according to claim 1, wherein, described bucking electrode extends vertically on a part for described active groove.
Device the most according to claim 1, wherein, described first grid polysilicon segment and described second grid polysilicon segment electrically connect in the third dimension.
Device the most according to claim 1, wherein, described first grid polysilicon segment and described second grid polysilicon segment electrically connect in the trench.
6. for the method forming buried conductive layer in forming groove on a semiconductor substrate, including:
Form groove in a substrate；
Form screen oxide in the trench；
Form shielding polysilicon in the trench；
Etch described screen oxide so that on the first side of described shielding polysilicon, form the first groove and form the second groove on the second side of described shielding polysilicon；
Described first groove and the sidewall of the second groove and diapire are formed grid oxic horizon；
Gate oxide level is formed on described first groove in described substrate and the top of described shielding polysilicon and described groove and the sidewall of described second groove and diapire；And
Grid polycrystalline silicon is formed in each being formed with described first groove of described grid oxic horizon and described second groove；
Wherein, described grid polycrystalline silicon covers dielectric materials layer.
Method the most according to claim 6, farther includes:
Make described grid polycrystalline silicon recessed.
Method the most according to claim 6, farther includes:
Before the described screen oxide of described etching, a part for described shielding polysilicon is made to expose.
Method the most according to claim 6, farther includes:
Etch described shielding polysilicon so that described shielding polysilicon is recessed at described groove.
Method the most according to claim 6, farther includes:
Formation trap injects；
Formation source electrode injects；
Form heavy doping main body to inject.
11. 1 kinds of semiconductor device, including:
Drift region, has the first conduction type；
Well region, extends on described drift region and has second conduction type contrary with described first conduction type；
Multiple active grooves, extend through described well region and enter described drift region, and the plurality of active groove limits an active area, is formed in each of the plurality of active groove:
First conductive gate electrode, is arranged in the first groove and by being formed at the grid oxic horizon on the sidewall of described first groove and diapire and described first channel insulation；
Second conductive gate electrode, is arranged in the second groove and is insulated with described second trenched side-wall by the grid oxic horizon being formed on the sidewall of described second groove and diapire；And
Conductive shielding electrode, is arranged between described first conductive gate electrode and described second conductive gate electrode, and described bucking electrode extends deeper in described groove compared to described first conductive gate electrode and described second conductive gate electrode and is insulated from；And
Source area, described source area has described first conduction type, in described source area is formed at described well region and adjacent to the plurality of active groove；
Wherein, described first conductive gate electrode and described second conductive gate electrode cover dielectric materials layer.
12. 1 kinds of methods forming buried conductive layer in the multiple grooves in semiconductor substrate, including:
Along the sidewall of each in the plurality of groove and bottom, the first dielectric materials layer is set；
The plurality of trench fill there is the first conductive material layer；
In the groove of each part exposing the first conductive material layer, from the upper surface of described substrate and the described sidewall of the plurality of groove, described first dielectric materials layer is removed to first degree of depth, and the part that described first conductive material layer is exposed forms two grooves in each groove；
Applying the surface of the described exposed portion of the second dielectric materials layer covering described upper surface of described substrate, the described sidewall of each groove and described first conductive material layer, described second dielectric materials layer covers sidewall and the diapire of described two grooves in each groove；
It is filled with the second conductive material layer in the said two groove being coated with described second dielectric materials layer in each groove；And
Described second conductive material layer is covered with the 3rd dielectric materials layer.
CN201310060514.1A 2003-12-30 2004-12-28 Form buried conductive layer method, material thickness control methods, form transistor method Expired - Fee Related CN103199017B (en)

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