CN104733535A - Power MOSFET - Google Patents

Abstract

The invention provides a power MOSFET, comprising: a substrate; an epitaxial layer, the epitaxial layer covers the substrate; a source doped region, the source doped region is located in the epitaxial layer; a well area, the well area is located in the epitaxial layer and located in the source doped Below the heterogeneous region; polycrystalline source, the polycrystalline source is surrounded by the epitaxial layer and located below the chip surface; multiple floating electrodes, the floating electrodes are surrounded by the epitaxial layer and located under the polycrystalline source; capacitor dielectric layer, capacitor dielectric The layer is located between the floating electrodes, between the floating electrode and the polycrystalline source, and between the floating electrode and the epitaxial layer at the bottom; and the sidewall dielectric layer, the sidewall dielectric layer is located between the epitaxial layer and the polycrystalline source Between the electrodes, and between the epitaxial layer and the floating electrodes. The power MOSFET combines the advantages of CC-MOSFET and SJ-MOSFET.

Description

A power MOSFET

technical field

The invention relates to the field of semiconductors, in particular to a power MOSFET.

Background technique

In the field of power semiconductors, a vertical metal-oxide semiconductor field effect transistor (MOSFET for short) formed by a vertical double diffusion process is called a VDMOSFET, or VDMOS for short. Because of its fast switching speed, high input impedance, and good frequency characteristics, it has been widely used. For traditional VDMOS, the breakdown voltage is generally increased by increasing the thickness of the epitaxial layer and reducing the doping concentration of the epitaxial layer. However, as the breakdown voltage increases, this method will significantly increase the resistance of the epitaxial layer. Studies have shown that there is a limit between the on-resistance and the breakdown voltage-called "silicon limit", making the on-resistance Cannot be lowered any further. Many device design methods have broken through this limit. For example, the insulated gate bipolar transistor (IGBT for short) device reduces the on-state resistance by injecting minority carriers into the epitaxial layer. Another type of technology uses the principle of charge balance. By introducing a lateral electric field into the epitaxial layer, the distribution of the vertical electric field is transformed from a triangle to a trapezoidal distribution, and the dependence between the breakdown voltage and the doping concentration is weakened to reduce the on-resistance. . Two commonly used techniques for introducing a lateral electric field include a charge balance insulated gate field effect transistor (CC-MOSFET for short) and a super junction field effect transistor (SJ-MOSFET for short).

CC-MOSFET was proposed by B. Jayant Baliga in 1995. By adding a source field plate or a gate field plate that runs through the entire drift region in the epitaxial layer, when the device is in the blocking state, all charges in the space charge region Balanced by the field plate, the purpose of transforming the longitudinal electric field into a trapezoidal distribution is achieved. Because this structure can be well integrated with the trench gate process, this device structure is widely used in the design of medium and low voltage power trench insulated gate field effect transistors (referred to as Trench MOSFET).

However, since the field plate running through the drift region is usually a source electrode or a gate electrode, this structure has two obvious defects in the design of a high-voltage structure. This is because the potential in the drift region changes with the longitudinal position. On the one hand, the potential difference between the drift region and the field plate at different longitudinal positions changes, and it is difficult to achieve a complete charge balance. With the increase of the breakdown voltage, this imbalance will cause the longitudinal electric field to seriously deviate from the trapezoidal distribution. This structure does not improve the on-resistance significantly. On the other hand, the dielectric layer near the drain of the field plate bears the entire source-drain voltage. In order to ensure that the dielectric layer does not break down in advance, its thickness will become thicker and thicker as the breakdown voltage of the device increases. This will cause its cell density to not be as large as that of low-voltage devices, and it will also affect the reduction of on-resistance.

SJ-MOSFET achieves charge balance through alternating PN structures in the drift region. When the device is in the blocking state, the charges in the P region and the N region are completely balanced, thereby realizing the purpose of transforming the vertical electric field into a trapezoidal distribution. As the vertical position changes, the potential difference between the P region and the N region is basically stable, so theoretically there is no phenomenon that the cell width increases with the increase of the breakdown voltage in the SJ-MOSFET.

However, SJ-MOSFETs are manufactured by multiple epitaxy or groove backfilling, and the higher the aspect ratio, the more difficult the process is, which restricts the reduction of cell density and affects the further improvement of on-resistance.

Therefore, there is a need for a power MOSFET that can reduce the on-resistance and overcome the shortcomings of the above-mentioned CC-MOSFET and SJ-MOSFET.

Contents of the invention

The present invention aims to solve the problems described above. The object of the present invention is to provide a power MOSFET which combines the advantages of CC-MOSFET and SJ-MOSFET.

According to one aspect of the present invention, a power MOSFET is provided, and the power MOSFET includes:

Substrate;

an epitaxial layer covering the substrate;

a source doped region located within the epitaxial layer;

a well region within the epitaxial layer and below the source doped region;

a polycrystalline source surrounded by the epitaxial layer and located below the surface of the chip;

a plurality of floating electrodes, the floating electrodes are surrounded by the epitaxial layer and located under the polycrystalline source;

Capacitive dielectric layer, the capacitive dielectric layer is located between the floating electrodes, between the floating electrodes and the polycrystalline source, and between the lowermost floating electrodes and the epitaxial layer ;as well as

A sidewall dielectric layer, the sidewall dielectric layer is located between the epitaxial layer and the polycrystalline source, and between the epitaxial layer and the floating electrode.

Wherein, the length of the floating electrode is 0.5um-8um, and the width is 0.5um-2um.

Wherein, the number of the floating electrodes is 1-20.

Wherein, the lengths of the plurality of floating electrodes are the same.

Wherein, the thickness of the capacitor dielectric layer is 10nm-500nm, and the material of the capacitor dielectric layer is SiO ₂ or Si ₃ N ₄ .

Wherein, the thickness of the sidewall dielectric layer is 100nm˜800nm, and the material of the sidewall dielectric layer is SiO ₂ or Si ₃ N ₄ .

Wherein, the power MOSFET also includes:

A source contact hole that passes through the source doped region and goes deep into the inside of the well region;

surrounded by the epitaxial layer, a polycrystalline gate located below the surface of the chip and above the polycrystalline source;

a gate oxide layer between the epitaxial layer and the polycrystalline gate;

an isolation dielectric layer between the polycrystalline gate and the polycrystalline source;

a surface oxide layer located above the polycrystalline gate and the source doped region;

a metal source electrode on the surface of the chip; and

A metal drain electrode located below the substrate.

In the power MOSFET with multi-layer floating structure of the present invention, a plurality of floating electrodes, capacitor dielectric layers and sidewall dielectric layers are added under the polycrystalline source electrode in the drift region of the epitaxial layer, thereby forming a series of power MOSFETs connected in series to the source electrode. Capacitance between the drain and the drain to achieve charge balance in the blocking state. In addition, the power MOSFET of the present invention only needs to increase the thickness of the epitaxial layer and the number of floating electrodes, which overcomes the disadvantages of high-voltage structure design of CC-MOSFET. At the same time, the power MOSFET of the present invention has little modification to the existing CC-MOSFET manufacturing process, and is compatible with the traditional Trench MOSFET process. Therefore, the power MOSFET provided by the present invention has both the advantages of CC-MOSFET and SJ-MOSFET.

Other features and advantages of the present invention will become apparent from the following description of exemplary embodiments read with reference to the accompanying drawings.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate the embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings, like reference numerals are used to denote like elements. The drawings in the following description are some, but not all, embodiments of the present invention. Those skilled in the art can obtain other drawings based on these drawings without creative efforts.

Fig. 1 exemplarily shows a schematic structural view of a power MOSFET according to the present invention;

Fig. 2 exemplarily shows an equivalent model of a power MOSFET according to the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

A schematic diagram of a layer structure according to an embodiment of the invention is shown in the drawing. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

In the power MOSFET proposed by the present invention, multiple floating electrodes, capacitor dielectric layers and sidewall dielectric layers are added under the polycrystalline source electrode in the drift region of the epitaxial layer, thereby forming a series of capacitors connected in series between the source electrode and the drain electrode. , to achieve charge balance in the blocking state. The power MOSFET includes: a substrate; an epitaxial layer covering the substrate; a source doped region located in the epitaxial layer; a well region located in the epitaxial layer and below the source doped region; surrounded by the epitaxial layer and located below the chip surface The polycrystalline source; the floating electrode surrounded by the epitaxial layer and located below the polycrystalline source; between the floating electrodes, between the floating electrode and the polycrystalline source, and the floating electrode and the epitaxial layer at the bottom The capacitance dielectric layer between them; and the sidewall dielectric layer between the epitaxial layer and the polycrystalline source, and between the epitaxial layer and the floating electrode.

The power MOSFET according to the present invention will be described in detail below with reference to the accompanying drawings.

Fig. 1 shows a schematic diagram of the structure of a power MOSFET according to the present invention. As shown in FIG. 1 , the power MOSFET includes a substrate 101; an epitaxial layer 102 covering the substrate 101; a source doped region 104 located in the epitaxial layer 102; a well located in the epitaxial layer 102 and below the source doped region 104 Region 103; the polycrystalline source 112 surrounded by the epitaxial layer 102 and located below the chip surface; the floating electrode 115 surrounded by the epitaxial layer 102 and located below the polycrystalline source 112; located between the floating electrodes 115, the floating electrode 115 and the polycrystalline source 112, and the capacitive dielectric layer 108 between the lowermost floating electrode 115 and the epitaxial layer 102; The sidewall dielectric layer 106 between the empty electrodes 115 .

The substrate 101 is of the first conductivity type, the epitaxial layer 102 is of the first conductivity type, the source doped region 104 is of the first conductivity type, the well region 103 is of the second conductivity type, and the polycrystalline source 112 is of the first conductivity type. The floating electrodes 115 are generally of the first polycrystalline conductivity type, but may be of the second conductivity type, and may even be metal electrodes.

In the epitaxial layer 102, a plurality of floating electrodes 115 are formed below the polycrystalline source electrode 112; between the uppermost floating electrode 115 and the polycrystalline source electrode 112 above it, between adjacent floating electrodes 115 and at the uppermost A capacitive dielectric layer 108 is formed between the lower floating electrode 115 and the lower epitaxial layer 102; sidewall dielectric layer 106 . The floating electrodes 115 , the capacitor dielectric layer 108 and the sidewall dielectric layer 106 form a series of capacitors connected in series between the source and the drain. Through the voltage-dividing action of these capacitances, a field plate is formed whose potential varies with longitudinal position. When the device is in the blocking state, the potential difference between the drift region and the field plate is basically uniform at different longitudinal positions, thereby achieving complete charge balance.

The length of the floating electrode 115 is generally 0.5um-8um, and the width is related to the technology level, generally 0.5um-2um. The lengths of the multiple floating electrodes 115 may be the same or different, and FIG. 1 is an example in which the lengths of the floating electrodes 115 are the same. In the case that the lengths of the floating electrodes 115 are different, the lengths may also be gradually changed. When the lengths of the floating electrodes 115 are different, in order to achieve charge balance, a certain process tolerance can be allowed in the manufacture of the power MOSFET. The length of each floating electrode 115 can be designed according to design requirements and process conditions. In addition, the number of floating electrodes 115 to be formed is related to the breakdown voltage of the device, and generally ranges from 1 to 20. The more the number of floating electrodes 115 formed, the higher the breakdown voltage of the device.

The capacitor dielectric layer 108 can be made of various materials such as SiO ₂ or Si ₃ N ₄ , and its thickness is 10 nm˜500 nm. The sidewall dielectric layer 106 can be made of various materials such as SiO ₂ or Si ₃ N ₄ , with a thickness of 100 nm˜800 nm. According to the thickness of the capacitor dielectric layer 108 and the thickness of the sidewall dielectric layer 106 , it can be seen that the capacitance of the formed sidewall dielectric layer 106 is smaller than the capacitance of the capacitor dielectric layer 108 .

Referring again to FIG. 1 , the power MOSFET may further include: a source contact hole 109 passing through the source doped region 104 and deep inside the well region 103; surrounded by the epitaxial layer 102, located below the chip surface, and a polycrystalline source 112 The upper polycrystalline gate 113; the gate oxide layer 105 between the epitaxial layer 102 and the polycrystalline gate 113; the isolation dielectric layer 107 between the polycrystalline gate 113 and the polycrystalline source 112; The surface oxide layer 110 above the electrode 113 and the source doped region 104 ; the metal source electrode 111 located on the chip surface; and the metal drain electrode 114 located below the substrate 101 .

Fig. 2 is an equivalent model of a power MOSFET according to the present invention. Fig. 2 illustrates the principle that the power MOSFET realizes the charge balance in the blocking state. In FIG. 2 , it is taken as an example to include five floating electrodes 115 with the same length. Wherein, it is assumed that the capacitance of the capacitor dielectric layer 108 is C ₁ , and the capacitance of the sidewall dielectric layer 106 is C ₂ . Complete charge balancing is achieved when capacitor _C1 is much larger than capacitor _C2 . When the device bears a relatively high reverse voltage, the potentials of the five floating electrodes 115 in FIG. 2 are: V _d /6, V _d /3, V _d /2, 2V _d /3, and 5V _d /6. These floating electrodes 115 completely deplete their corresponding epitaxial layers of different depths through the coupling effect of the capacitor C ₂ , forming a trapezoidal electric field distribution in the longitudinal direction, thereby achieving the purpose of reducing the on-resistance.

When designing a device with a higher breakdown voltage, the structure of the power MOSFET of the present invention is similar to that of the SJ-MOSFET, only the thickness of the epitaxial layer and the number of floating electrodes need to be increased, which overcomes the high voltage structure of the CC-MOSFET design Shortcomings. At the same time, the power MOSFET of the present invention has little modification to the existing CC-MOSFET manufacturing process, and is compatible with the traditional Trench MOSFET process. Therefore, the power MOSFET provided by the present invention has both the advantages of CC-MOSFET and SJ-MOSFET.

The content described above can be implemented alone or combined in various ways, and these variants are all within the protection scope of the present invention.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a" does not exclude the presence of additional same elements in the process, method, article or apparatus comprising said element.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various means in the prior art can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. The present invention has been described above with reference to the embodiments of the present invention. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present invention, and these substitutions and modifications should all fall within the scope of the present invention.

Claims (7)

1. A power MOSFET, characterized in that, the power MOSFET comprises: Substrate (101); an epitaxial layer (102), the epitaxial layer (102) covering the substrate (101); a source doped region (104), the source doped region (104) located within the epitaxial layer (102); a well region (103), the well region (103) is located within the epitaxial layer (102) and below the source doped region (104); a polycrystalline source (112) surrounded by the epitaxial layer (102) and located below the chip surface; a plurality of floating electrodes (115), the floating electrodes (115) are surrounded by the epitaxial layer (102) and located below the polycrystalline source (112); a capacitor dielectric layer (108), the capacitor dielectric layer (108) is located between the floating electrodes (115), between the floating electrodes (115) and the polycrystalline source (112), and is located between the lowermost floating electrode (115) and the epitaxial layer (102); and A sidewall dielectric layer (106), the sidewall dielectric layer (106) is located between the epitaxial layer (102) and the polycrystalline source (112), and the epitaxial layer (102) and the floating Between empty electrodes (115). 2. The power MOSFET according to claim 1, characterized in that, the length of the floating electrode (115) is 0.5um-8um, and the width is 0.5um-2um. 3. The power MOSFET according to claim 1, characterized in that, the number of said floating electrodes (115) is 1-20. 4. The power MOSFET according to claim 1, characterized in that the lengths of the plurality of floating electrodes (115) are the same. 5. The power MOSFET according to claim 1, characterized in that, the thickness of the capacitor dielectric layer (108) is 10 nm to 500 nm, and the material of the capacitor dielectric layer (108) is SiO ₂ or Si ₃ N ₄ . 6. The power MOSFET according to claim 1, characterized in that, the thickness of the sidewall dielectric layer (106) is 100 nm to 800 nm, and the material of the sidewall dielectric layer (106) is SiO ₂ or Si ₃ N ₄ . 7. The power MOSFET according to claim 1, wherein the power MOSFET further comprises: A source contact hole (109) penetrating through the source doped region (104) and deep inside the well region (103); Surrounded by the epitaxial layer (102), a polycrystalline gate (113) located below the chip surface and above the polycrystalline source (112); a gate oxide layer (105) located between the epitaxial layer (102) and the polycrystalline gate (113); an isolation dielectric layer (107) between the polycrystalline gate (113) and the polycrystalline source (112); a surface oxide layer (110) located above the polycrystalline gate (113) and the source doped region (104); a metal source electrode (111) on the surface of the chip; and A metal drain electrode (114) located under the substrate (101).