JP5195357B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device. In particular, the present invention relates to a vertical semiconductor device in which a surface electrode is disposed on the surface of a semiconductor substrate and a back electrode is disposed on the back surface of the semiconductor substrate.

  In recent years, semiconductor devices capable of controlling a large current such as a power MOS (Metal Oxide Semiconductor) have been developed. In general, there is a trade-off between increasing the breakdown voltage and reducing the on-resistance of a semiconductor device. For this reason, in the semiconductor device, when the breakdown voltage is increased, the on-resistance increases, and when the on-resistance is decreased, the breakdown voltage tends to decrease.

  Patent Document 1 describes a power MOS that has successfully achieved both high breakdown voltage and low on-resistance. FIG. 28A shows a cross-sectional view of the power MOS 600. The power MOS 600 includes a front surface electrode 218 disposed on the surface of the semiconductor substrate 224 and a back surface electrode 226 disposed on the back surface of the semiconductor substrate 224, and is a vertical type. A source region 220, a body region 214, a body contact region 216, a drift region 204, and a drain region 202 are disposed in the semiconductor substrate 224. The source region 220 is of the first conductivity type (n-type), is disposed on the surface side of the semiconductor substrate 224, and is electrically connected to the surface electrode 218. The drift region 204 is of the first conductivity type (n-type), is disposed on the back side of the semiconductor substrate 224, and is electrically connected to the back electrode 226 via the drain region 202 of the first conductivity type (n-type). ing. Body region 214 is of the second conductivity type (p-type) and separates source region 220 and drift region 204. The body contact region 216 contains the second conductivity type (p-type) impurity at a high concentration, and stabilizes the potential of the body region 214 by the potential of the surface electrode 218. The drain region 202 contains a first conductivity type (n-type) impurity in a high concentration, and decreases the contact resistance with the back electrode 226. In the semiconductor substrate 224, a trench 211 extending from the surface of the semiconductor substrate 224 through the source region 220 and the body region 216 until reaching the drift region 204 is disposed. An insulating film 222 a is disposed in the deep part of the trench 211. A gate electrode 212 is disposed in the shallow portion of the trench 211. The wall surface of the gate electrode 212 is covered with an insulating film 222b. The gate electrode 212 extends to a position deeper than the bottom surface 214a of the body region 204. In order to improve the breakdown voltage performance, a second conductivity type (p-type) impurity-containing region 206 is disposed in a range surrounding the bottom surface 211a of the trench 211. The impurity containing region 206 is disposed in the drift region 204. The gate electrode 212 is disposed only in a shallow portion in the drift region 204, and the bottom surface 212a of the gate electrode 212 and the impurity-containing region 206 are separated by an insulating film 222a.

When the profile in the depth direction of the electric field (V / cm) generated when the power MOS 600 is turned off is examined, as shown in FIG. 28B, the first one has a depth matching the bottom surface 212a of the gate electrode 212. It can be seen that it has a peak and has a second peak at a depth D1 near the lower portion of the impurity-containing region 206.
If the impurity-containing region 206 is not formed, an electric field intensity profile having only one peak at a depth matching the bottom surface 212a of the gate electrode 212 is obtained. The breakdown voltage of the semiconductor device is higher as the area shown by the hatch in FIG. When the impurity-containing region 206 is arranged so that two peaks are formed, a high breakdown voltage can be secured. On the other hand, if the required breakdown voltage is the same, the impurity concentration in the drift region 204 can be increased by arranging the impurity-containing region 206. If the impurity concentration in the drift region 204 can be increased, the on-resistance of the power MOS 600 is lowered. Since the power MOS 600 includes the impurity-containing region 204, it has succeeded in reducing the on-resistance while ensuring a necessary breakdown voltage. Note that a curve L indicated by a broken line in FIG. 28B represents an electric field intensity profile when the breakdown voltage and the on-resistance are theoretical limit values in the semiconductor device. Therefore, the closer the electric field intensity profile results to the shape of the curve L, the closer the breakdown voltage and the on-resistance approach the theoretical limit values.

FIG. 29 shows a trade-off relationship between breakdown voltage and on-resistance in a trench gate type power MOS. The vertical axis | shaft of FIG. 29 shows on-resistance (mohm * mm < ² >). The horizontal axis in FIG. 29 indicates the breakdown voltage (V). The curve in FIG. 29 shows a theoretical curve representing the theoretical limits of withstand voltage and on-resistance. It can be seen that increasing the breakdown voltage increases the on-resistance.
The conventional structure A shows a measured value of a trench gate type power MOS in which no impurity-containing region is formed. Conventional structure B shows the measured value of power MOS 600. When the required breakdown voltage is equal, the conventional structure B can reduce the on-resistance of the conventional structure A by about 60%. In the conventional structure B shown in FIG. 28, both high breakdown voltage and low on-resistance can be achieved as compared with the conventional semiconductor device.

JP-A-2005-116822

  However, in the structure of FIG. 28, a valley is formed between two peaks in the electric field intensity profile in the depth direction. For this reason, if the electric field intensity profile can be brought close to the curve L shown in FIG. 28B by reducing the depth of the valley, further increase in breakdown voltage and reduction in on-resistance should be realized. . Note that if the depth of the impurity-containing region 206 is reduced, the depth of the valley formed between the two peaks can be reduced. However, when the depth at which the impurity-containing region 206 is disposed is reduced, the drift region 204 between the body region 214 and the impurity-containing region 296 is narrowed. For this reason, when the power MOS 600 is turned on, there is a problem that an effective passing region for carriers flowing while bypassing the impurity-containing region 206 is restricted, thereby increasing the on-resistance.

  The present invention has been proposed for the above problems. The present invention provides a vertical semiconductor device that combines high breakdown voltage and low on-resistance by reducing the depth of a valley formed between two peaks of an electric field intensity profile without increasing the on-resistance. The purpose is to provide.

The technology disclosed in this specification relates to a vertical semiconductor device in which a surface electrode is disposed on the surface of a semiconductor substrate and a back electrode is disposed on the back surface of the semiconductor substrate.
One embodiment of a semiconductor device disclosed in this specification includes a body region, a drift region, a trench, an impurity-containing region, a gate electrode, and a floating electrode in a semiconductor substrate.
The body region is of the second conductivity type and is disposed on the surface side of the semiconductor substrate.
The drift region is of the first conductivity type and is disposed at a position deeper than the body region in the semiconductor substrate.
The trench extends from the surface of the semiconductor substrate to the drift region through the body region.
The impurity-containing region is of the second conductivity type and is disposed in a range surrounding the bottom surface of the trench. The center of the impurity-containing region is disposed at a position deeper than the intermediate depth of the drift region.
The gate electrode is disposed in the trench, and the wall surface is covered with an insulating film. The gate electrode extends to a position deeper than the bottom surface of the body region.
The floating electrode is disposed deeper than the gate electrode in the trench, and the wall surface is covered with an insulating film.
In the semiconductor device, a plurality of floating electrodes are arranged in the depth direction at intervals deeper than the gate electrode in the trench. The interval between the floating electrodes decreases geometrically along the depth direction.

Another form of semiconductor device disclosed in this specification includes a body region, a drift region, a trench, an impurity-containing region, a gate electrode, and a floating electrode in a semiconductor substrate.
The body region is of the second conductivity type and is disposed on the surface side of the semiconductor substrate.
The drift region is of the first conductivity type and is disposed at a position deeper than the body region in the semiconductor substrate.
The trench extends from the surface of the semiconductor substrate to the drift region through the body region.
The impurity-containing region is of the second conductivity type and is disposed in a range surrounding the bottom surface of the trench. The center of the impurity-containing region is disposed at a position deeper than the intermediate depth of the drift region.
The gate electrode is disposed in the trench, and the wall surface is covered with an insulating film. The gate electrode extends to a position deeper than the bottom surface of the body region.
The floating electrode is disposed deeper than the gate electrode in the trench, and the wall surface is covered with an insulating film.
In the above semiconductor device, in the electric field intensity profile in the depth direction, two peaks are formed at a depth matching the bottom surface of the gate electrode and a depth near the lower portion of the impurity-containing region, and the depth at which the floating electrode is disposed. In this case, high electric field strength is maintained. Since the floating electrode is disposed in the trench between the gate electrode and the impurity-containing region, the depth of the valley formed between the two peaks can be reduced. For this reason, the area of the range surrounded by the profile curve can be widened, and the breakdown voltage of the semiconductor device can be increased.
In addition, since the center of the impurity-containing region is formed at a position deeper than the intermediate depth of the drift region, the distance between the body region and the impurity-containing region is sufficiently large. For this reason, the carrier passing through the body region along the trench can sufficiently secure an effective passing region for carriers to flow to the back electrode while bypassing the impurity-containing region, thereby suppressing an increase in on-resistance. Can do.
According to the semiconductor device described above, a high breakdown voltage and a low on-resistance can be realized.

In the above semiconductor device, it is preferable that the thickness of the insulating film covering the side wall of the floating electrode is larger than the thickness of the insulating film covering the side wall of the gate electrode.
Compared with silicon or the like used as a material for a semiconductor substrate, silicon oxide or the like used as a material for an insulating film has a higher electric resistance. In the region where the electrical resistance is high, the potential gradient (electric field strength) increases. For this reason, as the thickness of the insulating film having high electrical resistance increases, the potential difference along the width direction of the insulating film increases, and the potential difference of the silicon layer on the side of the insulating film decreases. When the potential difference of the silicon layer on the side of the insulating film is reduced, the electric field strength generated in the silicon layer on the side of the insulating film is reduced. According to the above configuration, by increasing the thickness of the insulating film covering the sidewall of the floating electrode, the electric field strength of the silicon layer (drift region) generated on the side of the floating electrode when the semiconductor device is turned off is reduced. can do. Thereby, the shape of the electric field intensity profile can be brought close to the curve L shown in FIG. 28B while keeping the balance of the two peaks. The breakdown voltage of the semiconductor device can be further increased.

In the above-described semiconductor device, the drift region is adjacent to the body region at a deep position and has a high impurity concentration, and the first conductivity type high concentration region is adjacent to the high concentration region at a deep position, and more impurity than the high concentration region. It is preferable to provide a low concentration region of the first conductivity type having a low concentration.
In the carrier passage region formed when the semiconductor device is turned on, the carrier resistance can be reduced by increasing the impurity concentration of the first conductivity type. According to the above configuration, when the semiconductor device is turned on, carriers flow more easily in the carrier passage region formed in the high concentration region than in the carrier passage region formed in the low concentration region. For this reason, carriers that have passed through the body region along the trench can be quickly supplied to the back electrode, and the on-resistance of the semiconductor device can be further reduced.

In the above semiconductor device, it is preferable that the dielectric constant of the insulating film covering the side wall of the gate electrode is higher than the dielectric constant of the insulating film covering the side wall of the floating electrode.
According to this configuration, by increasing the dielectric constant of the insulating film covering the side wall of the gate electrode, the resistance of the channel formed in the body region on the side of the gate electrode can be reduced when the semiconductor device is turned on. Can do. Thereby, the on-resistance of the semiconductor device can be further reduced.
On the other hand, when the dielectric constant of the insulating film covering the side wall of the gate electrode is increased, the breakdown voltage is lowered. As a result, the breakdown voltage of the semiconductor device is reduced. In the above semiconductor device, by reducing the dielectric constant of the insulating film covering the side wall of the floating electrode, carriers are less likely to flow in the reverse direction at the depth where the floating electrode is disposed when the semiconductor device is off. For this reason, it can suppress that a breakdown voltage falls.

In the semiconductor device described above, a plurality of floating electrodes are arranged at intervals in a deep position in the trench, and the intervals between the floating electrodes are reduced geometrically along the depth direction. preferable.
According to this configuration, since the floating electrode is divided into a plurality of portions, the magnitude of the electric field strength generated on the side of the floating electrode by adjusting the positions of the plurality of floating electrodes is stepwise along the depth direction. Can be adjusted. Thereby, the electric field strength profile can be adjusted. Further, when the distance between adjacent floating electrodes is reduced in a geometric series, the electric field strength profile can be effectively adjusted along the depth direction of the trench. For this reason, the shape of the electric field strength profile can be brought close to the curve L shown in FIG. 28B, and the breakdown voltage of the semiconductor device can be further increased.

In the above semiconductor device, it is preferable that the thickness of each insulating film covering the side walls of the plurality of floating electrodes is increased along the depth direction.
By changing the thickness of the insulating film, the electric field strength of the silicon layer (drift region) on the side of the floating electrode can be adjusted. Therefore, the thickness of each insulating film covering the side surfaces of the plurality of floating electrodes can be adjusted so that the shape of the electrolytic strength profile in the depth direction approaches the curve L in FIG. Thereby, the breakdown voltage of the semiconductor device can be further increased.

  According to the present invention, the breakdown voltage and on-resistance of the semiconductor device can be brought close to a theoretical curve. As a result, a semiconductor device having both a high breakdown voltage and a low on-resistance can be realized.

Preferred features of the embodiments described below are listed.
(First Feature) The drift region includes a plurality of regions having different impurity concentrations along the depth direction, and the impurity concentration of each region is lowered along the depth direction.
(Second feature) LP-TEOS is used as a kind of silicon oxide film.
(Third feature) Polysilicon is used as a material for the gate electrode and the floating electrode.
(Fourth feature) The interval between the gate electrode and the floating electrode is adjusted according to the concentration of the drift region and the required breakdown voltage.
(Fifth feature) The upper end of the impurity-containing region is formed at a position shallower than the intermediate depth of the drift region.

(First embodiment)
FIG. 1 shows a cross-sectional view of a vertical power MOS (claimed semiconductor device) 100 according to the first embodiment, and a graph showing an electric field intensity profile in the power MOS 100.
The power MOS 100 includes a source electrode (front electrode in the claims) 18 disposed on the surface of the semiconductor substrate 24 and a drain electrode (back electrode in the claims) 26 disposed on the back surface of the semiconductor substrate 24. ing. A source region 20, a body region 14, a body contact region 16, a drift region 4, and a drain region 2 are arranged in the semiconductor substrate 24. The source region 20 is of the first conductivity type (n-type), is disposed on the surface side of the semiconductor substrate 24, and is electrically connected to the source electrode 18. The drift region 4 is of the first conductivity type (n-type), is disposed inside the semiconductor substrate 24, and is electrically connected to the drain electrode 26 via the drain region 2 of the first conductivity type (n-type). Yes. Body region 14 is of the second conductivity type (p-type) and separates source region 20 and drift region 4. The body contact region 16 contains a second conductivity type (p-type) impurity in a high concentration, and stabilizes the potential of the body region 14 by the potential of the source electrode 18. The drain region 2 contains a first conductivity type (n-type) impurity in a high concentration, and reduces the contact resistance with the drain electrode 26. In the semiconductor substrate 24, a trench 11 extending from the surface of the semiconductor substrate 24 through the source region 20 and the body region 14 until reaching the drift region 4 is disposed. A gate electrode 12 and a floating electrode 8 are disposed in the trench 11. The wall surface of the gate electrode 12 is covered with an insulating film 22. The bottom surface 12 a of the gate electrode 12 is located at a position deeper than the bottom surface 14 a of the body region 14. The floating electrode 8 is disposed deeper than the gate electrode 12 in the trench 11, and the wall surface is covered with an insulating film 22. The floating electrode 8 floats in the trench 11 and is insulated from a member outside the trench 10 by the insulating film 22. In order to improve the breakdown voltage performance, a second conductivity type (p-type) impurity-containing region 6 is formed in a range surrounding the bottom surface 11 a of the trench 11. The impurity-containing region 6 is formed in the drift region 4. Precisely, the depth of the center D2 of the impurity-containing region 6 is deeper than the intermediate depth D3 of the drift region 4. Further, the upper end of the impurity-containing region 6 is deeper than the intermediate depth D3 of the drift region 4.

  In the power MOS 100, a channel can be formed in the body region 14 by applying a voltage to the gate electrode 12. By forming a channel in the body region 14, conduction between the source region 20 and the drain region 2 can be controlled.

Next, a graph representing the electric field intensity profile of the power MOS 100 in FIG. 1A will be described with reference to FIG. The graph of FIG.1 (b) has shown the electric field strength profile along the XX line segment of Fig.1 (a). The horizontal axis of the graph indicates the electric field strength (V / cm). The vertical axis of the graph indicates the depth (μm) of the semiconductor substrate 24 and corresponds to the depth shown in the cross-sectional view of the power MOS 100 in FIG. Illustrated _{E c} represents the critical electric field strength. The magnitude of the breakdown voltage of the power MOS 100 is proportional to the area shown by the hatch in FIG. The power MOS ₁₀₀ has a _first electric field strength peak P ₁ at a depth corresponding to the bottom surface 12 a of the gate electrode 12. Further, the depth D1 corresponding to the vicinity of a lower portion of the impurity-containing region 6, and a second field intensity peak P _2. The electric field intensity at the first peak P _{1 and} the electric field intensity at the second peak P ₂ are both equal to the critical electric field intensity E _c . Further, even at a depth where the floating electrode 8 is arranged, which holds the high electric field strength E _1. In the power MOS ₁₀₀ , by disposing the floating electrode 8 below the gate electrode 12, the depth of the valley formed between the _two peaks P ₁ and P ₂ even if the two peaks P ₁ and P ₂ are separated from each other. The depth can be reduced. As a result, the electric field intensity profile can be brought close to the curve L shown in FIG. Since the area indicated by hatching in FIG. 1B is large, the breakdown voltage of the power MOS 100 is high.

In the power MOS 100, by adjusting the position of the floating electrode 8, it is possible to adjust the extension of the depletion layer formed from the vicinity of the bottom surface 12a of the gate electrode 12 toward the impurity-containing region 6 when the power MOS 100 is turned off. it can. By adjusting the shape of the electric field strength profile, higher pressure resistance performance can be obtained. In addition, since the gate electrode 12 is not arranged deep in the trench 11, the gate capacity can be reduced and the switching loss can be reduced. Furthermore, when the required breakdown voltage is low, the on-resistance can be reduced by increasing the impurity concentration of the drift region 4, so that a low-breakdown-voltage power MOS having a low on-resistance can be realized.
In addition, since the distance between the body region 14 and the impurity-containing region 6 can be sufficiently separated, carriers that have passed through the body region 14 along the gate electrode 12 bypass the impurity-containing region 6 and drain electrode 26. It is possible to secure a wide effective passage area for flowing into the water. For this reason, a low on-resistance can be realized. In the power MOS 100, both the breakdown voltage and the on-resistance can be improved to a level substantially equal to the theoretical limit value.

FIG. 2 shows a trade-off relationship between breakdown voltage and on-resistance in a trench gate type power MOS. The vertical axis in FIG. 2 indicates the on-resistance (mΩ · mm ² ). The horizontal axis in FIG. 2 indicates the breakdown voltage (V). The curve in FIG. 2 shows the theoretical curve showing the theoretical limit of withstand voltage and on-resistance. Conventional structure A and conventional structure B are the same as those described with reference to FIG. This example shows the measurement result of the power MOS 100.
As shown in FIG. 2, the power MOS 100 realizes a withstand voltage and an on-resistance that substantially match the theoretical curve at a required withstand voltage of 43 V, as compared with the conventional power MOS. In the power MOS 100, even with a required withstand voltage greater than 43V, it is predicted that the withstand voltage and the on-resistance can be realized so as to substantially match the theoretical curve.

3 to 11 show a method for manufacturing the power MOS 100.
First, as shown in FIG. 3, a semiconductor substrate 24 made of n ⁻ type silicon is prepared. Next, a body region 14 is formed on the surface side of the semiconductor substrate 24 by injecting a p-type impurity such as boron into the semiconductor substrate 24 and thermally diffusing it. A region in the semiconductor substrate 24 where the p-type impurity is not diffused becomes an n ⁻ -type drift region 4. Next, using a mask (not shown) transferred to a pattern in which the position where the trench 11 is formed is opened, the trench 11 reaching the drift region 4 from the surface of the semiconductor substrate 24 through the body region 14 is formed. . For example, silicon oxide can be used as a material for the mask. As a method of forming the trench 11, for example, a chemical dry etching method can be used. As a result, the trench 11 having a smooth side wall can be formed in the semiconductor substrate 24. The depth of the trench 11 can be set to a depth of 3.0 to 3.3 μm from the surface of the semiconductor substrate 24, for example. The width of the trench 11 can be set to 0.4 to 0.5 μm, for example. The taper angle of the trench 11 can be set to, for example, 86.0 ° to 89.0 °. Next, a thermal oxide film (not shown) is formed on the surface of the semiconductor substrate 24. Next, by using this thermal oxide film as a mask, p-type impurities are implanted into the bottom 11a of the trench 11 and thermally diffused, thereby forming the impurity-containing region 6 in a range surrounding the bottom surface 11a of the trench 11. Next, the mask and the thermal oxide film on the surface of the semiconductor substrate 24 are removed. As a result, a clean silicon surface is exposed on the surface of the semiconductor substrate 24. As a method for removing the mask and the thermal oxide film, for example, isotropic etching such as wet etching can be used.

Next, as shown in FIG. 4, a first thermal oxide film 21 a is formed on the surface of the semiconductor substrate 24 and the wall surface of the trench 11. The conditions for forming the first thermal oxide film 21a, for example, a heating temperature 800 ° C. C. to 1100 ° C., to a _H 2 / _{O 2} diluted the type of gas in _{O 2} or _H 2 / _{O 2} or _{N 2} Can do. The thickness of the first thermal oxide film 21a can be set to 20 nm, for example.

Next, as shown in FIG. 5, a first silicon oxide film 23a is formed on the surface of the first thermal oxide film 21a. As a method of forming the first silicon oxide film 23a, for example, a CVD (Chemical Vapor Deposition) method can be used. When the CVD method is used, the deposition amount of the first silicon oxide film 23a is adjusted according to the position of the bottom surface 8a of the floating electrode 8 after manufacture. As the type of the first silicon oxide film 23a, for example, LP-SiH ₄ —SiO _2, LP-TEOS—SiO _2, or AP—O ₃ TEOS—SiO ₂ can be used. The thickness of the first silicon oxide film 23a can be set to 55 nm to 65 nm, for example.

Next, as shown in FIG. 6, the inside of the trench 11 is filled with the first polysilicon 8a. At this time, the trench 11 is filled until it is completely filled with the first polysilicon 8a. The first polysilicon 8a corresponds to the floating electrode 8 in the power MOS 100 after manufacture. For example, SiH ₄ can be used as the type of the first polysilicon 8. The heating condition for filling the first polysilicon 8a can be set to 600 ° C., for example.

  Next, as shown in FIG. 7, a part of the first polysilicon 8a is removed by etching (etching back). At this time, the etch back amount is adjusted according to the position of the upper surface of the floating electrode 8 after manufacture. The etching depth can be, for example, 2.5 to 2.7 μm from the surface of the semiconductor substrate.

  Next, as shown in FIG. 8, a part of the first thermal oxide film 21a and a part of the first silicon oxide film 23a are etched and removed to the same depth as that etched in the step of FIG. . As an etching method, for example, a wet etching method or a dry etching method can be used.

  Next, as shown in FIG. 9, a second thermal oxide film 21 b is formed on the surface of the semiconductor substrate 24 and the exposed wall surface of the trench 11. Next, a second silicon oxide film 23 b is formed on the surface of the second thermal oxide film 21 b and the surface of the polysilicon 8. The conditions for forming the second thermal oxide film 21b and the second silicon oxide film 23b are the same as the conditions described in the steps of FIGS. When the second silicon oxide film 23b is formed by the CVD method, the deposition amount of the second silicon oxide film 23b is adjusted according to the position that becomes the bottom surface of the gate electrode 12 after manufacture.

  Next, as shown in FIG. 10, the inside of the trench 11 is filled with the second polysilicon 12a. At this time, the trench 11 is filled until it is completely filled with the second polysilicon 12a. The second polysilicon 12a corresponds to the gate electrode 12 in the power MOS 100 after manufacture. The type and heating conditions of the second polysilicon 12a are the same as those described in the process of FIG.

  Next, as shown in FIG. 11, a part of the second polysilicon 12a is removed by etching (etching back). At this time, the etch back amount is adjusted so that the upper surface of the second polysilicon 12 a substantially matches the height of the surface of the semiconductor substrate 24. Next, as shown in FIG. 1, the source region 20 and the body contact region 16 are formed on the surface side of the semiconductor substrate 24 by injecting impurities from the surface of the semiconductor substrate 24 and thermally diffusing them, and then the semiconductor substrate 24. A source electrode 18 is formed on the surface. Next, the drain region 2 is formed on the back surface side of the semiconductor substrate 24 by injecting impurities from the back surface of the semiconductor substrate 24 and thermally diffusing, and then the drain electrode 26 is formed on the back surface of the semiconductor substrate 24. The power MOS 100 is completed through the above steps. Note that the first thermal oxide film 21a, the second thermal oxide film 21b, the first silicon oxide film 23a, and the second silicon oxide film 23b shown in FIG. 11 all correspond to the insulating film 22 shown in FIG. .

(Second embodiment)
FIG. 12 shows a cross-sectional view of a power MOS 200 according to the second embodiment. In FIG. 12, the member obtained by adding the numeral 30 to the reference numeral in FIG. 1 is the same as the member described in FIG. In the power MOS 200, the thickness W1 of the insulating film 52b covering the side wall of the floating electrode 38 is larger than the thickness W2 of the insulating film 52a covering the side wall of the gate electrode 42.

  In the power MOS 200, by increasing the thickness of the insulating film 52a covering the side wall of the floating electrode 38, the strength of the electric field generated in the drift region 34 on the side of the floating electrode 38 when off is reduced. On the other hand, if the thickness of the insulating film 52a covering the side wall of the floating electrode 38 is made too thick, the electric field concentrates on the insulating film 52a covering the side wall of the floating electrode 38 and exceeds the critical electric field strength Ec. In some cases, breakdown occurs at a low breakdown voltage. In the power MOS 200, by adjusting the thickness of the insulating film 52a covering the side wall of the floating electrode 38, the shape of the electric field strength profile is maintained while maintaining the balance between the two peaks while suppressing breakdown. It is close to the curve L shown in b). Thereby, the breakdown voltage of the power MOS 200 can be further increased.

FIG. 13 and FIG. 14 show a method for manufacturing the power MOS 200.
The manufacturing process (corresponding to the steps of FIGS. 3 to 8 of the first embodiment) until part of the first thermal oxide film and part of the first silicon oxide film are removed by etching is the first. Since it is the same as the manufacturing method of an Example, description is abbreviate | omitted. FIG. 13 shows a state after a part of the first thermal oxide film 51a and a part of the first silicon oxide film 53a are removed by etching. 38a is the first polysilicon and corresponds to the floating electrode 38 after manufacture. In this embodiment, in the step of forming the first silicon oxide film 53a (corresponding to the step of FIG. 5 of the first embodiment), the first silicon oxide film 53a is formed thick (for example, 130 nm).

  In the manufacturing method of the present embodiment, after removing a part of the first thermal oxide film 51a and a part of the first silicon oxide film 53a by etching, as shown in FIG. A second thermal oxide film 51 b is formed on the exposed wall surface of the trench 11. Next, a second silicon oxide film 53 b is formed on the surface of the second thermal oxide film 51 b and the surface of the polysilicon 38. At this time, the thickness W3 of the second silicon oxide film 53b deposited on the sidewall of the trench 41 is smaller than the thickness W4 of the first silicon oxide film 53a deposited on the sidewall of the trench 41. A silicon oxide film 53b is formed (for example, 80 nm). The conditions for forming the second thermal oxide film 51b and the second silicon oxide film 53b are the same as the conditions described in the steps of FIGS. 4 and 5 of the first embodiment. In the case where the second silicon oxide film 53b is formed by the CVD method, the deposition amount of the second silicon oxide film 53b is adjusted according to the position of the bottom surface of the gate electrode 42 after manufacture. Thereafter, the power MOS 200 is completed by the same procedure as the steps of FIGS. 10 and 11 of the first embodiment.

(Third embodiment)
FIG. 15 is a sectional view of a power MOS 300 according to the third embodiment. In FIG. 15, the member obtained by adding the numeral 60 to the reference numeral in FIG. 1 is the same as the member described in FIG. In the power MOS 300, the drift regions 64a and 64b include a first conductivity type (n-type) high concentration region 64b having a high impurity concentration and a first conductivity type (n-type) low concentration having a lower impurity concentration than the high concentration region 64b. A density region 64a is provided. The high concentration region 64b is adjacent to the body region 74 at a deep position. The low concentration region 64a is adjacent to the high concentration region 64b at a deep position. The bottom surface of the high concentration region 64 b substantially coincides with the low surface of the floating electrode 68.

  In the power MOS 300, when turned on, carriers easily flow in the carrier passage region formed in the high concentration region 64b. Therefore, carriers that have passed through the body region 74 along the trench 71 can be quickly supplied to the drain electrode 86, and the on-resistance of the power MOS 300 can be further reduced. In addition, although the depletion layer is difficult to extend in the high concentration region 64b, the floating electrode 68 is disposed at a depth where the high concentration region 64b is disposed. Thereby, it is suppressed that the depletion layer becomes difficult to extend, and a sufficient breakdown voltage is secured.

In the method for manufacturing the power MOS 300, the high concentration region 64 b is formed in the semiconductor substrate 84 before the step of forming the body region 74 in the semiconductor substrate 84. Two methods can be used to form the high concentration region 64a. The first method is shown in FIG. The second method is shown in FIG. In the method shown in FIG. 16, n-type impurities 81 such as phosphorus are ion-implanted at a high concentration on the surface of the semiconductor substrate 84 and thermally diffused. As a result, a high concentration region 64 b having a thickness of several μm is formed on the surface side of the semiconductor substrate 84. A region in the semiconductor substrate 84 where the n-type impurity 81 is not thermally diffused becomes a low concentration region 64a. As ion implantation conditions, for example, phosphorus particle density can be set to 2 × 10 ¹³ (cm ⁻³ ), and acceleration voltage for ion implantation can be set to 60 keV. Next, a body region 74 is formed on the surface side of the high concentration region 64b by injecting p-type impurities into the surface of the semiconductor substrate 84 and heating. Thereafter, the power MOS 300 is completed by the same procedure as the steps of FIGS. 3 to 11 of the first embodiment.

In the method shown in FIG. 17, the first semiconductor region 85 to be the n ⁻ -type low concentration region 64 a is formed on the surface of the substrate to be the drain region 62 by epitaxial growth. Next, a second semiconductor substrate 87 to be an n ⁺ type high concentration region 64b is deposited on the surface 85a of the first semiconductor region 85 by epitaxial growth. As a condition of the substrate used when epitaxially growing the first semiconductor region 85, a substrate in which arsenic is implanted and the resistance is 0.3Ω can be used. As a condition of the substrate used when the second semiconductor region 87 is epitaxially grown, a substrate in which arsenic is implanted and the resistance is 0.18Ω can be used. Next, a body region 74 is formed on the surface side of the high concentration region 64b by injecting p-type impurities into the surface of the second semiconductor region 87 and heating. Thereafter, the power MOS 300 is completed by the same procedure as the steps of FIGS. 3 to 11 of the first embodiment.

In power MOS 300, drift regions 64a and 64b preferably include a plurality of regions having different impurity concentrations along the depth direction, and the impurity concentration of each region is preferably low along the depth direction. In this case, the carrier resistance can be reduced stepwise in the carrier passage region formed when the power MOS 300 is turned on. By adjusting the thickness and impurity concentration of each region, it is possible to adjust the ease of flow of carriers passing through the drift regions 64a and 64b when the power MOS 300 is turned on. As an example, the drift region can be divided into four regions. In this case, the thickness of the first region can be 3.7 μm and the impurity concentration can be 4.0 × 10 ¹⁶ (cm ⁻³ ) in order from a deep position along the depth direction. The thickness of the second region can be 0.5 μm, and the impurity concentration can be 5.0 × 10 ¹⁶ (cm ⁻³ ). The thickness of the third region can be 0.5 μm, and the impurity concentration can be 6.0 × 10 ¹⁶ (cm ⁻³ ). The thickness of the fourth region can be 1.8 μm, and the impurity concentration can be 7.0 × 10 ¹⁶ (cm ⁻³ ).

(Fourth embodiment)
FIG. 18 is a sectional view of a power MOS 400 according to the fourth embodiment. In FIG. 18, the member obtained by adding numeral 90 to the reference numeral in FIG. 1 is the same as the member described in FIG. In the power MOS 400, the dielectric constant of the insulating film 112 b covering the wall surface of the gate electrode 102 is higher than the dielectric constant of the insulating film 112 a covering the wall surface of the floating electrode 98.

  In the power MOS 400, as compared with the power MOS of the first to third embodiments, a channel is easily formed on the side of the gate electrode 102 when turned on. Thereby, the on-resistance of the power MOS 400 can be further reduced. Also, carriers are less likely to flow in the reverse direction at the depth where the floating electrode 98 is disposed when the power MOS 400 is off. For this reason, it can suppress that a breakdown voltage falls.

  The method for manufacturing the power MOS 400 is the same as the method for manufacturing the power MOS 100 of the first embodiment, and only the material for forming the insulating films 112a and 112b is different. In the method of manufacturing the power MOS 400, a high dielectric film having a high dielectric constant is deposited instead of the first silicon oxide film 23a in the step of FIG. 5 of the first embodiment. As a material for the high dielectric film, for example, TEOS can be used. The relative dielectric constant of the high dielectric film is preferably about 3.9. In the step of FIG. 9 of the first embodiment, a low dielectric film having a low dielectric constant is deposited instead of the second silicon oxide film 23b. As a material for the low dielectric film, for example, hafnium oxide can be used. The relative dielectric constant of the low dielectric film is preferably 10-14.

(5th Example)
FIG. 19 is a sectional view of a power MOS 500 according to the fifth embodiment. In FIG. 19, the member obtained by adding numeral 120 to the reference numeral in FIG. 1 is the same as the member described in FIG. In the power MOS 500, the impurity concentration of the drain region 122 is 1 × 10 ¹⁹ (cm ⁻³ ). The impurity concentration of the drift region 124 is 5 × 10 ¹⁶ (cm ⁻³ ). The impurity concentration of the body region 134 is 2 × 10 ¹⁷ (cm ⁻³ ). The impurity concentration of the body contact region 136 is 1 × 10 ¹⁹ (cm ⁻³ ). In the power MOS 500, four floating electrodes 128 a to 128 d are arranged at intervals along the depth direction of the trench 131. The thickness of each floating electrode 128a to 128d is 0.2 μm. Further, the distance between each of the floating electrodes 128 a to 128 d is reduced in a geometric series along the depth direction of the trench 131. That is, the distance D4 between the floating electrode 128c and the floating electrode 128d is 0.2 μm. The distance D5 between the floating electrode 128b and the floating electrode 128c is 0.1 μm. A distance D6 between the floating electrode 128a and the floating electrode 128b is 0.05 μm. Therefore, the relationship of D5 = 0.5 × D4 and D6 = 0.5 × D5 is established. Further, the thickness of each insulating film 142 covering the side walls of the floating electrodes 128 a to 128 d is increased along the depth direction of the trench 131. In the power MOS 500, the insulating film 142 covering the floating electrode 128d has a thickness W8, the insulating film 142 covering the floating electrode 128c has a thickness W7, and the insulating film covering the floating electrode 128b. Assuming that the thickness of 142 is the thickness W6 and the thickness of the insulating film 142 covering the floating electrode 128a is the thickness W5, W8 <W7 <W6 <W5 is established.

  In the power MOS 500, by adjusting the arrangement of the floating electrodes 128a to 128d in the trench 131 and the thickness of each insulating film 142 covering the plurality of floating electrodes 128a to 128d, the shape of the electric field strength profile is changed. It can be adjusted along the depth direction. Since the interval between the adjacent floating electrodes 128a to 128d is reduced in a geometric series, the shape of the electric field strength profile can be effectively adjusted. The breakdown voltage of the power MOS 500 can be further increased by bringing the shape of the electric field strength profile closer to the curve L shown in FIG.

20 to 27 show a method for manufacturing the power MOS 500.
The manufacturing process (corresponding to the steps of FIGS. 3 to 8 of the first embodiment) until part of the first thermal oxide film and part of the first silicon oxide film are removed by etching is the first. Since it is the same as the manufacturing method of an Example, description is abbreviate | omitted. FIG. 20 shows a state after part of the first thermal oxide film 141a and part of the first silicon oxide film 143a are removed by etching. The etching depth can be set to 2.65 μm, for example. 128a shown in the drawing is first polysilicon and corresponds to the floating electrode 128a after manufacture. In the manufacturing method of the present embodiment, in the step of forming the first silicon oxide film 143a (corresponding to the step of FIG. 5 of the first embodiment), the width of the side wall of the first silicon oxide film 143a is formed thickly ( For example, 200 nm).

  After etching and removing a part of the first thermal oxide film 141a and a part of the first silicon oxide film 143a, as shown in FIG. 21, the surface of the semiconductor substrate 144 and the exposed wall surface of the trench 131 are formed. A second thermal oxide film 141b is formed. Next, a second silicon oxide film 143b is formed on the surface of the second thermal oxide film 141b and the surface of the first polysilicon 128a1. At this time, the second silicon oxide film 143b is formed so that the distance between the first polysilicon 128a1 and a second polysilicon 128b1 described later becomes 0.05 μm. Further, the thickness W10 of the second silicon oxide film 143b deposited on the sidewall of the trench 131 is smaller than the thickness W9 of the first silicon oxide film 143a deposited on the sidewall of the first polysilicon 128a1. A second silicon oxide film 143b is formed (for example, 150 nm).

  Next, as shown in FIG. 22, the inside of the trench 131 is filled with the second polysilicon 128b1. At this time, the trench 131 is filled until it is completely filled with the second polysilicon 128b1. The second polysilicon 128b1 corresponds to the manufactured floating electrode 128b.

  Next, as shown in FIG. 23, a part of the second polysilicon 128b1 is removed by etching (etching back). At this time, the etch back amount is adjusted according to the position of the upper surface of the floating electrode 128b after manufacture. The etching depth can be set to 2.4 μm, for example. Next, a part of the second thermal oxide film 141b and a part of the second silicon oxide film 143b are etched and removed to the same depth as the depth of etching the second polysilicon 128b1.

  Next, as shown in FIG. 24, a third thermal oxide film 141 c is formed on the surface of the semiconductor substrate 144 and the wall surface of the trench 131. Next, a third silicon oxide film 143c is formed on the surface of the third thermal oxide film 141c and the surface of the second polysilicon 128b1. At this time, the third silicon oxide film 143c is formed so that the distance between the second polysilicon 128b1 and a third polysilicon 128c1 described later is 0.1 μm. Further, the thickness W11 of the third silicon oxide film 143c deposited on the sidewall of the trench 131 is smaller than the thickness W10 of the second silicon oxide film 143b deposited on the sidewall of the second polysilicon 128b1. A third silicon oxide film 143c is formed (for example, 100 nm).

  Next, as shown in FIG. 25, after filling the inside of the trench 131 with the third polysilicon 128c1, a part of the third polysilicon 128c1, A part of the third thermal oxide film 141c and a part of the third silicon oxide film 143c are removed by etching. At this time, the etch back amount of the third polysilicon 128c1 is adjusted according to the position of the upper surface of the floating electrode 128c after manufacture. The etching depth can be set to 2.1 μm, for example. The third polysilicon 128c1 corresponds to the manufactured floating electrode 128c.

  Next, as shown in FIG. 26, a fourth thermal oxide film 141 d is formed on the surface of the semiconductor substrate 144 and the wall surface of the trench 131. Next, a fourth silicon oxide film 143d is formed on the surface of the fourth thermal oxide film 141d and the surface of the third polysilicon 128c1. At this time, the fourth silicon oxide film 143d is formed so that the distance between the third polysilicon 128c1 and a later-described fourth polysilicon 128d1 is 0.2 μm. Further, the thickness W12 of the fourth silicon oxide film 143d deposited on the sidewall of the trench 131 is smaller than the thickness W11 of the third silicon oxide film 143c deposited on the sidewall of the third polysilicon 128c1. Then, a fourth silicon oxide film 143d is formed (for example, 50 nm).

  Next, as shown in FIG. 27, after filling the inside of the trench 131 with the fourth polysilicon 128d1, a part of the fourth polysilicon 128d1 and the second polysilicon 128d1 are formed by the same procedure as the steps of FIGS. A part of the fourth thermal oxide film 141c and a part of the fourth silicon oxide film 143d are removed by etching. At this time, the etch back amount is adjusted according to the position of the upper surface of the floating electrode 128d after manufacture. The etching depth can be set to 1.7 μm, for example. The fourth polysilicon 128d1 corresponds to the manufactured floating electrode 128d. Thereafter, the power MOS 500 is completed by the same procedure as the steps of FIGS. 9 to 11 of the first embodiment.

  In the manufacturing methods of the first to fifth embodiments, LP-TEOS is preferably used as the type of silicon oxide film. Since LP-TEOS has good coverage, the thickness of the silicon oxide film can be effectively controlled when the silicon oxide film is deposited by the CVD method.

  In the manufacturing methods of the first to fifth embodiments, it is preferable to use polysilicon as a material for the gate electrode and the floating electrode. This is because when a metal such as aluminum is used instead of polysilicon, it is necessary to form a protective film for protecting the electrode metal from contamination.

  In the manufacturing methods of the first to fifth embodiments, it is preferable to adjust the distance between the gate electrode and the floating electrode according to the concentration of the drift region and the required breakdown voltage. The shape of the electric field strength profile changes depending on the concentration of the drift region and the required breakdown voltage. By adjusting the distance between the gate electrode and the floating electrode in accordance with the concentration of the drift region and the required breakdown voltage, the shape of the electric field strength profile can be brought close to the curve L shown in FIG. Can be effectively increased.

  In the power MOSs of the first to fifth embodiments, it is preferable that the upper end of the impurity-containing region is formed at a position shallower than the intermediate depth of the drift region. If the position of the impurity-containing region is too deep, the resistance of carriers passing through the drift region increases and the on-resistance increases. For this reason, it is preferable that the position of the impurity-containing region is not too deep.

  In the first to fifth embodiments, the semiconductor device in which the n-type is the first conductivity type and the p-type is the second conductivity type is described. However, the n-type is the second conductivity type and the p-type is the first conductivity type. It is good. Even in this case, a power MOS having both a high breakdown voltage and a low on-resistance can be manufactured.

  In the first to fifth embodiments, the power MOS is described. However, other semiconductor devices such as an IGBT (Insulated Gate Bipolar Transistor) may be used. Even a semiconductor device other than a power MOS can realize a semiconductor device having both a high breakdown voltage and a low on-resistance.

As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

(A) shows sectional drawing of the semiconductor device 100 of 1st Example. (B) shows the electric field strength profile of the semiconductor device 100. The theoretical curves of on-resistance and breakdown voltage are shown. A process (1) for manufacturing the semiconductor device 100 will be described. A process (2) for manufacturing the semiconductor device 100 will be described. A process (3) for manufacturing the semiconductor device 100 will be described. A step (4) for manufacturing the semiconductor device 100 will be described. A process (5) for manufacturing the semiconductor device 100 will be described. A process (6) for manufacturing the semiconductor device 100 will be described. A process (7) for manufacturing the semiconductor device 100 will be described. A process (8) for manufacturing the semiconductor device 100 will be described. A process (9) for manufacturing the semiconductor device 100 will be described. Sectional drawing of the semiconductor device 200 of 2nd Example is shown. A process (1) for manufacturing the semiconductor device 200 will be described. A process (2) for manufacturing the semiconductor device 200 will be described. Sectional drawing of the semiconductor device 300 of 3rd Example is shown. A process (1) for manufacturing the semiconductor device 300 will be described. A process (2) for manufacturing the semiconductor device 300 will be described. Sectional drawing of the semiconductor device 400 of 4th Example is shown. Sectional drawing of the semiconductor device 500 of 5th Example is shown. A process (1) for manufacturing the semiconductor device 500 will be described. A process (2) for manufacturing the semiconductor device 500 will be described. A step (3) for manufacturing the semiconductor device 500 will be described. A process (4) for manufacturing the semiconductor device 500 will be described. A step (5) of manufacturing the semiconductor device 500 will be described. A process (6) for manufacturing the semiconductor device 500 will be described. A step (7) of manufacturing the semiconductor device 500 will be described. A step (8) of manufacturing the semiconductor device 500 will be described. (A) shows a cross-sectional view of a conventional semiconductor device 600. (B) shows the electric field strength profile of the semiconductor device 600. The theoretical curves of on-resistance and breakdown voltage are shown.

Explanation of symbols

2, 32, 62, 92, 122, 202: Drain regions 4, 34, 94, 124, 204: Drift regions 6, 36, 66, 96, 126, 206: Impurity-containing regions 8, 38, 68, 98, 128a 128b, 128c, 128d: floating electrodes 11, 41, 71, 101, 131, 211: trenches 11a, 41a, 71a, 101a, 131a, 211a: bottoms of trenches 12, 42, 72, 102, 132, 212: gates Electrodes 14, 44, 74, 104, 134, 214: body region 14a: bottom surface 16, 46, 76, 106, 136, 216 of body region: body contact regions 18, 48, 78, 108, 138, 218: surface electrode 20, 50, 80, 110, 140, 220: source regions 21a, 51a, 141a: first thermal oxide film 1b, 51b, 141b: second thermal oxide films 22, 52a, 52b, 82: insulating films 23a, 53a, 143a: first silicon oxide films 23b, 53b, 143b: second silicon oxide films 24, 54, 84, 114, 144, 224: Semiconductor substrate 26, 56, 86, 116, 146, 226: Back electrode 64a: Low concentration region (drift region)
64b: High concentration region (drift region)
81: n-type impurity 85: first semiconductor region 85a: surface of the first semiconductor region 87: second semiconductor region 100, 200, 300, 400, 500, 600: power MOS
128c1: third polysilicon 128d1: fourth polysilicon 141c: third thermal oxide film 141d: fourth thermal oxide film 143c: third silicon oxide film 143d: fourth silicon oxide film

Claims (5)

A front surface electrode is disposed on the front surface of the semiconductor substrate, and a back surface electrode is disposed on the back surface of the semiconductor substrate.
A body region of a second conductivity type disposed on the surface side of the semiconductor substrate;
A drift region of a first conductivity type disposed at a position deeper than the body region in the semiconductor substrate;
A trench extending from the surface of the semiconductor substrate to the drift region through the body region;
An impurity-containing region of a second conductivity type disposed in a range surrounding the bottom surface of the trench;
A gate electrode disposed in the trench, having a wall surface covered with an insulating film and extending to a position deeper than a bottom surface of the body region;
It is disposed at a position deeper than the gate electrode in the trench, and includes a floating electrode whose wall surface is covered with an insulating film,
The center of the impurity-containing region is disposed at a position deeper than the intermediate depth of the drift region ,
A plurality of floating electrodes are arranged in the depth direction at a position deeper than the gate electrode in the trench, and the intervals between the floating electrodes are reduced geometrically along the depth direction. A semiconductor device.   2. The semiconductor device according to claim 1, wherein a thickness of the insulating film covering the side wall of the floating electrode is larger than a thickness of the insulating film covering the side wall of the gate electrode.   The drift region is adjacent to the body region at a deep position and has a high impurity concentration and a first conductivity type high concentration region, and is adjacent to the high concentration region at a deep position and has an impurity concentration higher than that of the high concentration region. 3. The semiconductor device according to claim 1, further comprising a low concentration region of a low first conductivity type.   The dielectric constant of the insulating film covering the side wall of the gate electrode is higher than the dielectric constant of the insulating film covering the side wall of the floating electrode. A semiconductor device according to 1. 5. The semiconductor device according to claim 1, wherein a thickness of each insulating film covering the side walls of the plurality of floating electrodes is increased along a depth direction. 6.

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