JP2018152460A - Controller, and system including controller and semiconductor device controlled by that controller - Google Patents

Controller, and system including controller and semiconductor device controlled by that controller Download PDF

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JP2018152460A
JP2018152460A JP2017047537A JP2017047537A JP2018152460A JP 2018152460 A JP2018152460 A JP 2018152460A JP 2017047537 A JP2017047537 A JP 2017047537A JP 2017047537 A JP2017047537 A JP 2017047537A JP 2018152460 A JP2018152460 A JP 2018152460A
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semiconductor device
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昭夫 岩渕
Akio Iwabuchi
昭夫 岩渕
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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PROBLEM TO BE SOLVED: To provide a controller driving a semiconductor device capable of making the semiconductor device low ON-voltage and high breakdown voltage, and to provide a system including that controller and a semiconductor device driven by that controller.SOLUTION: A controller 2 controlling a semiconductor device 1 includes a control electrode 80 placed in a groove 30 facing a base region 40, an auxiliary electrode 70 placed in a groove 30 facing a drift region 20, a first main electrode 90 connected electrically with a source region 50, and a second main electrode 100 connected electrically with a drain region 10, and when a signal of potential less than a threshold level is outputted to the control electrode 80 of the semiconductor device 1, outputs a signal so that a potential less than the threshold level of the semiconductor device is given to the auxiliary electrode 70, and after a signal of potential equal to or exceeding the threshold level is outputted to the control electrode 80 of the semiconductor device, outputs a signal for increasing the voltage applied to the auxiliary electrode 70 to the voltage applied to the control electrode 80 or higher.SELECTED DRAWING: Figure 2

Description

本発明は、制御装置と、その制御装置とその制御装置により制御される半導体装置とを含むシステムに関する。   The present invention relates to a system including a control device, the control device, and a semiconductor device controlled by the control device.

大電流のスイッチング動作を行う半導体装置（パワー半導体素子）として、トレンチゲート型のＭＯＳＦＥＴが広く用いられている。   A trench gate type MOSFET is widely used as a semiconductor device (power semiconductor element) that performs a switching operation with a large current.

トレンチゲート型のＭＯＳＦＥＴは、図１の半導体装置１で示すように、一般的に第1導電型のドレイン領域１０と、第1導電型のドレイン領域１０の上に形成された第１導電型のドリフト領域２０と、第１導電型のドリフト領域２０上に形成された第２導電型のベース領域４０と、第２導電型のベース領域４０上に選択的に形成された第１導電型のソース領域５０と、ソース領域５０からベース領域４０を貫通してドリフト領域２０に達する溝３０と、ベース領域４０と対向する溝３０の側壁に絶縁膜６０を介して形成されたゲート電極８０と、ソース領域５０と電気的に接続したソース電極９０と、ドレイン領域１０と電気的に接続したドレイン電極１００と、ソース電極９０と電気的に接続し且つ溝３０内におけるゲート電極８０よりも下に形成された補助電極７０と、を備える。トレンチゲート型のＭＯＳＦＥＴはソース電極９０とドレイン電極１００との間に所定のドレイン・ソース間電圧を印加し、ソース電極９０とゲート電極８０との間に所定のゲート電圧を印加する。このとき半導体装置１はチャネル領域においてｐ型からｎ型に反転してチャネルが形成される。すると、ソース電極９０からチャネルを通過して、電子がドリフト領域２０に注入され、半導体装置１はオンすることができる。   As shown in the semiconductor device 1 of FIG. 1, the trench gate type MOSFET generally has a first conductivity type drain region 10 and a first conductivity type drain region 10 formed on the first conductivity type drain region 10. Drift region 20, second conductivity type base region 40 formed on first conductivity type drift region 20, and first conductivity type source selectively formed on second conductivity type base region 40 A region 50, a trench 30 extending from the source region 50 through the base region 40 to the drift region 20, a gate electrode 80 formed on the sidewall of the trench 30 facing the base region 40 via an insulating film 60, a source Source electrode 90 electrically connected to region 50, drain electrode 100 electrically connected to drain region 10, and electrically connected to source electrode 90 and more than gate electrode 80 in trench 30 It includes an auxiliary electrode 70 formed on, a. The trench gate type MOSFET applies a predetermined drain-source voltage between the source electrode 90 and the drain electrode 100, and applies a predetermined gate voltage between the source electrode 90 and the gate electrode 80. At this time, the semiconductor device 1 is inverted from p-type to n-type in the channel region to form a channel. Then, electrons pass through the channel from the source electrode 90 and are injected into the drift region 20, so that the semiconductor device 1 can be turned on.

ここで、特許文献１のように、トレンチゲート型のＭＯＳＦＥＴにおいて、補助電極７０の電位を数ボルトにすることで、低いオン電圧とゲート・ドレイン間容量の低減を図る構造が公知である。   Here, as in Patent Document 1, in a trench gate type MOSFET, a structure is known in which the potential of the auxiliary electrode 70 is set to several volts so as to reduce the on-voltage and the gate-drain capacitance.

特開昭６３−２９６２８２号公報JP 63-296282 A

特許文献１の構造において更なるオン抵抗の低減を図るため、ドリフト領域２０の不純物濃度を高めると半導体装置のオン電圧は低減されるが、半導体装置の耐圧は逆に低くなる。つまり、半導体装置のオン抵抗と耐圧はトレードオフの関係にある。 In order to further reduce the on-resistance in the structure of Patent Document 1, when the impurity concentration of the drift region 20 is increased, the on-voltage of the semiconductor device is reduced, but the breakdown voltage of the semiconductor device is conversely lowered. That is, the on-resistance and breakdown voltage of the semiconductor device are in a trade-off relationship.

そこで、本発明はかかる問題点に鑑みてなされたものであり、上記問題点を解決することができる制御装置、及びその制御装置とその制御装置で駆動する半導体装置を含むシステムを提供することを目的とする。   Therefore, the present invention has been made in view of the above problems, and provides a control device that can solve the above problems, and a system including the control device and a semiconductor device driven by the control device. Objective.

本発明は、上記課題を解決すべく、以下に掲げる構成とした。
本発明の半導体装置の制御装置は、第1導電型の第1半導体領域と、第1半導体領域上に配置され、前記第1半導体領域よりも不純物濃度の低い第１導電型の第２半導体領域と、第２半導体領域上に配置された、第1導電型と反対導電型である第２導電型の第３半導体領域と、第３半導体領域上に配置された、第１導電型の第４半導体領域と、第４半導体領域から第３半導体領域を貫通し、第２半導体領域に達する溝と、第３半導体領域と対向する溝の側壁上に絶縁膜を介して溝内に配置された制御電極と、第２半導体領域と対向する溝の壁面上に絶縁膜を介して溝内に配置された補助電極と、第４半導体領域と電気的に接続された第１の主電極と、第1半導体領域と電気的に接続された第２の主電極と、を備える半導体装置を制御する制御装置であって、制御装置は半導体装置の制御電極に閾値未満の電位の信号を出力している時、半導体装置の閾値未満の電位を補助電極に与えるように信号を出力し、半導体装置の制御電極に閾値以上の電位の信号を出力した後、補助電極に印加される電圧を制御電極に印加される電圧以上に上げる信号を出力することを特徴とする。 In order to solve the above problems, the present invention has the following configurations.
A control device for a semiconductor device according to the present invention includes a first conductive type first semiconductor region, and a first conductive type second semiconductor region disposed on the first semiconductor region and having a lower impurity concentration than the first semiconductor region. A third semiconductor region of a second conductivity type disposed on the second semiconductor region and having a conductivity type opposite to the first conductivity type, and a fourth of the first conductivity type disposed on the third semiconductor region. A semiconductor region, a trench penetrating from the fourth semiconductor region to the third semiconductor region, reaching the second semiconductor region, and a control disposed in the trench via an insulating film on a sidewall of the trench facing the third semiconductor region An electrode, an auxiliary electrode disposed in the groove on the wall surface of the groove facing the second semiconductor region via an insulating film, a first main electrode electrically connected to the fourth semiconductor region, a first And a second main electrode electrically connected to the semiconductor region. When the control device outputs a signal having a potential lower than the threshold value to the control electrode of the semiconductor device, the control device outputs a signal so that the potential lower than the threshold value of the semiconductor device is applied to the auxiliary electrode, and the threshold value is output to the control electrode of the semiconductor device. After outputting the signal having the above potential, a signal for increasing the voltage applied to the auxiliary electrode to be higher than the voltage applied to the control electrode is output.

本発明は以上のように構成されているので、半導体装置を低オン電圧で高耐圧とすることができる半導体装置を駆動する制御装置及びその制御装置と制御装置により駆動する半導体装置を含むシステムを提供することができる。   Since the present invention is configured as described above, a control device for driving a semiconductor device capable of increasing the breakdown voltage with a low on-voltage, and a system including the control device and the semiconductor device driven by the control device. Can be provided.

半導体装置１の断面図である。1 is a cross-sectional view of a semiconductor device 1. FIG. 半導体装置１と半導体装置１を制御する制御装置２とを含むシステム３に周辺部品を含めた接続図である。1 is a connection diagram including peripheral components in a system 3 including a semiconductor device 1 and a control device 2 that controls the semiconductor device 1. 制御装置２の出力信号と半導体装置１の動作を簡略した示す図である。FIG. 4 is a diagram schematically illustrating an output signal of a control device 2 and an operation of the semiconductor device 1.

以下、本発明の実施の形態となる半導体装置について説明する。なお、本発明において、図を参酌しながら詳細に説明するが、本発明はこれに限定されるものではない。
まず、半導体装置１の断面図を図１で示す。この半導体装置１は、ドレイン領域となるｎ＋領域（第1の半導体領域）１０の上に、ｎ＋領域１０よりも不純物濃度が低いドリフト領域となるｎ−領域（第２の半導体領域）２０、ベース領域となるｐ−領域（第３の半導体領域）４０を備える。また、半導体装置１は、ｐ−領域４０を貫通して底部がｎ−領域２０に達する第1の溝（溝）３０を備える。第1の溝３０は、図１における紙面と垂直方向に延伸し、紙面と平行方向に繰返し複数形成されている。 Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. Although the present invention will be described in detail with reference to the drawings, the present invention is not limited to this.
First, a cross-sectional view of the semiconductor device 1 is shown in FIG. The semiconductor device 1 includes an n − region (second semiconductor region) 20 serving as a drift region having an impurity concentration lower than that of the n + region 10 on an n + region (first semiconductor region) 10 serving as a drain region. , A p − region (third semiconductor region) 40 serving as a base region is provided. Further, the semiconductor device 1 includes a first groove (groove) 30 that penetrates the p − region 40 and reaches the n − region 20 at the bottom. The first groove 30 extends in a direction perpendicular to the paper surface in FIG. 1, and a plurality of first grooves 30 are repeatedly formed in a direction parallel to the paper surface.

第1の溝３０の両側に、ｎ−領域２０よりも不純物濃度が高いソース領域となるｎ＋領域（第４の半導体領域）５０が形成されている。第1の溝３０の内面（側面及び底面）には絶縁膜６０が形成されている。その絶縁膜６０を介してｐ−領域４０と対向するように、第1の溝３０内にゲート電極（制御電極）８０が形成されている。ゲート電極８０は、例えば高濃度にドープされた導電性の多結晶シリコン（ポリシリコン）で構成される。ゲート電極８０の下にはゲート電極８０及びｎ−領域２０と絶縁された補助電極７０が形成されている。絶縁膜６０を介してｎ−領域２０と対向するように、第1の溝３０内に補助電極７０が形成されていることにより、半導体装置１はゲート・コレクタ間の容量（Ｃｇｄ）を低減することができ、スイッチング損失を低減することができる。第１の溝３０の底面と第１の溝３０の側面及びゲート電極８０と補助電極７０との間において絶縁膜６０を備えるため、補助電極７０はゲート電極８０及びｎ−領域２０と絶縁されている。第１の溝３０の底面と第１の溝３０の側面及びゲート電極８０と補助電極７０との間の絶縁膜６０の少なくとも一部が異なる材料で形成されても良い。 On both sides of the first trench 30, n + regions (fourth semiconductor regions) 50 serving as source regions having a higher impurity concentration than the n − region 20 are formed. An insulating film 60 is formed on the inner surface (side surface and bottom surface) of the first groove 30. A gate electrode (control electrode) 80 is formed in the first trench 30 so as to face the p − region 40 through the insulating film 60. The gate electrode 80 is made of, for example, conductive polycrystalline silicon (polysilicon) doped at a high concentration. Under the gate electrode 80, the auxiliary electrode 70 insulated from the gate electrode 80 and the n − region 20 is formed. Since the auxiliary electrode 70 is formed in the first trench 30 so as to face the n − region 20 through the insulating film 60, the semiconductor device 1 reduces the gate-collector capacitance (Cgd). Switching loss can be reduced. Since the insulating film 60 is provided between the bottom surface of the first groove 30, the side surface of the first groove 30, and between the gate electrode 80 and the auxiliary electrode 70, the auxiliary electrode 70 is insulated from the gate electrode 80 and the n − region 20. Yes. The bottom surface of the first groove 30, the side surface of the first groove 30, and at least a part of the insulating film 60 between the gate electrode 80 and the auxiliary electrode 70 may be formed of different materials.

開口部にｎ＋領域５０が設けられた第1の溝３０間に、ｐ−領域４０を貫通しない第２の溝１２０と第２の溝１２０の底部にｐ＋コンタクト領域１１０が形成されている。第２の溝１２０は、第1の溝３０と同様に図１における紙面と垂直方向に延伸し、紙面と平行方向に第1の溝３０と第２の溝１２０が繰返し複数備える。ただし、第２の溝１２０とｐ＋コンタクト領域１１０は形成されていなくても良い。また、ｎ＋領域５０は紙面と垂直方向にある領域と無い領域が繰り返されていてもよい。また、図１の断面においてｎ＋領域５０とｐ＋コンタクト領域１１０は両方が設けられているが、ｎ＋領域５０とｐ＋コンタクト領域１１０は紙面と垂直方向に交互に繰り返し形成してもよい。 Between the first groove 30 in which the n + region 50 is provided in the opening, a second groove 120 that does not penetrate the p − region 40 and a p + contact region 110 are formed at the bottom of the second groove 120. . Similarly to the first groove 30, the second groove 120 extends in a direction perpendicular to the paper surface in FIG. 1, and a plurality of first grooves 30 and a plurality of second grooves 120 are provided in a direction parallel to the paper surface. However, the second trench 120 and the p + contact region 110 may not be formed. Further, the n + region 50 may be a region that is perpendicular to the paper surface and a region that is not present. Further, although both the n + region 50 and the p + contact region 110 are provided in the cross section of FIG. 1, the n + region 50 and the p + contact region 110 may be alternately and repeatedly formed in a direction perpendicular to the paper surface. .

ソース電極（第１の主電極）９０がゲート電極８０上の絶縁膜６０上及び第２の溝１２０内に形成され、ｎ＋領域５０と電気的に接続されている。ここで、ソース電極９０はｐ−領域４０と電気的に接続してもよい。これにより、ｐ−領域４とｎ＋領域５とのｐｎ接合界面近傍の電位上昇を抑制し、半導体装置１のアバランシェ耐量の低下を抑制することができる。また、第２の溝１２０の底部にｐ−領域４０よりも不純物濃度が高いｐ＋コンタクト領域１１０を備え、ｐ＋コンタクト領域１１０を介してｐ−領域４０とソース電極９０が電気的に接続しても良い。
半導体装置１のｎ＋層１０の裏面全面には、ｎ＋層１０と電気的に接続されるドレイン電極（第２の主電極）１００が形成されている。 A source electrode (first main electrode) 90 is formed on the insulating film 60 on the gate electrode 80 and in the second trench 120, and is electrically connected to the n + region 50. Here, the source electrode 90 may be electrically connected to the p − region 40. Thereby, an increase in potential in the vicinity of the pn junction interface between p − region 4 and n + region 5 can be suppressed, and a decrease in avalanche resistance of semiconductor device 1 can be suppressed. In addition, a p + contact region 110 having an impurity concentration higher than that of the p − region 40 is provided at the bottom of the second trench 120, and the p − region 40 and the source electrode 90 are electrically connected via the p + contact region 110. May be.
The entire back surface of the n + layer 10 of the semiconductor device 1, n + layer 10 and electrically connected to the drain electrode (second main electrode) 100 is formed.

半導体装置１を動作させる制御装置２及び半導体装置１と制御装置２を含むシステム３について、図２で説明する。図２は図１で示す半導体装置１と、ブロック図で示す制御装置２と、半導体装置１と制御装置２を含むシステム３と、システム３と電源や外部負荷などの周辺部品との接続関係を示す。
図２で示すように、制御装置２は半導体装置１のゲート電極８０へ信号を出力するドライバ回路Ｄ１と、ドライバ回路Ｄ１がオンとオフの信号を出力するように制御信号を出力するパルス回路Ｐ１と、パルス回路Ｐ１の出力信号に応じて出力する制御装置２の出力端子Ｔ１と、半導体装置１の補助電極７０へ信号を出力するドライバ回路Ｄ２と、ドライバ回路Ｄ２がオンとオフの信号を出力するように制御信号を出力するパルス回路Ｐ２と、パルス回路Ｐ２の出力信号に応じて出力する制御装置２の出力端子Ｔ２を備える。図２においてパルス回路Ｐ１とパルス回路Ｐ２を別々の装置として構成したが、パルス回路Ｐ１とパルス回路Ｐ２を１つのパルス回路内で２出力できる構成とし、ドライバ回路Ｄ２への制御信号をドライバ回路Ｄ１への制御信号よりも所定時間だけ早くオン・オフする若しくは所定時間だけ遅くオン・オフするように制御装置２を構成しても良い。また、制御装置２が１つのパルス回路内で２出力できるように構成され、ドライバ回路Ｄ２がドライバ回路Ｄ１よりも所定時間だけ早くオン・オフする若しくは所定時間だけ遅くオン・オフするように、制御装置２の中にパルス回路の代わりに別途リレー回路等を組み込んでも良い。また、ドライバ回路Ｄ１とドライバ回路Ｄ２の少なくとも何れか１つを制御装置２の外に設けて、パルス回路Ｐ１、Ｐ２の少なくとも何れか１つが制御装置２の出力端子と電気的に接続しても良い。 A control device 2 for operating the semiconductor device 1 and a system 3 including the semiconductor device 1 and the control device 2 will be described with reference to FIG. 2 shows the connection relationship between the semiconductor device 1 shown in FIG. 1, the control device 2 shown in the block diagram, the system 3 including the semiconductor device 1 and the control device 2, and the system 3 and peripheral components such as a power source and an external load. Show.
As shown in FIG. 2, the control device 2 outputs a driver circuit D1 that outputs a signal to the gate electrode 80 of the semiconductor device 1, and a pulse circuit P1 that outputs a control signal so that the driver circuit D1 outputs an on / off signal. The output terminal T1 of the control device 2 that outputs in response to the output signal of the pulse circuit P1, the driver circuit D2 that outputs a signal to the auxiliary electrode 70 of the semiconductor device 1, and the driver circuit D2 that outputs an on / off signal. The control circuit 2 includes a pulse circuit P2 that outputs a control signal and an output terminal T2 of the control device 2 that outputs the control signal according to the output signal of the pulse circuit P2. In FIG. 2, the pulse circuit P1 and the pulse circuit P2 are configured as separate devices. However, the pulse circuit P1 and the pulse circuit P2 are configured to output two signals in one pulse circuit, and a control signal to the driver circuit D2 is transmitted to the driver circuit D1. The control device 2 may be configured to turn on / off earlier than a control signal by a predetermined time or turn on / off later by a predetermined time. Further, the control device 2 is configured to be able to output two outputs in one pulse circuit, and the driver circuit D2 is controlled to turn on / off earlier than the driver circuit D1 by a predetermined time or turn on / off later by a predetermined time. A separate relay circuit or the like may be incorporated in the device 2 instead of the pulse circuit. Further, at least one of the driver circuit D1 and the driver circuit D2 is provided outside the control device 2, and at least one of the pulse circuits P1 and P2 is electrically connected to the output terminal of the control device 2. good.

半導体装置１及び制御装置２を含むシステム３において、半導体装置１のゲート電極８０と電気的に接続された端子Ｇと制御装置２の出力端子Ｔ１とが電気的に接続されている。そして半導体装置１の補助電極７０と電気的に接続した半導体装置１の端子Ｔ３と制御装置２の出力端子Ｔ２とが電気的に接続されている。
このようなシステム３において、半導体装置１のソース電極９０と電気的に接続した端子Sは、コイルやモータ等の誘導負荷や抵抗などの外部負荷Ｌの一方の端子Ｔ４と電気的に接続され、半導体装置１のドレイン電極１００と電気的に接続した端子Dは、入力（外部電源）ＶOの高圧側の端子Ｔ６と電気的に接続され、コイルやモータ等の誘導負荷や抵抗などの外部負荷Ｌの他方の端子Ｔ５は入力（外部電源）ＶOの低圧側の端子Ｔ７と電気的に接続される。システム３は外部負荷Ｌに流れる電流または電圧を制御する。 In the system 3 including the semiconductor device 1 and the control device 2, the terminal G electrically connected to the gate electrode 80 of the semiconductor device 1 and the output terminal T1 of the control device 2 are electrically connected. The terminal T3 of the semiconductor device 1 electrically connected to the auxiliary electrode 70 of the semiconductor device 1 and the output terminal T2 of the control device 2 are electrically connected.
In such a system 3, the terminal S electrically connected to the source electrode 90 of the semiconductor device 1 is electrically connected to one terminal T4 of an external load L such as an induction load such as a coil or a motor or a resistance, A terminal D electrically connected to the drain electrode 100 of the semiconductor device 1 is electrically connected to a terminal T6 on the high voltage side of the input (external power supply) VO, and an external load L such as an induction load or resistance such as a coil or a motor. The other terminal T5 is electrically connected to a terminal T7 on the low voltage side of the input (external power source) VO. The system 3 controls the current or voltage flowing through the external load L.

図３は制御装置２の端子Ｔ１とＴ２から出力する信号ＶＴ１とＶＴ２を図３で示す。なお、図３において制御装置２の信号に対して半導体装置１がどのようにドレイン・ソース間電流IＤＳとドレイン・ソース間電圧ＶＤＳが生じるか簡略的に説明する波形も併せて示す。
図２の半導体装置１がオフの時、図３の期間Ｐで示すように半導体装置１のゲート電極８０に負電位又はゼロ電位が印加されるように、制御装置２のパルス回路Ｐ１の信号はオフを出力し、ドライバ回路Ｄ１は負電位又はゼロ電位を出力する。よって、制御装置２の端子Ｔ１の電圧ＶＴ１は負電位又はゼロ電位を出力する。一方、図３で示すように半導体装置１の補助電極７０にゲート閾値電圧（閾値電圧）よりも低い正の電位ＶＴ２Ｌが印加されるように、制御装置２のパルス回路Ｐ２の信号はロウ信号を出力し、ドライバ回路Ｄ２は正の電位ＶＴ２Ｌを出力する。
図２の半導体装置１がオフの時、半導体装置１のドレイン・ソース間電流IＤＳは流れず、半導体装置１のドレイン・ソース間電圧ＶＤＳに所定の電圧が印加されている。そして外部負荷Lには電圧が印加されず、電流が流れない。
このとき、半導体装置１のｎ−領域２０には空乏層が広がっている。半導体装置１の補助電極７０にゲート閾値電圧（閾値電圧）よりも低い正の電位ＶＴ２Ｌが印加されているので、ｎ＋領域１０と補助電極７０との電位差は小さくなり、補助電極７０に近い溝近傍における電界集中が緩和される。よって、半導体装置１のオフ時の耐圧を高めることができる。 FIG. 3 shows signals VT1 and VT2 output from the terminals T1 and T2 of the control device 2 in FIG. 3 also shows waveforms that briefly explain how the semiconductor device 1 generates the drain-source current I DS and the drain-source voltage V DS with respect to the signal of the control device 2.
When the semiconductor device 1 of FIG. 2 is off, the signal of the pulse circuit P1 of the control device 2 is such that a negative potential or a zero potential is applied to the gate electrode 80 of the semiconductor device 1 as indicated by the period P of FIG. The driver circuit D1 outputs a negative potential or a zero potential. Therefore, the voltage VT1 at the terminal T1 of the control device 2 outputs a negative potential or a zero potential. On the other hand, as shown in FIG. 3, the signal of the pulse circuit P2 of the control device 2 is a low signal so that a positive potential VT2L lower than the gate threshold voltage (threshold voltage) is applied to the auxiliary electrode 70 of the semiconductor device 1. The driver circuit D2 outputs a positive potential VT2L.
When the semiconductor device 1 of FIG. 2 is off, the drain-source current I DS of the semiconductor device 1 does not flow, a predetermined voltage is applied to the drain-source voltage V DS of the semiconductor device 1. No voltage is applied to the external load L, and no current flows.
At this time, a depletion layer spreads in the n − region 20 of the semiconductor device 1. Since the positive potential VT2L lower than the gate threshold voltage (threshold voltage) is applied to the auxiliary electrode 70 of the semiconductor device 1, the potential difference between the n + region 10 and the auxiliary electrode 70 becomes small, and the groove close to the auxiliary electrode 70 Electric field concentration in the vicinity is relaxed. Therefore, the breakdown voltage when the semiconductor device 1 is turned off can be increased.

制御装置２のパルス回路Ｐ１の信号がオフからオンに切り替えると、図３に示すように、少し遅れてドレイン・ソース間電電流IＤＳは流れ、ドレイン・ソース間電圧ＶＤＳは下がる。これを詳細に見ると、図３の期間Ｑで示すように、制御装置２のパルス回路Ｐ１の信号をオフからオンに切り替えると、ドライバ回路Ｄ１の出力及び制御装置２の端子Ｔ１の電圧ＶＴ１は負電位又はゼロ電位から立ち上がる。半導体装置１のゲート電極８０の電圧ＶＧＳは除々に立ち上がり、電圧ＶＧＥは、やがて正の電圧が印加される。そして半導体装置１のゲート電極８０が半導体装置１の閾値電圧を超えると、図４で示すように半導体装置１のドレイン・ソース間電電流IＤＳが流れ始めて、ドレイン・ソース間電圧ＶＤＳは減少し始める。そして外部負荷Lには電圧が印加され、電流が流れる。
やがて、半導体装置１のドレイン・ソース間電電流IＤＳは、ほぼ一定の定常状態（オン状態）となる。
なお、上記期間Ｑにおいて、半導体装置１の補助電極７０に半導体装置１のゲート閾値電圧（閾値電圧）よりも低い正の電位ＶＴ２Ｌが印加されるように、制御装置２のパルス回路Ｐ２の信号はロウ信号を出力し、ドライバ回路Ｄ２は正の電位ＶＴ２Ｌを出力する。 When the signal of the pulse circuit P1 of the control device 2 is switched from OFF to ON, as shown in FIG. 3, the drain-source current I DS flows with a slight delay, and the drain-source voltage V DS decreases. Looking at this in detail, as shown by the period Q in FIG. 3, when the signal of the pulse circuit P1 of the control device 2 is switched from OFF to ON, the output of the driver circuit D1 and the voltage VT1 of the terminal T1 of the control device 2 are Rise from negative or zero potential. The voltage VGS of the gate electrode 80 of the semiconductor device 1 gradually rises, and a positive voltage is applied as the voltage VGE. When the gate electrode 80 of the semiconductor device 1 exceeds the threshold voltage of the semiconductor device 1, the drain-source current I DS of the semiconductor device 1 starts to flow as shown in FIG. 4, and the drain-source voltage V DS decreases. Begin to. A voltage is applied to the external load L, and a current flows.
Eventually, the drain-source electric current I DS of the semiconductor device 1 is substantially constant steady state (ON state).
In the period Q, the signal of the pulse circuit P2 of the control device 2 is such that a positive potential VT2L lower than the gate threshold voltage (threshold voltage) of the semiconductor device 1 is applied to the auxiliary electrode 70 of the semiconductor device 1. A low signal is output, and the driver circuit D2 outputs a positive potential VT2L.

半導体装置１のゲート電極８０の電圧ＶＧＳがある程度大きくなると、ミラー容量の効果によって、半導体装置１のゲート電極８０の電圧ＶＧＳがほぼ一定のまま、半導体装置１のドレイン・ソース間電圧ＶＤＳが減少する。ミラー効果の終わりになると、再び半導体装置１のゲート電極８０の電圧ＶＧＳが上昇し、やがて一定となる。チャネル抵抗は下がり、半導体装置１のドレイン・ソース間電圧ＶＤＳは低下する。 When the voltage VGS of the gate electrode 80 of the semiconductor device 1 is increased to some extent, by the effect of Miller capacitance, while the voltage VGS of the gate electrode 80 of the semiconductor device 1 is substantially constant, the drain-source voltage V DS of the semiconductor device 1 is reduced To do. When the mirror effect ends, the voltage VGS of the gate electrode 80 of the semiconductor device 1 rises again and becomes constant over time. Channel resistance is lowered, the drain-source voltage V DS of the semiconductor device 1 is lowered.

その後、図３の期間Ｒで示すように半導体装置１の補助電極７０にゲート電極８０の電圧ＶＧＳ以上の電位が印加されるように、制御装置２のパルス回路Ｐ２の出力をロウからハイに切り替え、制御装置２の端子Ｔ２の電圧ＶＴ２は立ち上がり、半導体装置１の補助電極７０に印加される信号がハイとなる。パルス回路Ｐ２がオンの時、半導体装置１の補助電極７０に印加される電圧が半導体装置１のゲート電極８０に印加される電圧以上になるように、制御装置２のドライバ回路Ｄ２の出力する電圧を正の電位ＶＴ２Ｌよりも高い正の電位ＶＴ２Ｈに調整する。一方、図３の期間Ｒで示すように、半導体装置１のゲート電極８０には引き続き閾値以上の正電位が印加されるように、制御装置２のパルス回路Ｐ１の信号はオン信号を出力し、ドライバ回路Ｄ１は正の電位を出力している。よって、制御装置２の端子Ｔ１の電位ＶＴ１は正電位を出力する。
ここで、半導体装置１の補助電極７０に印加される電圧を半導体装置１のゲート電極８０に印加される電圧以上とすることで、半導体装置１のｎ−領域２０の補助電極７０と対向する領域近傍に電子がより多く引きつけられる。これにより、半導体装置１のｎ−領域における補助電極７０と対向する領域の不純物濃度が高まり、半導体装置１のドレイン・ソース間電圧ＶＤＳをより低減することができる。ここで、半導体装置１の補助電極７０に印加される電圧を半導体装置１のゲート電極８０に印加される電圧よりも大きくすることが望ましい。これにより、半導体装置１のｎ−領域における補助電極７０と対向する領域の不純物濃度が更に高まり、半導体装置１のドレイン・ソース間電圧ＶＤＳを更に低減することができる。
なお、制御装置２のパルス回路Ｐ２の出力をオフからオンへ切り替える時点は、ミラー効果の終わりゲート電極８０に印加される電圧の上昇が終わる、ゲート電極８０がほぼ一定の値となった後であることが望ましい。それは、半導体装置１のドレイン・ソース間電圧ＶＤＳの減少に伴う半導体装置１のゲート電極８０と補助電極７０に蓄積された電荷の変化を、補助電極７０側でより効果的に吸収することができ、半導体装置１のドレイン・ソース間電圧ＶＤＳの立ち下がりを早くすることができるためである。なお、制御装置２のパルス回路Ｐ２の出力をオフからオンへ切り替える時点は、外部負荷Ｌ等の影響を考慮し、半導体装置１のドレイン・ソース間電流IＤＳの立ち上がりが終わってドレイン・ソース間電流IＤＳがほぼ一定となった後としても良い。 Thereafter, the output of the pulse circuit P2 of the control device 2 is switched from low to high so that a potential equal to or higher than the voltage VGS of the gate electrode 80 is applied to the auxiliary electrode 70 of the semiconductor device 1 as indicated by a period R in FIG. The voltage VT2 at the terminal T2 of the control device 2 rises, and the signal applied to the auxiliary electrode 70 of the semiconductor device 1 becomes high. The voltage output from the driver circuit D2 of the control device 2 so that the voltage applied to the auxiliary electrode 70 of the semiconductor device 1 is equal to or higher than the voltage applied to the gate electrode 80 of the semiconductor device 1 when the pulse circuit P2 is on. Is adjusted to a positive potential VT2H higher than the positive potential VT2L. On the other hand, as indicated by a period R in FIG. 3, the signal of the pulse circuit P1 of the control device 2 outputs an ON signal so that a positive potential equal to or higher than the threshold value is continuously applied to the gate electrode 80 of the semiconductor device 1. The driver circuit D1 outputs a positive potential. Therefore, the potential VT1 of the terminal T1 of the control device 2 outputs a positive potential.
Here, by setting the voltage applied to the auxiliary electrode 70 of the semiconductor device 1 to be equal to or higher than the voltage applied to the gate electrode 80 of the semiconductor device 1, the region facing the auxiliary electrode 70 of the n − region 20 of the semiconductor device 1. More electrons are attracted to the vicinity. Thereby, the impurity concentration of the region facing the auxiliary electrode 70 in the n − region of the semiconductor device 1 is increased, and the drain-source voltage V DS of the semiconductor device 1 can be further reduced. Here, it is desirable to make the voltage applied to the auxiliary electrode 70 of the semiconductor device 1 larger than the voltage applied to the gate electrode 80 of the semiconductor device 1. Thereby, the impurity concentration in the region facing the auxiliary electrode 70 in the n − region of the semiconductor device 1 is further increased, and the drain-source voltage V DS of the semiconductor device 1 can be further reduced.
Note that the time point when the output of the pulse circuit P2 of the control device 2 is switched from OFF to ON is after the end of the mirror effect and the rise of the voltage applied to the gate electrode 80 has ended, and the gate electrode 80 has reached a substantially constant value. It is desirable to be. That is, it is possible to more effectively absorb the change in the charges accumulated in the gate electrode 80 and the auxiliary electrode 70 of the semiconductor device 1 due to the decrease in the drain-source voltage VDS of the semiconductor device 1 on the auxiliary electrode 70 side. it can, is because it is possible to speed up the fall of the drain-to-source voltage V DS of the semiconductor device 1. Incidentally, when switching the output of the pulse circuit P2 of the control unit 2 from off to on, the external load effects considering such L, between the drain and source ends is rising of the drain-source current I DS of the semiconductor device 1 It may be after the current IDS becomes substantially constant.

図３の期間Ｒで示すように、制御装置２のパルス回路Ｐ２の出力をオフからオンに切り替えた後、制御装置２のパルス回路Ｐ２にロウ信号を出力するまで、半導体装置１のゲート電極８０と補助電極７０に一定の電位が印加されるように、制御装置２のパルス回路Ｐ１及びＰ２はオン信号を出力し、制御装置２のドライバ回路Ｄ１及びＤ２も所定の正の電圧を出力し、制御装置２のＶＴ１，ＶＴ２も所定の正の電圧を出力する。例えば、ゲート電極８０の電圧を５Ｖとなり、補助電極７０の電圧が１２Ｖとなるように、ドライバ回路Ｄ１及びＤ２は出力する。 As indicated by a period R in FIG. 3, after the output of the pulse circuit P2 of the control device 2 is switched from OFF to ON, the gate electrode 80 of the semiconductor device 1 is output until a low signal is output to the pulse circuit P2 of the control device 2. The pulse circuits P1 and P2 of the control device 2 output an ON signal so that a constant potential is applied to the auxiliary electrode 70, and the driver circuits D1 and D2 of the control device 2 also output a predetermined positive voltage, VT1 and VT2 of the control device 2 also output a predetermined positive voltage. For example, the driver circuits D1 and D2 output so that the voltage of the gate electrode 80 becomes 5V and the voltage of the auxiliary electrode 70 becomes 12V.

制御装置２のパルス回路Ｐ１の信号をオフとすることで、半導体装置１のドレイン・ソース間電流IＤＳが流れず、半導体装置１はオフとなる。図３の期間Ｓで示すように、制御装置２のパルス回路Ｐ１がオフ信号を出力する前に、制御装置２のパルス回路Ｐ２はハイからロウの信号に切り替え、制御装置２のドライブ回路Ｄ２の出力を下げ、制御装置２のＶＴ２も半導体装置１のゲート閾値電圧（閾値電圧）未満の正の電位ＶＴ２Ｌが印加されるように、信号を下げる。すると、半導体装置１の補助電極７０に印加される電圧ＶＦＧは徐々に下がり、やがて電圧ＶＦＧＳはオフ状態（電圧ＶＦＧＳが正の電位ＶＴ２Ｌ）となる。
一方、図３の期間Ｓにおいて、制御装置２のパルス回路Ｐ１はオン信号を出力して、制御装置２のドライバ回路Ｄ１も所定の正の電圧を出力し、制御装置２のＶＴ１も所定の正の電圧を出力する。
半導体装置１の補助電極７０に印加される電圧が立ち下がることで、半導体装置１のｎ−領域２０の補助電極７０と対向する領域近傍に電子が集まる量が補助電極７０に正の電位が印加された時に比べて減少し、ドレイン・ソース間電圧ＶＤＳは若干上昇する。これにより電力損失は若干上昇するが、短時間であるので、半導体装置１の発熱が大きく増加するなどの影響は小さい。 By turning off the signal of the pulse circuit P1 of the control device 2, the drain-source current IDS of the semiconductor device 1 does not flow, and the semiconductor device 1 is turned off. As indicated by a period S in FIG. 3, before the pulse circuit P1 of the control device 2 outputs an OFF signal, the pulse circuit P2 of the control device 2 switches from a high signal to a low signal, and the drive circuit D2 of the control device 2 The output is lowered and the signal is lowered so that a positive potential VT2L less than the gate threshold voltage (threshold voltage) of the semiconductor device 1 is also applied to VT2 of the control device 2. Then, the voltage VFG applied to the auxiliary electrode 70 of the semiconductor device 1 gradually decreases, and eventually the voltage VFGS is turned off (the voltage VFGS is a positive potential VT2L).
On the other hand, in the period S of FIG. 3, the pulse circuit P1 of the control device 2 outputs an ON signal, the driver circuit D1 of the control device 2 also outputs a predetermined positive voltage, and VT1 of the control device 2 also has a predetermined positive voltage. Is output.
When the voltage applied to the auxiliary electrode 70 of the semiconductor device 1 falls, the amount of electrons gathered in the vicinity of the region facing the auxiliary electrode 70 of the n − region 20 of the semiconductor device 1 applies a positive potential to the auxiliary electrode 70. is reduced compared to the time was, drain-to-source voltage V DS is increased slightly. As a result, the power loss increases slightly, but since it is a short time, the influence of a large increase in heat generation of the semiconductor device 1 is small.

その後、図３の期間Ｓで示すように、図２のシステムにおいて、制御装置２のパルス回路Ｐ１の信号をオンからオフに切り替える。制御装置２のパルス回路Ｐ１をオフすると、制御装置２のドライバ回路Ｄ１の出力が低下し、図３の期間Ｓで示すように半導体装置１のゲート電圧ＶＧＳは徐々に下がる。
一方、図３の期間Ｓにおいて、パルス回路Ｐ２の信号はハイからロウと切り替わっており、半導体装置１の補助電極７０に印加される電圧を半導体装置１のゲート閾値電圧（閾値電圧）よりも低い正の電位ＶＴ１Ｌとなるように制御装置２のドライバ回路Ｄ２は出力を設定している。
やがて、半導体装置１のゲート電圧ＶＧＳがある電圧にまで下がると、ミラー容量の効果により、半導体装置１のドレイン・ソース間電圧ＶＤＳは上昇するが、ゲート電圧ＶＧＳは一定となる。よって、図２の半導体装置１の電圧ＶＤＳの立ち上がりは早くなり、半導体装置１はより早くオフさせることができる。
ここで、制御装置２のパルス回路Ｐ１の信号をオンからオフに切り替えは、半導体装置１の補助電極７０に印加される電圧ＶＦＧＳの立ち下がりが終わってからの方が望ましい。また、半導体装置１をオンからオフへの切り替えは、図３の期間Ｓにおいて半導体装置１のドレイン・ソース間電圧ＶＤＳが若干上昇することが終わってからの方が望ましい。半導体装置１のドレイン・ソース間電圧ＶＤＳの増加に伴う半導体装置１のゲート電極８０と補助電極７０に蓄積された電荷の変化を、補助電極７０側でより効果的に吸収することができ、半導体装置１のドレイン・ソース間電圧ＶＤＳの立ち上がりを早め、ミラー容量の効果の終了による電流の立ち下がりを早くすることができる。そして半導体装置１がオフになると、外部負荷Lには電流が流れなくなる。 Thereafter, as indicated by a period S in FIG. 3, the signal of the pulse circuit P1 of the control device 2 is switched from on to off in the system of FIG. When the pulse circuit P1 of the control device 2 is turned off, the output of the driver circuit D1 of the control device 2 decreases, and the gate voltage VGS of the semiconductor device 1 gradually decreases as indicated by a period S in FIG.
On the other hand, in the period S of FIG. 3, the signal of the pulse circuit P <b> 2 switches from high to low, and the voltage applied to the auxiliary electrode 70 of the semiconductor device 1 is lower than the gate threshold voltage (threshold voltage) of the semiconductor device 1. The driver circuit D2 of the control device 2 sets an output so as to be a positive potential VT1L.
Eventually, once it has cooled down to a voltage that the gate voltage VGS of the semiconductor device 1, the effect of Miller capacitance, drain-source voltage V DS of the semiconductor device 1 is increased, the gate voltage VGS is constant. Therefore, the rise of the voltage VDS of the semiconductor device 1 in FIG. 2 is quickened, and the semiconductor device 1 can be turned off earlier.
Here, it is preferable that the signal of the pulse circuit P1 of the control device 2 is switched from on to off after the fall of the voltage VFGS applied to the auxiliary electrode 70 of the semiconductor device 1 is finished. Also, switching off the semiconductor device 1 from on, who after the end of the drain-source voltage V DS of the semiconductor device 1 is increased slightly in the period S in FIG. 3 is desirable. The change in the charge accumulated in the gate electrode 80 and the auxiliary electrode 70 of the semiconductor device 1 accompanying the increase in the drain-source voltage VDS of the semiconductor device 1 can be more effectively absorbed on the auxiliary electrode 70 side, the rise of the drain-source voltage V DS of the semiconductor device 1 can be advanced earlier, the fall of the current due to termination of the effect of Miller capacitance. When the semiconductor device 1 is turned off, no current flows through the external load L.

上記で示す期間Ｐ、Ｑ、Ｒ、Ｓを繰り返すことで、図３のように繰り返し波形となり、半導体装置は制御装置によって制御される。
なお、本発明は、上記実施形態に限定されるものではない。上記実施形態は、例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様の作用効果をそうするものは、いかなるものであっても本発明に含まれる。
たとえば、上記の構成は、いずれもｎチャネル型の素子であったが、導電型（ｐ型、ｎ型）を逆転させ、ｐチャネル型の半導体装置を同様に得ることができることは明らかである。
また、n−領域２０が深さ方向に不純物濃度が異なる複数の層からなる場合も同様の効果を奏することも明らかである。また、ゲート電極８０が溝の中央側で分断し、ゲート電極８０がｐ―領域４０と対向する第１の溝３０の側面のみに絶縁膜６０を介して配置されている場合も同様の効果を奏することも明らかである。
また、半導体装置１と制御装置２との間、ドライバ回路Ｄ１とパルス回路Ｐ１との間、またドライバ回路Ｄ２とパルス回路Ｐ２との間にフォトカプラのように半導体装置１と制御装置２とを絶縁する回路を設けた場合やアンプのような増幅回路を設けた場合においても、本発明を実現することができることも明らかである。 By repeating the periods P, Q, R, and S described above, a repetitive waveform is obtained as shown in FIG. 3, and the semiconductor device is controlled by the control device.
The present invention is not limited to the above embodiment. The above embodiment is an exemplification, and has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that has the same function and effect can be used. It is included in the present invention.
For example, each of the above configurations is an n-channel element, but it is apparent that a p-channel semiconductor device can be similarly obtained by reversing the conductivity type (p-type and n-type).
It is also clear that the same effect can be obtained when the n− region 20 is composed of a plurality of layers having different impurity concentrations in the depth direction. The same effect can also be obtained when the gate electrode 80 is divided at the center of the groove and the gate electrode 80 is disposed only on the side surface of the first groove 30 facing the p − region 40 via the insulating film 60. It is clear that he plays.
Further, between the semiconductor device 1 and the control device 2, between the driver circuit D1 and the pulse circuit P1, and between the driver circuit D2 and the pulse circuit P2, the semiconductor device 1 and the control device 2 are connected like a photocoupler. It is apparent that the present invention can be realized even when an insulating circuit is provided or an amplifier circuit such as an amplifier is provided.

１ 半導体装置
２ 制御装置
３ システム
１０ ｎ＋領域
２０ ｎ−領域
３０ 第１の溝
４０ ｐ―領域
５０ ｎ＋領域
６０ 絶縁膜
７０ 補助電極
８０ ゲート電極
９０ ソース電極
１００ ドレイン電極
１１０ ｐ＋コンタクト領域
１２０ 第２の溝
１４０ 層間絶縁膜
Ｄ１、Ｄ２ ドライバ回路
Ｐ１、Ｐ２ パルス回路 1 semiconductor device 2 control unit 3 system 10 n + region 20 n - region 30 first groove 40 p - region 50 n + region 60 insulating film 70 auxiliary electrode 80 gate electrode 90 source electrode 100 drain electrode 110 p + contact region 120 Second groove 140 Interlayer insulating film D1, D2 Driver circuit P1, P2 Pulse circuit

Claims (4)

第1導電型の第1半導体領域と、
前記第1半導体領域上に配置され、前記第1半導体領域よりも不純物濃度の低い第１導電型の第２半導体領域と、
前記第２半導体領域上に配置された、第1導電型と反対導電型である第２導電型の第３半導体領域と、
前記第３半導体領域上に配置された、第１導電型の第４半導体領域と、
前記第４半導体領域から前記第３半導体領域を貫通し、前記第２半導体領域に達する溝と、
前記第３半導体領域と対向する前記溝の側壁上に絶縁膜を介して前記溝内に配置された制御電極と、
前記第２半導体領域と対向する前記溝の壁面上に絶縁膜を介して前記溝内に配置された補助電極と、
前記第４半導体領域と電気的に接続された第１の主電極と、
前記第1半導体領域と電気的に接続された第２の主電極と、
を備える半導体装置を制御する制御装置であって、
前記制御装置は
前記半導体装置の前記制御電極に閾値未満の電位の信号を出力している時、前記半導体装置の閾値未満の電位を前記補助電極に与えるように信号を出力し、
前記半導体装置の前記制御電極に閾値以上の電位の信号を出力した後、前記補助電極に印加される電圧を前記制御電極に印加される電圧以上に上げる信号を出力することを特徴とする制御装置。 A first semiconductor region of a first conductivity type;
A second semiconductor region of a first conductivity type disposed on the first semiconductor region and having an impurity concentration lower than that of the first semiconductor region;
A third semiconductor region of a second conductivity type disposed on the second semiconductor region and having a conductivity type opposite to the first conductivity type;
A fourth semiconductor region of a first conductivity type disposed on the third semiconductor region;
A groove penetrating from the fourth semiconductor region to the third semiconductor region and reaching the second semiconductor region;
A control electrode disposed in the groove via an insulating film on a side wall of the groove facing the third semiconductor region;
An auxiliary electrode disposed in the groove on the wall surface of the groove facing the second semiconductor region via an insulating film;
A first main electrode electrically connected to the fourth semiconductor region;
A second main electrode electrically connected to the first semiconductor region;
A control device for controlling a semiconductor device comprising:
When the control device outputs a signal having a potential lower than a threshold value to the control electrode of the semiconductor device, the control device outputs a signal so that a potential lower than the threshold value of the semiconductor device is applied to the auxiliary electrode,
A control device that outputs a signal having a potential equal to or higher than a threshold value to the control electrode of the semiconductor device, and then increases a voltage applied to the auxiliary electrode to be higher than a voltage applied to the control electrode. . 前記補助電極を下げたことによる前記半導体装置の伝導度変調の飽和が浅くなった後に、前記半導体装置をオフさせるように前記制御電極にオフ信号を出力することを特徴とする請求項１の制御装置。   2. The control according to claim 1, wherein an off signal is output to the control electrode so as to turn off the semiconductor device after the saturation of conductivity modulation of the semiconductor device due to the lowering of the auxiliary electrode becomes shallow. apparatus. 前記半導体装置の前記補助電極と前記溝の底面と間にフローティング電位の導電層を含む、
又は前記溝の底面の下の前記第２半導体領域内に第２導電型のフローティング領域を含んだ半導体装置を制御することを特徴とする請求項１又は２の制御装置。 Including a conductive layer having a floating potential between the auxiliary electrode of the semiconductor device and a bottom surface of the groove;
The control device according to claim 1, wherein the control device controls a semiconductor device including a floating region of a second conductivity type in the second semiconductor region below the bottom surface of the groove. 請求項１〜３の何れか１項に記載の制御装置は、
前記半導体装置の前記制御電極へ信号を出力する第１のドライバ回路と、
前記第1のドライバ回路がオンとオフの信号を出力するように制御信号を出力する第１のパルス回路と、
前記第１のパルス回路の出力信号に応じて出力する第１の出力端子と、
前記半導体装置の前記補助電極へ信号を出力する第２のドライバ回路と、
前記第２のドライバ回路がオンとオフの信号を出力するように制御信号を出力する第２のパルス回路と、
前記第２のパルス回路の出力信号に応じて出力する第２の出力端子と、
を含み、
前記第１の出力端子は前記制御電極と電気的に接続し、
前記第２の出力端子は前記補助電極と電気的に接続し、
前記第１の主電極または第２の主電極と電気的に接続された外部負荷に印加される電圧を制御することを特徴とするシステム。 The control device according to any one of claims 1 to 3,
A first driver circuit for outputting a signal to the control electrode of the semiconductor device;
A first pulse circuit that outputs a control signal so that the first driver circuit outputs an on and off signal;
A first output terminal that outputs in response to an output signal of the first pulse circuit;
A second driver circuit for outputting a signal to the auxiliary electrode of the semiconductor device;
A second pulse circuit that outputs a control signal so that the second driver circuit outputs an on and off signal;
A second output terminal that outputs in accordance with an output signal of the second pulse circuit;
Including
The first output terminal is electrically connected to the control electrode;
The second output terminal is electrically connected to the auxiliary electrode;
A system for controlling a voltage applied to an external load electrically connected to the first main electrode or the second main electrode.
JP2017047537A 2017-03-13 2017-03-13 Controller, and system including controller and semiconductor device controlled by that controller Pending JP2018152460A (en)

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