JP2013251395A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a switching speed in turn-off.SOLUTION: A semiconductor device comprises a separation insulation film 8 arranged in each trench for dividing a gate electrode 7 into a first gate electrode 7a located on an opening side of the trench 5 and a second gate electrode 7b located on a bottom side of the trench 5 so as to enable independent control over the first and second gate electrodes 7a, 7b from each other. When electrical continuity is established, a voltage is applied to the first gate electrode 7a so as to form an inversion layer 14 in a base layer 4 at a part which contacts a gate insulation film 6 under the first gate electrode 7a, and a voltage is applied to the second gate electrode 7b so as to form an accumulation layer 15 in a drift layer 3 at a part which contacts the gate insulation film 6 under the second gate electrode 7b. When the semiconductor device is turned off, a voltage is applied to the second gate electrode 7b so as to vanish the accumulation layer 15 and subsequently, a voltage is applied to the first gate electrode 7a after the elapse of a predetermined period of time so as to vanish the inversion layer 14.

Description

  The present invention relates to a semiconductor device in which a trench gate type insulated gate bipolar transistor (hereinafter simply referred to as IGBT) is formed.

  Conventionally, as one of power conversion semiconductor devices, a semiconductor device in which an IGBT used in an electronic device such as an industrial motor is formed is known. A semiconductor device in which a general IGBT is formed is as follows. It is configured as follows.

That is, an N ⁻ type drift layer is formed on the P ⁺ type collector layer, a P type base layer is formed on the surface layer portion of the drift layer, and an N ⁺ type emitter layer is formed on the surface layer portion of the base layer. Is formed. In addition, a plurality of trenches that penetrate the base layer and the emitter layer and reach the drift layer are extended in a stripe shape. A gate insulating film and a gate electrode are sequentially formed on the wall surface of each trench.

  Further, an emitter electrode is provided on the base layer and the emitter layer via an interlayer insulating film, and the base layer, the emitter layer, and the emitter electrode are electrically connected via a contact hole formed in the interlayer insulating film. It is connected to the. Further, a collector electrode electrically connected to the collector layer is provided on the back surface of the collector layer.

  In such a semiconductor device, when a predetermined gate voltage is applied to the gate electrode, an inversion layer is formed in a portion of the base layer in contact with the gate insulating film disposed in the trench, and the drift layer An electron accumulation layer is formed in a portion in contact with the gate insulating film disposed in the trench. Then, electrons flow from the emitter layer into the drift layer through the inversion layer and the accumulation layer, and holes flow from the collector layer to the drift layer, and the resistance value of the drift layer is lowered by the conductivity modulation and turned on. .

  A semiconductor device in which such an IGBT is formed can achieve a lower on-voltage than a semiconductor device in which a MOSFET is formed. However, in recent years, it has been desired to further reduce the on-voltage.

  For this reason, for example, Patent Document 1 discloses that the width of the adjacent gate electrode is extremely narrow as 0.55 nm to 0.3 μm.

JP 2007-43123 A

  However, the semiconductor device disclosed in Patent Document 1 has a problem in that a large amount of holes are accumulated in the drift layer during conduction, resulting in a slow switching speed during turn-off.

  The above problem occurs not only in a semiconductor device in which an N-channel IGBT is formed but also in a semiconductor device in which a P-channel IGBT is formed.

  An object of the present invention is to provide a semiconductor device capable of increasing the switching speed at turn-off in view of the above points.

  In order to achieve the above object, according to the first aspect of the present invention, the drift layer (3) of the first conductivity type, the base layer (4) of the second conductivity type formed in the surface layer portion of the drift layer, and the drift A second conductivity type collector layer (1) formed at a position separated from the base layer, and a plurality of trenches (5) extending through the base layer to reach the drift layer and extending in a predetermined direction; The gate insulating film (6) formed on the wall surface of the trench, the gate electrode (7) respectively formed on the gate insulating film, and the surface layer portion of the base layer, formed on the side portion of the trench In a semiconductor device comprising a first conductivity type emitter layer (9), an emitter electrode (12) electrically connected to the emitter layer, and a collector electrode (13) electrically connected to the collector layer, It has the following features.

  That is, in the trench, the gate electrode is divided in the depth direction of the trench into a first gate electrode (7a) located on the opening side of the trench and a second gate electrode (7b) located on the bottom side of the trench. An isolation insulating film (8) is arranged, and the first and second gate electrodes can be controlled independently of each other. When conducting, a voltage is applied to the first gate electrode to form an inversion layer (14) in a portion of the base layer in contact with the gate insulating film below the first gate electrode, and the second layer When the gate electrode is applied with a voltage for forming the storage layer (15) in a portion of the drift layer in contact with the gate insulating film under the second gate electrode, the storage layer disappears in the second gate electrode when turned off. The voltage at which the inversion layer disappears is applied to the first gate electrode after a predetermined period has elapsed after the voltage to be applied is applied.

  According to this, after a voltage at which the storage layer disappears is applied to the second gate electrode, a voltage at which the inversion layer disappears is applied to the first gate electrode in order to turn off the semiconductor device. That is, a part of carriers (holes or electrons) accumulated in the drift layer is extracted in advance when the semiconductor device is conducting, and then the semiconductor device is turned off. Therefore, when the semiconductor device is turned off, that is, when a voltage at which the inversion layer disappears is applied to the first gate electrode, the extraction period of carriers (holes or electrons) accumulated in the drift layer is shortened. The switching speed can be increased. In other words, switching loss can be reduced.

  Further, as in the invention described in claim 2, at least a part of each of the isolation insulating films arranged in the plurality of trenches is located on the drift layer side with respect to the boundary between the base layer and the drift layer. be able to.

  According to this, the front-end | tip part by the side of the 2nd gate electrode among 1st gate electrodes is facing the drift layer through the gate insulating film arrange | positioned at the side wall of a trench. For this reason, even in the period from when the voltage at which the storage layer disappears is applied to the second gate electrode to when the voltage at which the inversion layer disappears is applied to the first gate electrode, the base layer changes from the emitter layer to the drift layer. A reaching inversion layer is formed. For this reason, even during this period, carriers (holes or electrons) easily flow from the emitter layer into the drift layer, and an increase in on-voltage can be suppressed.

  In this case, as in the third aspect of the invention, the remaining portions of the isolation insulating films disposed in the plurality of trenches are on the base layer side with respect to the boundary between the base layer and the drift layer, and the base layer It can be located on the drift layer side with respect to the portion where the impurity concentration is maximum.

  According to a fourth aspect of the present invention, at least a part of each of the isolation insulating films arranged in the plurality of trenches is closer to the base layer than the boundary between the base layer and the drift layer, and the base It can be located closer to the drift layer than the portion where the impurity concentration of the layer is maximum.

  According to the third and fourth aspects of the present invention, the tip of the first gate electrode on the second gate electrode side faces the base layer via the gate insulating film disposed on the sidewall of the trench. . Therefore, the base layer reaches the drift layer from the emitter layer during the period from when the voltage at which the accumulation layer disappears is applied to the second gate electrode to when the voltage at which the inversion layer disappears is applied to the first gate electrode. An inversion layer that is not formed is formed. For this reason, carriers (holes or electrons) accumulated in the drift layer easily flow into the base layer, and a large amount of carriers (holes or electrons) can be extracted during this period. For this reason, the switching speed can be further increased.

  When the voltage at which the storage layer disappears is applied to the second gate electrode as in the fifth aspect of the invention, the drift layer is inverted to a portion in contact with the gate insulating film below the second gate electrode. The voltage at which the layer (16) is formed can be applied.

  According to this, carriers (holes or electrons) accumulated in the drift layer by the accumulation layer can easily flow into the base layer, and a large amount of carriers (holes or electrons) can be extracted. For this reason, the switching speed can be further increased.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

It is a figure showing the section composition of the semiconductor device in a 1st embodiment of the present invention. 2A is a schematic diagram illustrating a state of the semiconductor device illustrated in FIG. 1, and FIG. 2A illustrates a state in which a voltage higher than a threshold voltage is applied to a first gate electrode and a positive voltage is applied to a second gate electrode. (B) is a schematic diagram showing a state in which a voltage higher than the threshold voltage is applied to the first gate electrode and 0 V is applied to the second gate electrode, and (c) is a threshold value applied to the first gate electrode. It is a schematic diagram which shows the state in which the voltage lower than a voltage is applied and the negative voltage is applied to the 2nd gate electrode. 2 is a timing chart when the semiconductor device shown in FIG. 1 is turned off. It is a figure which shows the relationship between the voltage applied to a 1st gate electrode and a 2nd gate electrode, and switching. It is a figure which shows the cross-sectional structure of the semiconductor device in 2nd Embodiment of this invention. FIG. 7 is a schematic diagram showing a state where a voltage higher than a threshold voltage is applied to the first gate electrode and 0 V is applied to the second gate electrode in the semiconductor device shown in FIG. 6. It is a figure which shows the cross-sectional structure of the semiconductor device in 3rd Embodiment of this invention. It is a figure which shows the cross-sectional structure of the semiconductor device in other embodiment of this invention. It is a figure which shows the cross-sectional structure of the semiconductor device in other embodiment of this invention. It is a figure which shows the cross-sectional structure of the semiconductor device in other embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings. As shown in FIG. 1, on the collector layer 1 of P ⁺ type, N-type field stop layer (hereinafter, FS layer hereinafter) 2 is formed, on the FS layer 2 is N ^- type The drift layer 3 is formed. The FS layer 2 is not necessarily required, but is provided to improve the breakdown voltage and steady loss performance by preventing the depletion layer from spreading. A P-type base layer 4 is formed on the surface layer portion of the drift layer 3.

  A plurality of trenches 5 that penetrate the base layer 4 and reach the drift layer 3 are formed. In the present embodiment, the plurality of trenches 5 are formed at a predetermined interval (pitch) and have a stripe structure extending in parallel in a predetermined direction (a direction perpendicular to the paper in FIG. 1). Here, a description will be given of a case where the plurality of trenches 5 have a stripe structure. However, the trenches 5 are formed in an annular structure by extending in parallel and then being routed at the tip portions thereof. May be.

  In each trench 5, a gate insulating film 6 made of a thermal oxide film or the like formed so as to cover the inner wall surface of each trench 5 and a gate electrode 7 made of polysilicon or the like are sequentially arranged, An isolation insulating film 8 that divides the gate electrode 7 in the depth direction of the trench 5 is disposed. That is, the gate electrode 7 is separated by the isolation insulating film 8 into the first gate electrode 7 a disposed on the opening side of the trench 5 and the second gate electrode 7 b disposed on the bottom side of the trench 5.

  The first gate electrode 7a is drawn on the base layer 4 in a cross section different from that of FIG. 1, and is electrically connected to the first gate pad via a gate wiring (not shown). Similarly, the second gate electrode 7b is drawn on the base layer 4 in a cross section different from that of FIG. 1, and is electrically connected to the second gate pad via a gate wiring (not shown). That is, the first and second gate electrodes 7a and 7b are controlled independently.

  In addition, the isolation insulating film 8 is disposed on the drift layer 3 side of the trench 5 with respect to the boundary between the drift layer 3 and the base layer 4. That is, the tip of the first gate electrode 7 a on the second gate electrode 7 b side faces the drift layer 3 through the gate insulating film 6 disposed on the side wall of the trench 5.

An N ⁺ type emitter layer 9 is formed on the surface layer portion of the base layer 4 so as to be in contact with the side surface of the trench 5, and a P ⁺ type body layer 10 is formed at a position away from the side surface of the trench 5. ing. Specifically, the emitter layer 9 is extended in a rod shape so as to be in contact with the side surface of the trench 5 along the longitudinal direction of the trench 5, and has a structure that terminates inside the tip of the trench 5. The body layer 10 is sandwiched between the two emitter layers 9 and extends in a rod shape along the longitudinal direction of the trench 5 (that is, the emitter layer 9), and terminates inside the tip of the trench 5 Has been. The emitter layer 9 and the body layer 10 are sufficiently higher in concentration than the base layer 4 and are structured to terminate in the base layer 4.

  An interlayer insulating film 11 made of BPSG or the like is formed on the base layer 4. A contact hole 11 a is formed in the interlayer insulating film 11, and a part of the emitter layer 9 and the body layer 10 are exposed from the interlayer insulating film 11. An emitter electrode 12 is formed on the interlayer insulating film 11, and the emitter electrode 12 is electrically connected to the emitter layer 9 and the body layer 10 through a contact hole 11a.

  A collector electrode 13 electrically connected to the collector layer 1 is formed on the back side of the collector layer 1.

The above is the configuration of the semiconductor device in this embodiment. In the present embodiment, the N type, N ⁻ type, and N ⁺ type correspond to the first conductivity type of the present invention, and the P type and P ⁺ type correspond to the second conductivity type of the present invention.

  Next, the operation of the semiconductor device will be described with reference to FIGS. In FIG. 2, the emitter layer 9, the body layer 10, and the interlayer insulating film 11 are omitted. The voltage Vth in FIGS. 2 and 3 is a threshold voltage for forming the inversion layer 14 in a portion of the base layer 4 in contact with the gate insulating film 6 below the first gate electrode 7a.

  First, a state where the semiconductor device is conductive (turned on) will be described. As shown in FIG. 2A, when a voltage higher than the threshold voltage Vth is applied to the first gate electrode 7a, an N-type is formed in a portion of the base layer 4 in contact with the gate insulating film 6 below the first gate electrode 7a. When an inversion layer 14 is formed and a positive voltage is applied to the second gate electrode 7b, the storage layer 15 is formed in a portion of the drift layer 3 in contact with the gate insulating film 6 below the first and second gate electrodes 7a and 7b. It is formed.

  Electrons flow from the emitter layer 9 into the drift layer 3 through the inversion layer 14 and the storage layer 15, and holes flow from the collector layer 1 into the drift layer 3, and the resistance value of the drift layer 3 is reduced by conductivity modulation. It drops and turns on.

  At this time, since a positive voltage is applied to the second gate electrode 7b to form the storage layer 15, the storage layers adjacent to each other have a circulation path for holes accumulated in the drift layer 3 to escape to the base layer 4. It becomes a region between 15 and narrows. For this reason, the on-voltage can be reduced.

  In the present embodiment, applying a positive voltage to the second gate electrode 7b corresponds to applying a voltage for forming a storage layer to the second gate electrode of the present invention. The first and second gate electrodes 7a and 7b can be controlled independently of each other as described above. However, when the semiconductor device is conductive, the first and second gate electrodes 7a and 7b have the same voltage. May be applied. That is, the same voltage as that of the first gate electrode 7a may be applied to the second gate electrode 7b, and in this case, an on-voltage similar to that of the conventional semiconductor device can be obtained.

  Next, a state when the semiconductor device is turned off will be described. As shown in FIG. 3, when the semiconductor device is turned off, 0 V is applied to the second gate electrode 7b at time T1, and then the first gate electrode 7a is lower than the threshold voltage Vth at time T2. A voltage is applied to turn off.

  That is, the period from time T1 to time T2 is a period in which a voltage higher than the threshold voltage Vth is applied to the first gate electrode 7a and a voltage of 0 V is applied to the second gate electrode 7b. At this time, as shown in FIG. 2B, the accumulation layer 15 formed in the portion in contact with the gate insulating film 6 under the second gate electrode 7b disappears, and the hole flow path in the drift layer 3 is expanded. . For this reason, holes accumulated in the drift layer 3 are more likely to flow into the base layer 4 than before time T1. That is, the period from time T1 to time T2 is a period during which the carrier concentration of the drift layer 3 is reduced. Note that this period is a period in which the semiconductor device is conductive although the on-state voltage slightly increases.

  As shown in FIG. 3, when a voltage lower than the threshold voltage Vth is applied to the first gate electrode 7a in order to turn off the semiconductor device at the time point T2, the collector-emitter voltage Vce increases. As a result, the collector current Ic decreases, and the semiconductor device is turned off. At this time, during the period from time T1 to time T2, a part of the holes accumulated in the drift layer 3 is extracted in advance, so that the switching speed when turned off can be increased.

  Further, as the voltage applied to the second gate electrode 7b at time T1, a negative voltage may be applied as shown in FIG. When a negative voltage is applied to the second gate electrode 7b, after the storage layer 15 formed in the portion of the drift layer 3 in contact with the gate insulating film 6 below the second gate electrode 7b disappears, this storage layer A P-type inversion layer 16 is formed in the region where 15 has been formed. That is, in the period from the time T1 to the time T2, the holes accumulated in the drift layer 3 are attracted to the vicinity of the trench 5 and easily flow into the base layer 4. For this reason, holes accumulated in the drift layer 3 can be extracted in advance while conducting the semiconductor device. Therefore, the switching speed when turned off can be further increased.

  As shown in FIGS. 3 and 4, in the semiconductor device, a period during which a voltage higher than the threshold voltage Vth is applied to the first gate electrode 7a (period until time T2) is a conducting period. The turn-off starts from time T2. That is, in the semiconductor device of this embodiment, the first gate electrode 7a exhibits a function of controlling switching (turn-on or turn-off), and the second gate electrode 7b does not control switching (turn-on or turn-off). It functions as a so-called control gate electrode for controlling the carrier concentration of the drift layer 3.

  Further, since the holes in the drift layer 3 are extracted as the period between the time point T1 and the time point T2 in FIG. 3 becomes longer, the switching speed at turn-off can be increased. However, the longer the period between the time point T1 and the time point T2, the more holes are extracted from the drift layer 3, so the on-voltage becomes higher. For this reason, the period between the time point T1 and the time point T2 cannot be determined unconditionally. For example, by setting 1 to 10 μs, it is possible to increase the switching speed while suppressing the ON voltage from becoming too high. it can.

  As described above, in the semiconductor device of this embodiment, the gate electrode 7 includes the first gate electrode 7 a located on the opening side of the trench 5 and the second gate electrode 7 b located on the bottom side of the trench 5. The first and second gate electrodes 7a and 7b are separated and separated by the isolation insulating film 8, and are controlled independently.

  Then, after 0V or a negative voltage is applied to the second gate electrode 7b, a voltage lower than the threshold voltage Vth is applied to the first gate electrode 7a in order to turn off the semiconductor device. That is, some of the holes accumulated in the drift layer 3 are extracted in advance when the semiconductor device is conducting, and then the semiconductor device is turned off. Therefore, when the semiconductor device is turned off, that is, when a voltage lower than the threshold voltage Vth is applied to the first gate electrode 7a, the extraction period of holes accumulated in the drift layer 3 can be shortened, The switching speed can be increased. In other words, switching loss can be reduced.

  The semiconductor device is effective if it is a trench gate type IGBT, but is particularly preferably applied to a device in which a large amount of holes are accumulated in the drift layer 3 when conducting. That is, it is preferably applied to a so-called narrow mesa type trench gate type IGBT in which the space between the trenches 5 is minimized in order to reduce the on-voltage.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the arrangement location of the isolation insulating film 8 is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment, and thus the description thereof is omitted here.

  As shown in FIG. 5, in this embodiment, the isolation insulating film 8 is located closer to the base layer 4 than the boundary between the drift layer 3 and the base layer 4. In other words, the tip of the first gate electrode 7 a on the second gate electrode 7 b side faces the base layer 4 with the gate insulating film 6 interposed therebetween. And the front-end | tip part by the side of the 2nd gate electrode 7b among the 1st gate electrodes 7a is formed from the area | region where the impurity concentration of the base layer 4 becomes the maximum to the drift layer 3 side.

  That is, as described above, the first gate electrode 7a controls switching of the semiconductor device, and the threshold voltage Vth of the MOS gate depends on the maximum impurity concentration of the base layer 4. When a voltage higher than the threshold voltage Vth is applied to the first gate electrode 7a, the tip of the first gate electrode 7a on the second gate electrode 7b side is from the region where the impurity concentration is maximum in the base layer 4. If it is formed up to the drift layer 3 side, a current flows between the collector and the emitter. For this reason, the first gate electrode 7 a is formed from the region of the base layer 4 where the impurity concentration is maximum to the drift layer 3 side, and terminates in the base layer 4.

  In such a semiconductor device, when 0 V is applied to the second gate electrode 7b at time T1 in FIG. 3, as shown in FIG. 6, the gate insulation under the second gate electrode 7b in the base layer 4 is performed. The inversion layer 14 in the portion in contact with the film 6 also disappears. That is, in the period from the time T1 to the time T2, although the semiconductor device is conductive, the inversion layer 14 that does not reach the drift layer 3 from the emitter layer 9 is formed, and holes accumulated in the drift layer 3 are formed. Part of the gas easily flows into the base layer 4. For this reason, holes can be further extracted during the period from the time point T1 to the time point T2, and the switching speed when turned off can be further increased.

(Third embodiment)
A third embodiment of the present invention will be described. The present embodiment is a combination of the first and second embodiments, and the other aspects are the same as those of the first embodiment, and thus the description thereof is omitted here.

  As shown in FIG. 7, in this embodiment, the base layer 4 is not fixed in depth, and is deepened in the vicinity of one of the adjacent trenches 5 and shallow in the vicinity of the other trench 5. ing. And in the gate electrode 7 arrange | positioned at the adjacent trench 5, the 1st gate electrode 7a arrange | positioned at one trench 5 is the gate insulation by which the front-end | tip part by the side of the 2nd gate electrode 7b was arrange | positioned at the side wall of the trench 5 The first gate electrode 7 a disposed opposite to the drift layer 3 through the film 6 and disposed in the other trench 5 has a gate insulating film 6 whose tip on the second gate electrode 7 b side is disposed on the sidewall of the trench 5. Via the base layer 4.

  In such a semiconductor device, when 0 V is applied to the second gate electrode 7b at time T1 in FIG. 3, the inversion layer 14 reaching the drift layer 3 from the emitter layer 9 is formed on the side of one trench 5. The inversion layer 14 that does not reach the drift layer 3 from the emitter layer 9 is formed on the side of the other trench 5 (see FIG. 6). That is, in the period from the time point T 1 to the time point T 2, electrons easily flow into the drift layer 3 at the side portion of the one trench 5, and holes easily flow into the base layer 4 at the side portion of the other trench 5. For this reason, it is possible to improve the switching speed while reducing the on-voltage.

  In such a semiconductor device, for example, when the base layer 4 is formed by ion-implanting impurities into the drift layer 3, the acceleration voltage and the mask are partially changed to reduce the depth of the base layer 4. It is manufactured by making it partially different.

(Other embodiments)
In each of the above embodiments, the first conductivity type is N type and the second conductivity type is P type. However, the first conductivity type may be P type and the second conductivity type may be N type. it can.

  In the third embodiment, for example, as shown in FIG. 8, when adjacent trenches 5 are set as a set, the base layer 4 is deepened in the vicinity of one set of trenches 5 in the adjacent set, and the other set is set. It may be shallow in the vicinity of the trench 5. In other words, the first gate electrode 7 a disposed in one of the adjacent pairs of trenches 5 has a drift layer via the gate insulating film 6 in which the tip on the second gate electrode 7 b side is disposed on the side wall of the trench 5. 3, the first gate electrode 7 a disposed in the other set of trenches 5 has a base layer 4 via a gate insulating film 6 having a tip on the second gate electrode 7 b side disposed on the side wall of the trench 5. You may make it oppose.

  Further, as shown in FIG. 9, the base layer 4 is deepened in the vicinity of the trench 5 formed on one side (left side in FIG. 8) in the direction perpendicular to the extending direction of the trench 5, and the other side (FIG. 9). 8 may be shallow in the vicinity of the trench 5 formed on the right side of the paper surface. That is, the first gate electrode 7 a disposed in the trench 5 formed on one side is connected to the drift layer 3 via the gate insulating film 6 having the tip on the second gate electrode 7 b side disposed on the sidewall of the trench 5. The first gate electrode 7a disposed in the trench 5 facing the other side of the base layer 4 via the gate insulating film 6 having the tip on the second gate electrode 7b side disposed on the side wall of the trench 5 is provided. You may make it oppose.

Further, in each of the above embodiments, as shown in FIG. 10, a semiconductor including an N ⁺ type cathode layer 17 adjacent to the collector layer 1 and the drift layer 3 formed on the collector layer 1 and the cathode layer 17. It is good also as an apparatus. That is, the present invention is applied to a semiconductor device in which a so-called RC (Reverse-Conducting) -IGBT in which a region where the collector layer 1 is formed is an IGBT region and a region where the cathode layer 17 is formed is a diode region is formed. You can also In this case, the collector layer 1 and the cathode layer 17 may be formed in a lattice shape.

  In each of the above embodiments, the vertical semiconductor device in which current flows in the thickness direction of the drift layer 3 has been described. However, the collector layer 1 is formed at a position separated from the base layer 4 in the surface layer portion of the drift layer 3. In addition, a lateral semiconductor device in which a current flows in the plane direction of the drift layer 3 can be obtained.

DESCRIPTION OF SYMBOLS 1 Collector layer 2 FS layer 3 Drift layer 4 Base layer 5 Trench 6 Gate insulating film 7 Gate electrode 7a 1st gate electrode 7b 2nd gate electrode 8 Separation insulating film 9 Emitter layer 10 Body layer 11 Interlayer insulating film 12 Emitter electrode 13 Collector electrode

Claims (6)

A first conductivity type drift layer (3);
A second conductivity type base layer (4) formed on the surface layer of the drift layer;
A collector layer (1) of a second conductivity type formed at a position separated from the base layer in the drift layer;
A plurality of trenches (5) extending through the base layer and reaching the drift layer in a predetermined direction;
Gate insulating films (6) respectively formed on the wall surfaces of the trenches;
Gate electrodes (7) respectively formed on the gate insulating film;
A first conductive type emitter layer (9) formed on a surface of the base layer and on a side of the trench;
An emitter electrode (12) electrically connected to the emitter layer;
A collector electrode (13) electrically connected to the collector layer,
In the trench, the gate electrode is divided into a first gate electrode (7a) located on the opening side of the trench and a second gate electrode (7b) located on the bottom side of the trench. An isolation insulating film (8) divided in the vertical direction is disposed, and the first and second gate electrodes can be controlled independently of each other,
When conducting, a voltage is applied to the first gate electrode to form an inversion layer (14) in a portion of the base layer in contact with the gate insulating film below the first gate electrode, and A voltage is applied to the second gate electrode to form a storage layer (15) in a portion of the drift layer in contact with the gate insulating film under the second gate electrode,
When turning off, a voltage at which the storage layer disappears is applied to the second gate electrode, and then a voltage at which the inversion layer disappears is applied to the first gate electrode after a predetermined period. A semiconductor device.   The at least one part of each said isolation insulating film arrange | positioned at these trenches is located in the said drift layer side rather than the boundary of the said base layer and the said drift layer, The Claim 1 characterized by the above-mentioned. The semiconductor device described.   The remaining part of each of the isolation insulating films arranged in the plurality of trenches is on the base layer side with respect to the boundary between the base layer and the drift layer, and the impurity concentration of the base layer is maximized The semiconductor device according to claim 2, wherein the semiconductor device is located closer to the drift layer.   At least a part of each of the isolation insulating films disposed in the plurality of trenches is closer to the base layer than the boundary between the base layer and the drift layer, and the impurity concentration of the base layer is maximum. The semiconductor device according to claim 1, wherein the semiconductor device is located closer to the drift layer than a portion to be formed.   When a voltage at which the storage layer disappears is applied to the second gate electrode, a voltage at which an inversion layer (16) is formed in a portion of the drift layer that is in contact with the gate insulating film below the second gate electrode 5 is applied to the semiconductor device according to claim 1.   6. The semiconductor device according to claim 1, further comprising a first conductive type cathode layer (17) adjacent to the collector layer.

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