JP2019012813A - Insulated gate bipolar transistor - Google Patents

Abstract

To provide an IGBT with low ON voltage and reduced switching loss.SOLUTION: An IGBT according to an embodiment includes a first electrode, a first semiconductor layer of a first conductivity type with a second electrode on the first semiconductor layer, a second semiconductor layer of a second conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type, and a fifth semiconductor layer of the second conductivity type in this order. The third electrode is provided on the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer via a gate insulating film, and is insulated from the first electrode and the second electrode. The fourth electrode is provided between the third electrode and the second semiconductor layer, and is insulated from the third electrode and the second semiconductor layer.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an insulated gate bipolar transistor.

An insulated gate bipolar transistor (hereinafter referred to as IGBT (Insulated Gate Bipolar Transistor)) is generally used as a power semiconductor element having a breakdown voltage of 600 V or higher. Since a power semiconductor device is generally used as a switch, it is desired that the on-resistance is low and the switching speed is high. In order to reduce the on-resistance, a trench gate structure extending from the channel region to the n ⁻ -type base layer is used. By using this structure, carriers are efficiently confined in the n ⁻ -type base layer between adjacent trench gates to cause conductivity modulation, and the on-resistance of the IGBT is reduced. However, because of the trench gate structure deeper than the channel, the delay of carrier accumulation is large when the IGBT is switched from the off state to the on state (turn on), and the carrier is discharged when the switch is from the on state to / off state (turn off). The delay is large. As a result, there is a problem that the switching loss at turn-on and the switching loss at turn-off are large.

Japanese Patent Laid-Open No. 2006-154218 JP 2013-251395 A

  Providing IGBT with low on-voltage and reduced switching loss.

  The insulated gate bipolar transistor of the embodiment includes a first electrode, a second electrode, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, 3 electrodes and a fourth electrode. The first semiconductor layer is provided between the first electrode and the second electrode and has a first conductivity type. The second semiconductor layer is provided between the second electrode and the first semiconductor layer and has a second conductivity type. The third semiconductor layer is provided between the second electrode and the second semiconductor layer, has a second conductivity type, and has an impurity concentration higher than that of the second semiconductor layer. The fourth semiconductor layer is provided between the second electrode and the third semiconductor layer, has a first conductivity type, and is electrically connected to the second electrode. The fifth semiconductor layer is selectively provided between the second electrode and the fourth semiconductor layer, has the second conductivity type, is electrically connected to the second electrode, and has a higher impurity concentration than the second semiconductor layer. . The third electrode is provided on the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer via a gate insulating film, and is insulated from the first electrode and the second electrode. The fourth electrode is provided between the third electrode and the second semiconductor layer, and is insulated from the third electrode and the second semiconductor layer.

1 is a cross-sectional view of an IGBT according to a first embodiment of the present invention. Sectional drawing of IGBT which concerns on a comparative example. The figure which compares the turn-off characteristic of IGBT which concerns on the 1st Embodiment of this invention, and IGBT which concerns on a comparative example. The figure which shows the time transition of the carrier concentration distribution at the time of turn-off in the n < ^- > type base layer of IGBT which concerns on a comparative example. The figure which shows the time transition of the carrier concentration distribution at the time of turn-off in the n < ^- > base layer of IGBT which concerns on the 1st Embodiment of this invention. The figure which compares the turn-on characteristic of IGBT which concerns on the 1st Embodiment of this invention, and IGBT which concerns on a comparative example. The IGBT according to the comparative example n ^- diagram illustrating the evolution in time of the carrier concentration distribution at the time of turn-on in the form the base layer. The figure which shows the time transition of the carrier concentration distribution at the time of turn-on in the n ^{− type} base layer of the IGBT according to the first embodiment of the present invention. Sectional drawing of IGBT which concerns on the modification of the 1st Embodiment of this invention. Sectional drawing of IGBT which concerns on the 2nd Embodiment of this invention. Sectional drawing of IGBT which concerns on the 3rd Embodiment of this invention. Sectional drawing of IGBT which concerns on the 4th Embodiment of this invention. Sectional drawing of IGBT which concerns on the 5th Embodiment of this invention. The perspective sectional view of IGBT which concerns on the 6th Embodiment of this invention. Sectional drawing of IGBT which concerns on the 7th Embodiment of this invention. The timing chart which shows the control method at the time of turn-off of IGBT which concerns on the 7th Embodiment of this invention. The carrier concentration distribution figure of IGBT which concerns on the 7th Embodiment of this invention. The timing chart which shows the control method at the time of turn-on of IGBT which concerns on the 7th Embodiment of this invention. The block diagram which shows the control circuit of IGBT which concerns on the 7th Embodiment of this invention. Sectional drawing of IGBT which concerns on the 8th Embodiment of this invention. Sectional drawing of IGBT which concerns on the 9th Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings used in the description in the embodiments are schematic for ease of description, and the shape, size, magnitude relationship, etc. of each element in the drawings are not necessarily shown in the drawings in actual implementation. The present invention is not limited to the above, and can be appropriately changed within a range in which the effect of the present invention can be obtained. Elements having similar properties, functions, or characteristics are denoted by the same reference numerals or the same reference symbols, and description thereof is omitted.

n ⁺ , n, and n ⁻ indicate an n-type semiconductor, and the n-type impurity concentration is set lower in this order. p ⁺ , p, and p ⁻ indicate a p-type semiconductor, and the p-type impurity concentration is set lower in this order. The n-type impurity concentration and the p-type impurity concentration do not indicate the actual n-type impurity concentration and the actual p-type impurity concentration, but indicate effective impurity concentrations after compensation. For example, when the actual p-type impurity concentration is higher than the actual n-type impurity concentration, the p-type impurity concentration is obtained by subtracting the actual n-type impurity concentration from the actual p-type impurity concentration. . The same applies to the n-type impurity concentration.

(Embodiment 1)
An insulated gate bipolar transistor (hereinafter, IGBT) according to the first embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1, the IGBT 1 according to this embodiment includes a collector electrode 10 (first electrode), an emitter electrode 11 (second electrode), a p ^{+ -type} collector layer 12 (first semiconductor layer), an n ⁻ Type base layer 13 (second semiconductor layer), n type barrier layer 14 (third semiconductor layer), p type base layer 15 (fourth semiconductor layer), and n ^{+ type} emitter layer 16 (fifth semiconductor layer). And a gate electrode 17 (third electrode) and a first field plate electrode 19 (fourth electrode).

The p ^{+ -type} collector layer 12 is a semiconductor layer provided between the emitter electrode 11 and the collector electrode 10 and having the first conductivity type. In this embodiment, the first conductivity type represents the p-type case, and the second conductivity type represents the n-type case. The semiconductor layer is illustrated using silicon (Si) as an example, but is not limited thereto. The p ^{+ -type} collector layer 12 has a p-type impurity total amount of about 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻² and a layer thickness of about 0.1 to 10 μm. The collector electrode 10 and the emitter electrode 11 are, for example, a metal including at least one selected from the group of aluminum (Al), titanium (Ti), nickel (Ni), tungsten (W), gold (Au), polysilicon, and the like. Consists of.

The n ⁻ -type base layer 13 is a semiconductor layer provided between the emitter electrode 11 and the p ^{+ -type} collector layer 12 and having a second conductivity type (hereinafter, n-type). n ^- n-type impurity concentration of -type base layer 13 is, for example, is about ^{1 × 10 12 ~1 × 10 15} (atoms / cm 3), can be set to any of the impurity concentration by the withstand voltage design of the device. The layer thickness is about 1 to 1000 μm, and can be set to an arbitrary thickness depending on the breakdown voltage design of the element.

The n-type barrier layer 14 is an n-type semiconductor layer and has an n-type irregularity concentration higher than the n-type impurity concentration of the n ⁻ -type base layer 13, and the total amount of impurities is 1 × 10 ¹² to 1 × 10 ^14. It is about cm- ² . The layer thickness of the n-type barrier layer 14 is about 0.1 to several μm.

The p-type base layer 15 is a p-type semiconductor layer and is provided between the emitter electrode 11 and the n-type barrier layer 14 and has a p-type impurity concentration generally lower than the p-type impurity concentration of the p ^{+ -type} collector layer 12. Have. The total amount of p-type impurities in the p-type base layer 15 is about 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² , and the layer thickness is about 0.1 to several μm. For this reason, depending on the design, there may be a p-type impurity concentration higher than the p-type impurity concentration of the p ^{+ -type} collector layer 12. The p-type base layer 15 is electrically connected to the emitter electrode 11.

The n ⁺ -type emitter layer 16 is an n-type semiconductor layer, is selectively provided between the emitter electrode 11 and the p-type base layer 15, and is electrically connected to the emitter electrode 11. The n ⁺ -type emitter layer 16 has an n-type impurity concentration higher than the n-type impurity concentration of the n ⁻ -type base layer 13, and the total amount of n-type impurities is about 1 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ^−2. . The layer thickness of the n ⁺ -type emitter layer 16 is about 0.1 to several μm and is smaller than the p-type base layer 15.

A plurality of trenches 21 passing through the n ⁺ -type emitter layer 16, the p-type base layer 15, and the n-type barrier layer 14 from the emitter electrode 11 side and reaching the n ⁻ -type base layer 13 are in the in-plane direction of the p-type base layer 15 ( In the horizontal direction). The depth of the trench 21 is about 1 to 10 μm. The period of adjacent trenches is about 0.1 to several μm. The n ⁺ -type emitter layer 16, the p-type base layer 15, the n-type barrier layer 14, and the n ⁻ -type base layer 13 are exposed on the sidewall of the trench 21. On the sidewall of the trench 21, the gate insulating film 18 covers the n ⁺ -type emitter layer 16, the p-type base layer 15, and the n-type barrier layer 14. A gate electrode 17 is provided on the n ⁺ -type emitter layer 16, the p-type base layer 15, and the n-type barrier layer 14 via the gate insulating film 18. A first interlayer insulating film 23 exists between the gate electrode 17 and the emitter electrode 11, and the first interlayer insulating film 23 insulates the gate electrode 17 from the emitter electrode 11. The gate electrode 17 is electrically connected to the gate pad region in a region not shown. The gate pad region is electrically connected to the gate terminal (not shown).

The first insulating film 22 covers the n-type barrier layer 14 and the n ⁻ -type base layer 13 on the side wall and bottom of the trench 21 and is continuous with the gate insulating film 18. The first field plate electrode 19 is provided between the gate electrode 17 and the n ⁻ -type base layer 13. An interelectrode insulating film 20 exists between the gate electrode 17 and the first field plate electrode 19. A first insulating film 22 exists between the first field plate electrode 19 and the n ⁻ -type base layer 13. The interelectrode insulating film 20 is continuous with the gate insulating film 18 and the first insulating film 22. The first field plate electrode 19 is electrically connected to the emitter electrode in a region not shown, and has the same potential as the emitter electrode.

In other words, on the sidewall of the trench 21, the gate electrode 17 (third electrode) is provided on the n ⁺ -type emitter layer 16, the p-type base layer 15, and the n-type barrier layer 14 via the gate insulating film 18. The gate electrode 17 is insulated from the emitter electrode 11 and the collector electrode 10. Further, the first field plate electrode 19, gate electrode 17 and the n ^- is provided between the -type base layer 13, the gate electrode 17 and the n ^- and -type base layer 13 is insulated, electrically connected to the emitter electrode 11 Is done.

Note that the gate electrode 17 may extend to the n ⁻ -type base layer 13.

The gate insulating film 18, the first interlayer insulating film 23, the first insulating film 22, and the interelectrode insulating film 20 are, for example, silicon oxide (SiO ₂ ), but are not limited thereto. In addition, the respective insulating films may be made of different materials instead of the same material. The gate insulating film 18 is desirably thinner than the first insulating film 22, but is not limited thereto. The gate electrode 17 and the first field plate electrode 19 are made of, for example, polysilicon containing n-type or p-type impurities, but are not limited thereto.

  A first trench gate structure constituted by the gate electrode 17, the gate insulating film 18, the first insulating film 22, the first field plate electrode 19, the interelectrode insulating film 20, and the first interlayer insulating film 23 in the trench 21, A plurality of unit cells are repeatedly provided in at least one direction within the horizontal plane of the p-type base layer 15. For example, the first trench gate structure is repeatedly provided in the p-type base layer 15 with a period of about 0.1 to several μm.

  Before describing the operation of the IGBT 1 according to the present embodiment, the structure of the IGBT 101 of the comparative example will be described. FIG. 2 is a cross-sectional view of the IGBT 101 according to the comparative example. The IGBT 101 according to the comparative example is different from the IGBT 1 according to the present embodiment in the following points.

The IGBT 101 according to the comparative example is similar to the IGBT 1 according to the present embodiment, the emitter electrode 11, the collector electrode 10, the p ^{+ type} collector layer 12, the n ^{− type} base layer 13, the n type barrier layer 14, A p-type base layer 15 and an n ⁺ -type emitter layer 16 are provided, and a trench 21 is provided.

  The IGBT 1 according to this embodiment includes a gate electrode 17, a gate insulating film 18, a first field plate electrode 19, a first insulating film 22, an interelectrode insulating film 20, and a first interlayer insulating film 23 provided in the trench 21. A trench gate structure. On the other hand, the IGBT 101 according to the comparative example has a trench gate structure including a gate electrode 117, a gate insulating film 118, and a first interlayer insulating film 23 provided in the trench 21.

The gate insulating film 118, ^{n +} -type emitter layer 16 exposed on the side wall, p-type base layer 15, n-type barrier layer 14 and n of the trench 21 ^- and -type base layer 13, exposed on the bottom n ^- -type base layer 13 It is provided so as to cover. The gate electrode 117 is provided in the trench 21 through only the gate insulating film 118. The gate electrode 117 is provided on the n ⁺ -type emitter layer 16, the p-type base layer 15, the n-type barrier layer 14, and the n ⁻ -type base layer 13 via the gate insulating film 118 on the sidewall of the trench 21. The gate electrode 117 extends from the n ⁺ -type emitter layer 16 to a part of the n ⁻ -type base layer 13 located at the bottom of the trench 21.

  The IGBT 101 according to the comparative example is different from the IGBT 1 according to the present embodiment in the trench gate structure as described above.

  The switching characteristics of the IGBT 1 according to this embodiment are compared with the switching characteristics of the IGBT 101 according to the comparative example. FIG. 3 shows the simulation result of the time change of the collector-emitter voltage and the collector current at the time of turn-off of the IGBT 1 according to the present embodiment and the IGBT 101 according to the comparative example. When the time is 0 second, the potential of the gate electrode is changed from the driving potential (for example, 15 V) to, for example, 0 V (turn-off start).

  First, the operation of the IGBT 101 according to the comparative example will be described. When a certain period of time elapses after the turn-off starts and the potential of the gate electrode becomes lower than the threshold voltage, the channel layer disappears. The disappearance of the channel layer requires time corresponding to the sum of the gate-emitter capacitance Cge and the gate-collector capacitance Cgc.

Therefore, the supply of electrons to the n ⁻ -type base layer 13 is cut off after a while from the start of turn-off, while the electrons accumulated in the n ⁻ -type base layer 13 are transferred to the collector and the holes are transferred to the emitter. Each begins to be discharged. As a result, after a while from the start of turn-off, the collector current decreases from the current during operation to zero. The time required for the current to decrease from the current value during operation to zero is determined by the time required for discharging electrons and holes in the n ⁻ -type base layer 13.

FIG. 4 shows a simulation result of the temporal change in the carrier concentration of electrons and holes in the n ⁻ -type base layer 13 after the IGBT 101 according to the comparative example is turned off. The carrier concentration of electrons and the carrier concentration of holes are equal (hereinafter simply referred to as carrier concentration refers to the carrier concentration of both electrons and holes). The carrier concentration is a value every 0.4 × 10 ⁻⁶ seconds after the start of turn-off. Note that e in the figure means that the base of the 冪 calculation is 10.

  As can be seen from FIG. 4, in the IGBT 101 according to the comparative example, the carrier concentration hardly changes until 1.2 microseconds, and the carrier concentration starts to decrease from the emitter side from 1.6 microseconds. Correspondingly, the collector current starts to decrease. In 2.8 microseconds, the carrier is depleted and the collector current becomes zero.

Simultaneously with the decrease in the collector current, the depletion layer extends from the interface between the p-type base layer 15 and the n-type barrier layer 14 toward the n ⁻ -type base layer 13, and the collector-emitter voltage increases from 0 V to the power supply voltage. To do. At the time of turn-off, the collector current decreases over a certain amount of time, and the collector-emitter voltage increases over a certain amount of time, so that a switching loss occurs. In the IGBT 101 according to the comparative example, the switching loss at the turn-off time was 21.1 mJ.

On the other hand, in the IGBT 1 according to the present embodiment, as shown in FIG. 3, the time until the start of the collector-emitter voltage increase after the start of turn-off and the time until the collector current starts to decrease are related to the comparative example. It is shortened to about half that of the IGBT 101. FIG. 5 shows a simulation result of the temporal change in the carrier concentration of electrons and holes in the n ⁻ -type base layer 13 after the IGBT 1 according to this embodiment is turned off. The carrier concentration begins to decrease between 0.4 and 0.8 microseconds after the start of turn-off. At 1.6 microseconds, the carrier concentration is almost depleted. As a result, as described above, the time until the collector current starts to decrease is shortened by about half.

The IGBT 101 according to the comparative example has a gate electrode 117 provided in the trench 21 with a gate insulating film 118 interposed therebetween. The gate electrode 117 extends from the n ⁺ -type emitter layer 16 to a part of the n ⁻ -type base layer 13 located at the bottom of the trench 21 on the sidewall of the trench 21. As a result, the gate electrode 117 has a gate-emitter capacitance Cge formed by the p-type base layer 15, the gate insulating film 118, and the gate electrode 117. Further, the gate electrode 117 has a gate-collector capacitance Cgc (feedback capacitance) formed by the n ⁻ -type base layer 13, the gate insulating film 118, and the gate electrode 117. Gate electrode 117 the n ^- by stretching up into -type base layer 13, n ^- to form an n-type accumulation layer is causing conductivity modulation in the form the base layer 13. However, with this structure, the gate-collector capacitance Cgc has a large value.

In contrast, the IGBT 1 according to the present embodiment includes the first field plate electrode 19 provided in the trench 21 via the first insulating film 22, the gate insulating film 18, and the interelectrode insulating film 20. And a gate electrode 17 provided. The first field plate electrode 19 is provided on the n ⁻ -type base layer 13 via the first insulating film 22. The gate electrode 17 is provided on the first field plate electrode 19 via the interelectrode insulating film 20 and on the p-type base layer 15 via the gate insulating film 18. Since the first field plate electrode 19 exists between the gate electrode 17 and the n ⁻ -type base layer 13, the gate electrode 17 is more n ⁻ -type base layer than the gate electrode 117 of the IGBT 101 according to the comparative example. 13 hardly stretches.

  Therefore, the gate-collector capacitance Cgc of the IGBT 1 according to the present embodiment is much smaller than the gate-collector capacitance Cgc of the IGBT 101 according to the comparative example. The disappearance of the channel portion of the IGBT is slower as the sum of the gate-emitter capacitance Cge and the gate-collector capacitance Cgc increases. The gate-collector capacitance Cgc of the IGBT 1 according to this embodiment is negligibly small compared to the gate-collector capacitance Cgc of the IGBT 101 according to the comparative example. Therefore, the channel portion disappears faster in the IGBT 1 according to the present embodiment than in the IGBT 101 according to the comparative example. Thereby, the time until the collector current starts to decrease is shorter in the IGBT 1 according to the present embodiment than in the IGBT 101 according to the comparative example, and the results shown in FIGS. 3 and 5 are obtained.

  Since the collector-emitter voltage starts to rise in conjunction with the start of the decrease in the collector current, the IGBT 1 according to this embodiment also has a longer time than the IGBT 101 according to the comparative example with respect to the time until the collector-emitter voltage starts to rise. Too early.

Furthermore, the collector current decreases over a certain amount of time during turn-off, and the collector-emitter voltage increases over a certain amount of time, resulting in a switching loss. In the IGBT 1 according to the present embodiment, the switching loss at the turn-off time was 18.2 mJ. This value decreased by 13.7% compared to the switching loss at the turn-off time of the IGBT 101 according to the comparative example. The smaller switching loss means that the IGBT 1 according to the present embodiment has a shorter time required for discharging the electrons and holes accumulated in the n ⁻ -type base layer 13 than the IGBT 101 according to the comparative example. It is done.

In the IGBT 101 according to the comparative example, the gate electrode 117 extends into the n ⁻ -type base layer 13. For this reason, the gate-collector capacitance Cgc is large, and at the time of turn-off, the time for discharging the gate-collector capacitance Cgc becomes longer, so that the carrier discharge time becomes longer.

On the other hand, in the IGBT 1 according to this embodiment, the gate electrode 117 according to the comparative example has a two-stage structure of the gate electrode 17 and the first field plate electrode 19, and protrudes into the n ⁻ -type base layer 13. The first field plate electrode 19 is connected to the emitter electrode. For this reason, the gate-collector capacitance Cgc is small, and the time for discharging the gate-collector capacitance Cgc at the time of turn-off is shortened, so that the carrier discharge time is shortened.

  As described above, it is considered that the switching loss at the turn-off of the IGBT 1 according to the present embodiment is reduced as compared with the IGBT 101 according to the comparative example.

Next, the characteristics at the time of turn-on of the IGBT 1 according to the present embodiment and the characteristics at the time of turn-on of the IGBT 101 according to the comparative example are compared. FIG. 6 shows temporal changes at the time of turn-on of the respective collector currents and collector-emitter voltages of the IGBT 1 according to this embodiment and the IGBT 101 according to the comparative example. FIG. 7 shows the change over time of the carrier concentration in the n ⁻ -type base layer 13 when the IGBT 101 according to the comparative example is turned on. FIG. 8 shows the change over time of the carrier concentration in the n ⁻ -type base layer 13 when the IGBT 1 according to this embodiment is turned on. In both figures, the time when the potential of the gate electrode is switched from 0 V to the driving potential during operation is set to 0 second (turn-on start). 7 and 8 show carrier concentration profiles when the time is switched in units of 0.1 microseconds. The horizontal axis indicates the depth in the n ⁻ -type base layer 13, the left side is the emitter side, and the right side is the collector side.

  First, the operation of the IGBT 101 according to the comparative example will be described. When the potential of the gate electrode becomes equal to or higher than the threshold voltage after the turn-on starts, a channel layer is formed. The formation of this channel layer requires time corresponding to the sum of the gate-emitter capacitance Cge and the gate-collector capacitance Cgc.

Therefore, electrons are supplied from the emitter to the n ⁻ -type base layer 13 via the channel layer after a while from the turn-on, so that holes are supplied from the p-type collector layer 12 into the n ⁻ -type base layer 13. start. As a result, after a while from the turn-on, the collector current rises from 0 A and becomes an operating current (in this case, 200 A). The time required to reach the current value during operation from 0 of the collector current is determined by the time required for accumulation of electrons and holes in the n ⁻ -type base layer 13. FIG. 7 shows the simulation result of the time change of the electron and hole carrier concentrations in the n ⁻ -type base layer 13 after the IGBT 101 according to the comparative example is turned on. The electron carrier concentration is the same as the hole carrier concentration. The carrier concentration is a value every 0.1 × 10 ⁻⁶ seconds (0.1 microseconds) after turn-on.

  As can be seen from FIG. 7, in the IGBT 101 according to the comparative example, the carrier concentration hardly changes until 0.4 microsecond, and the carrier concentration starts to increase from the collector side from 0.5 microsecond. Correspondingly, the collector current starts to increase. The collector current almost reaches the operating current in about 0.55 microseconds.

Simultaneously with the increase of the collector current, the depletion layer extending from the interface between the p-type base layer 15 and the n-type barrier layer 14 toward the n ⁻ -type base layer 13 is reduced, and the collector-emitter voltage becomes the power supply voltage (600 V). ) To 0V. At the time of turn-on, the collector current increases over time and the collector-emitter voltage decreases over time, resulting in switching loss. In the IGBT 101 according to the comparative example, the switching loss at the turn-on was 10.0 mJ.

On the other hand, in the IGBT 1 according to the present embodiment, as shown in FIG. 6, the time until the start of the decrease in the collector-emitter voltage after the turn-on and the time until the start of the increase in the collector current are related to the IGBT 101 according to the comparative example. It is shortened compared to that. FIG. 8 shows the simulation result of the time change of the carrier concentration of electrons and holes in the n ⁻ -type base layer 13 after the IGBT 1 according to the present embodiment is turned on. The carrier concentration begins to increase within 0.4 microseconds after turn-on. In 0.6 microseconds, the carrier concentration is almost saturated. As a result, as described above, in the IGBT 1 according to the present embodiment, the time until the collector current starts to increase is shortened.

  As described above, the gate-collector capacitance Cgc of the IGBT 1 according to the present embodiment is much smaller than the gate-collector capacitance Cgc of the IGBT 101 according to the comparative example. The formation of the IGBT channel portion is slower as the sum of the gate-emitter capacitance Cge and the gate-collector capacitance Cgc increases. The gate-collector capacitance Cgc of the IGBT 1 according to this embodiment is negligibly small compared to the gate-collector capacitance Cgc of the IGBT 101 according to the comparative example. Therefore, the channel portion of the IGBT 1 according to this embodiment is formed faster than the IGBT 101 according to the comparative example. Thereby, the time until the collector current starts increasing is shorter in the IGBT 1 according to the present embodiment than in the IGBT 101 according to the comparative example, and the results shown in FIGS. 6 and 8 are obtained.

  Since the collector-emitter voltage starts to decrease in conjunction with the start of the increase in the collector current, the IGBT 1 according to the present embodiment is also the IGBT 101 according to the comparative example with respect to the time until the collector-emitter voltage starts to decrease. Shorter than.

Furthermore, when the turn-on is performed, the collector current increases over time and the collector-emitter voltage decreases over time, so that a switching loss occurs. In the IGBT 1 according to the present embodiment, the switching loss at the time of turn-on was 3.2 mJ. This value was reduced by 68% compared to the switching loss at the turn-on time of the IGBT 101 according to the comparative example. The fact that the switching loss is smaller is considered that the IGBT 1 according to the present embodiment is faster in the rate at which electrons and holes are accumulated in the n ⁻ -type base layer 13 than the IGBT 101 according to the comparative example.

In the IGBT 101 according to the comparative example, the gate electrode 117 extends into the n ⁻ -type base layer 13. For this reason, the gate-collector capacitance Cgc is large, and the voltage drop time at turn-on becomes long.

In contrast, in IGBT1 according to the present embodiment has a two-stage structure of the gate electrode 17 and the first field plate electrode 19 instead of the gate electrode 117 according to the comparative example, n ^- -type base layer 13 in The first field plate electrode 19 protruding in the direction is connected to the emitter electrode. Therefore, the gate-collector capacitance Cgc is small, and the voltage drop time at turn-on is shortened.

  As a result, both the time until the collector current starts to increase and the voltage fall time, the IGBT 1 according to the present embodiment is speeded up, and the switching loss at turn-on is higher than that at the turn-off compared to the IGBT 101 according to the comparative example. It is thought that it decreased significantly.

(Modification of Embodiment 1)
An IGBT 1a according to a modification of the first embodiment of the present invention will be described with reference to FIG. In the IGBT 1 according to the first embodiment, the gate electrode 17 and the first field plate electrode 19 are stacked in the trench 21 from the emitter electrode 11 toward the collector electrode 10. In this modification, when the length of the gate electrode 17 in the collector electrode 10 direction is tg1, and the length of the first field plate electrode 19 in the collector electrode 10 direction is tg2, tg1> tg2. In this way, the gate electrode 17 the n ^- extends to during -type base layer 13, n ^- so to form a shape-based layer n-type accumulation layer in 13 cause conductivity modulation, to reduce the on-voltage be able to. On the other hand, when tg1 is shortened, the ON voltage increases. On the other hand, even if the length tg2 of the first field plate electrode 19 is short, the effect of reducing the gate-collector capacitance Cgc is sufficient, and the switching loss can be effectively reduced. From the above, tg1> tg2 is a better structure.

(Embodiment 2)
The IGBT 2 according to the second embodiment of the present invention will be described with reference to FIG. The IGBT 2 according to this embodiment is opposed to the gate electrode 17 and the first field plate electrode 19 on the n ⁻ -type base layer 13, the n-type barrier layer 14, and the p-type base layer 15 through the second insulating film 25. And the second field plate electrode 26 (fifth electrode) electrically connected to the emitter electrode 11 is different from the IGBT 1 according to the first embodiment. That is, the second field plate electrode 26 is buried through the second insulating film 25 in the trench 24 extending from the surface of the p-type base layer 15 through the n-type barrier layer 14 and into the n ⁻ -type base layer 13. It is.

  The depth of the trench 24 is substantially the same as the depth of the trench 21. Similar to the first field plate electrode 19, the second feel plate electrode is made of polysilicon. The distance between the one end of the first field plate electrode 19 on the collector electrode 10 side and the emitter electrode 11 is substantially the same as the distance between the one end of the second field plate electrode on the collector electrode 10 side and the emitter electrode 11. . Similar to the first insulating film 22, the second insulating film 25 is made of, for example, silicon oxide. The thickness of the second insulating film 25 is substantially the same as the thickness of the first insulating film 22.

In the IGBT 1 according to the first embodiment, the first trench gate structure including the gate electrode 17 and the first field plate electrode 19 provided in the trench 21 has at least one direction in the plane of the p-type base layer 15. A plurality of repetitions are provided. On the other hand, in the IGBT 2 according to the present embodiment, in the IGBT 1 according to the first embodiment, one of the adjacent first trench gate structures is embedded in the trench 24 via the second insulating film 25. It is replaced with a second trench gate structure composed of the field plate electrode 26, and this is repeatedly provided as a unit. Further, the n ⁺ -type emitter layer 16 is not adjacent to the second field plate electrode 26 via the second insulating film 25.

  The IGBT 2 according to the present embodiment has a structure in which the first trench gate structure is periodically replaced with the second trench gate structure as described above. For this reason, the IGBT 2 according to the present embodiment has a smaller gate-emitter capacitance than the IGBT 1 according to the first embodiment. As a result, the IGBT 2 according to the present embodiment has a shorter time until the collector current starts to decrease after turn-off and the time when the collector current starts to increase after the turn-on than the IGBT 1 according to the first embodiment. Therefore, the IGBT 2 according to the present embodiment has better switching characteristics than the IGBT 1 according to the first embodiment.

(Embodiment 3)
An IGBT 3 according to a third embodiment of the present invention will be described with reference to FIG. A description will be given centering on differences from the second embodiment. FIG. 11 is a cross-sectional view of the IGBT 3 according to the present embodiment. The IGBT 3 according to the present embodiment is different from the IGBT 2 according to the second embodiment in that the n-type barrier layer 14 does not exist in the IGBT 2 according to the second embodiment.

  The IGBT 3 according to the present embodiment has a slight disadvantage with respect to conductivity modulation because the n-type barrier layer 14 is not present. However, since the time required for discharging carriers at the time of turn-off is shortened, the second implementation is performed in the switching characteristics. It is superior to IGBT2 which concerns on a form.

(Embodiment 4)
The IGBT 4 according to the fourth embodiment of the present invention will be described with reference to FIG. A description will be given centering on differences from the second embodiment. FIG. 12 is a cross-sectional view of the IGBT 4 according to the present embodiment. In the IGBT 4 according to the present embodiment, the first trench gate structure is further replaced with the second trench gate structure in the IGBT 2 according to the second embodiment. It differs from IGBT2 which concerns on 2nd Embodiment by the structure which consists of two trench gate structures as a unit, and having this unit repeated several times periodically.

In other words, the IGBT 4 according to this embodiment includes the third field plate electrode 28 between the gate electrode 17 and the second field plate electrode 26. The third field plate electrode 28 is embedded through the third insulating film 29 in the trench 27 extending from the surface of the p-type base layer 15 through the n-type barrier layer 14 and into the n ⁻ -type base layer 13. Yes.

Similar to the second field plate electrode 26, the third field plate electrode 28 is made of polysilicon. The length of the third field plate electrode 28 extending from the p-type base layer 15 to the n ⁻ -type base layer 13 is the same as the length of the second field plate electrode 26. The third insulating film 29 is made of silicon oxide like the second insulating film 25.

  The IGBT 4 according to the present embodiment also has good switching characteristics as with the IGBT 2 according to the second embodiment.

  As an extension of the present embodiment, it is obvious that the same effect can be obtained even if a structure including an arbitrary number of second trench gate structures instead of three after one first trench gate structure is used as a unit. .

(Embodiment 5)
An IGBT 5 according to a fifth embodiment of the present invention will be described with reference to FIG. A description will be given centering on differences from the IGBT 4 according to the fourth embodiment. FIG. 13 is a cross-sectional view of the IGBT 5 according to the present embodiment. The IGBT 5 according to the present embodiment is different from the IGBT 5 according to the fourth embodiment in that the second interlayer insulating film 30 covering the p-type base layer 15 is provided between the adjacent second trench gate structure. 4 is different from the IGBT 4 according to the fourth embodiment.

  That is, the second interlayer insulating film 30 is provided between the emitter electrode 11 and the p-type base layer 15 and covers the p-type base layer 15. The second interlayer insulating film 30 is continuous with the second insulating film 25 and the third insulating film 29 and straddles the p-type base layer 15. The second interlayer insulating film 30 is made of, for example, silicon oxide.

In the IGBT 5 according to this embodiment, the second interlayer insulating film 30 suppresses the holes in the n ⁻ -type base layer 13 from escaping to the emitter electrode 11, so that the holes in the n ⁻ -type base layer 13 and The electron carrier concentration increases and conductivity modulation is promoted. The IGBT 5 according to the present embodiment is excellent in switching responsiveness, has a small switching loss, and has a low on-resistance like the IGBTs according to other embodiments.

(Embodiment 6)
The IGBT 6 according to the sixth embodiment of the present invention will be described with reference to FIG. A description will be given centering on differences from the IGBT 2 according to the second embodiment. FIG. 14 is a perspective sectional view of the IGBT 6 according to the present embodiment. The IGBT 6 according to the present embodiment is similar to the IGBT 2 according to the second embodiment in that the n ⁺ -type emitter layer 16 has a direction in which the gate electrodes 17 and the second field plate electrodes 26 are alternately arranged and the p-type base layer 15. A plurality of them are periodically spaced apart along a vertical direction. Each of the plurality of n ⁺ -type emitter layers 16 is connected to the gate electrode 17 via the gate insulating film 18 and is connected to the second field plate electrode 26 via the second insulating film 25. In the above points, the IGBT 6 according to the present embodiment is different from the IGBT 2 according to the second embodiment.

The IGBT 6 according to the present embodiment is excellent in switching responsiveness like the IGBT 2 according to the second embodiment, has low switching loss, and low on-resistance. Further, in the IGBT 6 according to the present embodiment, when the miniaturization is advanced and the distance between the gate electrode 17 and the second field plate electrode 26 is reduced, the n ⁺ -type emitter layer 16 and the p-type base layer 15 and the emitter electrode 11 are reduced. And have good contact with.

(Embodiment 7)
An IGBT according to Embodiment 7 of the present invention will be described with reference to FIGS. FIG. 15 is a cross-sectional view showing the IGBT according to the present embodiment. The description of the same parts as those of the first embodiment is omitted, and different points will be described. This embodiment is different from the first embodiment in that the potential of the fourth electrode can be changed similarly to the gate electrode. Others are the same as those in the first embodiment.

  That is, as shown in FIG. 15, in the IGBT 50 of this embodiment, each of the gate electrodes 17 (hereinafter referred to as the first gate electrode 17) is drawn on the p-type base layer 15 in a region not shown, It is electrically connected to the first gate pad 52 through one gate wiring. Similarly, the fourth electrode 19 (hereinafter referred to as the second gate electrode 19 for the sake of convenience. However, it is used herein to mean an electrode to which a voltage is applied as described above, and does not necessarily have a gate function. Each of them is drawn on the p-type base layer 15 in a region not shown, and is electrically connected to the second gate pad 53 via a second gate wiring not shown. The first gate electrode 17 and the second gate electrode 19 are electrically separated from each other and are configured to be independently supplied with a control voltage.

FIG. 16 is a timing chart showing a control method when the IGBT 50 of the present embodiment is turned off. In FIG. 16, the horizontal axis represents time, the vertical axis represents the first gate voltage Vg1 applied to the first gate electrode 17, the second gate voltage Vg2 applied to the second gate electrode 19, the collector-emitter voltage Vce, and the collector current. Ic is schematically shown.
Between time t0 and time t1, the IGBT 50 is in an on state (steady state), and between time t1 and time t2, the IGBT 50 is in an on state, but it is a period for adjusting the carrier concentration of the n ⁻ base layer 13. Show. Between the time t2 and the time t3 is a turn-off period in which the IGBT 50 is switched from the on state to the off state, and after the time t3, the IGBT 50 is in the off state.

  As shown in FIG. 16, in the ON state, a positive voltage (High) is applied to both the first gate electrode 17 and the second gate electrode 19. The first gate voltage Vg1 is a voltage equal to or higher than the threshold value Vth. The second gate voltage Vg2 is not particularly limited as long as it is a positive voltage, but may be the same voltage as the first gate voltage Vg1.

When the first gate voltage Vg1 is applied to the first gate electrode 17, an n-type channel layer (inversion layer) is formed in the p-type base layer 15 near the gate insulating film 18 provided on the side wall of the first gate electrode 17. The When the second gate voltage Vg <b> 2 is applied to the second gate electrode 19, an n-type storage layer is formed in the n ⁻ base layer 13 near the first insulating film 22 provided on the side wall of the second gate electrode 19.

As a result, electrons flow from the n ⁺ -type emitter layer 16 to the n ⁻ -type base layer 13 via the n-type channel layer, the n-type barrier layer 14, and the n-type storage layer, and holes from the p ^{+ -type} collector layer 12. The n ^{− type} base layer 13 flows into the n ^{− type} base layer 13, and the resistance value of the n ^{− type} base layer 13 decreases due to the conductivity modulation, and the on state (conductive state) is set.

At this time, the formation of the n-type accumulation layer promotes the accumulation of carriers (electrons) on the emitter side, and the accumulation of holes in the n ⁻ -type base layer 13 is promoted to reduce the on-resistance. The accumulation of holes in the n ⁻ -type base layer 13 is promoted because holes flowing into the n ⁻ -type base layer 13 pass through the region between the adjacent trenches 21 and escape to the p-type base layer 15. This is because the path through which holes pass through the p-type base layer 15 is narrowed by being sandwiched between adjacent n-type accumulation layers. Since the n-type storage layer can be controlled according to the second gate voltage Vg2 applied to the second gate electrode 19, a lower on-resistance can be obtained.

In addition, since the n-type barrier layer 14 has a high carrier concentration on the emitter side, holes are more difficult to escape from the n ⁻ -type base layer 13 to the p-type base layer 15. Accumulation of holes in the n ⁻ -type base layer 13 is promoted, and a further lower on-resistance can be obtained.

  The effect of the n-type barrier layer 14 will be specifically described. FIG. 17 is a diagram schematically illustrating the distribution of the carrier concentration of the IGBT 50 in the depth direction. 17A and 17B, the horizontal axis indicates the distance in the depth direction from the emitter electrode 11 side to the collector electrode 10 side, and the vertical axis indicates the carrier concentration. In FIG. 17A, a solid line A is a normal IGBT carrier concentration without an n-type barrier layer and an n-type accumulation layer, a broken line B is an IGBT carrier concentration with an n-type barrier layer, and a broken line C is an n-type barrier layer. And shows the carrier concentration of an IGBT having an n-type accumulation layer. In FIG. 17B, the alternate long and short dash line D indicates the carrier concentration of the IGBT having only the n-type accumulation layer.

  As shown in FIG. 17A, the carrier concentration B on the emitter side when the n-type barrier layer 14 is provided is higher than the carrier concentration A when the n-type barrier layer 14 is not provided. By adding the effect of the n-type accumulation layer generated by applying the second gate voltage Vg2 to the second gate electrode 19, the carrier concentration C of the IGBT having the n-type barrier layer and the n-type accumulation layer has the n-type barrier layer. It rises from the carrier concentration B of IGBT.

  On the other hand, as shown in FIG. 17B, the carrier concentration D of the IGBT having only the n-type accumulation layer is due to the effect of the n-type accumulation layer caused by applying the second gate voltage Vg2 to the second gate electrode 19. Although it is higher than the carrier concentration A of normal IGBT, the effect of the n-type barrier layer 14 cannot be obtained.

That is, the IGBT 50 of this embodiment has the effect of increasing the emitter-side carrier concentration by the n-type barrier layer 14 and the emitter-side carrier by the n-type accumulation layer generated by applying the second gate voltage Vg2 to the second gate electrode 19. Since the effect of increasing the concentration is added, the accumulation of electrons and holes in the n ⁻ -type base layer 13 is promoted and the on-resistance is remarkably reduced.

At the time of turn-off, at time t1, the second gate voltage Vg2 is set to Low before the first gate voltage Vg1. The second gate voltage Vg2 may be 0V or a negative voltage. By setting the second gate voltage Vg2 to Low first, the n-type accumulation layer formed in the n ⁻ -type base layer 13 disappears.

Thereby, the amount of accumulated carriers on the emitter side is reduced. Furthermore, since the hole flow path in the n ⁻ -type base layer 13 is widened and holes are likely to escape to the p-type base layer 15, the amount of accumulated holes in the n ⁻ -type base layer 13 is reduced. Between the time t1 and the time t2, it is a period during which the carrier concentration of the n ⁻ -type base layer 13 is reduced due to holes being lost to the p-type base layer 15. During this period, since the on-resistance increases slightly, the collector-emitter voltage Vce also increases slightly to allow the same collector current Ic to flow.

When the first gate voltage Vg1 is changed to Low after a predetermined time (t2-t1) has elapsed, the n-type channel layer disappears and the injection of electrons from the n ⁺ -type emitter layer 16 stops, so that the IGBT 50 is turned off. At this time, the second gate voltage Vg2 is set to Low first to reduce the carrier accumulation amount on the emitter side, so that the turn-off becomes faster and the turn-off loss is reduced.
When the second gate voltage Vg2 is a negative voltage, the p-type inversion layer is formed after the n-type accumulation layer formed in the n ⁻ -type base layer 13 under the second gate electrode 19 disappears. This makes it easier for holes to escape to the p-type base layer 15, which helps improve the switching speed at turn-off.

  The reduction amount of the turn-off loss is much larger than the increase amount of the steady loss due to the increase of the collector-emitter voltage Vce in order to cause the same collector current Ic to flow after the second gate voltage Vg2 is set to Low. Therefore, it is possible to significantly reduce the element loss in the entire switching operation.

  So far, the control method at the time of turn-off has been described. Next, a control method at turn-on will be described.

FIG. 18 is a timing chart showing a control method when the IGBT 50 of the present embodiment is turned on. In FIG. 18, the horizontal axis represents time, and the vertical axis represents the first gate voltage Vg1 applied to the first gate electrode 17, the second gate voltage Vg2 applied to the second gate electrode 19, the collector-emitter voltage Vce, and the collector current. Ic is schematically shown.
The IGBT 50 is in the OFF state between the time t0 and the time t1, and the IGBT 50 is in the turn-on period from the OFF state to the ON state between the time t1 and the time t2. Between time t2 and time t3, it indicates that the IGBT 50 is in an on state, and between time t3 and time t4, the IGBT 50 is in an on state, but it is a period for adjusting the carrier concentration of the n ⁻ base layer 13. Show.

As shown in FIG. 18, in the off state, a negative voltage or a zero potential is applied to both the first gate electrode 17 and the second gate electrode 19 (Low). At the time of turn-on, the first gate voltage Vg1 is set to a voltage (High) equal to or higher than the threshold value Vth at time t1. The second gate voltage Vg2 remains low.
When the first gate voltage Vg <b> 1 is applied to the first gate electrode 17, an n-type channel layer (inversion layer) is formed on the p-type base layer 15 in the vicinity of the gate insulating film 18 provided on the side wall of the trench 21 below the first gate electrode 17. ) Is formed. As a result, electrons flow from the n ⁺ -type emitter layer 16 to the n ⁻ -type base layer 13 through the n-type channel layer and the n-type barrier layer 14, and holes from the p ^{+ -type} collector layer 12 become the n ⁻ -type base layer. 13, and the resistance value of the n ⁻ -type base layer 13 decreases due to conductivity modulation, and is turned on (conductive state).

After a predetermined time (t3-t1) has elapsed, the second gate voltage Vg2 is set to High. The second gate voltage Vg2 is not particularly limited as long as it is a positive voltage, but may be the same voltage as the first gate voltage Vg1. When the second gate voltage Vg <b> 2 is applied to the second gate electrode 19, an n-type accumulation layer is formed in the n ⁻ base layer 13 near the first insulating film 22 provided on the side wall of the trench 21 below the second gate electrode 19. Is done.

By forming the n-type accumulation layer, the accumulation of carriers (electrons) on the emitter side is promoted, and the accumulation of holes in the n ⁻ -type base layer 13 is promoted, so that the on-resistance can be further reduced. Between the time t3 and the time t4 is a period in which the carrier concentration of the n ⁻ -type base layer 13 increases. During this time, the collector current Ic is constant, but it can be seen that the collector-emitter voltage Vce has decreased and the on-resistance has been reduced. Since the n-type storage layer can be controlled according to the second gate voltage Vg2 applied to the second gate electrode 19, a lower on-resistance can be obtained.

At the time of turn-on, first, the IGBT 50 is turned on only by the first gate electrode 17, so that the number of carriers that accumulate on the emitter side may be small and the turn-on can be performed at high speed. After the turn-on, the second gate voltage Vg 2 is applied to the second gate electrode 19, thereby forming an n-type accumulation layer on the n ⁻ base layer 13 in the vicinity of the first insulating film 22 provided on the sidewall of the trench 21. It is possible to form and cause further carrier accumulation on the emitter side to obtain even lower on-resistance.

  FIG. 19 is a block diagram showing a gate control circuit for the first gate electrode 17 and the second gate electrode 19. As shown in FIG. 19, the gate control circuit 55 receives the control signal Vs instructing the turn-on and turn-off of the IGBT 50, and receives the first gate voltage Vg1 and the second gate voltage according to the timing charts shown in FIGS. Vg2 is generated.

  For example, the gate control circuit 55 sets the first gate voltage Vg1 to High at the rise of the control signal Vs, and delays the first gate voltage Vg1 by a predetermined time (t2-t1 shown in FIG. 16) at the fall of the control signal Vs. The first gate control circuit to be low, the second gate voltage Vg2 is set high after a predetermined time (t3-t1 shown in FIG. 18) at the rising edge of the control signal Vs, and the second gate is turned on at the falling edge of the control signal Vs. And a second gate control circuit for setting the voltage Vg2 to Low. The first and second gate control circuits can be configured using, for example, a Schmitt trigger, a latch, an inverter, a digital or analog delay circuit, and the like. When the first and second gate voltages Vg1 and Vg2 are equal, the first and second gate control circuits can be shared except for a circuit related to delay.

  A first resistor R 1 is connected between the gate control circuit 55 and the first gate pad 52. The first resistor R1 is inserted to adjust the rising timing of the first gate voltage Vg1. A second resistor R2 is also connected between the gate control circuit 55 and the second gate pad 53. The second resistor R2 is inserted to adjust the rising timing of the second gate voltage Vg2. Note that the gate control circuit 55 can operate without the first and second resistors R1 and R2.

As described above, in the IGBT 50 of this embodiment, the fourth electrode 19 functions as the second gate electrode 19 that can be controlled independently of the first gate electrode 17. In accordance with the second gate voltage Vg 2 applied to the second gate electrode 19, an n-type accumulation layer is formed in the n ⁻ base layer 13 in the vicinity of the first insulating film 22 provided on the side wall of the second gate electrode 19. With the n-type accumulation layer, the amount of accumulated carriers on the emitter side and the amount of accumulated holes in the n ⁻ base layer 13 can be controlled. The n-type barrier layer 14 can promote the accumulation of carriers on the emitter side and the accumulation of holes in the n ⁻ -type base layer 13.
As a result, the effect of the n-type accumulation layer and the effect of the n-type barrier layer 14 are combined, so that a lower on-resistance can be obtained in the on state, and the turn-off loss can be further reduced when turned off. Therefore, an IGBT with a low on-voltage and reduced switching loss can be obtained.

In the IGBT 50, the length tg1 of the first gate electrode 17 is made longer than the length tg2 of the second gate electrode 19 in the direction from the collector electrode 10 to the emitter electrode 11, as in the IGBT 1a shown in FIG. You can also.
Furthermore, although the case where the second gate electrode 19 is set to Low before the first gate electrode 17 is described here, the order may be reversed. By setting the second gate electrode 19 to Low later, an effect of suppressing an abrupt voltage and current during a turn-off operation and suppressing an overshoot voltage can be obtained.
That is, the timing at which the first gate voltage Vg1 and the second gate voltage Vg2 are applied is not necessarily limited to the timing shown in FIGS. 16 and 18, and can be set as appropriate according to the purpose.

(Embodiment 8)
An IGBT according to Embodiment 8 of the present invention will be described with reference to FIG. FIG. 20 is a cross-sectional view showing the IGBT according to this embodiment. The description of the same parts as those of the seventh embodiment is omitted, and different points will be described. The present embodiment is different from the seventh embodiment in that a part of the plurality of fourth electrodes functions as a gate electrode while the other part functions as a field plate electrode. Others are the same as those in the first embodiment.
In other words, the IGBT according to the present embodiment is an IGBT in which the IGBT 1 shown in FIG. 1 and the IGBT 50 shown in FIG. 15 are mixedly mounted.

  As shown in FIG. 20, in the IGBT 60 of this embodiment, one of the adjacent fourth electrodes 19 functions as the second gate electrode, and the other fourth electrode 19 serves as the first field plate electrode. It is functioning as. That is, in the cross-sectional view of FIG. 20, the three fourth electrodes 19 located at both ends and the center function as the second gate electrode 19, and the remaining fourth electrode 19 functions as the first field plate electrode. As described above, in the present embodiment, the second gate electrodes and the first field plates are alternately provided adjacent to each other. Here, the second gate electrode 19 is connected to the second gate pad 53 and supplied with the second gate voltage Vg2. The first field plate electrode 19 is connected to the emitter electrode 11 and is given a fixed emitter potential.

  The second gate electrode 19 provides a lower on-resistance when turned on, and the turn-off loss is further reduced when turned off. Furthermore, the first field plate electrode 19 reduces the gate-collector capacitance Cgc, further reducing the turn-off loss during turn-off.

As described above, in the IGBT 60 of the present embodiment, the plurality of arranged fourth electrodes 19 function as the second gate electrode 19 and the first field plate electrode 19 and are provided adjacent to each other alternately. As a result, the effect of the second gate electrode 19 and the effect of the first field plate electrode 19 can be obtained together. Therefore, an IGBT with a low on-voltage and reduced switching loss can be obtained.
The second gate electrode 19 and the first field plate electrode 19 do not need to be arranged 1: 1. The ratio of arrangement can be freely set according to desired characteristics. That is, it can arrange | position to n: m (n and m are positive integers).

(Embodiment 9)
An IGBT according to Embodiment 9 of the present invention will be described with reference to FIG. FIG. 21 is a cross-sectional view showing the IGBT according to the present embodiment. The description of the same parts as those of the seventh embodiment is omitted, and different points will be described. The present embodiment is different from the seventh embodiment in that a second field plate electrode is provided so as to face the first and second gate electrodes. Others are the same as in the seventh embodiment.

That is, as shown in FIG. 21, the IGBT 70 of this embodiment includes the first gate electrode 17 on the n ⁻ -type base layer 13, the n-type barrier layer 14, and the p-type base layer 15 via the second insulating film 25. And a second field plate electrode 26 (fifth electrode) provided opposite to the second gate electrode 19 and electrically connected to the emitter electrode 11.
The second field plate electrode 26 passes through the p-type base layer 15 and the n-type barrier layer 14 from the emitter electrode 11 side, and extends into the n ⁻ -type base layer 13 via the second insulating film 25. Embedded.

  Since the second field plate electrode 26 has a larger area than the first field plate electrode 19, the field plate electrode is equivalently increased. The second field plate electrode 26 has a higher shielding effect than the first field plate electrode 19. Since the gate-collector capacitance Cgc is further reduced by the second field plate electrode 26, it is possible to further reduce the turn-off loss at the time of turn-off.

  As described above, the IGBT 70 of the present embodiment has the second field plate electrode 26 having a higher shielding effect than the first field plate electrode 19. As a result, the gate-collector capacitance Cgc is reduced, and turn-off loss at turn-off can be reduced. Therefore, an IGBT with a low on-voltage and reduced switching loss can be obtained.

In the IGBT 70, as in the IGBT 2 shown in FIG. 10, the distance between the one end of the second gate electrode 19 on the collector electrode 10 side and the emitter electrode 11 is the same as that of the second field plate electrode 26 on the collector electrode 10 side. And the distance between the emitter electrode 11 and the emitter electrode 11.
The first and second gate electrodes 17 and 19 and the second field plate electrode 26 need not be arranged 1: 1. The ratio of arrangement can be freely set according to desired characteristics. That is, it can arrange | position to n: m (n and m are positive integers).

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1 to 6, 50, 60, 70, 101 Insulated gate bipolar transistor 10 Collector electrode (second electrode)
11 Emitter electrode (first electrode)
12 p-type collector layer 13 n-type base layer 14 n-type barrier layer 15 p-type base layer 16 emitter layers 17 and 117 gate electrode (third electrode)
18, 118 Gate insulating film 19 First field plate electrode (second gate electrode, fourth electrode)
20 Interelectrode insulating films 21, 24, 27 Trench 22 First insulating films 23, 123 First interlayer insulating film 25 Second insulating film 26 Second field plate electrode 28 Third field plate electrode 29 Third insulating film 30 Second interlayer Insulation film

Claims (17)

A first electrode;
A second electrode;
A first semiconductor layer of a first conductivity type provided between the first electrode and the second electrode;
A second semiconductor layer of a second conductivity type provided between the second electrode and the first semiconductor layer;
A third semiconductor layer of the second conductivity type provided between the second electrode and the second semiconductor layer and having an impurity concentration higher than that of the second semiconductor layer;
A fourth semiconductor layer of the first conductivity type provided between the second electrode and the third semiconductor layer and electrically connected to the second electrode;
A fifth of the second conductivity type, which is selectively provided between the second electrode and the fourth semiconductor layer, is electrically connected to the second electrode, and has a higher impurity concentration than the second semiconductor layer. A semiconductor layer;
A third electrode provided on the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer via a gate insulating film, and insulated from the first electrode and the second electrode;
A fourth electrode provided between the third electrode and the second semiconductor layer and insulated from the third electrode and the second semiconductor layer;
Insulated gate bipolar transistor.   The insulated gate bipolar transistor according to claim 1, wherein the fourth electrode is electrically connected to the second electrode.   2. The insulated gate bipolar transistor according to claim 1, wherein the fourth electrode is supplied with a voltage for controlling a carrier concentration of the second semiconductor layer on the second electrode side. A first electrode;
A second electrode;
A first semiconductor layer of a first conductivity type provided between the first electrode and the second electrode;
A second semiconductor layer of a second conductivity type provided between the second electrode and the first semiconductor layer;
A third semiconductor layer of the second conductivity type provided between the second electrode and the second semiconductor layer and having an impurity concentration higher than that of the second semiconductor layer;
A fourth semiconductor layer of the first conductivity type provided between the second electrode and the third semiconductor layer and electrically connected to the second electrode;
A fifth of the second conductivity type, which is selectively provided between the second electrode and the fourth semiconductor layer, is electrically connected to the second electrode, and has a higher impurity concentration than the second semiconductor layer. A semiconductor layer;
A third electrode provided on the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer via a gate insulating film, and insulated from the first electrode and the second electrode;
A fourth electrode provided between the third electrode and the second semiconductor layer, insulated from the third electrode and the second semiconductor layer, and electrically connected to the second electrode. Insulated gate bipolar transistor.   5. The insulated gate bipolar transistor according to claim 4, wherein the length of the third electrode is longer than the length of the fourth electrode in the direction from the first electrode to the second electrode. 6.   An insulating film is provided on the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer so as to face the third electrode and the fourth electrode, and is electrically connected to the second electrode. The insulated gate bipolar transistor according to claim 4, further comprising a fifth electrode formed.   The distance between the one end of the fourth electrode on the first electrode side and the second electrode is the same as the distance between the one end of the fifth electrode on the first electrode side and the second electrode. The insulated gate bipolar transistor according to claim 6.   A sixth electrode provided on the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer via an insulating film and electrically connected to the second electrode is connected to the third electrode. The insulated gate bipolar transistor according to claim 6, further provided between the fifth electrode and the fifth electrode.   9. The interlayer insulating film according to claim 8, further comprising an interlayer insulating film provided between the second electrode and the fourth semiconductor layer between the fifth electrode and the sixth electrode and covering the fourth semiconductor layer. Insulated gate bipolar transistor.   10. The insulated gate bipolar transistor according to claim 6, wherein the fifth electrode is connected to the fifth semiconductor layer through the insulating film. 11. A first electrode;
A second electrode;
A first semiconductor layer of a first conductivity type provided between the first electrode and the second electrode;
A second semiconductor layer of a second conductivity type provided between the second electrode and the first semiconductor layer;
A third semiconductor layer of the second conductivity type provided between the second electrode and the second semiconductor layer and having an impurity concentration higher than that of the second semiconductor layer;
A fourth semiconductor layer of the first conductivity type provided between the second electrode and the third semiconductor layer and electrically connected to the second electrode;
A fifth of the second conductivity type, which is selectively provided between the second electrode and the fourth semiconductor layer, is electrically connected to the second electrode, and has a higher impurity concentration than the second semiconductor layer. A semiconductor layer;
A third electrode provided on the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer via a gate insulating film, and insulated from the first electrode and the second electrode;
A fourth electrode provided on at least the second semiconductor layer and the third electrode via an insulating film;
With
An insulated gate bipolar transistor in which a voltage is applied to the fourth electrode and the third electrode at a predetermined time interval during turn-on or turn-off operation.   The insulated gate bipolar transistor according to claim 11, wherein the fourth electrode is also provided on the third semiconductor layer via the insulating film.   12. The insulated gate bipolar transistor according to claim 11, wherein the length of the third electrode is longer than the length of the fourth electrode in the direction from the first electrode to the second electrode.   12. The insulated gate bipolar transistor according to claim 11, wherein a plurality of the third electrode and the fourth electrode are provided, and a part of the fourth electrode is electrically connected to the second electrode.   An insulating film is provided on the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer so as to face the third electrode and the fourth electrode, and is electrically connected to the second electrode. The insulated gate bipolar transistor according to claim 11, further comprising a fifth electrode formed.   The distance between the one end of the fourth electrode on the first electrode side and the second electrode is the same as the distance between the one end of the fifth electrode on the first electrode side and the second electrode. The insulated gate bipolar transistor according to claim 15.   The said 5th semiconductor layer is plurality, The said 5th semiconductor layer is any one of Claims 1 thru | or 16 spaced apart along the extending direction of the said 3rd electrode and the said 4th electrode. Insulated gate bipolar transistor.

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