CN105957884A - Split-gate gate trench structure and trench schottky diode and preparation method therefor - Google Patents
Split-gate gate trench structure and trench schottky diode and preparation method therefor Download PDFInfo
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- CN105957884A CN105957884A CN201610470770.1A CN201610470770A CN105957884A CN 105957884 A CN105957884 A CN 105957884A CN 201610470770 A CN201610470770 A CN 201610470770A CN 105957884 A CN105957884 A CN 105957884A
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- 238000002360 preparation method Methods 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 67
- 229920005591 polysilicon Polymers 0.000 claims abstract description 67
- 239000013049 sediment Substances 0.000 claims description 33
- 238000005530 etching Methods 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 230000000873 masking effect Effects 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000000605 extraction Methods 0.000 claims description 2
- 238000000407 epitaxy Methods 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 description 15
- 230000000694 effects Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
Abstract
The invention discloses a split-gate gate trench structure. The split-gate gate trench structure comprises a first gate oxide layer which is deposited at the bottom and on the side wall of the split-gate gate trench, wherein a polysilicon gate is deposited in the first gate oxide layer; the top part of the polysilicon gate protrudes out of the first gate oxide layer; the split-gate gate trench structure also comprises a second gate oxide layer; the second gate oxide layer is deposited on the upward side wall of the gate trench; the second gate oxide layer is positioned on the first gate oxide layer and the first polysilicon gate; and a second polysilicon gate is deposited in the interior of the second gate oxide layer. According to the split-gate gate trench structure and trench schottky diode, the split gate structure is introduced to the conventional trench schottky diode structure to increase reverse withstand voltage; through special terminal design, the withstand voltage of the terminal is ensured; meanwhile, the reverse withstand voltage of the trench schottky diode is effectively increased, so that epitaxy of lower resistivity can be chosen under the same withstand voltage condition so as to lower the forward switch-on voltage drop of the schottky diode.
Description
Technical field
The present invention relates to semiconductor applications, more precisely a kind of point of grid gate trench and trench schottky diode and preparation thereof
Method.
Background technology
The maximum field of conventional groove Schottky diode is usually located at channel bottom, and such as electric field to be reduced, increase is the most pressure,
Generally there are two kinds of methods: one is to sacrifice forward conduction voltage, selects the epitaxial layer of big resistivity；Two are to increase oxidated layer thickness,
Reduce groove pitch, reduce the utilization rate of epitaxial layer, sacrifice forward conduction voltage equally.
Conventional groove Schottky diode is the having lateral depletion utilizing groove structure, promotes the reverse breakdown of diode, so outside
Prolonging layer resistivity can be lower, and the forward conduction voltage of diode is the least.
When reverse bias, in the channel bottom of conventional groove Schottky diode and the epitaxial layer of sidewall, due to the shadow of potential difference
Ringing, can produce depletion layer, the depletion layer broadening of sidewall direction makes the epitaxial layer between adjacent trenches all exhaust, and makes longitudinal side
To depletion layer thickness be greatly increased, thus improve the breakdown reverse voltage of Schottky diode.And at channel bottom, owing to being subject to
The impact of adjacent trenches having lateral depletion layer is the least, and therefore its depletion layer thickness is the narrowest, and electric field is concentrated, device the most resistance to
Pressure also may be restricted to the breakdown voltage of this position.
Conventional groove Schottky diode is as the most pressure in increased, and generally has two kinds of methods: one is to increase the resistivity of epitaxial layer,
So doping content of epitaxial layer reduces, and the depletion layer of channel bottom is wider, reverse pressure lifting, but forward conduction voltage drop liter
High；Two thickness being to increase oxide layer, oxidated layer thickness increases, then the electric field in oxide layer reduces, according to Gauss law, with
The voltage of its adjacent epitaxial layer also can reduce accordingly, but the method also reduces the depletion width of trenched side-wall simultaneously, such as phase
The depletion layer of adjacent groove cannot connect, then cannot raise reverse pressure voltage, pressure voltage can be made on the contrary to reduce.
The maximum field of conventional groove Schottky diode is usually located at channel bottom, and such as electric field to be reduced, increase is the most pressure,
Generally there are two kinds of methods: one is to sacrifice forward conduction voltage, selects the epitaxial layer of big resistivity；Two are to increase oxidated layer thickness,
Reduce groove pitch, reduce the utilization rate of epitaxial layer, sacrifice forward conduction voltage equally.
Summary of the invention
It is an object of the invention to provide a kind of point of grid gate trench structure and trench schottky diode and preparation method thereof, it is permissible
Solve the shortcoming of reverse resistance to pressure reduction in prior art.
The present invention is by the following technical solutions:
A kind of point of grid gate trench structure, including a point grid gate trench: form sediment and be provided with a first grid in the bottom of described point of grid gate trench
Form sediment in oxide layer, and described first grid oxide layer and set one first polysilicon gate, and the top of described first polysilicon gate is protruded described
First grid oxide layer；Also include a second gate oxide layer, and described second gate oxide layer is formed sediment and is located at the upper side of described gate trench
On wall, described second gate oxide layer is in described first grid oxide layer and the top of described first polysilicon gate, one second polysilicon
Grid form sediment and are located at the inside of described second gate oxide layer.
The thickness of described first grid oxide layer is thicker than described second gate oxide layer.
A kind of trench schottky diode, containing above-mentioned point grid gate trench structure.
Also include that a knot end ring structure, described point of grid gate trench structure and described knot end ring structure are formed in an epitaxial layer.
Also include a substrate layer, and described epitaxial layer is formed at the side of a substrate.
Forming sediment and are provided with second gate oxide layer in the sidewall of end ring groove and bottom, described second gate oxide layer is formed sediment is provided with the second polysilicon
Grid, and the second polysilicon gate form sediment be located in sidewall and the bottom periphery of described end ring groove.
One dielectric layer forms sediment and is located on the second polysilicon gate of end ring trenched side-wall and the second gate oxide layer of end ring channel bottom
On, and dielectric layer do not forms sediment and sets the most described end ring groove, described dielectric layer also forms sediment in described end ring groove and a point grid gate trench
Between epitaxial layer on and the second gate oxide layer of point grid gate trench side adjacent with end ring groove of described end ring structure
Top also extends to the centre of the second polysilicon gate of end ring groove to opposite side.
Also including the first metal layer, epitaxial layer, the second polysilicon gate of described point of grid gate trench and second gate oxygen layer are located in its shallow lake
And on dielectric layer, and described the first metal layer forms sediment and is located on the dielectric layer of end ring groove half.
Also including one second metal level, its shallow lake is located on described the first metal layer.
The preparation method of a kind of trench schottky diode, comprises the following steps:
Epitaxial layer deposits masking layer, and carries out trench lithography, etch masking layer, form etching groove window；
Carry out etching groove, form groove and end ring groove；
Grow the first gate oxide；
Deposit the first polysilicon gate, fill groove and end ring groove；
Carrying out polysilicon gate etching, retain the first polysilicon gate of channel bottom, the polysilicon in end ring groove all etches away；
Carrying out the first oxide layer etching, etch away the first oxide layer, surface covering layer is also etched away, the oxidation of end ring groove
Layer is all etched away；
Grow one layer of second gate oxide layer, as the sealing coat of groove top half；
Deposit the second polysilicon gate, fill groove and end ring groove；
Carry out polysilicon gate etching, etch away the second polysilicon gate of epi-layer surface, retain the second polysilicon gate of trench interiors,
The second polysilicon gate is had to retain on the sidewall of big groove；
Dielectric layer deposited, and carry out contact hole etching, remove medium and the oxide layer of epi-layer surface, end is located at contact hole edge
The minor groove central authorities that end ring groove is adjacent；
Deposit the first metal layer, and anneal so that it is form Schottky contacts with epitaxial layer；
Deposit the second metal level, and to carrying out photoetching, etching, by first, second gold medal of end ring groove central authorities to chip edge
Belong to layer to remove；
Substrate back is carried out thinning, deposits metal layer on back, be used for encapsulating extraction.
The invention have the advantage that the present invention introduces grid dividing structure in conventional groove Schottky diode structure, increase the most resistance to
Pressure, simultaneously by special Terminal Design, it is ensured that terminal pressure.The present invention can effectively promote trench schottky two pole
Pipe the most pressure so that identical pressure in the case of, the extension of more low-resistivity can be selected, reduce Schottky diode
Forward conduction voltage drop.
Accompanying drawing explanation
Below in conjunction with embodiment and accompanying drawing, the present invention is described in detail, wherein:
Fig. 1 is the structural representation of the present invention.
Fig. 2 to Figure 13 is the structural representation of the intermediate of the present invention.
Detailed description of the invention
The detailed description of the invention of the present invention be expanded on further below in conjunction with the accompanying drawings:
As it is shown in figure 1, a kind of point of grid gate trench structure, including a point grid gate trench 24, the bottom of described point of grid gate trench
Form sediment in being provided with a first grid oxide layer 31, and described first grid oxide layer 31 and set one first polysilicon gate 41, and the first polycrystalline in shallow lake
Described first grid oxide layer 31 is protruded at the top of Si-gate 41；Also include a second gate oxide layer 32, described second gate oxide layer 32
Form sediment on the top sidewall being located at described point of grid gate trench, and described second gate oxide layer 32 is in described first grid oxide layer 31
And the top of described first polysilicon gate 41, one second polysilicon gate 42 forms sediment and is located at the inside of described second gate oxide layer 32, institute
The thickness stating first grid oxide layer is thicker than described second gate oxide layer.
The invention also discloses a kind of trench schottky diode, including some above-mentioned point grid gate trench structures and knot end ring knot
Structure, described point of grid gate trench structure and described knot end ring structure are formed in an epitaxial layer 20, and described epitaxial layer is formed at
The side of one substrate 10.
Knot end ring structure includes an above-mentioned point grid gate trench structure, and described end ring structure also includes an end ring groove 23,
Forming sediment and are provided with second gate oxide layer 32 in the sidewall of end ring groove and bottom, described second gate oxide layer 32 is formed sediment is provided with the second polycrystalline
Si-gate 42, and the second polysilicon gate 42 form sediment be located in sidewall and the bottom periphery of described end ring groove；One dielectric layer 50 forms sediment and sets
On the second polysilicon gate 42 of end ring trenched side-wall and in the second gate oxide layer of end ring channel bottom, and dielectric layer does not forms sediment
If full described end ring groove, outside described dielectric layer 50 also forms sediment between described end ring groove 23 and point grid gate trench 24
Prolong on layer and the top of second gate oxide layer of point grid gate trench 24 side adjacent with end ring groove of described end ring structure
And the centre of the second polysilicon gate 42 of end ring groove 24 is extended to opposite side.
Present invention additionally comprises the first metal layer 60, it forms sediment and is located at the second polysilicon of epitaxial layer 10, described point of grid gate trench 24
On grid 42 and second gate oxygen layer 32 and dielectric layer 50, described the first metal layer 60 also forms sediment and is located at point grid grid of end ring structure
In the groove second gate oxide layer away from end ring groove side, a point grid gate trench for end ring structure do not forms sediment and is provided with dielectric layer
In second gate oxide layer and dielectric layer on the dielectric layer 50 that end ring groove direction extends to end ring groove half.
Present invention additionally comprises one second metal level 70, its shallow lake is located on described the first metal layer 60.
The preparation method of a kind of trench schottky diode, comprises the following steps:
Epitaxial layer 20 deposits masking layer, and carries out trench lithography, etch masking layer 21, form etching groove window 22；Root
Suitable disk is selected, outside this disk is by the substrate 10 of low-resistivity and specific electric resistance according to the property requirements of Schottky diode
Prolong layer 20 to form；Growing one layer of masking layer 21 on epitaxial layer, the effect of this masking layer is to provide for etching groove below to shelter,
The composition of masking layer material is silicon dioxide, it is also possible to other materials substitutes；Carry out trench lithography, and masking layer performed etching,
Etch etching groove window 22, as shown in Figure 2.
Carry out etching groove, form groove；Carry out etching groove, under the masking action of masking layer, form groove 23, end ring
Groove 24, the end ring groove 24 in figure is large scale groove, as shown in Figure 3.
Grow the first gate oxide；Carry out sacrificial oxidation, and remove oxide layer；First one layer of thicker first grid oxide layer 31 of growth,
Form lower floor and divide the thick oxide layer of grid, as shown in Figure 4.
Deposit the first polysilicon, fill groove；And polysilicon is carried out heavy doping, reduce resistivity, as shown in Figure 5.
Carrying out etching polysilicon, retain the first polysilicon gate 40 of channel bottom specific thicknesses, the polysilicon in end ring groove is complete
Portion etches away；Etch away unnecessary polysilicon, form the grid of point grid, as shown in Figure 6.
Carrying out gate oxide etching, etch away thick first grid oxide layer, surface covering layer also can be etched away, end ring groove
First grid oxide layer is all etched away；Carry out oxide layer etching, remove first grid oxide layer and the extension table of groove top half
The masking layer in face；In order to ensure that gate oxide is etched totally, gate oxide is etched with certain excessive erosion amount, therefore at point grid
The oxide layer of marginal surface some be etched away, form little groove；As shown in Figure 7.
Grow one layer of second gate oxide layer, as the sealing coat of groove top half；The gate oxide of growth layer, as
Groove top half and epitaxial layer and the sealing coat of point grid, as shown in Figure 8.
Deposit the second polysilicon gate, fill groove；Depositing polysilicon grid, fill groove, and polysilicon gate are carried out heavy doping,
Reduce resistivity, as shown in Figure 9.
Carry out polysilicon gate etching, etch away the polysilicon gate of epi-layer surface, retain the polysilicon gate of trench interiors, big groove
Sidewall on have polysilicon gate to retain；Carry out polysilicon gate etching, etch away the polysilicon gate of epitaxial surface, retain in groove
Polysilicon gate, due to anisotropic etching characteristic on the sidewall in end ring groove, remains with polysilicon gate, as shown in Figure 10.
Dielectric layer deposited, its composition is silicon dioxide, and carries out contact hole photoetching, etching, remove the dielectric layer in contact hole and
Oxide layer, and the border of contact hole is different from the design of conventional groove Schottky diode, and the border of contact hole is placed on terminal
Point grid gate trench central authorities that circular groove groove is adjacent；Owing to there is not grid dividing structure in end ring groove, as with positive contact, then exist
Can reduce the most pressure of whole device during device reverse bias, therefore the polysilicon of terminal should be at quick condition, improves terminal
Pressure, as shown in figure 11.
Deposit the first metal layer, and anneal so that it is form Schottky contacts, the wherein material of the first metal layer with epitaxial layer
Can to be titanium, cobalt, nickel, silver, platinum or titanium any with the composite bed of titanium nitride etc. can form the material of Schottky contacts with epitaxial layer
Material, as shown in figure 12.
Deposit the second metal level, and to carrying out photoetching, etching, by first, second gold medal of end ring groove central authorities to chip edge
Belong to layer to remove, as shown in figure 13.
Carrying out thinning to substrate back, and deposit metal layer on back overleaf, for the back side, encapsulation is drawn, the selection of metal material
Relevant with packaging technology.
Point grid Schottky diode structure of the present invention of the present invention introduces a point grid knot in the bottom of conventional groove Schottky diode
Structure, reduces the big electric field of channel bottom；Remain the having lateral depletion effect of groove top half sidewall so that the present invention simultaneously
The Schottky diode of structure can more effectively utilize the having lateral depletion effect of groove, without the big electric field by channel bottom
Limit.The maximum field of conventional groove Schottky diode is usually located at channel bottom, and such as electric field to be reduced, increase is the most pressure,
Generally there are two kinds of methods: one is to sacrifice forward conduction voltage, selects the epitaxial layer of big resistivity；Two are to increase oxidated layer thickness,
Reduce groove pitch, reduce the utilization rate of epitaxial layer, sacrifice forward conduction voltage equally.
The present invention introduces grid dividing structure in the bottom of groove, and point grid current potential is owing to being induced potential, and when reverse-biased, its current potential is at negative electrode
High potential and the electronegative potential of anode between, compare conventional groove Schottky diode structure, potential difference reduces, thus reduces
Divide the electric field near grid.And the top half of groove, use the oxidated layer thickness thinner compared with conventional groove Schottky diode, increase
The having lateral depletion effect of strong trenched side-wall, the interval making groove can be bigger, promotes the utilization rate of epitaxial layer.
The present invention introduces grid dividing structure in conventional groove Schottky diode structure, increase the most pressure, simultaneously by special
Terminal Design, it is ensured that terminal pressure.The present invention can effectively promote the most pressure of trench schottky diode, makes
Must identical pressure in the case of, the extension of more low-resistivity can be selected, reduce the forward conduction voltage drop of Schottky diode.
The present invention introduces grid dividing structure in the bottom of groove, and point grid current potential is owing to being induced potential, and when reverse-biased, its current potential is at negative electrode
High potential and the electronegative potential of anode between, compare conventional groove Schottky diode structure, potential difference reduces, thus reduces
Divide the electric field near grid.And the top half of groove, use the oxidated layer thickness thinner compared with conventional groove Schottky diode, increase
The having lateral depletion effect of strong trenched side-wall, the interval making groove can be bigger, promotes the utilization rate of epitaxial layer.
Point grid Schottky diode structure of the present invention introduces grid dividing structure in the bottom of conventional groove Schottky diode, reduces
The big electric field of channel bottom；Remain the having lateral depletion effect of groove top half sidewall so that the Xiao Te of present configuration simultaneously
Based diode can more effectively utilize the having lateral depletion effect of groove, is limited without the big electric field by channel bottom.
Groove adjacent for original end ring groove is brought in end ring structure by the present invention by end ring structure, makes two grooves
Between N-type silicon epitaxy layer surface do not contact with metal level, the electric field in N-type silicon epitaxy layer extends in dielectric layer, according to height
This law, it is recognised that the electric field intensity in dielectric layer is much larger than the electric field on N-type silicon epitaxy layer surface, the most just can improve N-type
The Electric Field Distribution of channel bottom in silicon epitaxy layer.In original structure, the polysilicon profile of the 3rd trenched side-wall is unstable, and bar width is very
The little photoetching para-position at follow-up contact hole can cause the polysilicon of sidewall to contact bad with metal level with when etching, or contact hole
The situation that the polysilicon surrounding oxidic nitride layer of sidewall is etched away by etching, causes device property unstable, and this can be had by the present invention
Well improve.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all spirit in the present invention and former
Any amendment, equivalent and the improvement etc. made within then, should be included within the scope of the present invention.
Claims (10)
1. one kind of point of grid gate trench structure, it is characterised in that include a point grid gate trench: form sediment in the bottom of described point of grid gate trench
Form sediment in being provided with a first grid oxide layer, and described first grid oxide layer and set one first polysilicon gate, and described first polycrystalline
Described first grid oxide layer is protruded at the top of Si-gate；Also include a second gate oxide layer, and described second gate oxide layer is formed sediment
Being located on the top sidewall of described point of grid gate trench, described second gate oxide layer is in described first grid oxide layer and institute
Stating the top of the first polysilicon gate, one second polysilicon gate forms sediment and is located at the inside of described second gate oxide layer.
The most according to claim 1 point of grid gate trench structure, it is characterised in that the thickness of described first grid oxide layer is thicker than
Described second gate oxide layer.
3. a trench schottky diode, it is characterised in that containing as claimed in claim 1 or 2 point of grid gate trench structure.
Trench schottky diode the most according to claim 3, it is characterised in that also include a knot end ring structure, described point
Grid gate trench structure and described knot end ring structure are formed in an epitaxial layer.
5. according to the trench schottky diode described in claim 4 or 3, it is characterised in that also include a substrate layer and described
Epitaxial layer is formed at the side of a substrate.
Trench schottky diode the most according to claim 5, it is characterised in that form sediment and set in the sidewall of end ring groove and bottom
Having second gate oxide layer, described second gate oxide layer is formed sediment is provided with the second polysilicon gate, and the second polysilicon gate forms sediment and is located at
On the sidewall of described end ring groove and bottom periphery.
Trench schottky diode the most according to claim 6 a, it is characterised in that dielectric layer forms sediment and is located at end ring channel side
On second polysilicon gate of wall and in the second gate oxide layer of end ring channel bottom, and dielectric layer does not forms sediment and sets the most described end
End ring groove, described dielectric layer also forms sediment on the epitaxial layer between described end ring groove and point grid gate trench and described
The top of the second gate oxide layer of point grid gate trench side adjacent with end ring groove of end ring structure to opposite side
Extend to the centre of the second polysilicon gate of end ring groove.
Trench schottky diode the most according to claim 7, it is characterised in that also include the first metal layer, its shallow lake is located at
On epitaxial layer, the second polysilicon gate of described point of grid gate trench and second gate oxygen layer and dielectric layer, and described first gold medal
Belong to layer shallow lake to be located on the dielectric layer of end ring groove half.
Trench schottky diode the most according to claim 8, it is characterised in that also include one second metal level, its shallow lake sets
On described the first metal layer.
10. the preparation method of a trench schottky diode, it is characterised in that comprise the following steps:
Epitaxial layer deposits masking layer, and carries out trench lithography, etch masking layer, form etching groove window；
Carry out etching groove, form groove and end ring groove；
Grow the first gate oxide；
Deposit the first polysilicon gate, fill groove and end ring groove；
Carrying out polysilicon gate etching, retain the first polysilicon gate of channel bottom, the polysilicon in end ring groove all etches away；
Carrying out the first oxide layer etching, etch away the first oxide layer, surface covering layer is also etched away, the oxidation of end ring groove
Layer is all etched away；
Grow one layer of second gate oxide layer, as the sealing coat of groove top half；
Deposit the second polysilicon gate, fill groove and end ring groove；
Carry out polysilicon gate etching, etch away the second polysilicon gate of epi-layer surface, retain the second polysilicon gate of trench interiors,
The second polysilicon gate is had to retain on the sidewall of big groove；
Dielectric layer deposited, and carry out contact hole etching, remove medium and the oxide layer of epi-layer surface, end is located at contact hole edge
The minor groove central authorities that end ring groove is adjacent；
Deposit the first metal layer, and anneal so that it is form Schottky contacts with epitaxial layer；
Deposit the second metal level, and to carrying out photoetching, etching, by first, second gold medal of end ring groove central authorities to chip edge
Belong to layer to remove；
Substrate back is carried out thinning, deposits metal layer on back, be used for encapsulating extraction.
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| CN113903813A (en) * | 2021-09-30 | 2022-01-07 | 上海芯导电子科技股份有限公司 | Schottky diode, manufacturing method thereof and electronic device |
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