CN107393955B - High-efficiency high-reliability silicon carbide MOS tube and manufacturing method thereof - Google Patents
High-efficiency high-reliability silicon carbide MOS tube and manufacturing method thereof Download PDFInfo
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- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 3
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims description 2
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims description 2
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- 238000007254 oxidation reaction Methods 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 abstract description 20
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
A silicon carbide MOS tube with high efficiency and high reliability and a manufacturing method thereof belong to the technical field of semiconductor manufacturing. The silicon carbide semiconductor device comprises a silicon carbide substrate and a drift region above the substrate, wherein a base region, a source region and a top oxide layer are sequentially formed above the drift region, grooves penetrating through the source region and the base region and entering the drift region are formed, silicon oxide columns are arranged side by side above the substrate, extend to the substrate from the source region, penetrate through the source region, the base region and the drift region, the grooves are formed in the silicon oxide columns of a working region, contact holes are formed between adjacent silicon oxide columns in the working region, the contact holes penetrate through the top oxide layer and the source region from top to bottom and enter the base region, and surface metal connects the source region and the base region between the adjacent grooves through the contact holes to form a source. Has the beneficial effects of high conductive efficiency and high reliability.
Description
Technical Field
A silicon carbide MOS tube with high efficiency and high reliability and a manufacturing method thereof belong to the technical field of semiconductor manufacturing.
Background
The first generation of semiconductor materials, represented by silicon and germanium, and the third generation of semiconductor materials, represented by silicon carbide materials, have been widely used with the development of semiconductor technology. Compared with the first-generation semiconductor material represented by silicon and germanium, the third-generation semiconductor material represented by silicon carbide material has the advantages of bandwidth inhibition, high temperature resistance and high voltage resistance, thereby greatly improving the performance and quality of the semiconductor device.
Taking a common trench type MOS as an example, the structure of the trench type MOS tube is shown in fig. 8, the trench type MOS tube comprises an N+ type substrate 9, an N type drift region 8, a P type base region 5 and a plurality of trenches are sequentially arranged above the N+ type substrate 9, the upper surface of the P type base region 5 is provided with a plurality of trenches side by side, the trenches penetrate through the P type base region 5 and enter the N type drift region 8, an N+ type source region 2 is formed on the outer ring of the trenches, a top oxide layer 3 is arranged at the top of the trenches to form a MOS structure, a top metal layer 1 and a bottom metal layer 10 are respectively arranged at the upper part of the top oxide layer 3 and the lower part of the N+ type substrate 9, and then a grid electrode, a source electrode and a drain electrode of the MOS tube are led out. In the prior art, the doping concentration and thickness of the N-type drift region 8 in the MOS transistor are designed according to the voltage born by the PN junction formed between the N-type drift region 8 and the P-type base region 5 when the PN junction is empty and empty under the condition of the voltage resistance of the MOS transistor, so that the impedance of the N-type drift region 8 is also determined. In the prior art, in order to increase the voltage born by the MOS transistor when the PN junction is empty, the doping concentration of the N-type drift region 8 is often lower, so that the impedance of the N-type drift region 8 is also higher, i.e., the current conduction efficiency is lower.
Although the MOS transistor made of the silicon carbide material is structurally different from the MOS transistor made of the silicon material, the silicon carbide material has more severe requirements on the process in the manufacturing process, and specifically: the MOS tube made of silicon material is formed by ion implantation when the P-type base region 5 and the N+ type source region 2 are manufactured, the ion implantation process is mature for the MOS tube made of silicon material, but the ultra-high energy of more than 1MeV is needed when the P-type base region 5 and the N+ type source region 2 are manufactured by ion implantation for silicon carbide material, and high temperature of about 600 ℃ or more is needed, even if the two conditions are met, the ion implantation depth is only about 0.5 mu m to 1 mu m, the wafer damage caused by high-temperature annealing at about 1600 ℃ is needed to repair the high-energy ion implantation after the ion implantation is finished, the electric property of activated ions is activated, and the ions are very slowly diffused in silicon carbide under the high-temperature environment at 1600 ℃. As can be seen from the above, the silicon carbide material has very severe requirements on the process conditions in the manufacturing process, and at present, only some scientific research institutions and university laboratories have devices capable of meeting part of the requirements at home, while in most enterprises, in view of cost, very few enterprises can put very large funds into the introduction of the devices, so that the development of the silicon carbide material semiconductor devices is greatly limited. Aiming at the defects of the prior art, a technical scheme with high conductive efficiency and high reliability is urgently needed at present.
Disclosure of Invention
The invention aims to solve the technical problems that: overcomes the defects of the prior art and provides a silicon carbide MOS tube with high conductive efficiency, high reliability, high efficiency and high reliability and a manufacturing method thereof.
The technical scheme adopted for solving the technical problems is as follows: the high-efficiency high-reliability silicon carbide MOS tube comprises a silicon carbide substrate and a drift region above the substrate, wherein a base region, a source region and a top oxide layer are sequentially formed above the drift region, a groove penetrating through the source region and the base region and entering the drift region is formed, polysilicon is filled in the groove and a MOS structure is formed, and the high-efficiency high-reliability silicon carbide MOS tube is characterized in that: the silicon oxide columns extend to the upper surface of the substrate from the upper surface of the source region to the upper surface of the substrate through the source region, the base region and the drift region, the grooves are formed in the silicon oxide columns of the working region, contact holes are formed between adjacent silicon oxide columns in the working region, the contact holes penetrate through the top oxide layer and the source region from top to bottom and enter the base region, and surface metal connects the source region and the base region between the adjacent grooves through the contact holes to form a source electrode.
Preferably, a top metal layer is disposed over the top oxide layer.
Preferably, an underlying metal layer is disposed below the substrate.
Preferably, the substrate is an n+ type substrate, the drift region is an N type drift region, the base region is a P type base region, and the source region is an n+ type source region.
Preferably, the silicon oxide column outside the silicon oxide column provided with the groove at the outermost side is provided with a termination region.
A manufacturing method of a silicon carbide MOS tube with high efficiency and high reliability is characterized by comprising the following steps: the method comprises the following steps:
step a, a first oxide layer is taken as a substrate, and then a silicon oxide layer is deposited on the upper surface of the substrate to form a first oxide layer;
step b, etching the first oxide layer for the first time, etching the first oxide layer to the upper surface of the substrate, wherein the first oxide layer remained on the upper surface of the substrate is a silicon oxide column, and a first groove is formed between two adjacent silicon oxide columns at intervals;
step c, growing a drift region, a base region and a source region of single crystal epitaxy on the N+ type substrate in sequence according to a preset thickness in the first groove for the first time;
step d, etching the silicon oxide column in the working area according to the preset position of the working area to form a second groove, wherein the second groove passes through the source area and the base area and enters the drift area;
step e, the second oxide layer is formed by performing thermal oxidation or depositing silicon oxide and other oxides in the second groove to form an oxide layer in the groove, and filling is performed to form a filling layer;
step f, etching the surface of the second groove for the third time, and etching the filling layer to the surface of the source region;
step g, a third oxide layer, namely, depositing silicon oxide or other oxides on the upper surface of the source region to form a top oxide layer, wherein the top oxide layer is combined with the oxide layer in the groove;
and h, photoetching, namely photoetching two adjacent silicon oxide columns in the working area to form contact holes, wherein the contact holes downwards penetrate through the top oxide layer and the source area to enter the base area.
Preferably, the filling layer in the step e is polysilicon.
Preferably, in the step d, the depth of the second trench into the drift region is 0.1-0.5 μm.
Preferably, in the step h, the depth of the contact hole into the base region is 0.1-0.5 μm.
Compared with the prior art, the invention has the following beneficial effects:
1. the silicon carbide MOS tube with high efficiency and high reliability and the manufacturing method thereof have the beneficial effects of high conductive efficiency, high reliability, no need of high-temperature high-energy ion implantation, high-temperature ion activation and diffusion, effective formation and control of doping concentration and junction depth of a silicon carbide base region and a source region and wide application.
2. Because the silicon oxide column extends downwards to the N+ type substrate, a depletion region is formed between the outer ring of the silicon oxide column and the N type drift region, and therefore leakage current in the MOS tube is greatly reduced. Meanwhile, the depletion region formed between the outer ring of the silicon oxide column and the N-type drift region plays a role in auxiliary depletion, so that the thickness of the N-type drift region can be reduced and the doping concentration of the N-type drift region can be increased on the premise of the same voltage-withstanding requirement, the impedance of the N-type drift region is reduced, and the conduction efficiency of the MOS tube in forward conduction is improved.
3. By arranging the silicon oxide column, the capacitance Cgd between the grid electrode and the drain electrode can be reduced to the minimum, the switching loss is reduced, the working frequency is improved, and the power efficiency is improved.
4. Because the depletion region formed between the outer ring of the silicon oxide column and the N-type drift region plays a role in auxiliary depletion, the electric field pressure born by the gate oxide layer is greatly reduced, and the reliability of long-term operation of the gate oxide layer is ensured.
5. The manufacturing method overcomes the defect that the process requirements are very harsh when the silicon carbide semiconductor chip is manufactured in the prior art, adopts the technology of forming the silicon oxide layer groove and manufacturing the epitaxial crystal to manufacture the N-type drift region, the N+ type source region and the P-type base region, overcomes the current situation that high-temperature high-energy ion implantation and high-temperature activation cannot be completed at present, effectively forms and controls the doping concentration and the junction depth of the base region and the source region, greatly reduces the process requirements for manufacturing the silicon carbide semiconductor device, and ensures wider applicability of the silicon carbide device.
6. The P-type material layer and the N-type material layer are exchanged, and the same beneficial effects of the P-channel MOS tube can be achieved based on the same structure manufacturing sequence.
7. The invention is suitable for other similar structures of groove type elements and has the beneficial effect of wide application.
8. The invention is not limited to silicon carbide materials, and semiconductor materials such as silicon, gallium nitride and the like are also suitable for manufacturing the semiconductor device made of the silicon materials, and the invention has the beneficial effects of improving the efficiency and being widely applied.
Drawings
Fig. 1 is a schematic structural diagram of a silicon carbide MOS transistor with high efficiency and high reliability.
FIGS. 2-7 are flow charts of high efficiency and high reliability silicon carbide MOS tube manufacturing processes.
Fig. 8 is a schematic diagram of a prior art MOS transistor structure.
Wherein: 1. a top metal layer 2, an N+ type source region 3, a top oxide layer 4, a contact hole 5, a P type base region 6, a silicon oxide column 7, polysilicon 8, an N type drift region 9, an N+ type substrate 10, a bottom metal layer 11, a first oxide layer 12, a first trench 13 and a second trench.
Detailed Description
Fig. 1 to 7 are diagrams illustrating preferred embodiments of the present invention, and the present invention is further described below with reference to fig. 1 to 7.
As shown in fig. 1, the silicon carbide MOS transistor with high efficiency and high reliability is made of a silicon carbide semiconductor and comprises an n+ type substrate 9, an N type drift region 8 is arranged above the n+ type substrate 9, a P type base region 5 is arranged above the N type drift region 8, and an n+ type source region 2 is arranged on the upper surface of the P type base region 5. A plurality of silicon oxide columns 6 of silicon oxide materials are arranged above the N+ type substrate 9 side by side, and the silicon oxide columns 6 sequentially penetrate through the N+ type source region 2, the P type base region 5 and the N type drift region 8 downwards from the upper surface of the N+ type source region 2 and then extend downwards to the upper surface of the N+ type substrate 9. Trenches filled with polysilicon 7 are formed in the inner plurality of silicon oxide pillars 6. A plurality of silicon oxide pillars 6 not filled with polysilicon 7 are reserved outside the silicon oxide pillars 6 filled with polysilicon 7 at the outermost side as silicon oxide pillars 6 of the chip termination region.
The upper surface of the N+ type source region 2 is also provided with a top oxide layer 3, and the top oxide layer 3 is combined with a silicon oxide layer on the outer circle of the polysilicon 7. A contact hole 4 is formed between two adjacent silicon oxide columns 6 filled with polysilicon 7, and the contact hole 4 passes through the top oxide layer 3 and the N+ type source region 2 downwards from the upper surface of the top oxide layer 3 and then enters the P-type base region 5.
The upper surface of the top oxide layer 3 is also provided with a top metal layer 1, the lower part of the N+ type substrate 9 is also provided with a bottom metal layer 10, the top metal layer 1, the top oxide layer 3, the N+ type source region 2 and the P type base region 5 form a MOS structure of the silicon carbide MOS tube, the contact hole 4 is filled with a conductor, the N+ type source region 2 and the P type base region 5 corresponding to the contact hole 4 are connected through the conductor and are simultaneously connected with the top metal layer 1, the source electrode of the silicon carbide MOS tube is led out from the top metal layer 1, the drain electrode of the silicon carbide MOS tube is led out from the bottom metal layer 10, and the grid electrode of the silicon carbide MOS tube is led out from the polysilicon 7.
The specific working process and working principle are as follows:
when the MOS tube is in use, namely, the positive electrode of an external power supply is connected with the drain electrode (the bottom metal layer 10), the negative electrode of the external power supply is connected with the source electrode (the top metal layer 1), and at the moment, the PN junction formed between the N-type drift region 8 and the P-type base region 5 is reversely cut off, so that no current flows in the MOS tube. After a forward voltage is added between the grid electrode and the source electrode, when the voltage value of the forward voltage is larger than the starting voltage of the MOS tube, a conductive channel is formed in the MOS structure, and current flows in from the drain electrode through the conductive channel and flows out from the source electrode. When the gate voltage is lower than the starting voltage of the MOS transistor, the conducting channel of the MOS transistor is closed, except for a depletion region formed outside a PN junction between the N-type drift region 8 and the P-type base region 5, as the silicon oxide column 6 extends downwards to the position of the N+ type substrate 9, a depletion region is formed between the outer ring of the silicon oxide column 6 and the N-type drift region 8, and therefore leakage current in the MOS transistor is greatly reduced. Meanwhile, the depletion region formed between the outer ring of the silicon oxide column 6 and the N-type drift region 8 plays a role in auxiliary depletion, so that the thickness of the N-type drift region 8 can be reduced and the doping concentration of the N-type drift region 8 can be increased on the premise of the same voltage-withstanding requirement, the impedance of the N-type drift region 8 is reduced, and the conduction efficiency of the MOS tube in forward conduction is improved. By arranging the silicon oxide column 6, the capacitance Cgd between the gate and the drain can be reduced to the minimum, the switching loss is reduced, the working frequency is increased, and the power efficiency is improved. Because the depletion region formed between the outer ring of the silicon oxide column 6 and the N-type drift region 8 plays a role in auxiliary depletion, the electric field pressure born by the gate oxide layer is greatly reduced, and the reliability of long-term operation of the gate oxide layer is ensured.
As shown in fig. 2 to 7, the silicon carbide MOS transistor with high efficiency and high reliability as shown in fig. 1 is manufactured, and the method comprises the following steps:
In step 3, the N-type drift region 8, the P-type base region 5 and the n+ type source region 2 are sequentially grown in the first trench 12 according to a predetermined thickness, as shown in fig. 4.
And 4, etching the silicon oxide column 6 in the working area according to the preset position of the working area to form a second groove 13, wherein the second groove 13 penetrates through the N+ type source area 2 and the P type base area 5, and the bottom of the second groove 13 is lower than the upper surface of the N type drift area 8 by 0.1-0.5 mu m, as shown in figure 5.
And 5, manufacturing a second oxide in the second groove 13 to form an oxide layer in the groove, filling the polysilicon 7 in the groove, and etching the surface of the second groove 13 to etch the polysilicon 7 to the surface of the N+ type source region 2, as shown in fig. 6.
And 6, manufacturing a third oxide on the upper surface of the N+ type source region 2 to form a top oxide layer 3, combining the top oxide layer 3 with the oxide layer in the groove, and then photoetching the top oxide layer 3 between two adjacent silicon oxide columns 6 in the working region to form a contact hole 4, wherein the contact hole 4 passes through the top oxide layer 3 and the N+ type source region 2 downwards and then is positioned at 0.1-0.5 mu m of the P type base region 5, as shown in fig. 7.
And 7, forming a top metal layer 1 and a bottom metal layer 10, and leading out a grid electrode, a source electrode and a drain electrode to manufacture the high-efficiency high-reliability silicon carbide MOS tube shown in figure 1.
By the manufacturing method described in the steps 1 to 7, the defect that the process requirements are very strict when the silicon carbide semiconductor chip is manufactured in the prior art is overcome, the manufacturing of the N-type drift region 8, the N+ type source region 2 and the P-type base region 5 is realized by adopting the technology of opening the oxide layer groove and manufacturing the epitaxial epitaxy, the current situation that high-temperature high-energy ion implantation and high-temperature ion activation must not be completed at present is overcome, the process requirements of manufacturing the silicon carbide semiconductor device are greatly reduced, and the applicability is wider.
The silicon carbide material fabrication described above is exemplified by MOS, and the invention is also applicable to fabrication of various devices (including but not limited to diodes, MOS transistors, IGBTs, etc.) that use silicon or other semiconductors as materials.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the invention in any way, and any person skilled in the art may make modifications or alterations to the disclosed technical content to the equivalent embodiments. However, any simple modification, equivalent variation and variation of the above embodiments according to the technical substance of the present invention still fall within the protection scope of the technical solution of the present invention.
Claims (9)
1. The utility model provides a high-efficient high reliability carborundum MOS pipe, includes the drift region of carborundum substrate and substrate top, forms base region, source region and top layer oxide layer (3) in proper order in the top of drift region, is provided with the slot that passes source region, base region and get into the drift region, packs polycrystalline silicon (7) and forms MOS structure in the slot, its characterized in that: the silicon oxide columns (6) are arranged above the substrate side by side, the silicon oxide columns (6) downwards penetrate through the source region, the base region and the drift region from the upper surface of the source region to extend to the upper surface of the substrate, the grooves are formed in the silicon oxide columns (6) of the working region, contact holes (4) are formed between the adjacent silicon oxide columns (6) in the working region, the contact holes (4) penetrate through the top oxide layer (3) and the source region from top to bottom and enter the base region, and surface metal connects the source region and the base region between the adjacent grooves through the contact holes (4) to form the source electrode of the MOS tube.
2. The high efficiency high reliability silicon carbide MOS transistor of claim 1 wherein: a top metal layer (1) is arranged above the top oxide layer (3).
3. The high efficiency high reliability silicon carbide MOS transistor of claim 1 wherein: an underlying metal layer (10) is disposed below the substrate.
4. The high efficiency high reliability silicon carbide MOS transistor of claim 1 wherein: the substrate is an N+ type substrate (9), the drift region is an N type drift region (8), the base region is a P type base region (5), and the source region is an N+ type source region (2).
5. The high efficiency high reliability silicon carbide MOS transistor of claim 1 wherein: the silicon oxide column (6) outside the silicon oxide column (6) with the groove at the outermost side forms a termination region.
6. The method for manufacturing the high-efficiency high-reliability silicon carbide MOS tube according to any one of claims 1 to 5 is characterized by comprising the following steps: the method comprises the following steps:
step a, firstly, an oxide layer is taken as a substrate, and then a silicon oxide layer is deposited on the upper surface of the substrate to form a first oxide layer (11);
step b, etching the first oxide layer (11) for the first time, etching the first oxide layer (11) to the upper surface of the substrate, wherein the first oxide layer (11) remained on the upper surface of the substrate is a silicon oxide column (6), and a first groove (12) is formed between two adjacent silicon oxide columns (6) at intervals;
step c, growing a drift region, a base region and a source region of single crystal epitaxy on the N+ type substrate (9) in sequence according to a preset thickness in the first groove (12) for the first time;
step d, etching the silicon oxide column (6) in the working area according to the preset position of the working area to form a second groove (13), wherein the second groove (13) passes through the source area and the base area to enter the drift area;
e, performing thermal oxidation or depositing silicon oxide and other oxides in the second groove (13) to form an oxide layer in the groove, and filling to form a filling layer;
step f, etching the surface of the second groove (13) for the third time, and etching the filling layer to the surface of the source region;
step g, a third oxide layer, wherein silicon oxide deposition is carried out on the upper surface of the source region to form a top oxide layer (3), and the top oxide layer (3) is combined with the oxide layer in the groove;
and h, photoetching, namely photoetching two adjacent silicon oxide columns (6) in the working area to form a contact hole (4), wherein the contact hole (4) downwards passes through the top oxide layer (3) and the source area to enter the base area.
7. The manufacturing method according to claim 6, characterized in that: the filling layer in the step e is polysilicon (7).
8. The manufacturing method according to claim 6, characterized in that: in the step d, the depth of the second groove (13) into the drift region is 0.1-0.5 μm.
9. The manufacturing method according to claim 6, characterized in that: in the step h, the depth of the contact hole (4) entering the base region is 0.1-0.5 mu m.
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| CN105762176A (en) * | 2016-04-28 | 2016-07-13 | 电子科技大学 | Silicon carbide mosfet device and manufacturing method thereof |
| CN105957884A (en) * | 2016-06-24 | 2016-09-21 | 上海格瑞宝电子有限公司 | Split-gate gate trench structure and trench schottky diode and preparation method therefor |
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| CN105762176A (en) * | 2016-04-28 | 2016-07-13 | 电子科技大学 | Silicon carbide mosfet device and manufacturing method thereof |
| CN105957884A (en) * | 2016-06-24 | 2016-09-21 | 上海格瑞宝电子有限公司 | Split-gate gate trench structure and trench schottky diode and preparation method therefor |
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