CN103745996B - With lateral power and the making method of part insulation buried regions - Google Patents
With lateral power and the making method of part insulation buried regions Download PDFInfo
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- CN103745996B CN103745996B CN201310744626.9A CN201310744626A CN103745996B CN 103745996 B CN103745996 B CN 103745996B CN 201310744626 A CN201310744626 A CN 201310744626A CN 103745996 B CN103745996 B CN 103745996B
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- 238000009413 insulation Methods 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 17
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- 239000002019 doping agent Substances 0.000 claims abstract description 32
- 238000005468 ion implantation Methods 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims description 11
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- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000017525 heat dissipation Effects 0.000 abstract description 8
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- 230000008901 benefit Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
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- 239000012212 insulator Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
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- 238000000151 deposition Methods 0.000 description 3
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- 238000010586 diagram Methods 0.000 description 2
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- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of lateral power with part insulation buried regions, comprises support substrates, is positioned at the insulation buried regions on described support substrates surface and is positioned at the active layer on described insulation buried regions surface; Described insulation buried regions comprises a doping window; Described support substrates comprises the first buried dopant layer and the 2nd buried dopant layer, described first buried dopant layer is positioned at the lower section in drain region, described 2nd buried dopant layer is positioned at below source region, and described 2nd buried dopant layer is greater than the distance of described first buried dopant layer to described insulation buried regions to the distance of described insulation buried regions. For realizing the above-mentioned lateral power with part insulation buried regions, the present invention provides a kind of making method simultaneously, adopts twice ion implantation to form two buried regions in support substrates, in described support substrates surface etch to form doping window. It is an advantage of the current invention that, it is to increase the voltage breakdown of device, and can fall apart from substrate by the heat of generation by doping window, accelerate heat dissipation, it is to increase the reliability of device.
Description
Technical field
The present invention relates to a kind of lateral power with part insulation buried regions and making method, in particular to a kind of transverse diffusion metal oxide semiconductor device with part insulation buried regions and making method, belong to microelectronics and Solid State Electronics technical field.
Background technology
Power integrated circuit also claims high pressure unicircuit sometimes, it it is the important branch of modern electronics, the conversion of various power and the new-type circuit of energy treatment unit offer high speed, high integration, low-power consumption and Flouride-resistani acid phesphatase are provided, are widely used in current consumption field and many key areas such as national defence, space flight such as electric control system, automotive electronics, display device driving, communication and illumination. The rapid expansion of its range of application, it is also proposed higher requirement to the high tension apparatus of its core.
Owing to power integrated circuit usually combines high-voltage power transistor, the control function such as transmodulator and single logic function, therefore high tension apparatus and Low-Voltage Logic Devices must be on one chip integrated. Silicon-on-insulator is as a kind of desirable media isolated material, can effectively realize high and low power model, and the isolation between high-low voltage device, thoroughly eliminate electrical interference, simplify device structure design, and silicon-on-insulator isolated area area relatively tie isolation little, greatly saved die area, reduce stray capacitance, it is possible to conveniently integrated different circuit and device. Therefore, silicon-on-insulator technology is applied to high tension apparatus and power integrated circuit has obvious advantage and has wide practical use.
The IC product of integrated more than 600V silicon-on-insulator high voltage power device is widely used in luminescent lamp, the fields such as switch power supply control. Compared with body silicon high-voltage device, conventional silicon-on-insulator high tension apparatus, due to the existence of its dielectric buried layer, prevents depletion layer to expand to substrate, and its longitudinal voltage breakdown is lower. The design of usual 200V and following silicon-on-insulator high tension apparatus thereof is relatively easy, and the design difficulty of more than 600V product is bigger. The voltage breakdown of device is by the withstand voltage and longitudinal withstand voltage common decision of transverse direction, and transverse direction is withstand voltage can be obtained by increasing drift region length. The longitudinal direction of device is withstand voltage direct ratio, in the thickness of oxygen buried layer and top layer silicon, increases top layer silicon and can cause isolation difficulty, increase oxygen buried layer thickness and can cause heat dissipation problem. Also there is another major issue in silicon-on-insulator power device, the thermal conductivity being exactly silicon-dioxide only has mono-the percent of body silicon, power device relates to high-voltage large current, and therefore during ON state, body silicon device can by substrate by heat away, and silicon-on-insulator substrate is due to the existence of oxygen buried layer, make the very slow of heat dissipation, owing to heat accumulates in body district, it is easy to cause a lot of reliability problem, even can cause metal melting, thoroughly destroy device.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of transverse diffusion metal oxide semiconductor device with part insulation buried regions and making method, electric field can be introduced substrate, electric field is avoided to concentrate, improve the voltage breakdown of device, and can fall apart from substrate by the heat of generation by doping window, accelerate heat dissipation, it is to increase the reliability of device.
In order to solve the problem, the present invention provides a kind of lateral power with part insulation buried regions, the insulation buried regions comprise the support substrates with the first conduction type, being positioned at described support substrates surface and be positioned at the active layer on described insulation buried regions surface; Described active layer comprises grid region, lays respectively at source region and the drain region of both sides, described grid region, and described source region and described drain region have the 2nd conduction type; Described insulation buried regions comprises doping window, and described doping window is positioned at below described drain region, and described doping window is filled with the semiconductor material with the first conduction type; Described support substrates comprises the first buried dopant layer and the 2nd buried dopant layer, described first buried dopant layer is positioned at the lower section in described drain region, described 2nd buried dopant layer is positioned at below described source region, described 2nd buried dopant layer is greater than the distance of described first buried dopant layer to described insulation buried regions to the distance of described insulation buried regions, and described first buried dopant layer and described 2nd buried dopant layer all have the 2nd conduction type.
Can selection of land, described active layer also comprises trap district and drift region, and described trap district is positioned under described grid region, and described trap district has the first conduction type, and described drift region is between described trap district and described drain region, and described drift region has the 2nd conduction type.
Can selection of land, described first conduction type is N-type, and described 2nd conduction type is P type.
Can selection of land, described first conduction type is P type, and described 2nd conduction type is N-type.
Present invention also offers the making method of a kind of lateral power with part insulation buried regions, comprise the steps: to provide a support substrates with the first conduction type; Carry out first time ion implantation on described support substrates surface, form first buried dopant layer with the 2nd conduction type at the region opposite position intending being formed drain region; Carrying out second time ion implantation on described support substrates surface, form the 2nd buried dopant layer with the 2nd conduction type at the region opposite position intending being formed source region, the second time ion implantation degree of depth is greater than the first time ion implantation degree of depth; Support substrates surface opposite position above described 2nd buried dopant layer etches; Formation of deposits insulation buried regions is carried out in described etch areas; Described support substrates is bonded with a device substrate; Subtract thin described device substrate and it is formed with active layer.
Can selection of land, the described making method of lateral power with part insulation buried regions, anneals after being also included in second time ion implantation.
It is an advantage of the current invention that, this device traditional part with insulation buried regions transverse diffusion metal oxide semiconductor device basis on, support substrates adds 2 layers of buried dopant layer and insulation buried regions in formed doping window. The 2 layers of buried dopant layer added and insulation buried regions form the PN knot that doping window defines 3 transoids in support substrates, in order to undertake part longitudinal electric field, and modulate drift region electric field, surface potential is introduced support substrates, surface field can be reduced, avoid the voltage breakdown puncturing, improving device in advance, and, it is possible to fall apart from support substrates by the heat of generation by doping window, accelerate heat dissipation, it is to increase the reliability of device.
Accompanying drawing explanation
Accompanying drawing 1 illustrates the schematic diagram of the lateral power with part insulation buried regions according to embodiment.
Accompanying drawing 2 to accompanying drawing 13 illustrates the process flow sheet of the making method of the lateral power with part insulation buried regions according to embodiment.
Embodiment
Elaborate with the lateral power of part insulation buried regions and the embodiment of making method to provided by the invention below in conjunction with accompanying drawing.
With reference to the schematic diagram shown in accompanying drawing 1 being the lateral power with part insulation buried regions according to this embodiment, comprise P type support substrates 15, it be positioned at the insulation buried regions on described P type support substrates 15 surface and be positioned at the active layer 18 on described insulation buried regions surface; Described active layer 18 comprises grid region 3, lays respectively at source region 2 and the drain region 7 of both sides, described grid region, and described source region 2 and described drain region 7 are N-type doping; Described insulation buried regions comprises buried oxide region 12 and P type window 11, and described P type window 11 is positioned at below described drain region 7; Described P type support substrates comprises: the first n type buried layer 14 and the 2nd n type buried layer 13, described first n type buried layer 14 is positioned at the lower section in described drain region 7, described 2nd n type buried layer 13 is positioned at below described source region 2, and described 2nd n type buried layer 13 is greater than the distance of described first n type buried layer 14 to described insulation buried regions to the distance of described insulation buried regions.
Wherein, described active layer 18 also comprises: field oxide 4, P trap 10, N-type drift region 8, source metal 1, drain metal 6 and gate metal 5, and described P trap 10 is positioned under described grid region 3, and described N-type drift region 8 is between described P trap 10 and described drain region 7.
Wherein, should also comprising P type body zone of action 9 with the lateral power of part insulation buried regions, it is other that described P type body zone of action 9 is positioned at described source region 2, contacts with described P trap 10, for drawing the unnecessary electric charge that P trap 10 is assembled, avoids floater effect.
Principle of work with the lateral power of part insulation buried regions provided by the invention is as follows: when source electrode and grid short circuit, when drain terminal adds voltage, at the horizontal direction of device, the reverse PN of P trap 10 and N-type drift region 8 formation that voltage concentrates on source ties, in the vertical electric field concentrate on P type window 11 formed reverse PN tie, along with the voltage of drain terminal increases, P type support substrates will all exhaust near drain terminal place, electromotive force drops on the first n type buried layer 14, and electromotive force is introduced the P type support substrates 15 below source electrode by the equi-potential formed by the first n type buried layer 14, along with drain voltage increases further, P type support substrates 15 can exhaust gradually, electromotive force is fallen on N-type the 2nd buried regions 13, can by introducing support substrates further for electromotive force. when leaking pressure and increase, 2 layers of P buffer layer and 2 layers of n type buried layer realize fully-depleted. when drift region fully-depleted, device withstand voltage reaches maximum value.
Surface potential is introduced support substrates by the lateral power with part insulation buried regions provided by the invention, surface field can be reduced, avoid the voltage breakdown puncturing, improving device in advance, and, can fall apart from support substrates by the heat of generation by doping window, accelerate heat dissipation, it is to increase with the reliability of the lateral power of part insulation buried regions. It is withstand voltage that this device high pressure part can bear more than 800V under 60 microns of drift region length, and possesses the ON resistance lower than traditional devices, better dispels the heat.
The making method with the partly lateral power of insulation buried regions according to this specific embodiment shown in accompanying drawing 2 to accompanying drawing 13 is below described in detail in detail. The present invention at least comprises the following steps with the making method of the lateral power of part insulation buried regions:
With reference to shown in accompanying drawing 2, it is provided that a P type support substrates 15. In this embodiment. Described semi-conductor is silicon single crystal. In other implementations, described semi-conductor can also be germanium silicon, strained silicon and other compound semiconductors, such as gan or gallium arsenide etc. It can also be the MULTILAYER COMPOSITE substrat structure of above-mentioned and that other are common semiconductor material composition.
With reference to shown in accompanying drawing 3, the surface of described P type support substrates 15 is formed patterned first mask layer 16, forms the first ion implantation window 19; Carry out first time ion implantation by mask of described first mask layer 16, adopt phosphonium ion to inject and form the first n type buried layer 14.
Wherein, it is whole silicon chip carries out evenly blanket type inject that masked ion injects, and the masking film of ion implantation can be SiO2Film, it is also possible to be other films such as photoresist material. Mask mode is production efficiency height for the advantage adulterated, and equipment is relatively simple, and easily, so Application comparison is early, technics comparing is ripe in control.
With reference to shown in accompanying drawing 4, remove the first mask layer 16; The surface of described P support substrates 15 is formed patterned 2nd mask layer 17, forms the 2nd ion implantation window 20; Carry out second time ion implantation by mask of described 2nd mask layer 17, the second time ion implantation degree of depth is greater than the first time ion implantation degree of depth, adopts phosphonium ion to inject and forms the 2nd n type buried layer 13.
With reference to, shown in accompanying drawing 5, removing the 2nd mask layer 17, and anneal, thus form the two buried regions of substrate. Silicon chip owing to adopting ion implantation technique to carry out adulterating can produce lattice damage, is conducive to improving device performance so it carries out annealing so that the impurity of injection proceeds to displacement position to realize electro activation.
With reference to, shown in accompanying drawing 6, above described P type support substrates 15 surface, the 2nd n type buried layer 13, opposite position carries out surface etch, forms P type window 11.
With reference to shown in accompanying drawing 7, at the etching place deposition of silica on described P type support substrates 15 surface, forming oxygen buried layer 12, oxygen buried layer is discontinuous insulation buried regions, contacts with P type window 11.
With reference to, shown in accompanying drawing 8, described P type support substrates 15 and a wafer bonding, subtract thin described silicon chip and be formed with active layer 18.
With reference to shown in accompanying drawing 9, on described active layer 18 surface and be positioned at above the first n type buried layer 14, carry out shallow Doping Phosphorus injection, form N-type drift region 8. Utilize repeatedly ion implantation mode that the surperficial part ion except N-type drift region 8 of described active layer 18 is injected boron, form P trap 10.
With reference to shown in accompanying drawing 10, at described active layer 18 surface growth field oxide 4, and depositing polysilicon, doping form polysilicon gate material on gate oxide material, and on P trap 10, grid region 3 is produced in one end of close N-type drift region 8.
With reference to shown in accompanying drawing 11, above described 2nd n type buried layer 13, by ion implantation organizer zone of action 9 and source region 2 on P trap 10.
With reference to shown in accompanying drawing 12, above described first n type buried layer 14, by ion implantation formation drain region, one end 7 away from grid region in N-type drift region 8, thus complete the making of active layer 18.
Wherein, making P trap 10, grid region 3, source region 2, body zone of action 9 and drain region 7 and adopt the conventional semiconductor technology such as ion implantation, etching, the present embodiment is only a kind of preferred step method, can also have other change when specifically making.
With reference to, shown in accompanying drawing 13, covering field oxide at active layer 18 upper surface. Described field oxide etches window, and carve the contact hole in source region 2, drain region 7 and grid region 3, then depositing metal and etch, form the source metal 1 of LDMOS transistor, drain metal 6 and gate metal 5, finally, deposit silicon nitride, generates passivation layer.
In sum, instant invention overcomes the problems such as electric field is concentrated, heat dissipation is slow of traditional transverse diffusion metal oxide semiconductor device with part insulation buried regions, on the basis of traditional devices, support substrates adds 2 layers of buried dopant layer and in insulation buried regions, forms doping window. The 2 layers of buried dopant layer added and insulation buried regions form the PN knot that doping window defines 3 transoids in support substrates, in order to undertake part longitudinal electric field, and modulate drift region electric field, surface potential is introduced support substrates, surface field can be reduced, avoid the voltage breakdown puncturing, improving device in advance, and, it is possible to fall apart from support substrates by the heat of generation by doping window, accelerate heat dissipation, it is to increase with the reliability of the lateral power of part insulation buried regions.
The above is only the preferred embodiment of the present invention; it is noted that for those skilled in the art, under the premise without departing from the principles of the invention; can also making some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1. with a lateral power for part insulation buried regions, the insulation buried regions comprise the support substrates with the first conduction type, being positioned at described support substrates surface and be positioned at the active layer on described insulation buried regions surface;
Described active layer comprises grid region, lays respectively at source region and the drain region of both sides, described grid region, and described source region and described drain region have the 2nd conduction type;
It is characterized in that, described insulation buried regions comprises doping window, and described doping window is positioned at below described drain region, and described doping window is filled with the semiconductor material with the first conduction type;
Described support substrates comprises the first buried dopant layer and the 2nd buried dopant layer, described first buried dopant layer is positioned at the lower section in described drain region, described 2nd buried dopant layer is positioned at below described source region, described 2nd buried dopant layer is greater than the distance of described first buried dopant layer to described insulation buried regions to the distance of described insulation buried regions, and described first buried dopant layer and described 2nd buried dopant layer all have the 2nd conduction type.
2. the lateral power with part insulation buried regions according to claim 1, it is characterised in that, described active layer also comprises trap district and drift region; Described trap district is positioned under described grid region, and described trap district has the first conduction type; Described drift region is between described trap district and described drain region, and described drift region has the 2nd conduction type.
3. the lateral power with part insulation buried regions according to claim 1, it is characterised in that, described first conduction type is N-type, and described 2nd conduction type is P type.
4. the lateral power with part insulation buried regions according to claim 1, it is characterised in that, described first conduction type is P type, and described 2nd conduction type is N-type.
5. the making method with the lateral power of part insulation buried regions, it is characterised in that, comprise the steps:
Offer one has the support substrates of the first conduction type;
Carry out first time ion implantation on described support substrates surface, form first buried dopant layer with the 2nd conduction type at the region opposite position intending being formed drain region;
Carrying out second time ion implantation on described support substrates surface, form the 2nd buried dopant layer with the 2nd conduction type at the region opposite position intending being formed source region, the second time ion implantation degree of depth is greater than the first time ion implantation degree of depth;
Support substrates surface opposite position above described 2nd buried dopant layer etches;
Formation of deposits insulation buried regions is carried out in etch areas;
The surface of the side that described support substrates has insulation buried regions is bonded with a device substrate;
Described device substrate subtracts and thin is formed with active layer.
6. the making method of the lateral power with part insulation buried regions according to claim 5, it is characterised in that, anneal after being also included in second time ion implantation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310744626.9A CN103745996B (en) | 2013-12-31 | 2013-12-31 | With lateral power and the making method of part insulation buried regions |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310744626.9A CN103745996B (en) | 2013-12-31 | 2013-12-31 | With lateral power and the making method of part insulation buried regions |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103745996A CN103745996A (en) | 2014-04-23 |
| CN103745996B true CN103745996B (en) | 2016-06-01 |
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| CN113270480B (en) * | 2021-05-19 | 2023-01-31 | 济南大学 | Gallium nitride power device and preparation method thereof |
| CN115911100B (en) * | 2023-03-02 | 2023-05-16 | 北京智芯微电子科技有限公司 | Lateral double-diffusion field effect transistor, manufacturing method, chip and circuit |
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| CN101488525A (en) * | 2009-02-27 | 2009-07-22 | 东南大学 | P type SOI lateral double-diffused metal-oxide semiconductor transistor |
| CN102201445A (en) * | 2011-04-14 | 2011-09-28 | 中北大学 | Partial silicon on insulator (PSOI) lateral super-junction power semiconductor device |
| CN102637744A (en) * | 2012-05-08 | 2012-08-15 | 中北大学 | Signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device |
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| CN101916728B (en) * | 2010-07-20 | 2012-05-30 | 中国科学院上海微系统与信息技术研究所 | Manufacture technology of superstructure LDMOS structure on SOI capable of completely eliminating substrate-assisted depletion effect |
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| CN101488525A (en) * | 2009-02-27 | 2009-07-22 | 东南大学 | P type SOI lateral double-diffused metal-oxide semiconductor transistor |
| CN102201445A (en) * | 2011-04-14 | 2011-09-28 | 中北大学 | Partial silicon on insulator (PSOI) lateral super-junction power semiconductor device |
| CN102637744A (en) * | 2012-05-08 | 2012-08-15 | 中北大学 | Signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device |
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