CN107248533B - Silicon carbide VDMOS device and manufacturing method thereof - Google Patents
Silicon carbide VDMOS device and manufacturing method thereof Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The invention discloses a silicon carbide VDMOS device and a manufacturing method thereof, and belongs to the technical field of power semiconductors. According to the invention, the polycrystalline silicon layer is directly deposited on the surface of the JFET area of the silicon carbide VDMOS device to form the Si/SiC heterojunction, and then a diode is integrated in the device, so that the application of the device in the fields of inverter circuits, chopper circuits and the like is optimized. Compared with the prior art in which a VDMOS parasitic silicon carbide diode is directly adopted, the direct conduction is easier to realize, and the power loss is lower, the working speed is higher and the working efficiency is higher; compared with the prior art that an FRD is connected in anti-parallel outside the device, the invention reduces the using number of the device, reduces the connecting lines among the devices and is beneficial to the miniaturization development of the device; in addition, the invention reduces the gate width, reduces the gate capacitance and further improves the working speed of the device. Therefore, the VDMOS device provided by the invention has wide application prospect in the field of circuits such as inverter circuits, chopper circuits and the like.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a silicon carbide VDMOS device and a manufacturing method thereof.
Background
Since the 21 st century of human beings, the energy problem has been increasingly highlighted. At present, the demand for energy conservation and emission reduction is rising, the problem of electric energy conversion from small to household appliances and electric vehicles to large to industrial production and locomotive traction is very important, and scientific research personnel in the field of power electronics are very critical to the optimization and improvement of a power management system.
Power devices are the core of modern power systems. Because the performance of the traditional silicon-based power device is very close to the limit of silicon materials, the performance of the traditional silicon-based power device is difficult to be greatly improved. Therefore, some wide bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) have more attractive and excellent properties than silicon materials, so that the research on the silicon carbide and gallium nitride materials becomes a new hot spot of power devices.
Silicon carbide VDMOS devices are a new generation of semiconductor devices fabricated using the wide bandgap semiconductor material silicon carbide. Compared with silicon materials, the silicon carbide material has larger forbidden band width, high thermal conductivity, high electronic saturation drift velocity and high critical breakdown electric field, so that the silicon carbide material has very wide application prospect in the power application fields of high temperature, high pressure, strong radiation and high power.
Silicon carbide VDMOS devices have such excellent characteristics, and thus are widely used in circuits such as inverter circuits and chopper circuits. Silicon carbide VDMOS devices generally need to function together with an anti-parallel diode in circuit applications such as traditional inverter circuits and chopper circuits, and generally have the following two modes: the method comprises the following steps: the device Pbase, the N-region and the N + substrate are used directly to form a parasitic PIN diode. However, the parasitic silicon carbide diode obtained in this way has a large conduction voltage drop (the conduction voltage drop of the silicon carbide PN junction is about 3V), and has poor reverse recovery characteristics (a large amount of excess carriers are injected by drift region conductance modulation during forward conduction), resulting in high power loss, which is contrary to the application concept of emphasizing green environmental protection; meanwhile, the low working efficiency is caused by the low working speed, which is very unfavorable for the application of the silicon carbide VDMOS device in an inverter circuit, a chopper circuit and the like; the second is as follows: the device is used in anti-parallel with an external Fast Recovery Diode (FRD). However, this method may cause an increase in system cost, an increase in volume, and a decrease in reliability due to an increase in metal wiring, and finally, the popularization of the silicon carbide VDMOS device in circuit applications such as a conventional inverter circuit and a chopper circuit is hindered to some extent.
In summary, how to implement the silicon carbide VDMOS device to be widely applied to circuits such as inverter circuits and chopper circuits, and solve the problems of high power loss, low working efficiency, high system cost, and the like in the existing applications, is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In order to solve the problems in the prior art, the invention directly deposits the polysilicon layer on the surface of the JFET area of the silicon carbide VDMOS device, so that the polysilicon layer and the surface of the JFET area of the silicon carbide form a Si/SiC heterojunction.
In order to achieve the above purpose, on one hand, the invention discloses a technical scheme of a silicon carbide VDMOS device, which comprises the following specific technical scheme:
the technical scheme 1:
a silicon carbide VDMOS device, the cell structure of which comprises: metal drain electrodes 10, N arranged in sequence from bottom to top+Substrate 9 and N-An epitaxial layer 8; said N is-One end of the upper layer of the epitaxial layer 8 is provided with a first Pbase area 7, and N is-The other end of the upper layer of the epitaxial layer 8 is provided with a second Pbase area 71; the first Pbase region 7 has mutually independent first N+Source region 6 and first P+A contact zone 5; the second Pbase region 71 has second N independent of each other+Source region 61 and second P+A contact region 51; the first P+Contact region 5 and part of the first N+The upper surface of the source region 6 is provided with a first metal source electrode 3; the second P+Contact region 51 and part of the second N+The upper surface of the source region 61 has a second metal source electrode 31; the method is characterized in that: on the upper surface of the first Pbase region 7, on the upper surface of the first N + source region 6 and N-The upper surface of part of the epitaxial layer 8 is also provided with a first grid structure contacted with the upper surface; the first grid structure comprises a first grid dielectric layer 4, a first polysilicon grid 2 positioned on the upper surface of the first grid dielectric layer 4 and a first grid electrode 1 positioned on the upper surface of the first polysilicon grid 2; on the upper surface of the second Pbase region 71, on the upper surface of the second N + source region 61 and on N-The upper surface of part of the epitaxial layer 8 is also provided with a second gate structure contacted with the upper surface; the second gate structure comprises a second gate dielectric layer 41, a second polysilicon gate 21 positioned on the upper surface of the second gate dielectric layer 41, and a second gate electrode 11 positioned on the upper surface of the second polysilicon gate 21; the upper surface of the JFET area between the first gate structure and the second gate structure is also provided with N- Epitaxial layer 8 forms P of Si/SiC heterojunction+A polysilicon layer 12; the P is+The upper surface of the polysilicon layer 12 has a metal electrode 13, P+The polysilicon layer 12 and the metal electrode 13 are respectively connected with the first metal source electrode 3 and the second metal source electrode 31; between the metal structures and P+The polysilicon layer 12 is separated from the two polysilicon gates 2, 21 by a dielectric.
The technical scheme 2 is as follows:
a silicon carbide VDMOS device, the cell structure of which comprises: metal drain electrodes 10, N arranged in sequence from bottom to top+Substrate 9 and N-An epitaxial layer 8; said N is-One end of the upper layer of the epitaxial layer 8 is provided with a first Pbase area 7, and N is-The other end of the upper layer of the epitaxial layer 8 is provided with a second Pbase area 71; the first Pbase region 7 has mutually independent first N+Source region 6 and first P+A contact zone 5; the second Pbase region 71 has second N independent of each other+Source region 61 and second P+A contact region 51; the first P+Contact region 5 and part of the first N+The upper surface of the source region 6 is provided with a first metal source electrode 3; the second P+Contact region 51 and part of the second N+The upper surface of the source region 61 has a second metal source electrode 31; the method is characterized in that: on the upper surface of the first Pbase region 7, on the upper surface of the first N + source region 6 and N-The upper surface of part of the epitaxial layer 8 is also provided with a first grid structure contacted with the upper surface; the first grid structure comprises a first grid dielectric layer 4, a first polysilicon grid 2 positioned on the upper surface of the first grid dielectric layer 4 and a first grid electrode 1 positioned on the upper surface of the first polysilicon grid 2; on the upper surface of the second Pbase region 71, on the upper surface of the second N + source region 61 and on N-The upper surface of part of the epitaxial layer 8 is also provided with a second gate structure contacted with the upper surface; the second gate structure comprises a second gate dielectric layer 41, a second polysilicon gate 21 positioned on the upper surface of the second gate dielectric layer 41, and a second gate electrode 11 positioned on the upper surface of the second polysilicon gate 21; the upper surface of the JFET area between the first gate structure and the second gate structure is also provided with N- Epitaxial layer 8 forms P of Si/SiC heterojunction+A polysilicon layer 12; p+A first dielectric layer 14 and a second dielectric layer 15 which are independent of each other are arranged in the polysilicon layer 12, and the two dielectric layers 14 and 15 are both connected with N-The epitaxial layers 8 are in contact; the P is+The upper surface of the polysilicon layer 12 has a metal electrode 13, P+The polysilicon layer 12 and the metal electrode 13 are respectively connected with the first metal source electrode 3 and the second metal source electrode 31; between the metal structures and P+The polysilicon layer 12 is separated from the two polysilicon gates 2, 21 by a dielectric.
The invention adds technical characteristics on the basis of the technical scheme 1, namely P+The polysilicon layer 12 is also provided with N and N independently-A first dielectric layer 14 and a second dielectric layer 15 in contact with the epitaxial layer 8; when the diode is applied, the first dielectric layer 14 and the second dielectric layer 15 are in P+The electron accumulation layer formed below the polysilicon layer 12 can further reduce the drift region resistance of the device, thereby reducing the forward conduction voltage drop of the device.
Technical scheme 3:
a silicon carbide VDMOS device, the cell structure of which comprises: metal drain electrodes 10, N arranged in sequence from bottom to top+Substrate 9 and N-An epitaxial layer 8; said N is-One end of the upper layer of the epitaxial layer 8 is provided with a first Pbase area 7, and N is-The other end of the upper layer of the epitaxial layer 8 is provided with a second Pbase area 71; the first Pbase region 7 has mutually independent first N+Source region 6 and first P+A contact zone 5; the second Pbase region 71 has second N independent of each other+Source region 61 and second P+A contact region 51; the first P+Contact region 5 and part of the first N+The upper surface of the source region 6 is provided with a first metal source electrode 3; the second P+Contact region 51 and part of the second N+The upper surface of the source region 61 has a second metal source electrode 31; the method is characterized in that: in N-The epitaxial layer 8 and the first Pbase region 7 have a first P-type silicon carbide region 16 with a super junction or semi-super junction structure formed therein, and N is-A second P-type silicon carbide region 161 forming a super junction or semi-super junction structure is further arranged in the epitaxial layer 8 and below the second Pbase region 71; on the upper surface of the first Pbase region 7, on the upper surface of the first N + source region 6 and N-The upper surface of part of the epitaxial layer 8 is also provided with a first grid structure contacted with the upper surface; the first gate junctionThe structure comprises a first gate dielectric layer 4, a first polysilicon gate 2 positioned on the upper surface of the first gate dielectric layer 4 and a first gate electrode 1 positioned on the upper surface of the first polysilicon gate 2; on the upper surface of the second Pbase region 71, on the upper surface of the second N + source region 61 and on N-The upper surface of part of the epitaxial layer 8 is also provided with a second gate structure contacted with the upper surface; the second gate structure comprises a second gate dielectric layer 41, a second polysilicon gate 21 positioned on the upper surface of the second gate dielectric layer 41, and a second gate electrode 11 positioned on the upper surface of the second polysilicon gate 21; the upper surface of the JFET area between the first gate structure and the second gate structure is also provided with N- Epitaxial layer 8 forms P of Si/SiC heterojunction+A polysilicon layer 12; the P is+The upper surface of the polysilicon layer 12 has a metal electrode 13, P+The polysilicon layer 12 and the metal electrode 13 are respectively connected with the first metal source electrode 3 and the second metal source electrode 31; between the metal structures and P+The polysilicon layer 12 is separated from the two polysilicon gates 2, 21 by a dielectric.
The invention adds the technical characteristics on the basis of the technical scheme 1, namely N-The epitaxial layer 8 and the first Pbase region 7 have a first P-type silicon carbide region 16 with a super junction or semi-super junction structure formed therein, and N is-A second P-type silicon carbide region 161 forming a super junction or semi-super junction structure is further arranged in the epitaxial layer 8 and below the second Pbase region 71; the super junction or semi-super junction structure can further reduce the drift region resistance of the device when the diode and the MOS are applied, and further reduce the forward conduction voltage drop of the device.
The technical scheme 4 is as follows:
a silicon carbide VDMOS device, the cell structure of which comprises: metal drain electrodes 10, N arranged in sequence from bottom to top+Substrate 9 and N-An epitaxial layer 8; said N is-One end of the upper layer of the epitaxial layer 8 is provided with a first Pbase area 7, and N is-The other end of the upper layer of the epitaxial layer 8 is provided with a second Pbase area 71; the first Pbase region 7 has mutually independent first N+Source region 6 and first P+A contact zone 5; the second Pbase region 71 has second N independent of each other+Source region 61 and second P+A contact region 51; the first P+Contact region 5 and part of the first N+The upper surface of the source region 6 is provided with a first metal source electrode 3; the second P+Contact region 51 and part of the second N+The upper surface of the source region 61 has a second metal source electrode 31; the method is characterized in that: in N-The epitaxial layer 8 and the first Pbase region 7 have a first P-type silicon carbide region 16 with a super junction or semi-super junction structure formed therein, and N is-A second P-type silicon carbide region 161 forming a super junction or semi-super junction structure is further arranged in the epitaxial layer 8 and below the second Pbase region 71; on the upper surface of the first Pbase region 7, on the upper surface of the first N + source region 6 and N-The upper surface of part of the epitaxial layer 8 is also provided with a first grid structure contacted with the upper surface; the first grid structure comprises a first grid dielectric layer 4, a first polysilicon grid 2 positioned on the upper surface of the first grid dielectric layer 4 and a first grid electrode 1 positioned on the upper surface of the first polysilicon grid 2; on the upper surface of the second Pbase region 71, on the upper surface of the second N + source region 61 and on N-The upper surface of part of the epitaxial layer 8 is also provided with a second gate structure contacted with the upper surface; the second gate structure comprises a second gate dielectric layer 41, a second polysilicon gate 21 positioned on the upper surface of the second gate dielectric layer 41, and a second gate electrode 11 positioned on the upper surface of the second polysilicon gate 21; the upper surface of the JFET area between the first gate structure and the second gate structure is also provided with N- Epitaxial layer 8 forms P of Si/SiC heterojunction+A polysilicon layer 12; p+A first dielectric layer 14 and a second dielectric layer 15 which are independent of each other are arranged in the polysilicon layer 12, and the two dielectric layers 14 and 15 are both connected with N-The epitaxial layers 8 are in contact; the P is+The upper surface of the polysilicon layer 12 has a metal electrode 13, P+The polysilicon layer 12 and the metal electrode 13 are respectively connected with the first metal source electrode 3 and the second metal source electrode 31; between the metal structures and P+The polysilicon layer 12 is separated from the two polysilicon gates 2, 21 by a dielectric.
The invention adds technical characteristics on the basis of the technical scheme 1, namely P+The polysilicon layer 12 is also provided with N and N independently-A first dielectric layer 14 and a second dielectric layer 15 in contact with the epitaxial layer 8 and in contact with the epitaxial layer-Within the epitaxial layer 8 and below the two Pbase regions 7, 71, respectivelyThe semiconductor device also has P-type silicon carbide regions 16, 161 forming a super junction or semi-super junction structure; according to the technical scheme, the drift region resistance of the device is further reduced through the technical means, and the forward conduction voltage drop of the device is further reduced.
On the other hand, the invention discloses a technical scheme of the manufacturing method of the technical scheme, and the specific technical scheme is as follows:
the technical scheme 5 is as follows:
a manufacturing method of a silicon carbide VDMOS device is characterized by comprising the following steps:
the first step is as follows: by epitaxial process on silicon carbide N+The upper surface of the substrate 9 is made of N-An epitaxial layer 8;
the second step is that: by photolithography and ion implantation, in N-Injecting P-type semiconductor impurities into one end of the upper layer of the epitaxial layer 8 to form a first Pbase region 7 in N-Injecting P-type semiconductor impurities into the other end of the upper layer of the epitaxial layer 8 to form a second Pbase region 71;
the third step: implanting P-type semiconductor impurities into the upper layer of the first Pbase region 7 by photolithography and ion implantation to form a first P+A contact region 5 formed by implanting P-type semiconductor impurities on the upper layer of the second Pbase region 71 to form a second P+A contact region 51;
the fourth step: implanting N-type semiconductor impurity into the upper layer of the first Pbase region 7 by photolithography and ion implantation to form a first N+A source region 6, wherein N-type semiconductor impurities are injected into the upper layer of the second Pbase region 71 to form a second N + source region 61; the first P + contact region 5 and the first N + source region 6 are independent of each other, and the second P + contact region 51 and the second N + source region 61 are independent of each other; then activating the injected impurities by high-temperature annealing;
the fifth step: growing a gate dielectric layer on the upper surface of the device by adopting deposition and etching processes, etching to remove a part of the gate dielectric layer above the middle position of the JFET area to form a window, and depositing P on the upper surface of the device+Etching the polysilicon layer to remove the redundant polysilicon layer and redundant gate dielectric layer to obtain a first gate dielectric layer 4, a second gate dielectric layer 41, a first polysilicon gate 2, a second polysilicon gate 21 and a P+ A polysilicon layer 12, wherein: the first grid mediumThe layer 4 is on the upper surface of the first Pbase region 7, and has left and right sides respectively corresponding to the first N+Source region 6 has a portion of its upper surface and N-The upper surface of part of the epitaxial layer 8 is contacted, the first polysilicon gate 2 is arranged on the upper surface of the first gate dielectric layer 4, the second gate dielectric layer 41 is arranged on the upper surface of the second Pbase region 71, and the left side and the right side of the second gate dielectric layer are respectively contacted with the first N+Source region 6 has a portion of its upper surface and N-Part of the upper surface of the epitaxial layer 8 is contacted, and the second polysilicon gate 21 is arranged on the upper surface of the second gate dielectric layer 41, P+The polysilicon layer 12 is positioned between the first gate dielectric layer 4 and the second gate dielectric layer 41;
and a sixth step: using metal deposition and etching process at the first N+Source region 6 and first P+Generating a first metal source electrode 3 on the upper surface of the contact region 5; at the second N+Source region 61 and second P+Generating a second metal source electrode 31 on the upper surface of the contact region 51; forming a first gate electrode 1 on the upper surface of the first polysilicon gate 2; forming a second gate electrode 11 on the upper surface of the second polysilicon gate 21; thinning and depositing metal on the back of the device to form a drain electrode 10; at P+ A metal electrode 13 is formed on the upper surface of the polysilicon region 12; the metal electrode 13 is respectively connected with the first metal electrode 3 and the second metal source electrode 31; thus obtaining the silicon carbide VDMOS device.
Further, the method also comprises the following steps before the sixth step of the process: dielectric isolation is adopted between the metal structures and between the P + polysilicon region 12 and the two polysilicon gates 2 and 21 through dielectric deposition and etching processes.
Further, the process for manufacturing the silicon carbide VDMOS device according to claim 2 is substantially the same as the process disclosed in claim 5 of the present invention, and the main difference is that: in the fifth step, the remained P is etched away by changing the dimension of the layout when the unnecessary polysilicon layer and the gate dielectric layer below the unnecessary polysilicon layer are etched away+The size of the polysilicon region 12 is larger than that of the window formed by etching the gate dielectric layer, namely, the size of the window is larger than that of the window formed by etching the gate dielectric layer+The polysilicon layer 12 has N and N on its two sides-A first dielectric layer 14 and a second dielectric layer 15 in contact with the epitaxial layer 8. The materials of the first dielectric layer and the second dielectric layer in the present invention are not limited to the materials of the gate dielectric layer, and are usually selected by those skilled in the artIn other words, the dielectric layer of other materials can be formed by using the existing deposition and etching processes.
Further, the process for manufacturing the silicon carbide VDMOS device according to claim 3 is basically the same as the process disclosed in claim 5 of the present invention, and the main differences are as follows: a super junction or semi-super junction structure is formed in the N-epitaxial layer 8 by a multi-step photolithography and ion implantation process, and the manufacturing process of the super junction or semi-super junction structure is already the prior art and is not described herein again.
In addition, the technical scheme provided by the invention is not only suitable for the silicon carbide VDMOS device, but also suitable for the silicon carbide RC-IGBT device, and the RC-IGBT device uses N of the silicon carbide VDMOS device+The substrate 9 is replaced by a P-type collector region (17) and an N-type collector region (18) which are arranged in parallel; further, in N-An N-type Field Stop (FS) layer (19) can be arranged between the epitaxial layer (8) and the P-type collector region (17) and the N-type collector region (18).
As will be appreciated by one of ordinary skill in the art: in the structure of the silicon carbide power VDMOS device, acceptor ions and donor ions in each structure can be interchanged, and according to the technical means of the invention, a substrate and an epitaxial layer can be made of N-type semiconductor materials, and the doping type of a polysilicon layer which is additionally arranged correspondingly is P-type; the substrate and the epitaxial layer can be made of P-type semiconductor materials, and the doping type of the polysilicon layer added correspondingly in the invention is N-type. In addition, according to knowledge of heterojunction physics, by adjusting the doping concentrations of the epitaxial layer and the polycrystalline silicon layer, when the substrate and the epitaxial layer are made of N-type semiconductor materials, the doping type of the polycrystalline silicon layer can also be N-type, and when the substrate and the epitaxial layer are made of P-type semiconductor materials, the doping type of the polycrystalline silicon layer can also be P-type.
The gate dielectric layer and dielectric layer material used in the present invention may be silicon dioxide (SiO)2) But may be any suitable material, such as: silicon nitride (Si)3N4) Hafnium oxide (H)fO2) Aluminum oxide (Al)2O3) And high-K dielectric materials.
The working principle of the invention is explained as follows:
in application of an inverter circuit, a chopper circuit and the like, a power VDMOS device generally needs to be connected with a diode in an anti-parallel manner, and the power VDMOS device can be realized by the following two methods:
1) directly using its parasitic PIN diode, i.e. Pbase region, N-Drift region and N+A PIN diode formed in the substrate. As is known to those of ordinary skill in the art: the PN junction conduction voltage drop of the silicon carbide PIN diode is about 3V, high power loss and low working speed are caused by high conduction voltage drop, the VDMOS device is not favorable for application in an inverter circuit, a chopper circuit and the like, and in addition, the problem of poor reverse recovery characteristic is easily caused by directly utilizing a parasitic silicon carbide diode;
2) anti-parallel with a Fast Recovery Diode (FRD). This method can improve the characteristics of the diode to some extent, but has disadvantages such as high production cost, large system volume, and low reliability.
In the structure, a layer of polycrystalline silicon is deposited on the surface of a JFET area of a silicon carbide VDMOS device, and a heterojunction is formed by P-type (N-type) Si in the P-type (N-type) polycrystalline silicon and N-type (P-type) SiC in the surface of the silicon carbide JFET area to integrate a diode in the device. On one hand, the junction voltage drop of the heterojunction formed by the P-type polycrystalline silicon and the N-type silicon carbide or the N-type polycrystalline silicon and the P-type silicon carbide is about 1V, and compared with the junction voltage drop of a parasitic silicon carbide PN junction which is about 3V, the heterojunction formed by the P-type polycrystalline silicon and the N-type silicon carbide can be conducted under lower voltage drop, so that the diode is integrated in the device through the technical means of the invention, and the device has the advantage of low conduction voltage drop in practical application. On the other hand, the P-type polycrystalline silicon and the N-type silicon carbide form a heterojunction, when the diode is conducted in the forward direction, the heterojunction only conducts electrons and does not inject holes, and the conduction mode when the diode is applied is multi-photon conduction (the heterojunction formed by the method can be considered to have no injection of minority carriers when the diode is conducted in the forward direction), so that the reverse recovery time is short, and the reverse recovery charge is less, therefore, the diode has good reverse recovery characteristics; at the time of reverse voltage resistance, the heterojunction has an electron barrier height of about 1.5eV, and the first Pbase region 7 and the second Pbase region 71 provide an electric field shielding effect, so that the device structure disclosed by the invention has the same voltage blocking capability and low reverse leakage as the conventional VDMOS device. Meanwhile, when the VDMOS device is in a working mode, due to the introduction of the P-type polycrystalline silicon structure connecting the surface of the JFET area of the device and the source electrode, the grid width of the surface of the JFET area of the VDMOS device is reduced, the grid capacitance and the grid charge are reduced, the switching speed of the VDMOS device is improved on the basis of not influencing other characteristics of the VDMOS device, and the requirement on a driving circuit is reduced.
The invention has the beneficial effects that:
the invention provides a method for depositing polycrystalline silicon on the surface of a JFET area of a silicon carbide VDMOS device to enable the polycrystalline silicon and an epitaxial layer to form a heterojunction, and the technical means can have remarkable effects on improving the performance of the device:
(1) compared with a VDMOS parasitic silicon carbide diode which is directly used, the silicon carbide VDMOS device reduces forward conduction voltage drop through a technical means of integrating the diode in the device, so that forward conduction is easier to realize in electric energy conversion application such as an inverter circuit and a chopper circuit, and the silicon carbide VDMOS device has lower power loss and higher working efficiency.
(2) The invention provides a method for converting the conduction mode of a device structure from bipolar conduction (conductance modulation) of a silicon carbide parasitic diode into multi-photon conduction when the diode is applied, so that the device has the characteristics of short reverse recovery time, less reverse recovery charge and higher switching speed in the application of electric energy conversion such as an inverter circuit, a chopper circuit and the like.
(3) Compared with the application mode of reversely connecting a Fast Recovery Diode (FRD) in parallel outside the silicon carbide VDMOS device, the silicon carbide VDMOS device provided by the invention directly integrates a diode inside the device for use, reduces the using number of the device, reduces the connecting lines among the devices, and has the advantages of low production cost, high reliability of the device and small system volume.
(4) According to the silicon carbide VDMOS device, due to the fact that the heterojunction has the electron barrier height of about 1.5eV and the electric field shielding effect provided by the first Pbase region 7 and the second Pbase region 71, the structure has the same voltage blocking capability and low reverse leakage as a traditional VDMOS device when the device is in reverse voltage withstanding.
(5) According to the silicon carbide VDMOS device, the grid width and the grid charge of the surface of the JFET area are reduced, the switching speed of the VDMOS device is further improved on the basis of not influencing other characteristics of the VDMOS device, and the requirement on a driving circuit is reduced.
Drawings
FIG. 1 is a schematic diagram of a conventional silicon carbide VDMOS device cell structure;
FIG. 2 is a schematic diagram of a basic cell structure of a silicon carbide VDMOS device provided by the invention;
FIG. 3 is a schematic diagram of a first derivative structure of a basic cell structure of a silicon carbide VDMOS device according to the present invention;
FIG. 4 is a schematic diagram of a second derivative of the basic cell structure of a silicon carbide VDMOS device according to the present invention;
FIG. 5 is a schematic structural diagram of a silicon carbide VDMOS device fabricated by a method of the present invention after forming an N-silicon carbide epitaxial layer on a silicon carbide N + substrate;
FIG. 6 is a schematic structural diagram of a silicon carbide VDMOS device after a Pbase region is formed on a silicon carbide N-epitaxial layer by photolithography and ion implantation according to a method for fabricating a silicon carbide VDMOS device provided by the present invention;
FIG. 7 shows a method for forming a silicon carbide VDMOS device by photolithography and ion implantation in a Pbase region of silicon carbide to form a silicon carbide P+A schematic structure diagram behind the base region;
FIG. 8 is a schematic view of a method for forming a silicon carbide VDMOS device in a Pbase region of silicon carbide by photolithography and ion implantation to form N-type silicon carbide+A schematic structure diagram behind the source region;
FIG. 9 is a schematic structural diagram of a silicon carbide VDMOS device manufactured by the method of the present invention after a gate dielectric layer is formed on the surface of the device, and a P + polysilicon contact area window is formed by etching away a portion of the gate dielectric layer in the middle above the JFET;
FIG. 10 is a schematic structural diagram of a silicon carbide VDMOS device after a P + polysilicon layer is deposited on the surface of the device according to a method for manufacturing the silicon carbide VDMOS device;
FIG. 11 is a schematic structural diagram of a silicon carbide VDMOS device fabricated by a method according to the present invention after etching an unwanted polysilicon layer and an underlying gate dielectric layer on the surface of the device;
FIG. 12 is a schematic diagram of a silicon carbide VDMOS device fabrication method after metal contact formation;
in the figure: 1 is a first gate electrode, 11 is a second gate electrode, 2 is a first polysilicon gate, 21 is a second polysilicon gate, 3 is a first source electrode, 31 is a second source electrode, 4 is a first gate dielectric layer, 41 is a second gate dielectric layer, and 5 is a first P+Contact region, 51 is the second P+Contact region, 6 is the first N+Source region, 61 is the second N+A source region, 7 is a first Pbase region, 71 is a second Pbase region, and 8 is N-Epitaxial layer, 9 is N+Substrate, 10 drain electrode, 12P+The polysilicon layer 13 is a metal electrode, 14 is a first dielectric layer, 15 is a second dielectric layer, 16 is a first P-type silicon carbide region, and 161 is a second P-type silicon carbide region.
Detailed Description
The following describes the technical solution of the present invention in detail by taking a 1700V silicon carbide VDMOS device as an example, and further illustrates the principle and characteristics of the present invention in conjunction with the drawings of the specification. The present embodiment is provided only for explaining the present invention, and is not intended to limit the scope of the present invention.
Example 1:
the silicon carbide VDMOS device provided by the invention has a basic structure of which a cellular structure is shown in figure 2, and comprises a metal drain electrode 10 with the thickness of about 0.5-6 mu m and the doping concentration of 1 × 10 which are sequentially arranged from bottom to top18cm-3～1×1019cm-3N with a thickness of 50 to 200 μm+A substrate 9 with a thickness of 15-18 μm and a doping concentration of about 1 × 1015cm-3～5×1016cm-3N of (A)-An epitaxial layer 8, and a doping concentration of 1 × 10 above the N-epitaxial layer 817～7×1017cm-3A first Pbase region 7 implanted to a depth of about 0.5 to 1 μm, the other end of the upper layer having the same parametersSaid first Pbase region 7 having a doping concentration of 1 × 10 independent of each other19～1×1020cm-3A first N with an implantation depth of about 0.3 to 0.5 μm+Source region 6 and doping concentration of about 3 × 1019～1×1020cm-3A first P with an implantation depth of about 0.3-0.5 μm+Contact region 5, said second Pbase region 71 having a doping concentration of about 1 × 10 independent of each other19～1×1020cm-3A second N + source region 61 with an implantation depth of about 0.3-0.5 μm and a doping concentration of about 3 × 1019～1×1020cm-3A second P with an implantation depth of about 0.3-0.5 μm+A contact region 51; the first P+Contact region 5 and part of the first N+The upper surface of the source region 6 is provided with a first metal source electrode 3 with the thickness of about 1-6 mu m; the second P+Contact region 51 and part of the second N+The upper surface of the source region 61 is provided with a second metal source electrode 31 with the thickness of about 1-6 mu m; the method is characterized in that: the upper surface of the first Pbase region 7 and a first N+Source regions 6 and N-Part of the upper surface of the epitaxial layer 8 is also provided with a first gate structure, and the first gate structure is respectively connected with the first N on the left side and the right side of the first Pbase region 7+Source regions 6 and N-The surfaces of the epitaxial layers 8 are contacted, and the first grid structure consists of a first grid oxide layer 4, a first polysilicon grid 2 positioned above the first grid oxide layer 4 and a grid electrode 1 positioned on the upper surface of the first polysilicon grid 2; the upper surface of the second Pbase region 71, and the N-epitaxial layer 8 and the second N+A second gate structure is further arranged on part of the upper surface of the source region 61, and the second gate structure is respectively connected with the N-epitaxial layer 8 and the second N-epitaxial layer at the left side and the right side of the second Pbase region 71+The surfaces of the source regions 61 are contacted, the second gate structure is composed of a second gate oxide layer 41, a second polysilicon gate 21 positioned on the upper surface of the second gate oxide layer 41 and a gate electrode 11 positioned on the upper surface of the second polysilicon gate 21, the thicknesses of the gate oxide layers 4 and 41 are 0.02-0.2 mu m, the thicknesses of the polysilicon gates 2 and 21 are 0.3-1 mu m, the doping concentration is 1 × 1017～5×1019cm-3The thickness of the gate electrodes 1 and 11 is 0.5-6 μm, the gate structure and N+A source region 6,The length of the 61 contact is 0.1-0.5 μm, the gate structure and N-The contact length of the epitaxial layer 8 is 0.1-3 mu m; the surface of the device JFET region between the first gate structure and the second gate structure is also provided with P+A polysilicon layer 12 of P+Polysilicon layer 12 and N on the surface of JFET region-The epitaxial layers 8 are in direct contact and form a Si/SiC heterojunction, said P+The polysilicon layer 12 has a thickness of 0.3 to 1 μm, a width of 0.5 to 3 μm, and a doping concentration of 1 × 1017～5×1019cm-3The distance between the first grid structure and the second grid structure is 0.1-1 mu m; the P is+The upper surface of the polysilicon layer 12 has a metal electrode 13, P+The polycrystalline silicon layer 12 and the upper metal electrode 13 thereof are respectively connected with the metal source electrodes 3 and 31 through metal leads, and the thickness of the metal electrode 13 is 0.5-6 mu m; between said metal contacts, P+The polysilicon layer and the polysilicon gate are isolated from each other by BPSG or other suitable dielectric.
Example 2:
except for P+The polysilicon layer 12 has N and N on both sides-The epitaxial layer 8 directly contacts the first dielectric layer 14 and the second dielectric layer 15, and the rest of the structure of the embodiment is the same as that of the embodiment 1.
In diode applications, the first dielectric layer 14 and the second dielectric layer 15 are in P+The electron accumulation layer formed below the polysilicon layer 12 can further reduce the drift region resistance of the device, thereby reducing the forward conduction voltage drop of the device.
Example 3:
except at N-A first P-type silicon carbide region 16 forming a super junction or semi-super junction structure is also arranged in the epitaxial layer 8 and below the first Pbase region 7, and is positioned at N-The epitaxial layer 8 and the second P-type silicon carbide region 161 below the first Pbase region 7 have a super junction or semi-super junction structure, and the rest of the structure of this embodiment is the same as that of embodiment 1.
The super junction or semi-super junction structure can further reduce the drift region resistance of the device when the diode and the MOS are applied, and further reduce the forward conduction voltage drop of the device.
Compared with the traditional cellular structure of the silicon carbide VDMOS device shown in the figure 1, the invention has the advantages that the polycrystalline silicon layer is deposited on the surface of the JFET area of the silicon carbide VDMOS device, so that the Si/SiC heterojunction is formed, the application of the VDMOS device in the field of electric energy conversion such as an inverter circuit and a chopper circuit can be optimized by the technical means, and the method is as follows:
compared with a direct VDMOS parasitic silicon carbide diode, the Si/SiC heterojunction has lower conduction voltage drop (the conduction voltage drop of the Si/SiC heterojunction is about 1.2V, and the conduction voltage drop of the silicon carbide PN junction is about 3V) compared with the parasitic silicon carbide diode of a silicon carbide VDMOS device, so that the Si/SiC heterojunction conducts before the parasitic diode. The silicon carbide VDMOS device has the advantages of lower power loss, higher working speed and higher working efficiency in the application of inverter circuits, chopper circuits and the like; meanwhile, the conduction mode of the silicon carbide VDMOS device is converted from bipolar conduction (conductance modulation) of a silicon carbide parasitic diode into multi-photon conduction (no injection of minority carriers can be considered when the Si/SiC heterojunction is formed in the invention to be in forward conduction) when the diode is applied, so that the silicon carbide VDMOS device has the characteristics of short reverse recovery time and less reverse recovery charge in the application of an inverter circuit, a chopper circuit and the like, and has good reverse recovery characteristic and high switching speed.
Compared with the application mode that a Fast Recovery Diode (FRD) is connected in parallel in an anti-parallel mode outside a silicon carbide VDMOS device, the silicon carbide VDMOS device is directly integrated with a diode inside the device for use; the technical means reduces the using number of the devices, reduces the connecting lines among the devices, and has the advantages of low production cost, high device reliability and small system volume.
And (III) compared with the function of the silicon carbide VDMOS device, the silicon carbide VDMOS device reduces the gate capacitance by reducing the gate width, and the reduction of the gate capacitance is beneficial to the improvement of the working speed of the device.
Example 4:
the implementation provides a method for manufacturing a 1700V silicon carbide VDMOS device, which is characterized by comprising the following steps of:
the first step is as follows:by epitaxial process, the doping concentration is 1 × 1018cm-3～1×1019cm-3Silicon carbide N with the thickness of 300-500 mu m+The upper surface of the substrate 9 is made with a doping concentration of 1 × 1015cm-3～5×1016cm-3N with a thickness of 15 to 18 μm-An epitaxial layer 8, the cell width is in the range of 10 μm to 20 μm, as shown in fig. 5;
the second step is that: after photoetching, respectively performing N-ion implantation at 200-600 DEG C-P-type semiconductor impurity Al ions or B ions are implanted into the upper left and right ends of the epitaxial layer 8 to form a doped concentration of 1 × 1017cm-3～7×1017cm-3Two Pbase regions 7, 71 each having an implantation depth of about 0.5 μm to 1 μm, and a JFET region between the two Pbase regions 7, 71 having a width of about 3 μm to 10 μm, as shown in FIG. 6;
thirdly, after photoetching, respectively injecting P-type semiconductor impurity Al ions or B ions into the upper layers of the two Pbase areas 7 and 71 by adopting an ion injection process at the temperature of 200-600 ℃ to form a doping concentration of 1 × 1019cm-3～1×1020cm-3Two P with an implantation depth of about 0.3-0.5 μm+Contact zones 5, 51, as shown in fig. 7;
fourthly, after the photoetching is finished, injecting N-type semiconductor impurity P ions or N ions into the upper layers of the two Pbase areas 7 and 71 by adopting an ion injection process at the temperature of 200-600 ℃ to form the doping concentration of 3 × 1019cm-3～1×1020cm-3Two N with an implantation depth of about 0.3 to 0.5 μm+Source regions 6, 61; the first P+Contact region 5 and first N+The source regions 6 are independent of each other, the second P+Contact region 51 and second N+The source regions 61 are independent of each other; after ion implantation is finished, high-temperature annealing is carried out at the high temperature of 1300-1700 ℃, as shown in figure 8;
the fifth step: growing a gate dielectric material layer with the thickness of about 0.02-0.2 mu m on the surface of the device by adopting an oxidation or deposition process, then removing the gate dielectric material layer with the width of 0.5-3 mu m above the middle position of the JFET by adopting an etching process, and forming two gate dielectric material layers on the upper surface of the deviceForming independent gate dielectric material regions, etching the parts to form a subsequent process deposition P+The window of the polysilicon layer 12 is shown in fig. 9. a layer with a doping concentration of 1 × 10 is deposited on the device surface17cm-3～5×1019cm-3A P-type polysilicon layer with a thickness of 0.3-1 μm, as shown in fig. 10; etching off the unnecessary polysilicon layer and the gate dielectric material layer under the unnecessary polysilicon layer by an etching process to obtain two polysilicon gates 2 and 21, gate dielectric layers 4 and 41 and P+A polysilicon layer 12; formed P+The width of the polysilicon layer 12 is 0.5-3 μm, P+The distances between the polysilicon layer 12 and the polysilicon gates 2 and 21 are 0.1-1 μm, and the polysilicon gates 2 and 21 and the corresponding N+The contact length of the source regions 6 and 61 is 0.1-0.5 mu m, and the polysilicon gates 2 and 21 and N are respectively-The length of the contact of the epitaxial layer 8 is 0.1-3 μm, as shown in fig. 11;
and a sixth step: using metal deposition and etching process at first P+Contact region 5 and part of the first N+A first metal source electrode 3 is generated on the upper surface of the source region 6; at the second P+Contact region 51 and part of the second N+A second metal source electrode 31 is generated on the upper surface of the source region 61; at P+ A metal electrode 13 is formed on the upper surface of the polysilicon layer 12, and the metal electrode 13 is respectively connected with the two metal source electrodes 3 and 31 through metal leads; correspondingly generating gate electrodes 1 and 11 on the two polysilicon gates 2 and 21; thinning the back surface of the device and forming a drain electrode 10 by deposition, wherein the thickness of all metal electrodes 3, 31, 1, 11, 13 and 10 in the device is about 0.5-6 μm, as shown in FIG. 12; and finally preparing the silicon carbide VDMOS device which is symmetrical left and right.
Example 5:
in this embodiment, except for the fifth step, by changing the layout size, when the excess polysilicon layer and the gate dielectric material layer thereunder are etched away, the remaining P is made+The polysilicon region 12 is larger than the window formed by etching the gate dielectric material layer so as to form a window in P+Both sides under the polysilicon layer 12 are made of N-The operation is the same as in example 4 except that the first dielectric layer 14 and the second dielectric layer 15 in direct contact with the epitaxial layer 8 are different from example 4.
It should be noted that: the skilled worker can substitute the silicon carbide material with wide bandgap materials such as gallium nitride and diamond according to the basic knowledge in the field; the invention not only can adopt the P-type polycrystalline silicon material to realize the manufacture of the N-channel device, but also adopts the N-type polycrystalline silicon material to realize the manufacture of the P-channel device; the gate dielectric layer material of the present invention is not limited to silicon dioxide, and further comprises: silicon nitride (Si)3N4) Hafnium oxide (H)fO2) Aluminum oxide (Al)2O3) And high-K dielectric materials. Meanwhile, the specific implementation mode of the manufacturing process can be adjusted according to actual needs.
While the present invention has been described with reference to the embodiments illustrated in the drawings, the present invention is not limited to the embodiments, which are illustrative rather than restrictive, and it will be apparent to those skilled in the art that many more modifications and variations can be made without departing from the spirit of the invention and the scope of the appended claims.
Claims (9)
1. A silicon carbide VDMOS device, the cell structure of which comprises: a metal drain electrode (10) and N arranged from bottom to top in sequence+Substrate (9) and N-An epitaxial layer (8); said N is-One end of the upper layer of the epitaxial layer (8) is provided with a first Pbase area (7), and N is-The other end of the upper layer of the epitaxial layer (8) is provided with a second Pbase area (71); the first Pbase region (7) has mutually independent first N+A source region (6) and a first P+A contact zone (5); the second Pbase region (71) has second N independent of each other+A source region (61) and a second P+A contact zone (51); the first P+A contact region (5) and a portion of the first N+The upper surface of the source region (6) is provided with a first metal source electrode (3); the second P+A contact region (51) and a portion of the second N+The upper surface of the source region (61) is provided with a second metal source electrode (31); the method is characterized in that: further comprises a first N and an upper surface of the first Pbase region (7)+A source region (6) having a portion of its upper surface and N-Part of the upper surface of the epitaxial layer (8)A first gate structure in contact; the first grid structure comprises a first grid dielectric layer (4), a first polysilicon grid (2) positioned on the upper surface of the first grid dielectric layer (4) and a first grid electrode (1) positioned on the upper surface of the first polysilicon grid (2); further comprising a second N region adjacent to the upper surface of the second Pbase region (71)+A source region (61) having a portion of its upper surface and N-A second gate structure in contact with the upper surface of part of the epitaxial layer (8); the second gate structure comprises a second gate dielectric layer (41), a second polysilicon gate (21) positioned on the upper surface of the second gate dielectric layer (41) and a second gate electrode (11) positioned on the upper surface of the second polysilicon gate (21); further comprising P forming a Si/SiC heterojunction in surface contact with the upper surface of the JFET region between the first gate structure and the second gate structure+A polysilicon layer (12), the P+The upper surface of the polysilicon layer (12) is provided with a metal electrode (13), and the P is+The polycrystalline silicon layer (12) and the metal electrode (13) are respectively connected with the first metal source electrode (3) and the second metal source electrode (31); between metal structures and P+The polysilicon layer (12) is isolated from the two polysilicon gates (2, 21) through a medium;
N-the epitaxial layer (8) is also internally provided with a first P-type silicon carbide region (16) and a second P-type silicon carbide region (161) which are respectively arranged below the first Pbase region (7) and the second Pbase region (71) and form a super junction or semi-super junction structure;
P+the polysilicon layer (12) also has N and-a first dielectric layer (14) and a second dielectric layer (15) which are contacted with the epitaxial layer (8); the first dielectric layer (14) and the second dielectric layer (15) are made of silicon nitride, hafnium oxide or aluminum oxide.
2. A silicon carbide VDMOS device, the cell structure of which comprises: a metal drain electrode and P arranged from bottom to top in sequence+Substrate and P-An epitaxial layer; the P is-One end of the upper layer of the epitaxial layer is provided with a first Nbase area, and the P-The other end of the upper layer of the epitaxial layer is provided with a second Nbase area; the first Nbase region has mutually independent first P+Source region and first N+A contact zone; the second Nbase region has mutually independent second P+Source region and second N+Contact withA zone; the first N+A contact region (5) and a portion of the first P+The upper surface of the source region is provided with a first metal source electrode; the second N+Contact region and part of the second P+The upper surface of the source region is provided with a second metal source electrode; the method is characterized in that: further comprises a first P and a first Nbase region upper surface+Source region part upper surface and P-A first gate structure contacting the upper surface of the epitaxial layer portion; the first grid structure comprises a first grid dielectric layer, a first polysilicon grid positioned on the upper surface of the first grid dielectric layer and a first grid electrode positioned on the upper surface of the first polysilicon grid; further comprises a second P and an upper surface of a second Nbase region+Source region part upper surface and P-The upper surface of the epitaxial layer part is contacted with the second grid structure; the second grid structure comprises a second grid dielectric layer, a second polysilicon grid positioned on the upper surface of the second grid dielectric layer and a second grid electrode positioned on the upper surface of the second polysilicon grid; the semiconductor device further comprises N in surface contact with the upper surface of the JFET region between the first gate structure and the second gate structure to form a Si/SiC heterojunction+A polysilicon layer of said N+The upper surface of the polysilicon layer is provided with a metal electrode, N+The polycrystalline silicon layer and the metal electrode are respectively connected with the first metal source electrode and the second metal source electrode; between metal structures and N+The polysilicon layer and the two polysilicon gates are isolated from each other through a medium;
P-the epitaxial layer is also internally provided with a first N-type silicon carbide region and a second N-type silicon carbide region which are respectively arranged below the first Nbase region and the second Nbase region and form a super junction or semi-super junction structure;
N+the polysilicon layer also has P-A first dielectric layer (14) and a second dielectric layer (15) in contact with the epitaxial layer; the first dielectric layer (14) and the second dielectric layer (15) are made of silicon nitride, hafnium oxide or aluminum oxide.
3. A silicon carbide VDMOS device, the cell structure of which comprises: a metal drain electrode (10) and N arranged from bottom to top in sequence+Substrate (9) and N-An epitaxial layer (8); said N is-One end of the upper layer of the epitaxial layer (8) is provided with a first Pbase area(7) Said N is-The other end of the upper layer of the epitaxial layer (8) is provided with a second Pbase area (71); the first Pbase region (7) has mutually independent first N+A source region (6) and a first P+A contact zone (5); the second Pbase region (71) has second N independent of each other+A source region (61) and a second P+A contact zone (51); the first P+A contact region (5) and a portion of the first N+The upper surface of the source region (6) is provided with a first metal source electrode (3); the second P+A contact region (51) and a portion of the second N+The upper surface of the source region (61) is provided with a second metal source electrode (31); the method is characterized in that: further comprises a first N and an upper surface of the first Pbase region (7)+A source region (6) having a portion of its upper surface and N-A first grid structure with the upper surface of the partial epitaxial layer (8) contacted; the first grid structure comprises a first grid dielectric layer (4), a first polysilicon grid (2) positioned on the upper surface of the first grid dielectric layer (4) and a first grid electrode (1) positioned on the upper surface of the first polysilicon grid (2); further comprising a second N region adjacent to the upper surface of the second Pbase region (71)+A source region (61) having a portion of its upper surface and N-A second gate structure in contact with the upper surface of part of the epitaxial layer (8); the second gate structure comprises a second gate dielectric layer (41), a second polysilicon gate (21) positioned on the upper surface of the second gate dielectric layer (41) and a second gate electrode (11) positioned on the upper surface of the second polysilicon gate (21); the semiconductor device further comprises N in surface contact with the upper surface of the JFET region between the first gate structure and the second gate structure to form a Si/SiC heterojunction+A polysilicon layer of said N+The upper surface of the polysilicon layer is provided with a metal electrode (13), and N is+The polycrystalline silicon layer and the metal electrode (13) are respectively connected with the first metal source electrode (3) and the second metal source electrode (31); between metal structures and N+The polysilicon layer and the two polysilicon gates (2, 21) are isolated from each other by a dielectric.
4. A silicon carbide VDMOS device, the cell structure of which comprises: a metal drain electrode and P arranged from bottom to top in sequence+Substrate and P-An epitaxial layer; the P is-One end of the upper layer of the epitaxial layer is provided with a first Nbase area, and the P-The other end of the upper layer of the epitaxial layer is provided with a second Nbase area; the first Nbase region has mutually independent first P+Source region and first N+A contact zone; the second Nbase region has mutually independent second P+Source region and second N+A contact zone; the first N+A contact region (5) and a portion of the first P+The upper surface of the source region is provided with a first metal source electrode; the second N+Contact region and part of the second P+The upper surface of the source region is provided with a second metal source electrode; the method is characterized in that: further comprises a first P and a first Nbase region upper surface+Source region part upper surface and P-A first gate structure contacting the upper surface of the epitaxial layer portion; the first grid structure comprises a first grid dielectric layer, a first polysilicon grid positioned on the upper surface of the first grid dielectric layer and a first grid electrode positioned on the upper surface of the first polysilicon grid; further comprises a second P and an upper surface of a second Nbase region+Source region part upper surface and P-The upper surface of the epitaxial layer part is contacted with the second grid structure; the second grid structure comprises a second grid dielectric layer, a second polysilicon grid positioned on the upper surface of the second grid dielectric layer and a second grid electrode positioned on the upper surface of the second polysilicon grid; further comprising P forming a Si/SiC heterojunction in surface contact with the upper surface of the JFET region between the first gate structure and the second gate structure+A polysilicon layer of P+The upper surface of the polysilicon layer is provided with a metal electrode, P+The polycrystalline silicon layer and the metal electrode are respectively connected with the first metal source electrode and the second metal source electrode; between metal structures and P+The polysilicon layer and the two polysilicon gates are isolated from each other through a medium.
5. A silicon carbide VDMOS device according to claim 3 or 4, wherein N is+Polysilicon layer or P+In the polysilicon layer, N is respectively-Epitaxial layer (8) or P-A first dielectric layer (14) and a second dielectric layer (15) in contact with the epitaxial layer; the first dielectric layer (14) and the second dielectric layer (15) are made of silicon nitride, hafnium oxide or aluminum oxide;
N-epitaxial layer or P-The epitaxial layer is also internally provided with a second Pbase region and a second Pbase region which are respectively arranged below the first Pbase regionAnd a first P-type silicon carbide region and a second P-type silicon carbide region or a first N-type silicon carbide region and a second N-type silicon carbide region which are of a super junction or semi-super junction structure are formed below the Pbase region or below the first Nbase region and below the second Nbase region.
6. A manufacturing method of a silicon carbide VDMOS device is characterized by comprising the following steps:
the first step is as follows: by epitaxial process on silicon carbide N+The upper surface of the substrate (9) is made to be N-An epitaxial layer (8);
the second step is that: after photoetching, adopting an ion implantation process at the temperature of 200-600 ℃ and carrying out N-Injecting P-type semiconductor impurities into one end of the upper layer of the epitaxial layer (8) to form a first Pbase region (7) in the N region-Injecting P-type semiconductor impurities into the other end of the upper layer of the epitaxial layer (8) to form a second Pbase region (71);
the third step: after photoetching, injecting P-type semiconductor impurities into the upper layer of the first Pbase area (7) at 200-600 ℃ by adopting an ion injection process to form first P+A contact region (5) formed by implanting P-type semiconductor impurities on the upper layer of the second Pbase region (71) to form a second P+A contact zone (51);
the fourth step: after photoetching, injecting N-type semiconductor impurities into the upper layer of the first Pbase area (7) at 200-600 ℃ by adopting an ion injection process to form first N+A source region (6) formed by implanting N-type semiconductor impurities into the upper layer of the second Pbase region (71) to form a second N+A source region (61); the first P+A contact region (5) and a first N+The source regions (6) being independent of each other, the second P+A contact region (51) and a second N+The source regions (61) are independent of each other; then activating the injected impurities by high-temperature annealing at 1300-1700 ℃;
the fifth step: growing a gate dielectric layer on the upper surface of the device by adopting deposition or oxidation and etching processes, etching to remove a part of the gate dielectric layer above the middle position of the JFET area to form a window, and depositing N on the upper surface of the device+Etching the polysilicon layer to remove the redundant polysilicon layer and the redundant gate dielectric layer to obtain a first gate dielectric layer (4), a second gate dielectric layer (41), a first polysilicon gate (2), a second polysilicon gate (21) and an N+PolycrystallineA silicon layer, wherein: the first gate dielectric layer (4) is arranged on the upper surface of the first Pbase area (7), and the left side and the right side of the first gate dielectric layer are respectively connected with the first N+A source region (6) having a portion of its upper surface and N-The upper surfaces of parts of the epitaxial layers (8) are contacted, the first polysilicon gate (2) is arranged on the upper surface of the first gate dielectric layer (4), the second gate dielectric layer (41) is arranged on the upper surface of the second Pbase area (71), and the left side and the right side of the second gate dielectric layer are respectively contacted with the first N+A source region (6) having a portion of its upper surface and N-Part of the upper surface of the epitaxial layer (8) is contacted, the second polysilicon gate (21) is arranged on the upper surface of the second gate dielectric layer (41), and N+The polycrystalline silicon layer is positioned between the first gate dielectric layer (4) and the second gate dielectric layer (41);
and a sixth step: using metal deposition and etching process at the first N+A source region (6) and a first P+Generating a first metal source electrode (3) on the upper surface of the contact region (5); at the second N+A source region (61) and a second P+Generating a second metal source electrode (31) on the upper surface of the contact region (51); generating a first gate electrode (1) on the upper surface of the first polysilicon gate (2); generating a second gate electrode (11) on the upper surface of the second polysilicon gate (21); thinning and depositing metal on the back of the device to form a drain electrode (10); in N+Forming a metal electrode (13) on the upper surface of the polycrystalline silicon layer; the metal electrode (13) is respectively connected with the first metal source electrode (3) and the second metal source electrode (31); thus obtaining the silicon carbide VDMOS device.
7. A method for manufacturing a silicon carbide VDMOS device is characterized by comprising the following steps: by epitaxial process on silicon carbide N+The upper surface of the substrate (9) is made to be N-An epitaxial layer (8);
the second step is that: after photoetching, adopting an ion implantation process at the temperature of 200-600 ℃ and carrying out N-One end of the upper layer of the epitaxial layer (8) is injected with P-type semiconductor impurity Al ions or B ions to form a first Pbase area (7), and N is arranged in the first Pbase area-Injecting P-type semiconductor impurities into the other end of the upper layer of the epitaxial layer (8) to form a second Pbase region (71);
the third step: after photoetching, injecting P-type semiconductor impurity Al ions or B ions into the upper layer of the first Pbase area (7) at 200-600 ℃ by adopting an ion injection process to form first P+A contact region (5) formed by implanting P-type dopant in the second Pbase region (71)Forming second P from semiconductor impurity Al ion or B ion+A contact zone (51);
the fourth step: after photoetching, injecting N-type semiconductor impurity P ions or N ions into the upper layer of the first Pbase area (7) at 200-600 ℃ by adopting an ion injection process to form first N+A source region (6) for forming a second N by implanting P ions or N ions of N-type semiconductor impurity into the upper layer of the second Pbase region (71)+A source region (61); the first P+A contact region (5) and a first N+The source regions (6) being independent of each other, the second P+A contact region (51) and a second N+The source regions (61) are independent of each other; then activating the injected impurities by high-temperature annealing at 1300-1700 ℃;
the fifth step: growing a gate dielectric layer on the upper surface of the device by adopting deposition and etching processes, etching to remove a part of the gate dielectric layer above the middle position of the JFET area to form a window, and depositing P on the upper surface of the device+And etching the polysilicon layer to remove the redundant polysilicon layer and the redundant gate dielectric layer to obtain a first gate dielectric layer (4), a second gate dielectric layer (41), a first polysilicon gate (2), a second polysilicon gate (21), a first dielectric layer (14), a second dielectric layer (15) and a P+A polysilicon layer (12), wherein: the first gate dielectric layer (4) is arranged on the upper surface of the first Pbase area (7), and the left side and the right side of the first gate dielectric layer are respectively connected with the first N+A source region (6) having a portion of its upper surface and N-The upper surfaces of parts of the epitaxial layers (8) are contacted, the first polysilicon gate (2) is arranged on the upper surface of the first gate dielectric layer (4), the second gate dielectric layer (41) is arranged on the upper surface of the second Pbase area (71), and the left side and the right side of the second gate dielectric layer are respectively contacted with the first N+A source region (6) having a portion of its upper surface and N-Part of the upper surface of the epitaxial layer (8) is contacted, the second polysilicon gate (21) is arranged on the upper surface of the second gate dielectric layer (41), and P is+The polysilicon layer (12) is positioned between the first gate dielectric layer (4) and the second gate dielectric layer (41) at P+The polycrystalline silicon layer (12) is internally provided with a first dielectric layer (14) and a second dielectric layer (15);
and a sixth step: using metal deposition and etching process at the first N+A source region (6) and a first P+Generating a first metal source electrode (3) on the upper surface of the contact region (5); at the second N+A source region (61) and a second P+Forming a second metal source electrode on the upper surface of the contact region (51)(31) (ii) a Generating a first gate electrode (1) on the upper surface of the first polysilicon gate (2); generating a second gate electrode (11) on the upper surface of the second polysilicon gate (21); thinning and depositing metal on the back of the device to form a drain electrode (10); at P+A metal electrode (13) is formed on the upper surface of the polycrystalline silicon layer (12); the metal electrode (13) is respectively connected with the first metal source electrode (3) and the second metal source electrode (31); thus obtaining the silicon carbide VDMOS device.
8. The method as claimed in claim 6 or 7, further comprising forming N and between metal structures by dielectric deposition and etching process before the sixth step+Polysilicon layer or P+The polysilicon layer (12) is isolated from the two polysilicon gates (2, 21) by a medium.
9. The method of claim 8, wherein prior to performing the second step to form the Pbase region, further comprising: by a multi-step photolithography and ion implantation process, in N-A super or semi super junction structure is formed in the epitaxial layer (8).
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| CN110212026B (en) * | 2019-05-06 | 2022-09-16 | 上海功成半导体科技有限公司 | Super junction MOS device structure and preparation method thereof |
| CN110379861A (en) * | 2019-08-12 | 2019-10-25 | 派恩杰半导体（杭州）有限公司 | A kind of silicon carbide heterojunction diode power device |
| CN110429138B (en) * | 2019-08-15 | 2023-03-14 | 西安电子科技大学 | U-MOSFET with partial gallium nitride/silicon semiconductor material heterojunction and manufacturing method thereof |
| CN110473872A (en) * | 2019-10-14 | 2019-11-19 | 派恩杰半导体（杭州）有限公司 | A kind of carbide MOS devices with majority carrier diode |
| CN112349781A (en) * | 2020-11-05 | 2021-02-09 | 湖南大学 | SiC MOSFET device of heterogeneous integrated diode |
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