CN104347403A - Manufacturing method of insulated gate bipolar transistor - Google Patents
Manufacturing method of insulated gate bipolar transistor Download PDFInfo
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- CN104347403A CN104347403A CN201310329221.9A CN201310329221A CN104347403A CN 104347403 A CN104347403 A CN 104347403A CN 201310329221 A CN201310329221 A CN 201310329221A CN 104347403 A CN104347403 A CN 104347403A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 66
- 239000004065 semiconductor Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 238000001259 photo etching Methods 0.000 claims abstract description 17
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000000137 annealing Methods 0.000 description 8
- 239000012535 impurity Substances 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910016570 AlCu Inorganic materials 0.000 description 1
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 208000032750 Device leakage Diseases 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
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- 150000001875 compounds Chemical class 0.000 description 1
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- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Thyristors (AREA)
Abstract
The invention discloses a manufacturing method of an insulated gate bipolar transistor. The manufacturing method comprises the steps that a first conduction type semiconductor substrate is provided, and the semiconductor substrate is provided with a first main surface and a second main surface; active region photoetching and first conduction type ion implantation are performed on the first conduction type semiconductor substrate; a second conduction type base region is formed on the first main surface of an active region of the first conduction type semiconductor substrate, and a second conduction type protecting terminal is formed on the outer side of the first main surface of the active region; a remaining first main surface structure of the insulated gate bipolar transistor is formed on the first main surface of the semiconductor substrate on the basis of the formed base region; a second main surface structure of the insulated gate bipolar transistor is formed on the second main surface side of the semiconductor substrate. The invention provides the manufacturing method of the IGBT (insulated gate bipolar transistor) which has the advantages of reduction of the use quantity of photoetching plates, simple process flow, low manufacturing cost and high application reliability.
Description
Technical field
The invention belongs to power semiconductor device technology field, relate to insulated gate bipolar transistor (IGBT), especially the preparation method of the insulated gate bipolar transistor of Simplified flowsheet.
Background technology
IGBT is by GTR(Giant Transistor, power transistor or huge transistor) and MOSFET(Metal-Oxide-Semiconductor-Field-Effect-Transistor, mos field effect transistor) the compound full-control type voltage driven type power semiconductor that forms, have the advantage of the high input impedance of MOSFET and low conduction voltage drop two aspect of GTR concurrently, there is operating frequency high, control circuit is simple, current density is high, on-state such as to force down at the feature, is widely used in power control field.
IGBT, according to the structure type of grid, can be divided into plane IGBT and groove-shaped IGBT, the architectural feature of the two and individual features is known to those skilled in the art knows.But, these two kinds of IGBT are in the process of preparation, include front technique and back process, wherein, front technique has been mainly used to the grid (Gate, G) of IGBT and the preparation of emitter (Emitter, E), back process has been mainly used to the preparation of the collector electrode (Collector, C) of IGBT.
Normally, existing plane IGBT is formed mainly through following two kinds of methods preparation.
The first completes front technique on a monocrystaline silicon substrate, then, the back side thinning to substrate back repeatedly ion implantation form collector electrode to draw; This method does not rely on epitaxy technique, but depending on energetic ion injects and annealing activation technology process, and it is also higher that the equipment cost that energetic ion injects is high, technical process realizes cost; Further, the activity ratio of doped source of the collector area that ion implantation annealing are formed is not high, and then causes the saturation characteristic of IGBT not good.
The second is, the epitaxial loayer that transoid epitaxial growth is thicker on a monocrystaline silicon substrate, and completes front technique on this epitaxial loayer, then thinning and form collector electrode to silicon substrate at its back side; This method adopts epitaxy technique and mainly prepares more than IGBT(resilient coating with epitaxial loayer and formed by epitaxial loayer), epitaxial loayer is thicker and to the performance requirement of epitaxial loayer very high (such as defect counts), usually cause because the quality of epitaxial loayer is good not IGBT degradation (such as, overvoltage ability to bear and overcurrent ability to bear poor) or rate of finished products low.
Along with the world is to the demand of energy-saving and emission-reduction, IGBT application is more and more extensive, and IGBT is used for multiple circuit, be not difficult to find, existing technological process is that terminal structure has independent reticle, complex process, manufacturing cost is higher, therefore, is necessary to provide a kind of technical scheme of improvement to overcome the problems referred to above.
Summary of the invention
The object of this part is some aspects of general introduction embodiments of the invention and briefly introduces some preferred embodiments.May do in the specification digest and denomination of invention of this part and the application a little simplify or omit with avoid making this part, specification digest and denomination of invention object fuzzy, and this simplification or omit and can not be used for limiting the scope of the invention.
In view of Problems existing in the manufacture method of above-mentioned and/or existing IGBT, propose the present invention.
Therefore, the object of the invention is for existing procedure technique is that terminal structure has independent reticle, complex process, manufacturing cost is higher, there is provided a kind of and reduce reticle usage quantity, technological process is simple, and manufacturing cost reduces and the high IGBT manufacture method of application reliability.
For solving the problems of the technologies described above, the invention provides following technical scheme: a kind of manufacture method of insulated gate bipolar transistor, comprises, providing the Semiconductor substrate of the first conduction type, this Semiconductor substrate has the first interarea and the second interarea; The ion implantation of active area photoetching and the first conduction type is carried out in the Semiconductor substrate of the first conduction type; Form the base of the second conduction type at active area first interarea of the Semiconductor substrate of the first conduction type and outside the interarea of active area first, form the protection terminal of the second conduction type; The residue first interarea structure of insulated gate bipolar transistor is formed based on the base formed at the first interarea of this Semiconductor substrate; The second interarea structure of insulated gate bipolar transistor is formed in the second interarea side of this Semiconductor substrate.
As a kind of preferred version of the manufacture method of insulated gate bipolar transistor of the present invention, wherein: the process forming described protection terminal and described base comprises: on the first interarea of the Semiconductor substrate of the first conduction type, generate field oxide; Protection terminal and base photoetching, etching, the second conductive type ion inject, push away trap to form described protection terminal and described base; First interarea of active area grows gate oxide.
As a kind of preferred version of the manufacture method of insulated gate bipolar transistor of the present invention, wherein: the second interarea structure that described the second interarea side in this Semiconductor substrate forms insulated gate bipolar transistor comprises: by technique for thinning back side, by thinning from the second interarea for the thick end of the Semiconductor substrate of the first conduction type; Form the second semiconductor layer of the second conduction type towards Semiconductor substrate inside from the second interarea of the Semiconductor substrate after thinning; Second semiconductor layer of the second conduction type forms metal level to form the second main electrode.
As a kind of preferred version of the manufacture method of insulated gate bipolar transistor of the present invention, wherein: the first conduction type is N-type, the second conduction type is P type.
As a kind of preferred version of the manufacture method of insulated gate bipolar transistor of the present invention, wherein: the residue first interarea structure forming insulated gate bipolar transistor based on the base formed at the first interarea of this Semiconductor substrate comprises: optionally in the Semiconductor substrate of the first conduction type, form the first conduction type emitter region along the surface of the base of the second conduction type; Deposit forms dielectric layer; Etch contact hole in the dielectric layer; Adopt depositing metal and flatening process deposit layer of surface metal level to form the first main electrode.
As a kind of preferred version of the manufacture method of insulated gate bipolar transistor of the present invention, wherein: the Facad structure of described IGBT also comprises: be formed at the passivation layer outside the first main electrode described in the first interarea.
As a kind of preferred version of the manufacture method of insulated gate bipolar transistor of the present invention, wherein: described second conductive type ion injects, and the energy of ion implantation is 20KeV ~ 1MeV, and dosage is 1E11/cm
2~ 1E14/cm
2.
The invention provides a kind of manufacture method of insulated gate bipolar transistor, POLY photoetching and P-Body region and Ring region etch in the method IGBT structure, p type impurity injection, pushes away trap formation body trap and P trap in Ring district completes in same step, reduces the use number of plies of reticle.The present invention is directed to existing procedure technique is the problems such as terminal structure has independent reticle, complex process, and manufacturing cost is higher, and provide a kind of and reduce reticle usage quantity, technological process is simple, and manufacturing cost reduces and the high IGBT manufacture method of application reliability.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 ~ Figure 11 is the method flow schematic diagram making IGBT according to first embodiment of the invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
First embodiment of the invention is Semiconductor substrate with silicon chip, and relate to a kind of method making IGBT device, idiographic flow is as shown in Fig. 1 ~ Figure 11.
It should be noted that, Semiconductor substrate in the present embodiment can comprise semiconductor element, the silicon of such as monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe), also the semiconductor structure of mixing can be comprised, such as carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or its combination; Also can be silicon-on-insulator (SOI).In addition, Semiconductor substrate can also comprise other material, the sandwich construction of such as epitaxial loayer or buried layer.Although there is described herein several examples of the material that can form Semiconductor substrate, all the spirit and scope of the present invention can be fallen into as any material of Semiconductor substrate.
As shown in Figure 1, the first step, provides the Semiconductor substrate of the first conduction type, and this Semiconductor substrate has the first interarea and the second interarea.In the present embodiment, specifically, first-selected N-type substrate 101 silicon chip, N-doping content and thickness are selected according to required IGBT characteristic, and such as puncture voltage is higher, and the doping content of N-requires lower, thickness requirement is thicker, and on the first interarea, form thickness be 300
~
oxide layer 102.
Second step, as shown in Figure 2, carries out the ion implantation of active area photoetching and the first conduction type in the Semiconductor substrate of the first conduction type.Be specially, be etched with the oxide layer 102 in source region 100 by photoetching process at the first interarea of described N-type substrate 101, with the oxide layer figure of terminal area 200, carry out JFET injection afterwards, carry out N-type impurity injection, in the present embodiment, the energy of ion implantation is 20KeV ~ 1MeV, and dosage is such as 1E11/cm
2~ 1E14/cm
2, form JFET region.
3rd step, active area 100 first interarea forms one deck gate oxide 401 by thermal oxide growth technique, and as shown in Figure 3 and Figure 4, on gate oxide 401, deposit one deck polysilicon layer 402 is in order to manufacture polysilicon gate.
See Fig. 3, active area 100 first interarea forms gate oxide 401, gate oxide 401 in the present embodiment at least comprises silica, the mode forming gate oxide 401 can be, on the interarea of active area 100 first, once property grows gate oxide 401, in the present embodiment, adopt and form gate oxide 401 relative to the thermal oxidation method of conventional high temperature process lower temperature, be specially, first dry oxygen 5min 800 DEG C ~ 850 DEG C time, oxidated layer thickness as required carries out H afterwards
2-O
2synthesis oxidation, then at 800 DEG C ~ 850 DEG C dry-oxygen oxidation 3min ~ 5min, finally N 1000 DEG C ~ 1250 DEG C time
2anneal in atmosphere 10min ~ 1000min; Because the high-temperature oxidation process continued can increase SiO in grid greatly like this
2the interface charge of layer and the lattice defect density of silicon, cause high device leakage current, the reliability of device and Radiation hardness are declined, and low thermal oxidation then can suppress the growth of the defects such as stacking fault and the fractional condensation of channel region impurity, and high annealing can reduce SiO
2the fixed charge of layer, improves quality of oxide layer, and forming thickness is 500
gate oxide 401.
As shown in Figure 4, depositing polysilicon layer 402 on gate oxide 401, in the present embodiment, forming thickness is
~
polysilicon layer 402, wherein polysilicon layer 402 can adopt chemical vapor deposition, physical vapor deposition or alternate manner to be formed, and the present embodiment is not specifically limited.
4th step, forms the base of the second conduction type at active area first interarea of the Semiconductor substrate of the first conduction type and outside the interarea of active area first, forms the terminal protection district 200 of the second conduction type.As shown in Figure 5, be specially, in the active area 100 of the first interarea of described N-type substrate 101 by photoetching process etching gate oxide 401 and polysilicon layer 402, photoetching process is adopted to form the photoresist layer with grid region pattern on the surface at this gate polysilicon layer, afterwards there is the photoresist layer of grid region pattern for mask, the mode of dry etching is adopted to form polysilicon gate 501(see Fig. 5) and the figure of a P well region 301 and the 2nd P well region 302, the terminal protection district 200 of the second conduction type is formed outside the interarea of photoetching first simultaneously, the mode of ion implantation is adopted to form the ion implanted layer of a P well region 301, the ion implanted layer of the 2nd P well region 302, and terminal P well region 201, to the ion implanted layer of a P well region 301, the ion implanted layer of the 2nd P well region 302 and P well area 201 carry out advancing and activate the p type impurity injected, form a P well region 301, 2nd P well region 302 and terminal P well region 201.In the present embodiment, the energy of ion implantation is 20KeV ~ 1MeV, and dosage is such as 1E12/cm
2~ 1E16/cm
2, then under the condition of 1100 DEG C ~ 1250 DEG C, push away trap 20min ~ 1000min.
5th step, as shown in Figure 6, in the Semiconductor substrate (in this case N-type substrate 101) of the first conduction type, the active area of the first conduction type (in this case N-type) is optionally formed along the surface of the base (in this case a P well region 301 and the 2nd P well region 302) of the second conduction type.Be specially, select N+ to inject window by photoetching process on the surface of a described P well region 301 and the 2nd P well region 302, adopt ion implantation and annealing process to form N-type heavy doping first source region 602 and the second source region 601 respectively in a P well region 301 and the 2nd P well region 302 of polysilicon gate 501 down either side.In the present embodiment, the energy of ion implantation is 20KeV ~ 1MeV, and dosage is such as 1E15/cm
2~ 1E16/cm
2; Described annealing process, its annealing temperature is 800 DEG C ~ 1000 DEG C, and the time is 10min ~ 1000min, forms N-type heavy doping first source region 602 and the second source region 601.
6th step, see Fig. 7, in the present embodiment, medium in described 5th step deposit formed dielectric layer 701 surround polysilicon gate 501(see Fig. 7) side and end face, contact hole is etched in dielectric layer 701, then carry out N-type impurity twice injection in hole, the energy of ion implantation is 20KeV ~ 90KeV for the first time, and dosage is such as 1E12/cm
2~ 1E16/cm
2; The energy of second time ion implantation is 20KeV ~ 1MeV, and dosage is such as 1E13/cm
2~ 1E16/cm
2.Certainly, the N-type impurity in hole also can be used once to inject.
7th step, adopt depositing metal, in silicon chip surface deposit layer of surface metal level (Al/AlCu/AlSiCu/AlSi), in the present embodiment, this metal layer thickness is about 2um ~ 6um, then photoetching and etching are carried out to metal level, form metal wiring layer 801, form the first main electrode (in this case emitter).Silicon chip section after these steps all complete as shown in Figure 8.
See Fig. 9, the 8th step, deposit passivation layer 901 on the first main electrode (in this case emitter) metal wiring layer 801 and oxide layer 102.Be specially; by the mode of chemical vapor deposition; in the first main electrode (in this case emitter) and oxide layer 102, deposit is not subject to the passivation layer 901 of extraneous ion contamination for the protection of chip surface; and by photoetching, etching technics, etch the PAD(pad for drawing gate electrode and emitter) region (not shown).
9th step, by technique for thinning back side, by thinning for the thick end of the Semiconductor substrate (in this case N-type substrate 101) of the first conduction type.Be specially, from the second interarea of N-type substrate 101, grind this Semiconductor substrate, make the thickness requirement that it conforms with the regulations, and adopt wet method to remove back side silicon stressor layers.
Tenth step; as shown in Figure 10; see Fig. 3; from second interarea in the terminal protection district 200 of the N-type substrate 101 after thinning, form second semiconductor layer (in this case P+ collector layer 1101) of the second conduction type towards N-type substrate 101 inside, and from the second interarea of active area 100, optionally form second semiconductor layer (in this case P+ collector layer 1101) of the second conduction type towards Semiconductor substrate inside.Be specially, at the second interarea from the N-type Semiconductor substrate 1 after grinding by photoetching process optionally implanting p-type impurity, form P+ collector layer 1101 and activation of annealing.In the present embodiment, the energy of ion implantation is 20KeV ~ 80KeV, and dosage is such as 1E12/cm
2~ 1E16/cm
2; During annealing, temperature is 300 DEG C ~ 550 DEG C, duration 10min ~ 500min.
Finally, back metal deposit, as shown in figure 11, at the upper metal level 1201 that formed of second semiconductor layer (in this case P+ collector layer 1101) of the second conduction type to form the second main electrode.
Be not difficult to find, in the present embodiment, POLY photoetching and P-Body region and Ring region etch in IGBT structure, p type impurity injects, and pushes away trap and forms body trap and P trap in Ring district completes in same step, reduce the use number of plies of reticle.
It should be noted that, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not departing from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of right of the present invention.
Claims (7)
1. a manufacture method for insulated gate bipolar transistor, is characterized in that: comprise,
There is provided the Semiconductor substrate of the first conduction type, this Semiconductor substrate has the first interarea and the second interarea;
The ion implantation of active area photoetching and the first conduction type is carried out in the Semiconductor substrate of the first conduction type;
Form the base of the second conduction type at active area first interarea of the Semiconductor substrate of the first conduction type and outside the interarea of active area first, form the protection terminal of the second conduction type;
The residue first interarea structure of insulated gate bipolar transistor is formed based on the base formed at the first interarea of this Semiconductor substrate;
The second interarea structure of insulated gate bipolar transistor is formed in the second interarea side of this Semiconductor substrate.
2. the manufacture method of insulated gate bipolar transistor as claimed in claim 1, is characterized in that:
The process forming described protection terminal and described base comprises:
First interarea of the Semiconductor substrate of the first conduction type generates field oxide;
Protection terminal and base photoetching, etching, the second conductive type ion inject, push away trap to form described protection terminal and described base;
First interarea of active area grows gate oxide.
3. the manufacture method of insulated gate bipolar transistor according to claim 1, is characterized in that:
The second interarea structure that described the second interarea side in this Semiconductor substrate forms insulated gate bipolar transistor comprises:
By technique for thinning back side, by thinning from the second interarea for the thick end of the Semiconductor substrate of the first conduction type;
Form the second semiconductor layer of the second conduction type towards Semiconductor substrate inside from the second interarea of the Semiconductor substrate after thinning;
Second semiconductor layer of the second conduction type forms metal level to form the second main electrode.
4. the manufacture method of insulated gate bipolar transistor according to claim 1, is characterized in that:
First conduction type is N-type, and the second conduction type is P type.
5. the manufacture method of insulated gate bipolar transistor according to claim 2, is characterized in that:
The residue first interarea structure forming insulated gate bipolar transistor based on the base formed at the first interarea of this Semiconductor substrate comprises:
Optionally in the Semiconductor substrate of the first conduction type, form the first conduction type emitter region along the surface of the base of the second conduction type;
Deposit forms dielectric layer;
Etch contact hole in the dielectric layer;
Adopt depositing metal and flatening process deposit layer of surface metal level to form the first main electrode.
6. the manufacture method of IGBT according to claim 5, is characterized in that: the Facad structure of described IGBT also comprises:
Be formed at the passivation layer outside the first main electrode described in the first interarea.
7. the manufacture method of insulated gate bipolar transistor according to claim 2, is characterized in that: described second conductive type ion injects, and the energy of ion implantation is 20KeV ~ 1MeV, and dosage is 1E11/cm
2~ 1E14/cm
2.
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| PCT/CN2014/083345 WO2015014289A1 (en) | 2013-07-31 | 2014-07-30 | Insulated-gate bipolar transistor manufacturing method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783573A (en) * | 2016-12-15 | 2017-05-31 | 中国电子科技集团公司第四十七研究所 | A kind of method for improving VDMOS device Radiation hardness |
| CN108269816A (en) * | 2018-01-19 | 2018-07-10 | 德淮半导体有限公司 | A kind of method for reducing cmos image sensor white-spot defects |
| CN110047758A (en) * | 2019-04-24 | 2019-07-23 | 贵州芯长征科技有限公司 | A kind of preparation process of low cost trench-type power semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5945692A (en) * | 1994-05-31 | 1999-08-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of fabricating same |
| CN1264164A (en) * | 1998-12-23 | 2000-08-23 | 因芬尼昂技术北美公司 | Method for formation grid oxide of metal oxide semiconductor |
| US20040061170A1 (en) * | 1995-07-31 | 2004-04-01 | Ixys Corporation | Reverse blocking IGBT |
| CN102142372A (en) * | 2010-12-24 | 2011-08-03 | 江苏宏微科技有限公司 | Preparation method of field blocking type bipolar transistor of insulated gate |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7019358B2 (en) * | 2003-07-31 | 2006-03-28 | Clare, Inc. | High voltage semiconductor device having an increased breakdown voltage relative to its on-resistance |
| JP2009194330A (en) * | 2008-02-18 | 2009-08-27 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
| JP4635067B2 (en) * | 2008-03-24 | 2011-02-16 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| JP2010109031A (en) * | 2008-10-29 | 2010-05-13 | Sanken Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| CN102800591A (en) * | 2012-08-31 | 2012-11-28 | 电子科技大学 | Preparation method for FS-IGBT device |
| CN103050523B (en) * | 2012-12-14 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | Insulated gate bipolar transistor and manufacture method thereof |
-
2013
- 2013-07-31 CN CN201310329221.9A patent/CN104347403B/en active Active
-
2014
- 2014-07-30 WO PCT/CN2014/083345 patent/WO2015014289A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5945692A (en) * | 1994-05-31 | 1999-08-31 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of fabricating same |
| US20040061170A1 (en) * | 1995-07-31 | 2004-04-01 | Ixys Corporation | Reverse blocking IGBT |
| CN1264164A (en) * | 1998-12-23 | 2000-08-23 | 因芬尼昂技术北美公司 | Method for formation grid oxide of metal oxide semiconductor |
| CN102142372A (en) * | 2010-12-24 | 2011-08-03 | 江苏宏微科技有限公司 | Preparation method of field blocking type bipolar transistor of insulated gate |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783573A (en) * | 2016-12-15 | 2017-05-31 | 中国电子科技集团公司第四十七研究所 | A kind of method for improving VDMOS device Radiation hardness |
| CN108269816A (en) * | 2018-01-19 | 2018-07-10 | 德淮半导体有限公司 | A kind of method for reducing cmos image sensor white-spot defects |
| CN110047758A (en) * | 2019-04-24 | 2019-07-23 | 贵州芯长征科技有限公司 | A kind of preparation process of low cost trench-type power semiconductor device |
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| CN104347403B (en) | 2017-11-14 |
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