CN107731898B - CSTBT device and manufacturing method thereof - Google Patents

CSTBT device and manufacturing method thereof Download PDF

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CN107731898B
CN107731898B CN201710985725.4A CN201710985725A CN107731898B CN 107731898 B CN107731898 B CN 107731898B CN 201710985725 A CN201710985725 A CN 201710985725A CN 107731898 B CN107731898 B CN 107731898B
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CN107731898A (en
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张金平
赵倩
刘竞秀
李泽宏
任敏
张波
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University of Electronic Science and Technology of China
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    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A CSTBT device and a manufacturing method thereof belong to the field of semiconductor power devices. According to the CSTBT device, the groove splitting electrode is introduced below the gate electrode to form a groove gate structure together, the P-type layer is introduced below the groove splitting electrode, and the series diode structure is arranged above the groove splitting electrode, so that the problem that the contradiction relationship exists between the forward conduction performance and the voltage resistance performance of the device caused by the fact that the doping concentration of the N-type charge storage layer is improved in the traditional CSTBT device is solved; the saturation current density is reduced, and the short-circuit safe working area of the device is improved; the grid capacitance of the device is reduced, the switching speed is increased, the switching loss is reduced, and the switching performance of the device is improved; the electric field concentration effect at the bottom of the groove is improved, so that the breakdown voltage of the device is improved; the carrier enhancement effect of the emitter terminal of the device is improved, the carrier concentration distribution of the whole N-drift region is improved, and the compromise characteristic of forward conduction voltage drop and turn-off loss is further optimized; meanwhile, the manufacturing method of the CSTBT device is compatible with the manufacturing process of the conventional CSTBT device.

Description

CSTBT device and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductor power devices, particularly relates to an Insulated Gate Bipolar Transistor (IGBT), and particularly relates to a trench gate charge storage type insulated gate bipolar transistor (CSTBT) and a manufacturing method thereof.
Background
Insulated Gate Bipolar Transistors (IGBTs) are widely used in various fields such as traffic, communication, household appliances, aerospace, and the like as one of the core electronic components in modern power electronic circuits. An Insulated Gate Bipolar Transistor (IGBT) is a novel power electronic device formed by compounding an insulated field effect transistor (MOSFET) and a Bipolar Junction Transistor (BJT), and can be equivalent to the MOSFET driven by the bipolar junction transistor. The IGBT mixes the working mechanism of the MOSFET structure and the bipolar junction transistor, has the advantages of easy driving of the MOSFET, low input impedance and high switching speed, and also has the advantages of high on-state current density, low on-state voltage reduction, low loss and good stability of the BJT, so that the application of the IGBT improves the performance of a power electronic system. Since the invention of the IGBT, people are always working on improving the performance of the IGBT, and through twenty years of development, six generations of IGBT device structures are proposed successively to continuously improve the performance of the device. According to the sixth generation IGBT structure, a trench gate charge storage type insulated gate bipolar transistor (CSTBT), a hole potential barrier is introduced below a P-type base region by introducing an N-type charge storage layer with higher doping concentration and certain thickness below the P-type base region, so that the hole concentration of a device close to an emitter terminal is greatly improved, the electron concentration of the device is greatly increased according to the electric neutral requirement, the carrier concentration distribution of the whole N-drift region is improved, the conductivity modulation effect of the N-drift region is enhanced, and the IGBT obtains lower forward conduction voltage drop and better compromise relationship between the forward conduction voltage drop and turn-off loss. The higher the doping concentration of the N-type charge storage layer is, the greater the CSTBT conductivity modulation effect is improved, and the better the forward conduction characteristic of the device is. However, with the increasing doping concentration of the N-type charge storage layer, the breakdown voltage of the CSTBT device is remarkably reduced. In the conventional csbt device structure shown in fig. 1, in order to effectively shield the adverse effect of the N-type charge storage layer and obtain a higher device withstand voltage, the following two methods are mainly adopted:
(1) a deep trench gate depth, typically such that the trench gate depth is greater than the junction depth of the N-type charge storage layer;
(2) the width of the unit cell is small, namely the channel density of the MOS structure is improved to ensure that the distance between the groove gates is as small as possible;
while the method (1) is implemented, the gate-emitter capacitance and the gate-collector capacitance are increased, and the switching process of the IGBT is essentially a process of charging/discharging the gate capacitance, so that the increase of the gate capacitance increases the charging/discharging time, and further, the switching speed is reduced. Therefore, the deep trench gate depth can reduce the switching speed of the device, increase the switching loss of the device and influence the compromise characteristic of the conduction voltage drop and the switching loss of the device; the implementation of the mode (2) will increase the gate capacitance of the device, resulting in the reduction of the switching speed and the increase of the switching loss of the device, and affecting the compromise characteristics of the conduction voltage drop and the switching loss of the device, and will also increase the saturation current density of the device, and make the short-circuit safe working area of the device worse. In addition, a gate oxide layer in a trench gate structure is formed in a trench through one-time thermal oxidation, in order to guarantee a certain threshold voltage, the thickness of the whole gate oxide layer is required to be smaller, however, the size of an MOS capacitor is inversely proportional to the thickness of the oxide layer, so that the thickness of the thin gate oxide layer in the traditional CSTBT device can obviously increase the gate capacitance of the device, and meanwhile, the electric field concentration effect at the bottom of the trench can reduce the breakdown voltage of the device, so that the reliability of the device is poor.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the trench gate charge storage type insulated gate bipolar transistor with excellent comprehensive performance and the manufacturing method thereof are provided, and the problem of contradiction between the forward conduction performance and the voltage resistance performance of a device caused by improving the doping concentration of an N-type charge storage layer in the traditional CSTBT device is solved by reasonably optimizing the structure of the device on the premise of ensuring certain depth of a device trench and density of a trench MOS structure; the saturation current density of the device is reduced, and the short-circuit safe working area of the device is improved; the electric field concentration effect at the bottom of the groove is improved, and the breakdown voltage of the device is improved; the grid capacitance of the device is reduced, the switching speed of the device is improved, and the switching loss is reduced; the carrier enhancement effect of the emitter terminal of the device is further improved, the carrier concentration distribution of the whole N-drift region is improved, and the compromise characteristic of forward conduction voltage drop and switching loss is further optimized; except that the manufacturing method of the device of the invention is compatible with the manufacturing process of the existing CSTBT device.
In order to achieve the purpose, the invention provides the following technical scheme:
on one hand, the invention provides a device structure of a CSTBT device, which is specifically described in the technical scheme I and the technical scheme II:
the first technical scheme is as follows:
a CSTBT device, the cellular structure of which comprises: the device comprises a collector structure, a drift region structure, an emitter structure and a trench gate structure; the collector structure comprises a P + collector region 12 and a collector metal 13 positioned on the lower surface of the P + collector region 12; the drift region structure comprises an N-type electric field stop layer 11 and an N-type drift region layer 10 positioned on the upper surface of the N-type electric field stop layer 11, wherein the N-type electric field stop layer 11 is positioned on the upper surface of a P + collector region 12; the trench gate structure penetrates into the N-type drift region 10 along the vertical direction of the device, the emitter structure is positioned on one side of the trench gate structure and connected with the trench gate structure, and the emitter structure comprises emitter metal 1, an N + emitter region 3, a P + contact region 4, a P-type base region 5 and an N-type charge storage layer 6; the N-type charge storage layer 6 is positioned between the P-type base region 5 and the N-type drift region layer 10, the N + emitter region 3 and the P + contact region 4 are mutually contacted and are arranged on the top layer of the P-type base region 5 side by side, the P + contact region 4 and the N + emitter region 3 are connected with the emitter metal 1 above, and the N + emitter region 3 is connected with the trench gate structure; the P-type body region 9 is positioned at one side of the trench gate structure and connected with the trench gate structure, and the junction depth of the P-type body region 9 is greater than that of the N-type drift region 10; the trench gate structure includes: the gate dielectric layer 7 and the gate electrode 8 are characterized in that: the trench gate structure further includes: a trench split electrode 14 and a trench split electrode dielectric layer 15; the groove splitting electrode 14 is in an L shape and is arranged by half surrounding the gate electrode 8; the depth of the gate electrode 8 is larger than the junction depth of the P-type base region 5 and smaller than the junction depth of the N-type charge storage layer 6, the gate electrode 8 is connected with the N + emission region 3, the P + emission region 4, the P-type base region 5 and the N-type charge storage layer 6 on one side through the gate dielectric layer 7 on the side face, and the gate electrode 8 is connected with the groove split electrode 14 through the gate dielectric layers 7 on the side face and the bottom face; the depth of the groove splitting electrode 14 is greater than the depth of the junction depth of the N-type charge storage layer 6, and the groove splitting electrode 14 is respectively connected with the P-type body region 9 and the N-type drift region 10 through groove splitting electrode medium layers 15 on two sides; a first dielectric layer 21 connected with the P-type body region 9 and the groove split electrode dielectric layer 15 on the near side of the P-type body region; the upper surfaces of the gate electrode 8, the gate dielectric layer 7 and part of the trench splitting electrode 14 are also provided with a second dielectric layer 22, and the upper surfaces of the second dielectric layer 22 and part of the trench splitting electrode 14 are also provided with a series diode structure connected with the metal emitter 1; the trench splitting electrode 14 also has a P-type layer 17 connected to it below, the width of the P-type layer 17 being greater than the width of the trench.
Further, the series diode structure in the invention adopts a PN junction diode, a schottky diode or a zener diode structure. When the PN junction diode and the Schottky diode are adopted, the anode/cathode connection modes of the diodes are the same, and the specific details are shown in the embodiment, and the number of the serially connected diode structures can be 1, 2 or more; when the zener diode structure is adopted, the anode/cathode connection of the diode is opposite to the connection of the two diode structures of the PN junction diode and the schottky diode, and it is generally sufficient to adopt one zener diode structure.
According to an embodiment of the present invention, the series diode structure of the present invention includes: the diode comprises a first P-type doped region 1601, a first N-type doped region 1602, a second P-type doped region 1603 and a second N-type doped region 1604, wherein the first P-type doped region 1601 is adjacent to and in contact with the first N-type doped region 1602 to form a first PN junction diode, and the second P-type doped region 1603 is adjacent to and in contact with the second N-type doped region 1604 to form a second PN junction diode; wherein: a first P-type doped region 1601 is located on the upper surface of the trench splitting electrode 14, and a first N-type doped region 1602, a second P-type doped region 1603 and a second N-type doped region 1604 are located on the upper surface of the second dielectric layer 22; the first N-type doped region 1602 and the second P-type doped region 1603 are connected through a floating electrode 18, and the second N-type doped region 1604 is connected to the metal emitter 1.
Further, the junction depth of the P-type body region 9 in the present invention is greater than or equal to the trench depth of the trench structure.
Further, the N-type drift region structure is an NPT structure or an FS structure.
Furthermore, the semiconductor material of the IGBT device adopts Si, SiC, GaAs or GaN, the groove filling material adopts polycrystalline Si, SiC, GaAs or GaN, and each part can adopt the same material or different material combinations.
The second technical scheme is as follows:
a CSTBT device, the cellular structure of which comprises: the device comprises a collector structure, a drift region structure, an emitter structure and a trench gate structure; the collector structure comprises a P + collector region 12 and a collector metal 13 positioned on the lower surface of the P + collector region 12; the drift region structure comprises an N-type electric field stop layer 11 and an N-type drift region layer 10 positioned on the upper surface of the N-type electric field stop layer 11, wherein the N-type electric field stop layer 11 is positioned on the upper surface of a P + collector region 12; the trench gate structure is a trench gate structure, the trench gate structure penetrates into the N-type drift region 10 along the vertical direction of the device to form a trench, and the emitter structures are located on two sides of the trench gate structure and connected with the trench gate structure; the emitter structure comprises an emitter metal 1, an N + emitter region 3, a P + contact region 4, a P-type base region 5 and an N-type charge storage layer 6; the N-type charge storage layer 6 is positioned between the P-type base region 5 and the N-type drift region layer 10, the N + emitter region 3 and the P + contact region 4 are mutually contacted and are arranged on the top layer of the P-type base region 5 side by side, the P + contact region 4 and the N + emitter region 3 are connected with the emitter metal 1 above, and the N + emitter region 3 is connected with the trench gate structure; the method is characterized in that: the trench gate structure includes: a first gate electrode 81, a second gate electrode 82, a gate dielectric layer 7, a trench split electrode 14 and a trench split electrode dielectric layer 15; the trench split electrode 14 is provided in an inverted "T" shape, and is provided so as to half surround the first gate electrode 81 and the second gate electrode 82, respectively; the depths of the first gate electrode 81 and the second gate electrode 82 are greater than the junction depth of the P-type base region 5 and less than the junction depth of the N-type charge storage layer 6, the first gate electrode 81 and the second gate electrode 82 are connected with the N + emission region 3, the P + emission region 4, the P-type base region 5 and the N-type charge storage layer 6 on one side through the gate dielectric layer 7 on the side surface, and the first gate electrode 81 and the second gate electrode 82 are connected with the trench split electrode 14 through the gate dielectric layers 7 on the side surface and the bottom surface; the depth of the groove splitting electrode 14 is greater than the depth of the junction depth of the N-type charge storage layer 6, and the groove splitting electrode 14 is connected with the N-type charge storage layer 6 and the N-type drift region 10 through groove splitting electrode dielectric layers 15 on two sides; the upper surfaces of the first gate electrode 81 and the gate dielectric layers 7 on the two sides are also provided with a third dielectric layer 23, the upper surfaces of the second gate electrode 82, the gate dielectric layers 7 and part of the groove split electrode 14 are also provided with a fourth dielectric layer 24, and the upper surfaces of the second dielectric layer 22 and part of the groove split electrode 14 are also provided with a series diode structure connected with the metal emitter 1; the trench splitting electrode 14 also has a P-type layer 17 connected to it below, the width of the P-type layer 17 being greater than the width of the trench.
Further, the series diode structure in the invention adopts a PN junction diode, a schottky diode or a zener diode structure. When the PN junction diode and the Schottky diode are adopted, the anode/cathode connection modes of the diodes are the same, and the specific details are shown in the embodiment, and the number of the serially connected diode structures can be 1, 2 or more; when the zener diode structure is adopted, the anode/cathode connection of the diode is opposite to the connection of the two diode structures of the PN junction diode and the schottky diode, and it is generally sufficient to adopt one zener diode structure.
According to an embodiment of the present invention, the series diode structure of the present invention includes: the diode comprises a first P-type doped region 1601, a first N-type doped region 1602, a second P-type doped region 1603 and a second N-type doped region 1604, wherein the first P-type doped region 1601 is adjacent to and in contact with the first N-type doped region 1602 to form a first PN junction diode, and the second P-type doped region 1603 is adjacent to and in contact with the second N-type doped region 1604 to form a second PN junction diode; wherein: a first P-type doped region 1601 is located on the upper surface of the trench splitting electrode 14, and a first N-type doped region 1602, a second P-type doped region 1603 and a second N-type doped region 1604 are located on the upper surface of the second dielectric layer 22; the first N-type doped region 1602 and the second P-type doped region 1603 are connected through a floating electrode 18, and the second N-type doped region 1604 is connected to the metal emitter 1.
Further, the junction depth of the P-type body region 9 in the present invention is greater than or equal to the trench depth of the trench structure.
Further, the N-type drift region structure is an NPT structure or an FS structure.
Furthermore, the semiconductor material of the IGBT device adopts Si, SiC, GaAs or GaN, the groove filling material adopts polycrystalline Si, SiC, GaAs or GaN, and each part can adopt the same material or different material combinations.
In another aspect, the present invention further provides a method for manufacturing a CSTBT device, comprising the steps of:
step 1: an N-type lightly doped monocrystalline silicon wafer is used as an N-type drift region 10 of a device, a protective layer is deposited on the surface of the silicon wafer, a window is photoetched, and a first groove is obtained by etching at the middle position of the N-type drift region 10;
step 2: growing a field oxide layer on the surface of a silicon wafer, photoetching to obtain an active region, then growing a pre-oxide layer, and then injecting P-type impurities into the N-type drift region 10 below the first groove through ions and carrying out annealing treatment to obtain a P-type layer 17; then, injecting N-type impurities into the N-type drift region 10 on one side of the first groove through ions to obtain an N-type charge storage layer 6, wherein the junction depth of the N-type charge storage layer 6 is smaller than the depth of the groove structure; respectively implanting P-type impurities above the N-type drift region 10 and the N-type charge storage layer 6 on the other side of the first groove through ions, and performing annealing treatment to sequentially obtain a P-type base region 5 and a P-type body region 9;
and step 3: forming a dielectric layer on the inner wall of the first groove, etching the dielectric layer on the bottom wall of the first groove to expose the P-type layer 17 below the first groove, depositing polycrystalline silicon in the first groove, etching part of the polycrystalline silicon and part of the dielectric layer in the first groove by adopting a photoetching process to form a second groove, wherein the depth of the second groove is greater than the junction depth of the P-type base region 5 and less than the junction depth of the N-type charge storage layer 6, the rest polycrystalline silicon is used as a groove splitting electrode 14, and the rest dielectric layer is used as a groove splitting electrode dielectric layer 15;
and 4, step 4: forming a gate dielectric layer 7 on the inner wall of the second groove, and then depositing polycrystalline silicon in the second groove to form a gate electrode 8;
and 5: respectively injecting N-type impurities and P-type impurities into the top layer of the P-type base region 5 by adopting photoetching and ion injection processes to obtain an N + emitter region 3 and a P + emitter region 4, wherein the N + emitter region 3 and the P + emitter region 4 are mutually contacted and arranged side by side, and the N + emitter region 3 is connected with a side gate dielectric layer 7;
step 6: depositing on the surface of the device, and forming a first dielectric layer 21 on the upper surface of the trench split electrode dielectric layer 15 positioned in the P-type body region 9 and the close side thereof and a second dielectric layer 22 on the upper surfaces of the gate electrode 8, the gate dielectric layer 7 and part of the trench split electrode 14 by adopting photoetching and etching processes;
and 7: epitaxially growing an N-type layer on the surface of the device, and forming a series diode structure above the partial groove split electrode 14 and the second dielectric layer 22 by adopting photoetching, ion implantation process and annealing process;
and 8: depositing metal on the surface of the device, and respectively forming emitter metal 1 on the upper surfaces of the N + emitting region 3 and the P + emitting region 4 and forming a floating electrode 18 between two adjacent PN junction diodes in a series diode structure by adopting photoetching and etching processes;
and step 9: and turning over the silicon wafer, reducing the thickness of the silicon wafer, injecting N-type impurities into the back of the silicon wafer, annealing to manufacture an N-type field stop layer 11 of the device, injecting P-type impurities into the back of the N-type field stop layer 11 to form a P-type collector region 12, and depositing metal on the back to form collector metal 13.
Furthermore, in step 2 of the present invention, a photolithography step can be added to form the N-type charge storage layer 6, the P-type base region 5, the P-type body region 9 and the P-type layer 17 by four times.
According to the invention, the groove splitting electrode is introduced into the groove gate structure, the series diode structure is formed above the groove splitting electrode, and the P-type layer is formed below the groove splitting electrode, so that the working principle of the device is optimized, and the method comprises the following steps:
(I) in a device blocking state:
the PN junction formed by the P type body region 9 and the P type layer 17 and the N-drift region 10 below the trench split electrode 14 is reversely biased, and due to the charge shielding effect provided by the lateral expansion of the P type layer 17, the N type drift region 10 below the N type charge storage layer 6 is fully depleted before the device is broken down, so that almost all reverse voltage is borne by the N type drift region, the breakdown voltage of the device is not influenced while the doping concentration of the charge storage layer 6 is improved, and the contradiction between the forward conduction characteristic and the withstand voltage of the traditional CSTBT structure is overcome. In addition, the thick trench split electrode dielectric layer 15 can further reduce the electric field at the bottom of the trench gate, improve the electric field concentration effect at the bottom of the trench, improve the breakdown voltage of the device, and improve the reliability of the device.
(II) when the device is in forward conduction:
the potential of the P-type layer 17 under the split electrode 14 increases with the increase of the voltage of the collector metal 13, and when the IGBT is in a normal on-state, the potential of the P-type layer 17 is lower than the on-state voltage drop V of the series diode structure because the voltage of the collector metal 13 is lowerDCNo current flows through the diode series structure, and the device characteristics are the same as those of the traditional CSTBT structure; when the IGBT is in a short-circuit state, the potential of the P-type layer 17 rises to exceed the conduction voltage drop V of the series diode structure due to the large voltage of the collector metal 13DCAt this time, the series diode structure is conducted, so that the potential of the P-type layer 17 is clamped at VDCTherefore, the device channel voltage is clamped at a smaller value, the saturation current density of the IGBT device is reduced, and the short-circuit safe working area characteristic of the device is improved. Meanwhile, due to the existence of the groove splitting electrode 14, the channel density of the IGBT is reduced under the conditions of certain groove depth and certain MOS structure density, so that the saturation current density is also reduced, and the short-circuit safe working area of the device is further improved. In addition, the high doping concentration of the N-type charge storage layer 6 further improves the enhancement effect of the carrier concentration of the emitter, and further reduces the forward conduction voltage drop of the device.
(III) switching state of the device:
according to the invention, the depth of the gate electrode 8 is between the P-type base region 5 and the N-type charge storage layer 6, and the width of the gate electrode 8 is smaller than that of the N-type charge storage layer, so that on one hand, the capacitance between the gate and the emitter and the capacitance between the gate and the collector are obviously reduced under the condition of not influencing the turn-on of the device, thereby achieving the purpose of reducing the capacitance of the whole gate, improving the switching speed of the device, reducing the switching loss of the device, reducing the driving loss of the device, and enabling the device to obtain better compromise characteristics between the conduction voltage drop and the switching loss; on the other hand, the high doping concentration of the N-type charge storage layer 6 further improves the carrier concentration enhancement effect of the emitter, improves the carrier concentration distribution, and further improves the compromise characteristic between the conduction voltage drop and the switching loss. The P-type body region 9 on one side of the trench gate junction further reduces the extraction area of holes, improves the carrier enhancement effect of the emitter terminal, and further improves the carrier concentration distribution of the whole N-type drift region.
In conclusion, compared with the prior art, the invention has the beneficial effects that:
the invention provides a novel CSTBT device and a manufacturing method thereof through improvement on the structure of the traditional CSTBT device. The device structure is reasonably designed to comprehensively improve the performance of the device, the groove splitting electrodes are introduced below the gate electrodes to form a groove gate structure together, the P-type layer is introduced below the groove splitting electrodes, and the series diode structure is arranged above the groove splitting electrodes, so that in the forward conduction state of the device, when the potential of the P-type body region rises to or exceeds the conduction voltage drop VDC of the series diode structure, the series diode structure is conducted, the potential of the P-type layer is clamped at the VDC, the channel voltage of the device is clamped at a small value, the saturation current density of the device is reduced, the short-circuit safe working area is improved, and the conduction loss is reduced; under the blocking state of the device, the P-type layer transversely extends into the N-type drift region below the N-type charge storage layer to fully deplete the N-type drift region, so that almost all reverse voltage is borne by a PN junction formed by the P-type layer and the N-type drift region, the breakdown voltage of the device can be prevented from being influenced by increasing the doping concentration of the charge storage layer, and the contradiction relation between the forward conduction and the voltage resistance of the traditional CSTBT device structure is overcome; according to the invention, by reducing the depth of the gate electrode, the depth of the gate electrode is smaller than the junction depth of the N-type charge storage layer, the gate-emitter capacitance and the gate-collector capacitance are reduced, the switching speed of the device is improved, the switching loss is reduced, and the device obtains better compromise characteristics between conduction voltage drop and switching loss; according to the invention, the thick groove split electrode dielectric layer is introduced, so that the electric field concentration effect at the bottom of the groove can be improved, the breakdown voltage of the device is improved, and the reliability of the device is improved; meanwhile, due to the existence of the groove split electrode, the channel density of the IGBT is reduced under the conditions of certain groove depth and certain MOS structure density, so that the saturation current density is also reduced, and the short-circuit safe working area of the device is further improved.
Drawings
FIG. 1 is a schematic diagram of a conventional cell structure of a CSTBT device;
fig. 2 is a schematic diagram of a cell structure of a CSTBT device according to embodiment 1 of the present invention;
fig. 3 is a schematic diagram of a cell structure of a CSTBT device according to embodiment 2 of the present invention;
FIG. 4 is a schematic diagram of a cell structure of a CSTBT device according to embodiment 3 of the present invention;
in fig. 1 to 4: 1 is an emitter metal, 21 is a first dielectric layer, 22 is a second dielectric layer, 23 is a third dielectric layer, 24 is a fourth dielectric layer, 3 is an N + emitter region, 4 is a P + emitter region, 5 is a P-type base region, 6 is an N-type charge storage layer, 7 is a gate dielectric layer, 8 is a gate electrode, 81 is a first gate electrode, 82 is a second gate electrode, 9 is a P-type body region, 10 is an N-type drift region, 11 is an N-type field stop layer, 12 is a P-type collector region, 13 is a collector metal, 14 is a grip electrode, 15 is a grip electrode dielectric layer, 1601 is a first P-type doped region, 1602 is a first N-type doped region, 1603 is a second P-type doped region, 1604 is a second N-type doped region, and 18 is a floating electrode.
Fig. 5 is a schematic structural diagram of a device after forming a trench by ion implantation and then etching and forming a dielectric layer on an inner wall of the trench in the manufacturing method of embodiment 1 of the present invention;
fig. 6 is a schematic view of the device structure after depositing polysilicon in the trench in the manufacturing method of embodiment 1 of the present invention;
FIG. 7 is a schematic structural diagram of a device after trench split electrodes are formed by etching excess polysilicon and a dielectric layer in a trench in the manufacturing method of embodiment 1 of the present invention;
fig. 8 is a schematic view of the device structure after a gate dielectric layer is formed in the trench in the manufacturing method of embodiment 1 of the present invention;
fig. 9 is a schematic view of the device structure after forming a gate electrode in a trench in the manufacturing method of embodiment 1 of the present invention;
fig. 10 is a schematic view of the device structure after forming an N + emitter region and a P + emitter region in the manufacturing method of embodiment 1 of the present invention;
fig. 11 is a schematic view of the device structure after a dielectric layer is formed on the surface of the device in the manufacturing method of embodiment 1 of the present invention;
fig. 12 is a schematic view of the device structure after the series diode structure is formed on the surface of the device in the manufacturing method of embodiment 1 of the present invention;
fig. 13 is a schematic view of the device structure after forming the surface emitter electrode and the floating electrode in the manufacturing method of embodiment 1 of the present invention;
fig. 14 is a schematic view of a device structure formed after completion of all the steps in the manufacturing method of embodiment 1 of the present invention;
fig. 15 is a schematic view of the device structure after a gate dielectric layer is formed in the trench in the manufacturing method of embodiment 2 of the present invention;
fig. 16 is a schematic view of the device structure after forming a gate electrode in the trench in the manufacturing method of embodiment 2 of the present invention;
FIG. 17 is a schematic diagram of the device structure after forming the gripping electrodes by etching the excess polysilicon and dielectric layers in the trenches in the method of embodiment 3 of the present invention;
fig. 18 is a schematic view of the device structure after the gate dielectric layer is formed in the manufacturing method of embodiment 3 of the invention;
fig. 19 is a schematic view of the device structure after the gate electrode is formed in the manufacturing method of embodiment 3 of the invention;
Detailed Description
The principles and features of the present invention are described in detail below with reference to the accompanying drawings and specific embodiments:
example 1:
in this embodiment, a CSTBT device as shown in fig. 2 is proposed, wherein the cell structure includes: the device comprises a collector structure, a drift region structure, an emitter structure and a trench gate structure; the collector structure comprises a P + collector region 12 and a collector metal 13 positioned on the lower surface of the P + collector region 12; the drift region structure comprises an N-type electric field stop layer 11 and an N-type drift region layer 10 positioned on the upper surface of the N-type electric field stop layer 11, wherein the N-type electric field stop layer 11 is positioned on the upper surface of a P + collector region 12; the trench gate structure is a trench gate structure, the trench gate structure penetrates into the N-type drift region 10 along the vertical direction of the device to form a trench, the emitter structure is positioned on one side of the trench gate structure and connected with the trench gate structure, and the emitter structure comprises emitter metal 1, an N + emitter region 3, a P + contact region 4, a P-type base region 5 and an N-type charge storage layer 6; the N-type charge storage layer 6 is positioned between the P-type base region 5 and the N-type drift region layer 10, the N + emitter region 3 and the P + contact region 4 are mutually contacted and are arranged on the top layer of the P-type base region 5 side by side, the P + contact region 4 and the N + emitter region 3 are connected with the emitter metal 1 above, and the N + emitter region 3 is connected with the trench gate structure; the P-type body region 9 is positioned at one side of the trench gate structure and connected with the trench gate structure, and the junction depth of the P-type body region 9 is greater than that of the N-type drift region 10; the trench gate structure includes: the gate dielectric layer 7 and the gate electrode 8 are characterized in that: the trench gate structure further includes: a trench split electrode 14 and a trench split electrode dielectric layer 15; the groove splitting electrode 14 is in an L shape and is arranged by half surrounding the gate electrode 8; the depth of the gate electrode 8 is larger than the junction depth of the P-type base region 5 and smaller than the junction depth of the N-type charge storage layer 6, the gate electrode 8 is connected with the N + emission region 3, the P + emission region 4, the P-type base region 5 and the N-type charge storage layer 6 on one side through the gate dielectric layer 7 on the side face, and the gate electrode 8 is connected with the groove split electrode 14 through the gate dielectric layers 7 on the side face and the bottom face; the depth of the groove splitting electrode 14 is greater than the depth of the junction depth of the N-type charge storage layer 6, and the groove splitting electrode 14 is respectively connected with the P-type body region 9 and the N-type drift region 10 through groove splitting electrode medium layers 15 on two sides; a first dielectric layer 21 connected with the P-type body region 9 and the groove split electrode dielectric layer 15 on the near side of the P-type body region; the upper surfaces of the gate electrode 8, the gate dielectric layer 7 and part of the trench splitting electrode 14 are further provided with a second dielectric layer 22, the upper surfaces of the second dielectric layer 22 and part of the trench splitting electrode 14 are further provided with a series diode structure connected with the metal emitter 1, and the series diode structure in this embodiment includes: the diode comprises a first P-type doped region 1601, a first N-type doped region 1602, a second P-type doped region 1603 and a second N-type doped region 1604, wherein the first P-type doped region 1601 is adjacent to and in contact with the first N-type doped region 1602 to form a first PN junction diode, and the second P-type doped region 1603 is adjacent to and in contact with the second N-type doped region 1604 to form a second PN junction diode; wherein: a first P-type doped region 1601 is located on the upper surface of the trench splitting electrode 14, and a first N-type doped region 1602, a second P-type doped region 1603 and a second N-type doped region 1604 are located on the upper surface of the second dielectric layer 22; the first N-type doped region 1602 and the second P-type doped region 1603 are connected through a floating electrode 18, and the second N-type doped region 1604 is connected with the metal emitter 1; the trench splitting electrode 14 also has a P-type layer 17 connected to it below, the width of the P-type layer 17 being greater than the width of the trench.
Example 2:
this example presents a CSTBT device as shown in fig. 3, which is the same as example 1 except that the thickness of the trench split electrode dielectric layer 15 is greater than that of the gate dielectric layer 7.
Compared with embodiment 1, on one hand, the gate capacitance can be further reduced, the switching speed of the device is increased, the switching loss is reduced, on the other hand, the electric field concentration effect at the bottom of the trench can be further improved, the breakdown voltage of the device is increased, and the reliability of the device is improved.
Example 3:
in this embodiment, a CSTBT device as shown in fig. 4 is proposed, wherein the cell structure includes: the device comprises a collector structure, a drift region structure, an emitter structure and a trench gate structure; the collector structure comprises a P + collector region 12 and a collector metal 13 positioned on the lower surface of the P + collector region 12; the drift region structure comprises an N-type electric field stop layer 11 and an N-type drift region layer 10 positioned on the upper surface of the N-type electric field stop layer 11, wherein the N-type electric field stop layer 11 is positioned on the upper surface of a P + collector region 12; the trench gate structure is a trench gate structure, the trench gate structure penetrates into the N-type drift region 10 along the vertical direction of the device to form a trench, and the emitter structures are located on two sides of the trench gate structure and connected with the trench gate structure; the emitter structure comprises an emitter metal 1, an N + emitter region 3, a P + contact region 4, a P-type base region 5 and an N-type charge storage layer 6; the N-type charge storage layer 6 is positioned between the P-type base region 5 and the N-type drift region layer 10, the N + emitter region 3 and the P + contact region 4 are mutually contacted and are arranged on the top layer of the P-type base region 5 side by side, the P + contact region 4 and the N + emitter region 3 are connected with the emitter metal 1 above, and the N + emitter region 3 is connected with the trench gate structure; the method is characterized in that: the trench gate structure includes: a first gate electrode 81, a second gate electrode 82, a gate dielectric layer 7, a trench split electrode 14 and a trench split electrode dielectric layer 15; the trench split electrode 14 is provided in an inverted "T" shape, and is provided so as to half surround the first gate electrode 81 and the second gate electrode 82, respectively; the depths of the first gate electrode 81 and the second gate electrode 82 are greater than the junction depth of the P-type base region 5 and less than the junction depth of the N-type charge storage layer 6, the first gate electrode 81 and the second gate electrode 82 are connected with the N + emission region 3, the P + emission region 4, the P-type base region 5 and the N-type charge storage layer 6 on one side through the gate dielectric layer 7 on the side surface, and the first gate electrode 81 and the second gate electrode 82 are connected with the trench split electrode 14 through the gate dielectric layers 7 on the side surface and the bottom surface; the depth of the groove splitting electrode 14 is greater than the depth of the junction depth of the N-type charge storage layer 6, and the groove splitting electrode 14 is connected with the N-type charge storage layer 6 and the N-type drift region 10 through groove splitting electrode dielectric layers 15 on two sides; the upper surfaces of the first gate electrode 81 and the gate dielectric layers 7 on the two sides are further provided with a third dielectric layer 23, the upper surfaces of the second gate electrode 82, the gate dielectric layers 7 and a part of the trench split electrode 14 are further provided with a fourth dielectric layer 24, and the upper surfaces of the second dielectric layer 22 and a part of the trench split electrode 14 are further provided with a series diode structure connected with the metal emitter 1, wherein the series diode structure in this embodiment includes: the diode comprises a first P-type doped region 1601, a first N-type doped region 1602, a second P-type doped region 1603 and a second N-type doped region 1604, wherein the first P-type doped region 1601 is adjacent to and in contact with the first N-type doped region 1602 to form a first PN junction diode, and the second P-type doped region 1603 is adjacent to and in contact with the second N-type doped region 1604 to form a second PN junction diode; wherein: a first P-type doped region 1601 is located on the upper surface of the trench splitting electrode 14, and a first N-type doped region 1602, a second P-type doped region 1603 and a second N-type doped region 1604 are located on the upper surface of the second dielectric layer 22; the first N-type doped region 1602 and the second P-type doped region 1603 are connected through a floating electrode 18, and the second N-type doped region 1604 is connected with the metal emitter 1; the trench splitting electrode 14 also has a P-type layer 17 connected to it below, the width of the P-type layer 17 being greater than the width of the trench.
Example 4:
the present embodiment takes a CSTBT device with a 1200V voltage level as an example for explanation, and according to the common knowledge in the art, devices with different performance parameters can be prepared according to actual requirements, and specifically provides a manufacturing method of a CSTBT device, which includes the following steps:
step 1: an N-type lightly doped monocrystalline silicon wafer is used as an N-type drift region 10 of the device, the thickness of the selected silicon wafer is 300-600 um, and the doping concentration is 1013～1014Per cm3(ii) a Depositing a protective layer on the surface of the silicon wafer, photoetching a window, and etching the middle position of the N-type drift region 10 to obtain a first groove;
step 2: growing a field oxide layer on the surface of a silicon wafer, photoetching to obtain an active region, then growing a pre-oxide layer, implanting P-type impurities in an N-type drift region 10 below a first groove by ions, and annealing to obtain a P-type layer 17, wherein the energy of ion implantation is 60-120 keV, and the implantation dosage is 10 keV13～1014Per cm2Annealing at 1100-1150 deg.c for 10-30 min; then, N-type impurities are implanted into the N-type drift region 10 on one side of the first groove through ions, the energy of the ion implantation is 200-500 keV, and the implantation dosage is 1013～1014Per cm2Preparing an N-type charge storage layer 6, wherein the junction depth of the N-type charge storage layer 6 is smaller than the depth of the groove structure; respectively implanting P-type impurities above the N-type drift region 10 and the N-type charge storage layer 6 on the other side of the first groove by ions, and carrying out annealing treatment, wherein the energy of ion implantation is 60-120 keV, and the implantation dosage is 1013～1014Per cm2Annealing at 1100-1150 ℃ for 10-30 minutes to sequentially obtain a P-type base region 5 and a P-type body region 9;
and step 3: forming oxide layers on the inner walls of the first trenches under an O2 atmosphere at 1050-1150 ℃, etching the oxide layers on the bottom walls of the first trenches to expose the underlying P-type layer 17, depositing polysilicon in the first trenches at 750-950 ℃, and etching a portion of the polysilicon and a portion of the dielectric layers in the first trenches by photolithography to form second trenches, wherein the depth of the second trenches is greater than the junction depth of the P-type base region 5 and less than the junction depth of the N-type charge storage layer 6, the remaining polysilicon is used as clamp electrodes 14, and the remaining dielectric layers are used as clamp electrodes 15;
and 4, step 4: forming a gate dielectric layer 7 on the inner wall of the second trench at 1050-1150 ℃ in O2 atmosphere, and then depositing polycrystalline silicon in the second trench at 750-950 ℃ to form a gate electrode 8;
and 5: respectively injecting N-type impurities and P-type impurities into the top layer of the P-type base region 5 by adopting photoetching and ion injection processes to prepare an N + emitter region 3 and a P + emitter region 4, wherein the energy of the N-type impurities injected by ions is 30-60 keV, and the injection dosage is 1015～1016Per cm2The energy of ion implantation of P-type impurity is 60-80 keV, and the implantation dosage is 1015～1016Per cm2Annealing at 900 ℃ for 20-30 minutes; the N + emission region 3 and the P + emission region 4 are in mutual contact and arranged side by side, and the N + emission region 3 is connected with the side gate dielectric layer 7;
step 6: depositing on the surface of the device, and forming a first dielectric layer 21 on the upper surface of the trench split electrode dielectric layer 15 positioned in the P-type body region 9 and the close side thereof and a second dielectric layer 22 on the upper surfaces of the gate electrode 8, the gate dielectric layer 7 and part of the trench split electrode 14 by adopting photoetching and etching processes;
and 7: epitaxially growing an N-type layer on the surface of the device, and forming a series diode structure above the partial groove split electrode 14 and the second dielectric layer 22 by adopting photoetching, ion implantation process and annealing process;
and 8: depositing metal on the surface of the device, and respectively forming emitter metal 1 on the upper surfaces of the N + emitting region 3 and the P + emitting region 4 and forming a floating electrode 18 between two adjacent PN junction diodes in a series diode structure by adopting photoetching and etching processes;
and step 9: turning over the silicon wafer, reducing the thickness of the silicon wafer, injecting N-type impurities into the back of the silicon wafer, annealing to manufacture an N-type field stop layer 11 of the device, wherein the thickness of the N-type field stop layer 11 is 15-30 microns, the ion injection energy is 1500-2000 keV, and the injection dosage is 10 keV13～1014Per cm2Annealing ofThe temperature is 1200-1250 ℃, and the time is 300-600 minutes; implanting P-type impurities into the back of the N-type field stop layer 11 to form a P-type collector region 12 with an implantation energy of 40-60 keV and an implantation dose of 1012～1013Per cm2In H2And N2Carrying out back annealing in a mixed atmosphere at the temperature of 400-450 ℃ for 20-30 minutes; and depositing metal on the back to form a collector metal 13, thus finishing the preparation of the trench gate charge storage type IGBT.
Furthermore, in step 2 of the present invention, a photolithography step can be added to form the N-type charge storage layer 6, the P-type base region 5, the P-type body region 9 and the P-type layer 17 by four times.
Further, in step 4 of the present invention, the device structure shown in fig. 3 can be obtained by controlling the reaction conditions such that the thickness of the formed gate dielectric layer 7 is less than the thickness of the dielectric layer around the gripping electrodes.
Furthermore, in step 3 of the present invention, two symmetrical trenches are formed at two ends of the polysilicon in the first trench by adding a photolithography step, and then the structures of the first gate 81 and the second gate 82 are prepared, so as to obtain the device structure shown in fig. 4.
Furthermore, the sequence of the process steps for etching the groove and the process steps for forming the P-type base region 5, the N-type charge storage layer 6 and the P-type layer 17 can be interchanged, namely, the groove can be etched in the N-type drift region 10 first and then the doping region is doped.
Further, the materials of the clamping electrode medium layer 15, the gate medium layer 7 and the clamping electrode medium layer 15 may be the same or different.
Further, the preparation of the N-type field stop layer 11 in the present invention may be omitted.
Further, the preparation of the N-type field stop layer 11 in step 9 of the present invention may be performed before the preparation of the front structure of the device; or a double-layer epitaxial material with the N-type field stop layer 11 and the N-type drift region 10 can be directly selected as a silicon wafer material for starting the process.

Claims (5)

1. A CSTBT device, the cellular structure of which comprises: the device comprises a collector structure, a drift region structure, an emitter structure and a trench gate structure; the collector structure comprises a P + collector region (12) and a collector metal (13) positioned on the lower surface of the P + collector region (12); the drift region structure comprises an N-type electric field stop layer (11) and an N-type drift region layer (10) located on the upper surface of the N-type electric field stop layer (11), wherein the N-type electric field stop layer (11) is located on the upper surface of a P + collector region (12); the trench gate structure is a trench gate structure, the trench gate structure penetrates into the N-type drift region (10) along the vertical direction of a device to form a trench, the emitter structure is positioned on one side of the trench gate structure and connected with the trench gate structure, and the emitter structure comprises emitter metal (1), an N + emitter region (3), a P + contact region (4), a P-type base region (5) and an N-type charge storage layer (6); the N-type charge storage layer (6) is positioned between the P-type base region (5) and the N-type drift region layer (10), the N + emission region (3) and the P + contact region (4) are mutually contacted and are arranged on the top layer of the P-type base region (5) side by side, the P + contact region (4) and the N + emission region (3) are connected with the upper emitter metal (1), and the N + emission region (3) is connected with the trench gate structure; the P-type body region (9) is positioned at one side of the trench gate structure and is connected with the trench gate structure, and the junction depth of the P-type body region (9) is greater than that of the P-type base region (5); the trench gate structure includes: a gate dielectric layer (7) and a gate electrode (8), characterized in that: the trench gate structure further includes: a trench split electrode (14) and a trench split electrode dielectric layer (15); the groove split electrode (14) is L-shaped and is arranged by half surrounding the gate electrode (8); the depth of the gate electrode (8) is larger than the junction depth of the P-type base region (5) and smaller than the junction depth of the N-type charge storage layer (6), the gate electrode (8) is connected with the N + emission region (3), the P + emission region (4), the P-type base region (5) and the N-type charge storage layer (6) on one side through the gate dielectric layer (7) on the side face, and the gate electrode (8) is connected with the groove split electrode (14) through the gate dielectric layers (7) on the side face and the bottom face; the depth of the groove splitting electrode (14) is greater than the depth of the junction depth of the N-type charge storage layer (6), and the groove splitting electrode (14) is respectively connected with the P-type body region (9) and the N-type drift region (10) through groove splitting electrode dielectric layers (15) on two sides; a first dielectric layer (21) connected with the P-type body region (9) and the groove split electrode dielectric layer (15) close to the P-type body region is arranged above the two dielectric layers; the upper surfaces of the gate electrode (8), the gate dielectric layer (7) and part of the trench split electrode (14) are also provided with a second dielectric layer (22), and the upper surfaces of the second dielectric layer (22) and part of the trench split electrode (14) are also provided with a series diode structure (16) connected with the metal emitter (1); and a P-type layer (17) connected with the groove splitting electrode (14) is arranged below the groove splitting electrode, and the width of the P-type layer (17) is larger than that of the groove.
2. A CSTBT device according to claim 1 wherein: the series diode structure (16) comprises: the diode comprises a first P-type doped region (1601), a first N-type doped region (1602), a second P-type doped region (1603) and a second N-type doped region (1604), wherein the first P-type doped region (1601) is adjacent to and in contact with the first N-type doped region (1602) to form a first PN junction diode, and the second P-type doped region (1603) is adjacent to and in contact with the second N-type doped region (1604) to form a second PN junction diode; wherein: the first P-type doped region (1601) is located on the upper surface of the trench splitting electrode (14), and the first N-type doped region (1602), the second P-type doped region (1603) and the second N-type doped region (1604) are located on the upper surface of the second dielectric layer (22); the first N-type doped region (1602) and the second P-type doped region (1603) are connected through a floating electrode (18), and the second N-type doped region (1604) is connected with the metal emitter (1).
3. A CSTBT device, the cellular structure of which comprises: the device comprises a collector structure, a drift region structure, an emitter structure and a trench gate structure; the collector structure comprises a P + collector region (12) and a collector metal (13) positioned on the lower surface of the P + collector region (12); the drift region structure comprises an N-type electric field stop layer (11) and an N-type drift region layer (10) located on the upper surface of the N-type electric field stop layer (11), wherein the N-type electric field stop layer (11) is located on the upper surface of a P + collector region (12); the groove gate structure is a groove gate structure, the groove gate structure penetrates into the N-type drift region (10) along the vertical direction of the device to form a groove, and the emitter structures are located on two sides of the groove gate structure and connected with the groove gate structure; the emitter structure comprises an emitter metal (1), an N + emitter region (3), a P + contact region (4), a P-type base region (5) and an N-type charge storage layer (6); the N-type charge storage layer (6) is positioned between the P-type base region (5) and the N-type drift region layer (10), the N + emission region (3) and the P + contact region (4) are mutually contacted and are arranged on the top layer of the P-type base region (5) side by side, the P + contact region (4) and the N + emission region (3) are connected with the upper emitter metal (1), and the N + emission region (3) is connected with the trench gate structure; the method is characterized in that: the trench gate structure includes: the gate structure comprises a first gate electrode (81), a second gate electrode (82), a gate dielectric layer (7), a trench split electrode (14) and a trench split electrode dielectric layer (15); the trench splitting electrode (14) is arranged in an inverted T shape and is respectively arranged to half surround the first gate electrode (81) and the second gate electrode (82); the depth of the first gate electrode (81) and the depth of the second gate electrode (82) are larger than the junction depth of the P-type base region (5) and smaller than the junction depth of the N-type charge storage layer (6), the first gate electrode (81) and the second gate electrode (82) are connected with the N + emission region (3), the P + emission region (4), the P-type base region (5) and the N-type charge storage layer (6) on one side through the gate dielectric layers (7) on the side faces, and the first gate electrode (81) and the second gate electrode (82) are connected with the groove splitting electrode (14) through the gate dielectric layers (7) on the side faces and the bottom face; the depth of the groove splitting electrode (14) is larger than the depth of the junction depth of the N-type charge storage layer (6), and the groove splitting electrode (14) is connected with the N-type charge storage layer (6) and the N-type drift region (10) through groove splitting electrode dielectric layers (15) on two sides; the upper surfaces of the first gate electrode (81) and the gate dielectric layers (7) on the two sides are also provided with a third dielectric layer (23), the upper surfaces of the second gate electrode (82), the gate dielectric layers (7) and part of the groove split electrodes (14) are also provided with a fourth dielectric layer (24), and the upper surfaces of the fourth dielectric layer (24) and part of the groove split electrodes (14) are also provided with a series diode structure (16) connected with the metal emitter (1); and a P-type layer (17) connected with the groove splitting electrode (14) is arranged below the groove splitting electrode, and the width of the P-type layer (17) is larger than that of the groove.
4. A method for manufacturing a CSTBT device is characterized by comprising the following steps:
step 1: an N-type lightly doped monocrystalline silicon wafer is used as an N-type drift region (10) of a device, a protective layer is deposited on the surface of the silicon wafer, a window is photoetched, and a first groove is obtained by etching at the middle position of the N-type drift region (10);
step 2: growing a field oxide layer on the surface of a silicon wafer, photoetching to obtain an active region, then growing a pre-oxide layer, and then injecting P-type impurities into an N-type drift region (10) below a first groove through ions and carrying out annealing treatment to obtain a P-type layer (17); then, injecting N-type impurities into the N-type drift region (10) on one side of the first groove through ions to obtain an N-type charge storage layer (6), wherein the junction depth of the N-type charge storage layer (6) is smaller than the depth of the groove structure; respectively implanting P-type impurities into the upper parts of the N-type drift region (10) and the N-type charge storage layer (6) on the other side of the first groove through ions and carrying out annealing treatment to sequentially prepare a P-type base region (5) and a P-type body region (9);
and step 3: forming a dielectric layer on the inner wall of the first groove, etching the dielectric layer on the bottom wall of the first groove to expose a P-type layer (17) below, depositing polycrystalline silicon in the first groove, etching part of the polycrystalline silicon and part of the dielectric layer in the first groove by adopting a photoetching process to form a second groove, wherein the depth of the second groove is greater than the junction depth of the P-type base region (5) and less than the junction depth of the N-type charge storage layer (6), the rest polycrystalline silicon is used as a groove splitting electrode (14), and the rest dielectric layer is used as a groove splitting electrode dielectric layer (15);
and 4, step 4: forming a gate dielectric layer (7) on the inner wall of the second groove, and then depositing polycrystalline silicon in the second groove to form a gate electrode (8);
and 5: respectively injecting N-type impurities and P-type impurities into the top layer of the P-type base region (5) by adopting photoetching and ion injection processes to obtain an N + emitter region (3) and a P + emitter region (4), wherein the N + emitter region (3) and the P + emitter region (4) are mutually contacted and arranged side by side, and the N + emitter region (3) is connected with a side gate dielectric layer (7);
step 6: depositing on the surface of the device, and forming a first dielectric layer (21) on the upper surface of the P-type body region (9) and the trench split electrode dielectric layer (15) close to the P-type body region by adopting photoetching and etching processes, and a second dielectric layer (22) on the upper surfaces of the gate electrode (8), the gate dielectric layer (7) and part of the trench split electrode (14);
and 7: epitaxially growing an N-type layer on the surface of the device, and forming a series diode structure (16) above the partial groove split electrode (14) and the second dielectric layer (22) by adopting photoetching, ion implantation process and annealing process;
and 8: depositing metal on the surface of the device, and respectively forming emitter metal (1) on the upper surfaces of the N + emitter region (3) and the P + emitter region (4) and forming a floating electrode (18) between two adjacent PN junction diodes in the series diode structure (16) by adopting photoetching and etching processes;
and step 9: and turning over the silicon wafer, reducing the thickness of the silicon wafer, injecting N-type impurities into the back of the silicon wafer, annealing to manufacture an N-type field stop layer (11) of the device, injecting P-type impurities into the back of the N-type field stop layer (11) to form a P-type collector region (12), and depositing metal on the back to form collector metal (13).
5. The method of claim 4 wherein said CSTBT device comprises: in the step 2 of the invention, an N-type charge storage layer (6), a P-type base region (5), a P-type body region (9) and a P-type layer (17) are formed by adding a photoetching step for four times respectively.
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