CN107731898A - A kind of CSTBT devices and its manufacture method - Google Patents

A kind of CSTBT devices and its manufacture method Download PDF

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CN107731898A
CN107731898A CN201710985725.4A CN201710985725A CN107731898A CN 107731898 A CN107731898 A CN 107731898A CN 201710985725 A CN201710985725 A CN 201710985725A CN 107731898 A CN107731898 A CN 107731898A
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layer
groove
electrode
dielectric layer
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CN107731898B (en
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张金平
赵倩
刘竞秀
李泽宏
任敏
张波
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University of Electronic Science and Technology of China
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    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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Abstract

A kind of CSTBT devices and its manufacture method, belong to field of semiconductor.The present invention introduces groove Split Electrode by side under the gate electrode and is collectively forming trench gate structure, P-type layer is introduced below groove Split Electrode, series diode structure is set above groove Split Electrode, solves the problems, such as to cause contradictory relation be present between device forward conduction performance and pressure-resistant performance by improving N-type charge storage layer doping concentration in traditional C/S TBT devices；Saturation current density is reduced, improves shorted devices safety operation area；The grid capacitance of device is reduced, improving switching speed reduces switching loss, improves the switch performance of device；Improve channel bottom electric field concentration effect and then improve device electric breakdown strength；The carrier enhancement effect of device emitter terminal is improved, improves the carrier concentration profile of whole N drift regions, further optimizes the compromise characteristic of forward conduction voltage drop and turn-off power loss；Meanwhile the manufacture method of device of the present invention is compatible with the manufacturing process of existing CSTBT devices.

Description

A kind of CSTBT devices and its manufacture method
Technical field
The invention belongs to semiconductor power device technology field, more particularly to a kind of insulated gate bipolar transistor (IGBT), and in particular to a kind of trench gate electric charge memory type insulated gate bipolar transistor (CSTBT) and its manufacture method.
Background technology
Insulated gate bipolar transistor (IGBT) is as one of core electron component in modern power electronic circuit, quilt It is widely used in the every field such as traffic, communication, household electrical appliance and Aero-Space.Insulated gate bipolar transistor (IGBT) is one The novel power transistor that kind insulated type FET (MOSFET) and bipolar junction transistor (BJT) are combined, can be waited Imitate the MOSFET for bipolar junction transistor driving.IGBT is mixed with the working machine of MOSFET structure and bipolar junction transistor Reason, both with the advantages of MOSFET is easy to driving, input impedance is low, switching speed is fast, have again BJT on state currents density it is big, The advantages of conduction voltage drop is low, loss is small, stability is good, thus, IGBT with the performance for improving power electronic system.From Since IGBT inventions, people are directed to improving always IGBT performance, by the development of twenties years, propose for six generations in succession IGBT device structure constantly to be lifted the performance of device.6th generation IGBT structure --- trench gate charge storage type insulated gate bipolar Transistor npn npn (CSTBT) is to be stored by being introduced below p-type base with higher-doped concentration and certain thickness N-type electric charge Layer introduces hole barrier below p-type base so that and device greatly promotes close to the hole concentration of emitter terminal, and according to electricity Neutral requirement will greatly increase electron concentration herein, improve the carrier concentration profile of whole N- drift regions, enhancing N- drifts with this The conductivity modulation effect in area is moved, IGBT is obtained lower forward conduction voltage drop and more excellent forward conduction voltage drop and shut-off The tradeoff of loss.As N-type charge storage layer doping concentration is higher, the improvement of CSTBT conductivity modulation effects is bigger, device Forward conduction characteristic is also better.However, with the continuous improvement of N-type charge storage layer doping concentration, CSTBT devices can be caused Breakdown voltage significantly reduces.In traditional C/S TBT device architectures as shown in Figure 1, in order to effectively shield N-type charge storage layer not Profit influences, and the higher device of acquisition is pressure-resistant, mainly uses the following two kinds mode：
(1) trench gate depth deep, the depth of trench gate is generally made to be more than the junction depth of N-type charge storage layer；
(2) cellular width small, that is, improving MOS structure gully density makes trench gate spacing as small as possible；
Mode (1) can increase gate-emitter electric capacity and grid-collector capacitance while implementation, and IGBT switch It is exactly the process that charge/discharge is carried out to grid capacitance on process nature, so, when the increase of grid capacitance can cause charge/discharge Between increase, in turn result in switching speed reduction.Thus, deep trench gate depth will reduce devices switch speed, increase device Switching loss, have influence on the compromise characteristic of break-over of device pressure drop and switching loss；And the implementation of mode (2) is on the one hand by enhancer The grid capacitance of part, cause devices switch speed to reduce, switching loss increase, influence the folding of break-over of device pressure drop and switching loss It middle characteristic, on the other hand will also increase the saturation current density of device, shorted devices safety operation area is deteriorated.In addition, groove Gate oxide in grid structure is formed in the trench by a thermal oxide, in order to ensure certain threshold voltage, therefore will Ask the thickness of whole gate oxide smaller, but the thickness of mos capacitance size and oxide layer is inversely proportional, this allows for tradition Thin gate oxide thickness can dramatically increase the grid capacitance of device in CSTBT devices, while the electric field of channel bottom concentrates effect The breakdown voltage of device should will be reduced, causes the reliability of device poor.
The content of the invention
The technical problems to be solved by the invention are：The trench gate electric charge memory type for providing a kind of excellent combination property is exhausted Edge grid bipolar transistor and its manufacture method, by reasonably optimizing device architecture, ensure certain device trench depth and On the premise of trench MOS structure density, solve in traditional C/S TBT devices and made by improving N-type charge storage layer doping concentration The problem of contradictory relation be present between device forward conduction performance and pressure-resistant performance；The saturation current density of device is reduced, Improve shorted devices safety operation area；Channel bottom electric field concentration effect is improved, improves device electric breakdown strength；Reduce The grid capacitance of device, device switching speed is improved, reduces switching loss；Further increase the load of device emitter terminal Sub- enhancement effect is flowed, improves the carrier concentration profile of whole N- drift regions, further optimizes forward conduction voltage drop and switch The compromise characteristic of loss；Except, the manufacture method of device of the present invention is compatible with the manufacturing process of existing CSTBT devices.
To achieve the above object, the present invention provides following technical scheme：
On the one hand the present invention provides the device architecture of CSTBT devices, specifically as described in technical scheme one and technical scheme two：
Technical scheme one：
A kind of CSTBT devices, its structure cell include：Collector structure, drift region structure, emitter structure and groove grid knot Structure；The collector structure includes P+ collecting zones 12 and the collector electrode metal 13 positioned at the lower surface of P+ collecting zones 12；The drift Plot structure includes N-type electric field trapping layer 11 and the N-type drift region layer 10 positioned at the upper surface of N-type electric field trapping layer 11, the N-type electricity Field stop layer 11 is located at the upper surface of P+ collecting zones 12；The trench gate structure penetrates N-type drift region 10 along device vertical direction In, the emitter structure be located at the side of trench gate structure and be attached thereto the emitter structure include emitter metal 1, N+ launch sites 3, P+ contact zones 4, p-type base 5 and N-type charge storage layer 6；The N-type charge storage layer 6 be located at p-type base 5 with Between N-type drift region layer 10, the N+ launch sites 3 and P+ contact zones 4 contact with each other and are arranged side by side in the top layer of p-type base 5, P+ contact zones 4 and N+ launch sites 3 are connected with top emitter metal 1, and N+ launch sites 3 are connected with trench gate structure；The p-type body Area 9 is located at the side of trench gate structure and is attached thereto, and the junction depth in PXing Ti areas 9 is more than the junction depth of N-type drift region 10；Institute Stating trench gate structure includes：Gate dielectric layer 7 and gate electrode 8, it is characterised in that：The trench gate structure also includes：Groove divides Electrode 14 and groove Split Electrode dielectric layer 15；Groove Split Electrode 14 is L-shaped and semi-surrounding gate electrode 8 is set；The grid The depth of electrode 8 is more than the junction depth of p-type base 5 and is situated between less than the junction depth of N-type charge storage layer 6, gate electrode 8 by the grid of side Matter layer 7 is connected with N+ launch sites 3, P+ launch sites 4, p-type base 5 and the N-type charge storage layer 6 of side, and gate electrode 8 passes through side It is connected with the gate dielectric layer 7 of bottom surface with groove Split Electrode 14；The depth of the groove Split Electrode 14 stores more than N-type electric charge The depth of the junction depth of layer 6, groove Split Electrode 14 by the groove Split Electrode dielectric layers 15 of both sides respectively with PXing Ti areas 9 and N Type drift region 10 is connected；PXing Ti areas 9 have with its phase close to the top of the groove Split Electrode dielectric layer 15 of side to be connected with the two First medium layer 21；The upper surface of gate electrode 8, gate dielectric layer 7 and part of trench Split Electrode 14 also has second dielectric layer 22, second dielectric layer 22 also has the pole of series connection two being connected with metal emitting 1 with the upper surface of part of trench Split Electrode 14 Tubular construction；The lower section of groove Split Electrode 14 also has the P-type layer 17 being attached thereto, and the width of the P-type layer 17 is more than groove Width.
Further, series diode structure uses PN junction diode, Schottky diode or Zener two in the present invention Pole pipe structure.During using PN junction diode and Schottky diode structure, the anode/cathode connected mode of diode is identical, tool Body detailed in Example, and the diode structure number connected can be 1,2 or more；Using zener diode structure When, the connection of both diode structures of the anode/cathode connected mode Yu PN junction diode and Schottky diode of diode Mode is on the contrary, and it is sufficient that one zener diode structure of generally use.
According to embodiments of the present invention, series diode structure includes in the present invention：First p-type doped region 1601, the first N-type Doped region 1602, the second p-type doped region 1603 and the second n-type doping area 1604, the first p-type doped region 1601 are mixed with the first N-type Miscellaneous area 1602 is adjacent and contact forms the first PN junction diode, the second p-type doped region 1603 and the second n-type doping area 1604 Adjacent and contact forms the second PN junction diode；Wherein：First p-type doped region 1601 is located at the upper table of groove Split Electrode 14 Face, the first n-type doping area 1602, the second p-type doped region 1603 and the second n-type doping area 1604 are located at the upper of second dielectric layer 22 Surface；It is connected between first n-type doping area 1602 and the second p-type doped region 1603 by floating electrode 18, the second n-type doping area 1604 are connected with metal emitting 1.
Further, the junction depth in ZhongPXing Ti areas 9 of the present invention is more than or equal to the groove depth of groove structure.
Further, N-type drift region structure is NPT structures or FS structures in the present invention.
Further, the semi-conducting material of IGBT device uses Si, SiC, GaAs or GaN, trench fill in the present invention Material can use same material also to use not same material group using polycrystalline Si, SiC, GaAs or GaN, and each several part Close.
Technical scheme two：
A kind of CSTBT devices, its structure cell include：Collector structure, drift region structure, emitter structure and groove grid knot Structure；The collector structure includes P+ collecting zones 12 and the collector electrode metal 13 positioned at the lower surface of P+ collecting zones 12；The drift Plot structure includes N-type electric field trapping layer 11 and the N-type drift region layer 10 positioned at the upper surface of N-type electric field trapping layer 11, the N-type electricity Field stop layer 11 is located at the upper surface of P+ collecting zones 12；The slot grid structure is trench gate structure, and the trench gate structure is along device Part vertical direction, which is penetrated in N-type drift region 10, forms groove, and the emitter structure is located at trench gate structure both sides and therewith phase Even；The emitter structure includes emitter metal 1, N+ launch sites 3, P+ contact zones 4, p-type base 5 and N-type charge storage layer 6；The N-type charge storage layer 6 is between p-type base 5 and N-type drift region layer 10, the N+ launch sites 3 and P+ contact zones 4 Contact with each other and be arranged side by side and be connected in the top layer of p-type base 5, P+ contact zones 4 and N+ launch sites 3 with top emitter metal 1, N+ launch sites 3 are connected with trench gate structure；It is characterized in that：The trench gate structure includes：First gate electrode 81, second gate electricity Pole 82, gate dielectric layer 7, groove Split Electrode 14 and groove Split Electrode dielectric layer 15；Groove Split Electrode 14 is set in inverted " t " type Put, and the gate electrode 82 of semi-surrounding first gate electrode 81 and second is set respectively；The gate electrode of first gate electrode 81 and second 82 depth is more than the junction depth of p-type base 5 and less than the junction depth of N-type charge storage layer 6, the gate electrode of first gate electrode 81 and second 82 pass through the gate dielectric layer 7 and N+ launch sites 3, P+ launch sites 4, p-type base 5 and the phase of N-type charge storage layer 6 of side of side Even, the gate electrode 82 of first gate electrode 81 and second is connected by the gate dielectric layer 7 of side and bottom surface with groove Split Electrode 14； The depth of the groove Split Electrode 14 is more than the depth of the junction depth of N-type charge storage layer 6, and groove Split Electrode 14 passes through both sides Groove Split Electrode dielectric layer 15 be connected with N-type charge storage layer 6 and N-type drift region 10；First gate electrode 81 and both sides grid The upper surface of dielectric layer 7 also has the 3rd dielectric layer 23, the second gate electrode 82, gate dielectric layer 7 and part of trench Split Electrode 14 Upper surface also there is the 4th dielectric layer 24, the upper surface of second dielectric layer 22 and part of trench Split Electrode 14 also has and gold Belong to the connected series diode structure of emitter stage 1；The lower section of groove Split Electrode 14 also has the P-type layer 17 being attached thereto, the P The width of type layer 17 is more than the width of groove.
Further, series diode structure uses PN junction diode, Schottky diode or Zener two in the present invention Pole pipe structure.During using PN junction diode and Schottky diode structure, the anode/cathode connected mode of diode is identical, tool Body detailed in Example, and the diode structure number connected can be 1,2 or more；Using zener diode structure When, the connection of both diode structures of the anode/cathode connected mode Yu PN junction diode and Schottky diode of diode Mode is on the contrary, and it is sufficient that one zener diode structure of generally use.
According to embodiments of the present invention, series diode structure includes in the present invention：First p-type doped region 1601, the first N-type Doped region 1602, the second p-type doped region 1603 and the second n-type doping area 1604, the first p-type doped region 1601 are mixed with the first N-type Miscellaneous area 1602 is adjacent and contact forms the first PN junction diode, the second p-type doped region 1603 and the second n-type doping area 1604 Adjacent and contact forms the second PN junction diode；Wherein：First p-type doped region 1601 is located at the upper table of groove Split Electrode 14 Face, the first n-type doping area 1602, the second p-type doped region 1603 and the second n-type doping area 1604 are located at the upper of second dielectric layer 22 Surface；It is connected between first n-type doping area 1602 and the second p-type doped region 1603 by floating electrode 18, the second n-type doping area 1604 are connected with metal emitting 1.
Further, the junction depth in ZhongPXing Ti areas 9 of the present invention is more than or equal to the groove depth of groove structure.
Further, N-type drift region structure is NPT structures or FS structures in the present invention.
Further, the semi-conducting material of IGBT device uses Si, SiC, GaAs or GaN, trench fill in the present invention Material can use same material also to use not same material group using polycrystalline Si, SiC, GaAs or GaN, and each several part Close.
On the other hand the present invention also provides a kind of manufacture method of CSTBT devices, it is characterised in that comprises the following steps：
Step 1：N-type drift region 10 of the monocrystalline silicon piece as device is lightly doped using N-type, deposits and protects in silicon chip surface Layer, makes window by lithography, etches to obtain first groove in the centre position of N-type drift region 10；
Step 2：One layer of field oxide is grown in silicon chip surface, is lithographically derived active area, then one layer of pre-oxidation of regrowth Layer, then by ion implanting p type impurity and made annealing treatment in the N-type drift region 10 below first groove, p-type is made Layer 17；Then N-type charge storage layer 6 is made by ion implanting N-type impurity in the N-type drift region 10 of first groove side, The junction depth of the N-type charge storage layer 6 is less than the depth of groove structure；Again in the N-type drift region 10 and N of first groove opposite side The top of type charge storage layer 6 by ion implanting p type impurity and is made annealing treatment respectively, and p-type base 5 and p-type are made successively Body area 9；
Step 3：First groove inwall formed dielectric layer, etch first groove bottom wall dielectric layer with expose lower section P Type layer 17, then the depositing polysilicon in first groove, using photoetching process, etches first groove inside points polysilicon and part Dielectric layer forms second groove, and the depth of second groove is more than the junction depth of p-type base 5 and less than N-type charge storage layer 6 Junction depth, remaining polysilicon is as groove Split Electrode 14, and remaining dielectric layer is as groove Split Electrode dielectric layer 15；
Step 4：Gate dielectric layer 7 is formed in second groove inwall, then depositing polysilicon forms grid electricity in second groove Pole 8；
Step 5：Using photoetching, ion implantation technology is injected separately into N-type impurity in the top layer of p-type base 5 and p type impurity is made N+ launch sites 3 and P+ launch sites 4, N+ launch sites 3 and P+ launch sites 4 contact with each other and are arranged side by side, the N+ launch sites 3 with Side gate dielectric layer 7 is connected；
Step 6：Deposit in device surface, and formed using photoetching, etching technics positioned at PXing Ti areas 9 and its mutually close to side Groove Split Electrode dielectric layer 15 upper surface first medium layer 21 and positioned at gate electrode 8, gate dielectric layer 7 and part of trench The second dielectric layer 22 of the upper surface of Split Electrode 14；
Step 7：In device surface epitaxial growth N-type layer, using photoetching, ion implantation technology and annealing process in part ditch Groove Split Electrode 14 and the top of second dielectric layer 22 form series diode structure；
Step 8：Metal is deposited in device surface, and using photoetching, etching technics respectively in N+ launch sites 3 and P+ launch sites 4 upper surfaces form emitter metal 1 and form floating electricity between two neighboring PN junction diode in series diode structure Pole 18；
Step 9：Silicon chip is overturn, silicon wafer thickness is thinned, N-type impurity is injected in silicon chip back side and makes annealing treatment making devices N-type field stop layer 11, p-type collecting zone 12 is formed in the back side implanting p-type impurity of N-type field stop layer 11, back side deposit metal is formed Collector electrode metal 13.
Further, lithography step can be increased in step 2 of the invention and form N-type charge storage layer 6, P respectively in four times Type base 5, PXing Ti areas 9 and P-type layer 17.
The present invention forms series connection by introducing groove Split Electrode in trench gate structure above groove Split Electrode Diode structure, it is described in detail below so as to optimize the operation principle of device in groove Split Electrode P-type layer formed below：
(1), during device blocking state：
The PN junction that the P-type layer 17 and N- drift regions 10 of PXing Ti areas 9 and the lower section of groove Split Electrode 14 are formed is reverse-biased, by Acted in the electron screening of 17 offer extending transversely of P-type layer, the N-type drift below N-type charge storage layer 6 is caused before device breakdown The fully- depleted of area 10 is moved, and then thus almost all backward voltage is born, so as to improve the doping concentration of charge storage layer 6 While will not influence the breakdown voltage of device, which overcome traditional C/S TBT structure forward conduction characteristics and it is pressure-resistant between lance Shield.In addition, thick groove Split Electrode dielectric layer 15 can further reduce the electric field of trench gate bottom, improve channel bottom electric field Concentration effect, the breakdown voltage of device is improved, improve the reliability of device.
(2), during device forward conduction：
The current potential of the P-type layer 17 of the lower section of Split Electrode 14 increases with the increase of the voltage of collector electrode metal 13, works as IGBT During in normally state, because the voltage of collector electrode metal 13 is relatively low, now the current potential of P-type layer 17 is less than series diode The conduction voltage drop V of structureDC, no current flows through Diode series structure, and now device property is identical with traditional C/S TBT structures；When When IGBT is in short-circuit condition, because the voltage of collector electrode metal 13 is very big, the current potential of P-type layer 17 is increased over two poles of series connection The conduction voltage drop V of tubular constructionDC, now series diode structure turn on, will cause the current potential of this P-type layer 17 by Pliers positions in VDC, from And cause device channel voltage by Pliers positions in less value, so as to subtract the saturation current density of IGBT gadgets, improve device Short-circuit trouble free service zone properties.Simultaneously as the presence of groove Split Electrode 14, in certain gash depth and certain MOS IGBT gully density is reduced under the conditions of density of texture, so as to also reduce saturation current density, further improves device Short-circuit safety operation area.In addition, the high-dopant concentration of N-type charge storage layer 6 further increases emitter stage carrier concentration Enhancement effect, further reduce the forward conduction voltage drop of device.
(3), devices switch state：
The invention enables the depth of gate electrode 8 between p-type base 5 and N-type charge storage layer 6, and makes gate electrode 8 Width is less than the width of N-type charge storage layer, and grid and hair are on the one hand significantly reduced in the case where not influenceing device and opening The electric capacity between electric capacity and grid and colelctor electrode between emitter-base bandgap grading, so as to reach the purpose for reducing whole grid capacitance, improve The switching speed of device, reduces the switching loss of device, and reduces the drive loss of device, obtains device and preferably leads Logical compromise characteristic between pressure drop and switching loss；On the other hand, the high-dopant concentration of N-type charge storage layer 6 further increases Emitter stage carrier concentration enhancement effect, improves carrier concentration profile, further improves between conduction voltage drop and switching loss Compromise characteristic.The extraction area in hole is further reduced positioned at the PXing Ti areas 9 of trench gate knot side, improves emitter stage The carrier enhancement effect at end, further improve the carrier concentration profile of whole N-type drift region.
In summary, the beneficial effect of the present invention compared with prior art is：
The present invention on the basis of traditional C/S TBT device architectures by improve provide a kind of novel C STBT devices and its Manufacture method.The present invention rationally designs device architecture to integrate the performance of raising device, passes through side under the gate electrode and introduces groove Split Electrode is collectively forming trench gate structure, and P-type layer is introduced below groove Split Electrode, is set above groove Split Electrode Series diode structure so that under device forward conduction state, current potential rises to or more than in series diode when PXing Ti areas During the conduction voltage drop VDC of structure, the conducting of series diode structure, this P-type layer current potential will be caused by Pliers positions in VDC, so that Device channel voltage Pliers positions so as to reduce device saturation current density, improve short-circuit safety operation area in the value of very little, drop Low conduction loss；Under device blocking state, because P-type layer is extended laterally to below N-type charge storage layer in N-type drift region So that N-type drift region fully- depleted, causes most backward voltage to be born by P-type layer and the PN junction that N-type drift region is formed, energy Enough avoiding, which increases charge storage layer doping concentration, will not influence the breakdown voltage of device, so as to overcome traditional C/S TBT device junctions Contradictory relation between structure forward conduction and pressure-resistant performance；Depth of the invention by reducing gate electrode, make the depth of gate electrode Junction depth less than N-type charge storage layer reduces gate-emitter electric capacity and grid-collector capacitance, improves opening for device Speed is closed, reduces switching loss, device is obtained the compromise characteristic between more preferable conduction voltage drop and switching loss；The present invention is logical Channel bottom electric field concentration effect can be improved by crossing the thick groove Split Electrode dielectric layer of introducing, improve the breakdown voltage of device, Improve the reliability of device；Simultaneously because the presence of groove Split Electrode, in certain gash depth and certain MOS structure IGBT gully density is reduced under density conditions, so as to also reduce saturation current density, further improves the short of device Road safety operation area.
Brief description of the drawings
Fig. 1 is the structure cell schematic diagram of traditional CSTBT devices；
Fig. 2 is that the embodiment of the present invention 1 provides a kind of structure cell schematic diagram of CSTBT devices；
Fig. 3 is that the embodiment of the present invention 2 provides a kind of structure cell schematic diagram of CSTBT devices；
Fig. 4 is that the embodiment of the present invention 3 provides a kind of structure cell schematic diagram of CSTBT devices；
In Fig. 1 to 4：1 is emitter metal, and 21 be first medium layer, and 22 be second dielectric layer, and 23 be the 3rd dielectric layer, 24 be the 4th dielectric layer, and 3 be N+ launch sites, and 4 be P+ launch sites, and 5 be p-type base, and 6 be N-type charge storage layer, and 7 be gate medium Layer, 8 be gate electrode, and 81 be first gate electrode, and 82 be the second gate electrode, and 9 be PXing Ti areas, and 10 be N-type drift region, and 11 be N-type field Trapping layer, 12 be p-type collecting zone, and 13 be collector electrode metal, and 14 be Pliers positions electrode, and 15 be Pliers positions electrode dielectric, and 1601 be One p-type doped region, 1602 be the first n-type doping area, and 1603 be the second p-type doped region, and 1604 be the second n-type doping area, and 18 are Floating electrode.
Fig. 5 be the embodiment of the present invention 1 manufacture method in formed first pass through ion implanting then etch to be formed groove and The device architecture schematic diagram that trench wall is formed after dielectric layer；
Fig. 6 be the embodiment of the present invention 1 manufacture method in device architecture schematic diagram in groove after depositing polysilicon；
Fig. 7 be the embodiment of the present invention 1 manufacture method in etching groove excess polysilicon and dielectric layer form groove point Split the device architecture schematic diagram after electrode；
Fig. 8 is the device architecture schematic diagram formed in the trench in the manufacture method of the embodiment of the present invention 1 after gate dielectric layer；
Fig. 9 is the device architecture schematic diagram formed in the trench in the manufacture method of the embodiment of the present invention 1 after gate electrode；
Figure 10 is the device architecture signal formed in the manufacture method of the embodiment of the present invention 1 behind N+ launch sites and P+ launch sites Figure；
Figure 11 be the embodiment of the present invention 1 manufacture method in device surface formed dielectric layer after device architecture signal Figure；
Figure 12 be the embodiment of the present invention 1 manufacture method in device surface formed series diode structure after device junction Structure schematic diagram；
Figure 13 is the device junction formed in the manufacture method of the embodiment of the present invention 1 after surface emitting pole electrode and floating electrode Structure schematic diagram；
Figure 14 is the device architecture schematic diagram formed in the manufacture method of the embodiment of the present invention 1 after the completion of whole processes；
The device architecture schematic diagram formed in the trench in the manufacture method of Figure 15 embodiment of the present invention 2 after gate dielectric layer；
Figure 16 is the device architecture schematic diagram formed in the trench in the manufacture method of the embodiment of the present invention 2 after gate electrode；
Figure 17 be the embodiment of the present invention 3 manufacture method in etching groove excess polysilicon and dielectric layer form Pliers positions electricity Device architecture schematic diagram after extremely；
Figure 18 is the device architecture schematic diagram formed in the manufacture method of the embodiment of the present invention 3 after gate dielectric layer；
Figure 19 is the device architecture schematic diagram formed in the manufacture method of the embodiment of the present invention 3 after gate electrode；
Embodiment
The principle and characteristic of the present invention are described in detail with reference to Figure of description and specific embodiment：
Embodiment 1：
The present embodiment proposes a kind of CSTBT devices as shown in Figure 2, and its structure cell includes：Collector structure, drift region Structure, emitter structure and slot grid structure；The collector structure includes P+ collecting zones 12 and positioned at the lower surface of P+ collecting zones 12 Collector electrode metal 13；The drift region structure includes N-type electric field trapping layer 11 and positioned at the upper surface of N-type electric field trapping layer 11 N-type drift region layer 10, the N-type electric field trapping layer 11 are located at the upper surface of P+ collecting zones 12；The slot grid structure is trench gate Structure, the trench gate structure penetrate in N-type drift region 10 along device vertical direction and form groove, and the emitter structure is located at The side of trench gate structure and be attached thereto the emitter structure include emitter metal 1, N+ launch sites 3, P+ contact zones 4, P Type base 5 and N-type charge storage layer 6；The N-type charge storage layer 6 is between p-type base 5 and N-type drift region layer 10, institute N+ launch sites 3 and P+ contact zones 4 is stated to contact with each other and be arranged side by side in the top layer of p-type base 5, P+ contact zones 4 and N+ launch sites 3 It is connected with top emitter metal 1, N+ launch sites 3 are connected with trench gate structure；The PXing Ti areas 9 are located at trench gate structure Side is simultaneously attached thereto, and the junction depth in PXing Ti areas 9 is more than the junction depth of N-type drift region 10；The trench gate structure includes：Grid Dielectric layer 7 and gate electrode 8, it is characterised in that：The trench gate structure also includes：Groove Split Electrode 14 and groove Split Electrode Dielectric layer 15；Groove Split Electrode 14 is L-shaped and semi-surrounding gate electrode 8 is set；The depth of the gate electrode 8 is more than p-type base The junction depth in area 5 and the junction depth for being less than N-type charge storage layer 6, gate electrode 8 pass through the gate dielectric layer 7 of side and launched with the N+ of side Area 3, P+ launch sites 4, p-type base 5 are connected with N-type charge storage layer 6, gate electrode 8 by the gate dielectric layer 7 of side and bottom surface with Groove Split Electrode 14 is connected；The depth of the groove Split Electrode 14 is more than the depth of the junction depth of N-type charge storage layer 6, ditch Groove Split Electrode 14 is connected with PXing Ti areas 9 and N-type drift region 10 respectively by the groove Split Electrode dielectric layer 15 of both sides；P-type Body area 9 has the first medium floor 21 being connected with the two with its phase close to the top of the groove Split Electrode dielectric layer 15 of side；Grid The upper surface of electrode 8, gate dielectric layer 7 and part of trench Split Electrode 14 also has a second dielectric layer 22, second dielectric layer 22 with The upper surface of part of trench Split Electrode 14 also has the series diode structure that is connected with metal emitting 1, in the present embodiment Series diode structure includes：First p-type doped region 1601, the first n-type doping area 1602, the second p-type doped region 1603 and Two n-type doping areas 1604, the first p-type doped region 1601 is adjacent with the first n-type doping area 1602 and contacts and forms the first PN junction two Pole pipe, 1604 adjacent and contact the second PN junction diode of formation of the second p-type doped region 1603 and the second n-type doping area；Its In：First p-type doped region 1601 is located at the upper surface of groove Split Electrode 14, the first n-type doping area 1602, the doping of the second p-type N-type doping area 1604 of area 1603 and second is located at the upper surface of second dielectric layer 22；First n-type doping area 1602 and the second p-type It is connected between doped region 1603 by floating electrode 18, the second n-type doping area 1604 is connected with metal emitting 1；Groove divides The lower section of electrode 14 also has the P-type layer 17 being attached thereto, and the width of the P-type layer 17 is more than the width of groove.
Embodiment 2：
The present embodiment proposes a kind of CSTBT devices as shown in Figure 3, except the thickness of groove Split Electrode dielectric layer 15 is big Beyond the thickness of gate dielectric layer 7, remaining structure is same as Example 1.
The present embodiment compares embodiment 1, on the one hand can further reduce grid capacitance, improves the switch speed of device Spend and reduce switching loss, on the other hand can further improve channel bottom electric field concentration effect, improve device breakdown electricity Pressure, improve device reliability.
Embodiment 3：
The present embodiment proposes a kind of CSTBT devices as shown in Figure 4, its structure cell includes：Collector structure, drift Plot structure, emitter structure and slot grid structure；The collector structure includes P+ collecting zones 12 and positioned at the following table of P+ collecting zones 12 The collector electrode metal 13 in face；The drift region structure includes N-type electric field trapping layer 11 and positioned at the upper surface of N-type electric field trapping layer 11 N-type drift region layer 10, the N-type electric field trapping layer 11 is located at the upper surface of P+ collecting zones 12；The slot grid structure is groove Grid structure, the trench gate structure penetrate in N-type drift region 10 along device vertical direction and form groove, the emitter structure position In trench gate structure both sides and it is attached thereto；The emitter structure include emitter metal 1, N+ launch sites 3, P+ contact zones 4, P-type base 5 and N-type charge storage layer 6；The N-type charge storage layer 6 is between p-type base 5 and N-type drift region layer 10, institute N+ launch sites 3 and P+ contact zones 4 is stated to contact with each other and be arranged side by side in the top layer of p-type base 5, P+ contact zones 4 and N+ launch sites 3 It is connected with top emitter metal 1, N+ launch sites 3 are connected with trench gate structure；It is characterized in that：The trench gate structure bag Include：First gate electrode 81, the second gate electrode 82, gate dielectric layer 7, groove Split Electrode 14 and groove Split Electrode dielectric layer 15； Groove Split Electrode 14 is set in inverted " t " type, and the gate electrode 82 of semi-surrounding first gate electrode 81 and second is set respectively；It is described The depth of the gate electrode 82 of first gate electrode 81 and second is more than the junction depth of p-type base 5 and is less than the junction depth of N-type charge storage layer 6, Gate dielectric layer 7 and the N+ launch site 3, P+ launch site 4, P of side of the gate electrode 82 of first gate electrode 81 and second by side Type base 5 is connected with N-type charge storage layer 6, and the gate electrode 82 of first gate electrode 81 and second is situated between by the grid of side and bottom surface Matter layer 7 is connected with groove Split Electrode 14；The depth of the groove Split Electrode 14 is more than the junction depth of N-type charge storage layer 6 Depth, the groove Split Electrode dielectric layer 15 and N-type charge storage layer 6 and N-type drift region that groove Split Electrode 14 passes through both sides 10 are connected；The upper surface of first gate electrode 81 and both sides gate dielectric layer 7 also has the 3rd dielectric layer 23, the second gate electrode 82, grid The upper surface of dielectric layer 7 and part of trench Split Electrode 14 also has the 4th dielectric layer 24, second dielectric layer 22 and part of trench The upper surface of Split Electrode 14 also has the series diode structure being connected with metal emitting 1, two poles of being connected in the present embodiment Tubular construction includes：First p-type doped region 1601, the first n-type doping area 1602, the second p-type doped region 1603 and the second n-type doping Area 1604, the first p-type doped region 1601 is adjacent with the first n-type doping area 1602 and contacts and forms the first PN junction diode, described 1604 adjacent and contact the second PN junction diode of formation of second p-type doped region 1603 and the second n-type doping area；Wherein：First p-type Doped region 1601 is located at the upper surface of groove Split Electrode 14, the first n-type doping area 1602, the second p-type doped region 1603 and Two n-type doping areas 1604 are located at the upper surface of second dielectric layer 22；First n-type doping area 1602 and the second p-type doped region 1603 Between by floating electrode 18 be connected, the second n-type doping area 1604 is connected with metal emitting 1；The lower section of groove Split Electrode 14 Also there is the P-type layer 17 being attached thereto, the width of the P-type layer 17 is more than the width of groove.
Embodiment 4：
The present embodiment illustrates by taking the CSTBT devices of 1200V voltage class as an example, can be according to reality according to common sense in the field Border demand prepares the device of different performance parameter, specifically provides a kind of manufacture method of CSTBT devices, comprises the following steps：
Step 1：N-type drift region 10 of the monocrystalline silicon piece as device is lightly doped using N-type, the thickness of selected silicon chip is 300 ~600um, doping concentration 1013~1014Individual/cm3；Protective layer is deposited in silicon chip surface, window is made by lithography, in N-type drift region 10 centre position etches to obtain first groove；
Step 2：One layer of field oxide is grown in silicon chip surface, is lithographically derived active area, then one layer of pre-oxidation of regrowth Layer, then by ion implanting p type impurity and made annealing treatment in the N-type drift region 10 below first groove, p-type is made Layer 17, the energy of ion implanting are 60~120keV, implantation dosage 1013~1014Individual/cm2, annealing temperature is 1100~1150 DEG C, annealing time is 10~30 minutes；Then in the N-type drift region 10 of first groove side by ion implanting N-type impurity, The energy of ion implanting is 200~500keV, implantation dosage 1013~1014Individual/cm2, N-type charge storage layer 6, the N is made The junction depth of type charge storage layer 6 is less than the depth of groove structure；Again in N-type drift region 10 and the N-type electricity of first groove opposite side The top of lotus accumulation layer 6 by ion implanting p type impurity and is made annealing treatment respectively, the energy of ion implanting for 60~ 120keV, implantation dosage 1013~1014Individual/cm2, annealing temperature is 1100~1150 DEG C, and annealing time is 10~30 minutes, P-type base 5 and PXing Ti areas 9 are made successively；
Step 3：Inwall in first groove under 1050 DEG C~1150 DEG C of O2 atmosphere is respectively formed oxide layer, etching first Then the oxide layer of groove bottom wall deposits polycrystalline at 750 DEG C~950 DEG C to expose the P-type layer 17 of lower section in first groove Silicon, using photoetching process, etch first groove inside points polysilicon and certain media layer forms second groove, and second groove Depth be more than the junction depth of p-type base 5 and less than the junction depth of N-type charge storage layer 6, remaining polysilicon as Pliers positions electrode 14, Remaining dielectric layer is as Pliers positions electrode dielectric 15；
Step 4：Inwall in second groove under 1050 DEG C~1150 DEG C of O2 atmosphere forms gate dielectric layer 7, Ran Houyu Depositing polysilicon forms gate electrode 8 in second groove at 750 DEG C~950 DEG C；
Step 5：Using photoetching, ion implantation technology is injected separately into N-type impurity in the top layer of p-type base 5 and p type impurity is made N+ launch sites 3 and P+ launch sites 4, the energy of ion implanting N-type impurity are 30~60keV, implantation dosage 1015~1016Individual/ cm2, the energy of ion implanting p type impurity is 60~80keV, implantation dosage 1015~1016Individual/cm2, annealing temperature 900 DEG C, the time is 20~30 minutes；N+ launch sites 3 and P+ launch sites 4 contact with each other and are arranged side by side, the N+ launch sites 3 and side Face gate dielectric layer 7 is connected；
Step 6：Deposit in device surface, and formed using photoetching, etching technics positioned at PXing Ti areas 9 and its mutually close to side The upper surface of groove Split Electrode dielectric layer 15 first medium layer 21 and positioned at gate electrode 8, gate dielectric layer 7 and part of trench point Split the second dielectric layer 22 of the upper surface of electrode 14；
Step 7：In device surface epitaxial growth N-type layer, using photoetching, ion implantation technology and annealing process in part ditch Groove Split Electrode 14 and the top of second dielectric layer 22 form series diode structure；
Step 8：Metal is deposited in device surface, and using photoetching, etching technics respectively in N+ launch sites 3 and P+ launch sites 4 upper surfaces form emitter metal 1 and form floating electricity between two neighboring PN junction diode in series diode structure Pole 18；
Step 9：Silicon chip is overturn, silicon wafer thickness is thinned, N-type impurity is injected in silicon chip back side and makes annealing treatment making devices N-type field stop layer 11, the thickness of N-type field stop layer 11 is 15~30 microns, and the energy of ion implanting is 1500~2000keV, Implantation dosage is 1013~1014Individual/cm2, annealing temperature is 1200~1250 DEG C, and the time is 300~600 minutes；Hindered in N-type field Only the back side implanting p-type impurity of layer 11 forms p-type collecting zone 12, and Implantation Energy is 40~60keV, implantation dosage 1012~1013 Individual/cm2, in H2With N2Back side annealing is carried out under the atmosphere of mixing, temperature is 400~450 DEG C, and the time is 20~30 minutes；The back side Deposit metal and form collector electrode metal 13, so far complete trench gate charge storage type IGBT preparation.
Further, lithography step can be increased in step 2 of the invention and form N-type charge storage layer 6, P respectively in four times Type base 5, PXing Ti areas 9 and P-type layer 17.
Further, can be less than in step 4 of the invention by controlling reaction condition to form the thickness of gate dielectric layer 7 The thickness of Pliers positions surrounding them dielectric layer, you can obtain device architecture as shown in Figure 3.
Further, can be by increasing lithography step in step 3 of the invention, polysilicon both ends are distinguished in first groove Symmetrical two grooves are formed, the structure of first grid 81 and second grid 82 is then prepared, you can are obtained as shown in Figure 4 Device architecture.
It is further the processing step of etching groove and formation p-type base 5, N-type electric charge storage layer 6 and P in the present invention The order of the processing step of type layer 17 is interchangeable, i.e., also can first etching forms after groove doped region again in N-type drift region 10.
Further, the material of dielectric layer of the present invention, gate dielectric layer 7 and Pliers positions electrode dielectric 15 can be with identical, also Can be different.
Further, the preparation of N-type field stop layer 11 can omit in the present invention.
Further, the preparation of N-type field stop layer 11 can be before the Facad structure of device be prepared in step 9 of the invention Prepared；Or directly the two-layer epitaxial material with N-type field stop layer 11 and N-type drift region 10 can be selected to be risen as technique The silicon sheet material of beginning.

Claims (5)

1. a kind of CSTBT devices, its structure cell include：Collector structure, drift region structure, emitter structure and groove grid knot Structure；The collector structure includes P+ collecting zones (12) and the collector electrode metal (13) positioned at P+ collecting zones (12) lower surface；Institute Stating drift region structure includes N-type electric field trapping layer (11) and the N-type drift region layer positioned at N-type electric field trapping layer (11) upper surface (10), the N-type electric field trapping layer (11) is located at the upper surface of P+ collecting zones (12)；The slot grid structure is trench gate structure, The trench gate structure forms groove in penetrating N-type drift region (10) along device vertical direction, and the emitter structure is located at ditch The side of slot grid structure and be attached thereto the emitter structure include emitter metal (1), N+ launch sites (3), P+ contact zones (4), p-type base (5) and N-type charge storage layer (6)；The N-type charge storage layer (6) is located at p-type base (5) and drifted about with N-type Between region layer (10), the N+ launch sites (3) and P+ contact zones (4) contact with each other and are arranged side by side in the top of p-type base (5) Layer, P+ contact zones (4) and N+ launch sites (3) are connected with top emitter metal (1), N+ launch sites (3) and trench gate structure phase Even；The PXing Ti areas (9) are located at the side of trench gate structure and are attached thereto, and the junction depth of PXing Ti areas (9) floats more than N-type Move the junction depth of area (10)；The trench gate structure includes：Gate dielectric layer (7) and gate electrode (8), it is characterised in that：The groove Grid structure also includes：Groove Split Electrode (14) and groove Split Electrode dielectric layer (15)；Groove Split Electrode (14) is L-shaped And semi-surrounding gate electrode (8) is set；The depth of the gate electrode (8) is more than the junction depth of p-type base (5) and deposited less than N-type electric charge The junction depth of reservoir (6), gate electrode (8) pass through N+ launch site (3) of the gate dielectric layer (7) of side with side, P+ launch sites (4), P Type base (5) is connected with N-type charge storage layer (6), and gate electrode (8) passes through the gate dielectric layer of side and bottom surface (7) and groove point Electrode (14) is split to be connected；The depth of the groove Split Electrode (14) is more than the depth of the junction depth of N-type charge storage layer (6), ditch Groove Split Electrode (14) by the groove Split Electrode dielectric layers (15) of both sides respectively with PXing Ti areas (9) and N-type drift region (10) It is connected；PXing Ti areas (9) have be connected with the two first with its phase close to the top of the groove Split Electrode dielectric layer (15) of side Dielectric layer (21)；The upper surface of gate electrode (8), gate dielectric layer (7) and part of trench Split Electrode (14) also has second medium Layer (22), second dielectric layer (22) also has with the upper surface of part of trench Split Electrode (14) to be connected with metal emitting (1) Series diode structure (16)；Also there is the P-type layer (17) being attached thereto, the P-type layer below groove Split Electrode (14) (17) width is more than the width of groove.
2. a kind of CSTBT devices, its structure cell include：Collector structure, drift region structure, emitter structure and groove grid knot Structure；The collector structure includes P+ collecting zones (12) and the collector electrode metal (13) positioned at P+ collecting zones (12) lower surface；Institute Stating drift region structure includes N-type electric field trapping layer (11) and the N-type drift region layer positioned at N-type electric field trapping layer (11) upper surface (10), the N-type electric field trapping layer (11) is located at the upper surface of P+ collecting zones (12)；The slot grid structure is trench gate structure, The trench gate structure forms groove in penetrating N-type drift region (10) along device vertical direction, and the emitter structure is located at ditch Slot grid structure both sides and it is attached thereto；The emitter structure includes emitter metal (1), N+ launch sites (3), P+ contact zones (4), p-type base (5) and N-type charge storage layer (6)；The N-type charge storage layer (6) is located at p-type base (5) and drifted about with N-type Between region layer (10), the N+ launch sites (3) and P+ contact zones (4) contact with each other and are arranged side by side in the top of p-type base (5) Layer, P+ contact zones (4) and N+ launch sites (3) are connected with top emitter metal (1), N+ launch sites (3) and trench gate structure phase Even；It is characterized in that：The trench gate structure includes：First gate electrode (81), the second gate electrode (82), gate dielectric layer (7), ditch Groove Split Electrode (14) and groove Split Electrode dielectric layer (15)；Groove Split Electrode (14) is set in inverted " t " type, and respectively Semi-surrounding first gate electrode (81) and the second gate electrode (82) are set；The first gate electrode (81) and the second gate electrode (82) Depth is more than the junction depth of p-type base (5) and less than the junction depth of N-type charge storage layer (6), first gate electrode (81) and second gate electricity Pole (82) passes through N+ launch site (3) of the gate dielectric layer (7) of side with side, P+ launch sites (4), p-type base (5) and N-type Charge storage layer (6) is connected, and first gate electrode (81) and the second gate electrode (82) pass through the gate dielectric layer of side and bottom surface (7) It is connected with groove Split Electrode (14)；The depth of the groove Split Electrode (14) is more than the junction depth of N-type charge storage layer (6) Depth, the groove Split Electrode dielectric layer (15) and N-type charge storage layer (6) and N-type that groove Split Electrode (14) passes through both sides Drift region (10) is connected；The upper surface of first gate electrode (81) and both sides gate dielectric layer (7) also has the 3rd dielectric layer (23), the The upper surface of two gate electrode (82), gate dielectric layer (7) and part of trench Split Electrode (14) also has the 4th dielectric layer (24), the The upper surface of second medium layer (22) and part of trench Split Electrode (14) also has the pole of series connection two being connected with metal emitting (1) Tubular construction (16)；Also there is the P-type layer (17) being attached thereto, the width of the P-type layer (17) below groove Split Electrode (14) More than the width of groove.
A kind of 3. CSTBT devices according to claim 1, it is characterised in that：The series diode structure (16) includes： First p-type doped region (1601), the first n-type doping area (1602), the second p-type doped region (1603) and the second n-type doping area (1604), the first p-type doped region (1601) is adjacent with the first n-type doping area (1602) and contacts the first PN junction diode of formation, The second p-type doped region (1603) and the second n-type doping area (1604) it is adjacent and contact formed the second PN junction diode；Its In：First p-type doped region (1601) is located at the upper surface of groove Split Electrode (14), the first n-type doping area (1602), the 2nd P Type doped region (1603) and the second n-type doping area (1604) are located at the upper surface of second dielectric layer (22)；First n-type doping area (1602) it is connected between the second p-type doped region (1603) by floating electrode (18), the second n-type doping area (1604) and metal Emitter stage (1) is connected.
4. a kind of manufacture method of CSTBT devices, it is characterised in that comprise the following steps：
Step 1：N-type drift region (10) of the monocrystalline silicon piece as device is lightly doped using N-type, protective layer is deposited in silicon chip surface, Make window by lithography, etch to obtain first groove in the centre position of N-type drift region (10)；
Step 2：One layer of field oxide is grown in silicon chip surface, is lithographically derived active area, then one layer of pre-oxidation layer of regrowth, and By ion implanting p type impurity and made annealing treatment in the N-type drift region below first groove (10) afterwards, P-type layer is made (17)；Then N-type charge storage layer is made by ion implanting N-type impurity in the N-type drift region (10) of first groove side (6), the junction depth of the N-type charge storage layer (6) is less than the depth of groove structure；Drifted about again in the N-type of first groove opposite side Area (10) and N-type charge storage layer (6) top by ion implanting p type impurity and are made annealing treatment respectively, and p-type is made successively Base (5) and PXing Ti areas (9)；
Step 3：First groove inwall formed dielectric layer, etch first groove bottom wall dielectric layer with expose lower section P-type layer (17), the then depositing polysilicon in first groove, using photoetching process, etching first groove inside points polysilicon and part are situated between Matter layer forms second groove, and the depth of second groove is more than the junction depth of p-type base (5) and is less than N-type charge storage layer (6) Junction depth, remaining polysilicon is as groove Split Electrode (14), and remaining dielectric layer is as groove Split Electrode dielectric layer (15)；
Step 4：Gate dielectric layer (7) is formed in second groove inwall, then depositing polysilicon forms gate electrode in second groove (8)；
Step 5：Using photoetching, ion implantation technology is injected separately into N-type impurity in p-type base (5) top layer and N+ is made in p type impurity Launch site (3) and P+ launch sites (4), N+ launch sites (3) and P+ launch sites (4), contact with each other and are arranged side by side, the N+ transmittings Area (3) is connected with side gate dielectric layer (7)；
Step 6：Deposit in device surface, and formed using photoetching, etching technics positioned at PXing Ti areas (9) and its mutually close to side The first medium layer (21) of the upper surface of groove Split Electrode dielectric layer (15) and positioned at gate electrode (8), gate dielectric layer (7) and portion Divide the second dielectric layer (22) of groove Split Electrode (14) upper surface；
Step 7：In device surface epitaxial growth N-type layer, divided using photoetching, ion implantation technology and annealing process in part of trench Split and series diode structure (16) is formed above electrode (14) and second dielectric layer (22)；
Step 8：Metal is deposited in device surface, and using photoetching, etching technics respectively in N+ launch sites (3) and P+ launch sites (4) upper surface forms emitter metal (1) and the shape between two neighboring PN junction diode in series diode structure (16) Into floating electrode (18)；
Step 9：Silicon chip is overturn, silicon wafer thickness is thinned, N-type impurity is injected in silicon chip back side and makes annealing treatment the N-type of making devices Field stop layer (11), at N-type field stop layer (11) back side, implanting p-type impurity forms p-type collecting zone (12), back side deposit metal shape Into collector electrode metal (13).
A kind of 5. manufacture method of CSTBT devices according to claim 1, it is characterised in that：Lead in the step 2 of the present invention Cross increase lithography step and form N-type charge storage layer (6), p-type base (5), PXing Ti areas (9) and P-type layer in four times respectively (17)。
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110491937A (en) * 2019-08-22 2019-11-22 电子科技大学 One kind having automatic biasing separate gate structures IGBT
CN110504312A (en) * 2019-08-29 2019-11-26 电子科技大学 A kind of transversal I GBT with short-circuit self-shield ability
CN110504260A (en) * 2019-08-29 2019-11-26 电子科技大学 A kind of lateral trench type IGBT and preparation method thereof with automatic biasing PMOS
CN110504259A (en) * 2019-08-29 2019-11-26 电子科技大学 A kind of transversal I GBT with overcurrent protection ability
CN111146285A (en) * 2018-11-02 2020-05-12 苏州东微半导体有限公司 Semiconductor power transistor and method of manufacturing the same
CN111403486A (en) * 2020-03-30 2020-07-10 中国科学院微电子研究所 Groove type MOSFET structure and manufacturing method thereof
CN117747651A (en) * 2023-12-28 2024-03-22 龙腾半导体股份有限公司 Structure with trench isolation gate IGBT and preparation method
CN118367016A (en) * 2024-05-14 2024-07-19 深圳天狼芯半导体有限公司 Silicon carbide split gate MOS device, preparation method thereof and chip

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050263853A1 (en) * 2004-05-31 2005-12-01 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device
CN103956379A (en) * 2014-05-09 2014-07-30 常州中明半导体技术有限公司 CSTBT device with optimized plugged cell structure
CN105789291A (en) * 2016-04-26 2016-07-20 电子科技大学 Double split trench gate charge storage type insulated gate bipolar transistor (IGBT) and manufacturing method thereof
CN105932042A (en) * 2016-04-26 2016-09-07 电子科技大学 Double-split groove gate charge storage type IGBT and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050263853A1 (en) * 2004-05-31 2005-12-01 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device
CN103956379A (en) * 2014-05-09 2014-07-30 常州中明半导体技术有限公司 CSTBT device with optimized plugged cell structure
CN105789291A (en) * 2016-04-26 2016-07-20 电子科技大学 Double split trench gate charge storage type insulated gate bipolar transistor (IGBT) and manufacturing method thereof
CN105932042A (en) * 2016-04-26 2016-09-07 电子科技大学 Double-split groove gate charge storage type IGBT and manufacturing method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PING LI，ETAL: "A novel diode-clamped CSTBT with ultra-low on-state voltage and saturation current", 《2016 28TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS》 *

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111146285A (en) * 2018-11-02 2020-05-12 苏州东微半导体有限公司 Semiconductor power transistor and method of manufacturing the same
CN111146285B (en) * 2018-11-02 2023-08-25 苏州东微半导体股份有限公司 Semiconductor power transistor and method of manufacturing the same
CN110491937A (en) * 2019-08-22 2019-11-22 电子科技大学 One kind having automatic biasing separate gate structures IGBT
CN110504312A (en) * 2019-08-29 2019-11-26 电子科技大学 A kind of transversal I GBT with short-circuit self-shield ability
CN110504260A (en) * 2019-08-29 2019-11-26 电子科技大学 A kind of lateral trench type IGBT and preparation method thereof with automatic biasing PMOS
CN110504259A (en) * 2019-08-29 2019-11-26 电子科技大学 A kind of transversal I GBT with overcurrent protection ability
CN110504260B (en) * 2019-08-29 2022-11-04 电子科技大学 Transverse groove type IGBT with self-bias PMOS and preparation method thereof
CN111403486A (en) * 2020-03-30 2020-07-10 中国科学院微电子研究所 Groove type MOSFET structure and manufacturing method thereof
CN111403486B (en) * 2020-03-30 2022-12-23 中国科学院微电子研究所 Groove type MOSFET structure and manufacturing method thereof
CN117747651A (en) * 2023-12-28 2024-03-22 龙腾半导体股份有限公司 Structure with trench isolation gate IGBT and preparation method
CN118367016A (en) * 2024-05-14 2024-07-19 深圳天狼芯半导体有限公司 Silicon carbide split gate MOS device, preparation method thereof and chip
CN118367016B (en) * 2024-05-14 2024-09-24 深圳天狼芯半导体有限公司 Silicon carbide split gate MOS device, preparation method thereof and chip

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