CN105932055B - A kind of planar gate IGBT and preparation method thereof - Google Patents
A kind of planar gate IGBT and preparation method thereof Download PDFInfo
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Abstract
The invention belongs to power semiconductor device technology field, it is related to a kind of planar gate IGBT and preparation method thereof.The present invention is on the basis of conventional planar grid IGBT device structure, pass through the introducing of surface recombination device architecture, reduce the grid capacitance of device, especially grid collector capacitance, the switching speed for improving device, reduces the switching loss of device, while improving forward conduction voltage drop and the drift region carrier concentration distribution of device, the performance of device is improved, while the blocking characteristics of device will not be made to deteriorate.
Description
Technical field
The invention belongs to power semiconductor device technology fields, are related to insulated gate bipolar transistor (IGBT), specifically relate to
And planar gate insulated gate bipolar transistor.
Background technology
Insulated gate bipolar transistor (IGBT) is a kind of MOS field-effects and the compound novel electric power electricity of bipolar transistor
Sub- device.Its existing MOSFET is easy to drive, and controls simple advantage, and has power transistor turns pressure drop low, on state current
Greatly, small advantage is lost, it has also become one of core electron component in modern power electronic circuit is widely used in such as
The every field of the national economy such as communication, the energy, traffic, industry, medicine, household electrical appliance and aerospace.The application pair of IGBT
The promotion of power electronic system performance plays particularly important effect.
Since IGBT inventions, people have been devoted to improve the performance of IGBT.By development in twenties years, carry in succession
Go out mostly for IGBT device structure, device performance is made to have obtained steady promotion.Trench gate IGBT structure eliminates planar gate
The areas the JFET resistance of IGBT structure, and higher MOS gully densities are can get, it is significantly carried so as to make the characteristic of device obtain
It is high.However, compared with planar gate IGBT structure, the big grid capacitance of trench gate structure and channel bottom thin gate oxide are brought
High electric field be influence its Performance And Reliability one of major factor, thus at present high pressure IGBT still mainly use planar gate knot
Structure.For high voltage planar grid IGBT, in order to reduce the areas the JFET resistance between device p-type base area and lead in device forward conduction
Cross the carrier injection enhancement effect that the electron accumulation layer that is formed under the areas JFET gate electrode improves device, device p-type base area it
Between the areas JFET it is very wide.The gate structure on the wide areas JFET top still brings big device capacitor, especially grid-collector electricity
Hold, reduces the switching speed of device, increase the switching loss of device, while improving to device gate drive circuit ability
It is required that.In addition, the grid capacitance on the areas device JFET top, can form negative differential capacitance effect in device low current opening process
It answers, so that device is led to the problem of in opening process and shake and thus bring electromagnetic radiation.
Invention content
In order to further decrease the grid capacitance of device, especially grid-collector capacitance, the switch for improving device are fast
Degree, the carrier concentration profile and conduction voltage drop of device when reducing the switching loss of device, while improving forward conduction, further
Improve the compromise of forward conduction voltage drop and switching loss, and reduce the requirement to device gate drive circuit ability, overcomes negative differential
Concussion problem in the opening process that capacity effect is brought, it is flat in conventional high-tension in the case where not influencing device blocking voltage
On the basis of the grid IGBT device structure of face (as shown in Figure 1), the present invention provide a kind of high voltage planar grid IGBT (half structure cell and
It is as shown in Figures 2 and 3 along the section of AB lines) and preparation method thereof.The present invention passes through in device surface MOS structure and the drift regions N-
The N-type layer of one layer of higher-doped concentration is introduced between 7, and is introduced than N-type layer depth perpendicular to one end of MOS orientations
The trenched electrode structures being connect with emitter, and the upper part region of the areas device surface JFET oxide layer introduce and send out
The surface electrode of emitter-base bandgap grading connection, makes the emitter connection surface electrode be formed perpendicular to MOS orientations with grid
It is spaced apart, is dielectric layer between the two, the emitter connection surface electrode is in the N-type layer upper surface perpendicular to MOS ditches
The length of road length direction is less than the diffusion length of bipolar carrier in the areas device JFET N-type layer, and is being parallel to MOS raceway grooves
The length of length direction is more than it in the length perpendicular to MOS orientations, the emitter connection table being usually arranged
The length that face electrode is parallel to MOS orientations in the N-type layer upper surface is it perpendicular to MOS orientations
4 times or more of length.In device forward conduction, in the areas JFET from grid toward emitter in MOS orientations
The lateral carrier of connection surface electrode direction is spread, make the areas JFET under emitter connection surface electrode have under grid
The almost the same carrier concentration profile in the areas JFET, under conditions of not significantly affecting device forward conduction, reduce device
The grid capacitance of part, especially grid-collector capacitance, improve the switching speed of device, reduce the switching loss of device；
Simultaneously the present invention by the introducing of higher-doped concentration N-type layer between device surface MOS structure and the drift regions N- 7 compensate for due to
Negative effect of the introducing of emitter connection surface electrode to forward conduction characteristic is acted on by the hole barrier that N-type layer provides
It further decreases the forward conduction voltage drop of device and improves the concentration distribution of carrier；Meanwhile the ditch by being connect with emitter
The electron screening effect of slot electrode shields N-type layer introducing to the adverse effect of breakdown characteristic of device, will not make the blocking of device
Deterioration in characteristics.In addition, the reduction of the areas device JFET upper gate capacitance, it is negative micro- under low current open state to reduce device
Divide capacity effect, avoids concussion of the device in opening process and the electromagnetic radiation thus brought, improve device
Performance And Reliability, and reduce the requirement to device gate drive circuit ability.Production method provided by the invention and tradition IGBT
Production method is compatible with.
Technical solution of the present invention is as follows：
A kind of planar gate IGBT, half structure cell and as shown in Figures 2 and 3 along the section of AB lines, including：From bottom to up
Back collector electrode metal 10, p-type collecting zone 9, N-type field stop layer 8 and the drift regions N- 7 being cascading；It is characterized in that,
Also there is N-type layer 13, the doping concentration of the N-type layer 13 to be more than the doping concentration of the drift regions N- 7 on 7 upper layer of the drift regions N-；
There is 13 upper layer both sides of the N-type layer p-type base area 4,4 upper layer of p-type base area there is mutually independent N+ emitter region 3 and P+ to send out
Penetrate area 2；Also there is in the N-type layer 13 of one end the groove being made of first medium layer 14 and first electrode 15 along the longitudinal direction
Structure, the depth of the groove structure are more than the depth of N-type layer 13 and run through N-type layer 13 along device horizontal direction, p-type base area 4,
N+ emitter region 3 and P+ emitter region 2, side pass through first medium layer 14 and N-type layer 13, p-type base area 4, N+ emitter region 3, P+ hairs
It penetrates area 2 and the drift regions N- 7 to be in contact, bottom and the drift regions N- 7 are in contact；2 upper table mask of the N+ emitter region 3 and P+ emitter region
There are emitter metal 1, the upper table extendable in the longitudinal direction to first medium layer 14 and first electrode 15 of the emitter metal 1
Face；Semiconductor surface between the emitter metal 1 of both sides has compound gate structure, compound gate structure and emitter
There is spacing between metal 1；The compound gate structure includes second dielectric layer 5 and the grid on second dielectric layer 5
Electrode 6, second electrode 11 and third dielectric layer 12, the gate electrode 6, second electrode 11 and third dielectric layer 12 are being parallel to
The cellular center of MOS orientations is symmetrical；The lower surface of the second dielectric layer 5 and part N+ emitter region 3, p-type
Base area 4, N-type layer 13, first medium layer 14 are connected with the upper surface of first electrode 15；Along device longitudinal direction, second electrode 11
Device both ends are located at gate electrode 6, while along device horizontal direction, the both sides of second electrode 11 are surrounded by gate electrode 6, institute
It states and is isolated by third dielectric layer 12 between second electrode 11 and gate electrode 6；The underface of second electrode 11 is N-type layer 13, the
One dielectric layer 14 and first electrode 15；Perpendicular to MOS orientations, the second electrode 11 is in 13 upper surface of N-type layer
Length be less than device N-type layer 13 in bipolar carrier diffusion length, the second electrode 11 is with the gate electrode 6 parallel
It is more than it in the length perpendicular to MOS orientations in the length of MOS orientations；The second electrode 11 and
One electrode 15 is electrically connected with emitter metal 1.
Further, a kind of planar gate IGBT, half structure cell and as shown in Figure 4 and Figure 5 along the section of AB lines, in device
Also there is one layer of p-type buried layer 16, the thickness of the p-type buried layer 16 in the N-type layer 13 between part horizontal direction p-type base area 4
Less than the thickness of p-type base area 4；The p-type buried layer 16 described in longitudinal direction be located at the other end of the relatively described groove structure and not with
The groove structure is in contact；
Further, a kind of planar gate IGBT, the section along AB lines is as shown in fig. 6, the p-type described in device longitudinal direction
Buried layer 16 is discontinuous and is uniformly distributed in N-type layer 13；
Further, a kind of planar gate IGBT, half structure cell and as shown in Figure 7 and Figure 8 along the section of AB lines, in institute
It states and also has one layer of N-type layer 17, the doping concentration of the N-type layer 17 big between second dielectric layer 5 and p-type buried layer 16 and N-type layer 13
In the doping concentration of N-type layer 13；
Further, a kind of planar gate IGBT, half structure cell and as shown in Figure 9 and Figure 10, the edge along the section of AB lines
Device longitudinal direction, second electrode 11 run through the entire half dollar cellular surface between gate electrode 6；
Further, in the second electrode 11 of 13 upper surface of N-type layer in the length for being parallel to MOS orientations
It is it perpendicular to 4 times or more of MOS orientation length；
Further, the thickness of the first medium layer 14 is more than the thickness of second dielectric layer 5 and its material can phase
It is same to can also be different；
Further, lower section of the thickness and material of the second dielectric layer 5 in the lower section of gate electrode 6 and second electrode 11
It can be the same or different；
Further, the drift region structure is NPT structures or FS structures；The IGBT device uses semi-conducting material
Si, SiC, GaAs or GaN make.
Further, the device architecture is applicable not only to IGBT device, and the p-type collecting zone 9 at the device back side is changed to N+
Layer, the structure are equally applicable to MOSFET element.
A kind of production method of planar gate IGBT, includes the following steps：
The first step：That chooses certain thickness and concentration is lightly doped FZ silicon chips to form the drift regions N- 7 of device；In silicon chip
The N-type field stop layer 8 that the back side passes through ion implanting N-type impurity and making devices of annealing；
Second step：Silicon chip is overturn and be thinned, is moved back by pre-oxidation, photoetching, etching, ion implanting and high temperature in silicon chip surface
Ignition technique, in the terminal structure of front side of silicon wafer making devices；
Third walks：Active area is etched, ion implanting N-type impurity is simultaneously annealed, and N-type layer 13 is made in front side of silicon wafer；
4th step：One layer of TEOS is deposited in silicon chip surface, after making window by lithography, groove silicon etching is carried out, etches groove,
The gash depth of formation is more than the depth of N-type layer 13 and one end positioned at device longitudinal direction；After the completion of etching groove, pass through HF
Solution is by the TEOS rinsed cleans on surface；
5th step：Form first medium layer 14 in the trench by thermal oxide；Then accumulation fills polysilicon in the trench,
Form first electrode 15；
6th step：By thermal oxide second dielectric layer 5 is formed on surface；Then the depositing polysilicon in second dielectric layer 5
Layer, and photoetching, etching form gate electrode 6 and second electrode 11；Along device longitudinal direction, second electrode 11 and gate electrode 6 are distinguished
Positioned at device both ends, while second electrode 11 is located at the upper surface of the groove structure of the 5th step formation；Simultaneously along device transverse direction side
To the both sides of second electrode 11 are surrounded by gate electrode 6；
7th step：It using photoetching process, by ion implanting p type impurity and anneals, p is formed in 13 upper layer both sides of N-type layer
Type base area 4；
8th step：Using photoetching process, by ion implanting N-type impurity, N+ emitter region 3 is formed on 4 upper layer of p-type base area；
9th step：Using photoetching process, by ion implanting p type impurity, in 4 upper layer shape P+ emitter region 2, P+ of p-type base area
Emitter region 2 and N+ emitter region 3 are mutual indepedent；
Tenth step：Dielectric layer deposited, and photoetching, etching form third dielectric layer between second electrode 11 and gate electrode 6
12；
11st step：Metal, and photoetching, etching are deposited, the device surface in gate electrode both sides forms metal collector 1；
12nd step：Silicon chip is overturn, silicon wafer thickness is thinned, in silicon chip back side implanting p-type impurity and anneals, is hindered in N-type field
Only 8 lower surface of layer forms p-type collecting zone 9；
13rd step：The back side deposits metal, and metal collector 10 is formed in 9 lower surface of p-type collecting zone.It is prepared into this hair
Bright planar gate IGBT.
Further, the thickness of the first medium layer 14 of formation is more than the thickness of the second dielectric layer 5 formed in subsequent technique
Degree；
Further, the 5th step and first medium layer 14 in the 6th step and second dielectric layer 5 can be formed simultaneously, and then may be used
It is formed simultaneously first electrode 15, second electrode 11 and gate electrode 6.
It should be noted that simplify the description, above-mentioned device architecture and preparation method are by taking n-channel IGBT device as an example
Illustrate, but the present disclosure applies equally to the preparation of p-channel IGBT device.And the processing step in above-mentioned device preparation method and
Process conditions can carry out additions and deletions and adjustment according to actual needs.
In said program, the corresponding X-direction in coordinate system shown in Fig. 2 of the device horizontal direction, device
The corresponding Z-direction in coordinate system shown in Fig. 2 of part longitudinal direction.
The operation principle of the present invention：
The switching process of IGBT is exactly the process rushed, discharged to grid capacitance, and grid capacitance gets over favourable opposition, discharge time
It is longer.Thus, in the switching process of IGBT, grid capacitance, especially grid-collector capacitance have the switching loss of device
There is important influence.For high voltage planar grid IGBT device, in order to reduce the areas the JFET resistance between device p-type base area and in device
The carrier that device is improved by the electron accumulation layer formed under the areas JFET gate electrode when part forward conduction injects enhancement effect,
Improve the concentration distribution of drift region carrier, reduce forward conduction voltage drop, improves the compromise of forward conduction voltage drop and turn-off power loss,
The areas JFET between device p-type base area are very wide.The gate structure on the wide areas JFET top brings big device capacitor, especially grid
Pole-collector capacitance reduces the switching speed of device, increases the switching loss of device, while improving and being driven to device gate
The requirement of dynamic circuit capacity.In addition, the grid capacitance on the areas device JFET top, can form negative in device low current opening process
Differential capacitance effect makes device be led to the problem of in opening process and shakes and thus bring electromagnetic radiation.By directly taking away
The gate electrode on the areas JFET top and the method for only retaining the gate electrode of p-type base area top MOS channel regions, although device can be reduced
Grid capacitance cannot be in device but in device forward conduction since the areas JFET top does not have the effect of gate electrode
The areas JFET surface forms the electron accumulation layer of high concentration, as conductance modulation type device, this also means that cannot be obtained in the areas JFET
High hole concentration is obtained, which results in the reductions of the regional Electronic and hole concentration of the entire areas JFET and the areas JFET lower part, while by
The extraction in hole is acted in p-type base area, a concentration of the 0 of the interface holoe carrier of p-type base area 9 and the drift regions N- 7, because
This so that the carrier concentration profile of the entire drift regions N- 7 is deteriorated, and eliminates the current-carrying that the gate structure on the areas JFET top is brought
Son injection enhancement effect, makes the forward conduction voltage drop of device increased dramatically, and affect the turn-off characteristic of device, is especially off
The characteristic in Carrier recombination stage after device voltage reaches busbar voltage in the process, makes the hangover in device turn off process
Time increases, and increases turn-off power loss.Structure of the invention by the upper part region of the areas device JFET oxide layer introduce with
The second electrode 11 of emitter connection, the emitter connection second electrode 11 is with gate electrode 6 perpendicular to the channel length sides MOS
It is spaced apart to formation, and the second electrode 11 is less than the areas device JFET in the length perpendicular to MOS orientations
Bipolar carrier diffusion length, the effect of the areas JFET surface in device forward conduction below gate electrode 6 due to gate electrode
The electron accumulation layer for forming high concentration, since the hole that JFET area of the conductance modulation below gate electrode 6 also obtains high concentration is dense
Degree, makes the areas JFET below gate electrode obtain high electrons and holes concentration；Simultaneously below emitter connection second electrode 11
The areas JFET, although the electron accumulation layer of high concentration cannot be formed by the effect of electrode, due to perpendicular to MOS raceway grooves
The high electrons and holes concentration in the areas JFET below length direction gate electrode, by MOS orientations from grid
Electrode 6 makes 11 lower section of emitter connection second electrode toward the lateral carrier diffusion in 11 direction of emitter connection second electrode
The areas JFET also obtain high electrons and holes concentration similar with the areas JFET of 6 lower section of gate electrode, make the JFET of entire device
Area and the areas JFET lower part obtain high electrons and holes concentration, have carrier similar with conventional planar grid IGBT structure dense
Degree distribution and forward conduction characteristic.By making the second electrode 11 and the gate electrode 6 be parallel to MOS orientations
Length be more than it in the length perpendicular to MOS orientations, and the second electrode 11 is made to be parallel to MOS raceway grooves
The length of length direction is it perpendicular to 4 times or more of MOS orientation length, and the present invention is not significantly affecting device
The grid capacitance of device, especially grid-collector are reduced in the case of forward conduction characteristic and breakdown characteristics as far as possible
Capacitance improves the switching speed of device, reduces the switching loss of device.Meanwhile the present invention by device surface MOS structure and
The introducing of higher-doped concentration N-type layer is further compensated due to the introducing pair of emitter connection surface electrode between the drift regions N- 7
The negative effect of forward conduction characteristic, and the hole barrier effect provided by N-type layer further decreases the forward conduction of device
Pressure drop and the concentration distribution for improving carrier；Meanwhile the electron screening by connecting trenched electrode structures with emitter acts on screen
N-type layer introducing has been covered to the adverse effect of breakdown characteristic of device, and the blocking characteristics of device will not be made to deteriorate.In addition, device JFET
The reduction of area's upper gate capacitance reduces negative differential capacity effect of the device under low current open state, avoids device
Concussion in opening process and the electromagnetic radiation thus brought, improve the Performance And Reliability of device.The present invention carries
The production method emitter connection second electrode 11 of confession is formed with gate electrode 6 by a step process, and additional work need not be increased
Skill step is compatible with conventional planar grid IGBT production methods.
Beneficial effects of the present invention are shown：
Structure of the invention reduces the grid capacitance of device, especially grid-by the introducing of surface recombination device architecture
Collector capacitance improves the switching speed of device, reduces the switching loss of device, while improving the forward conduction of device
The concentration distribution of pressure drop and carrier improves the compromise of device forward conduction voltage drop and switching loss, improves the property of device
Can, while the blocking characteristics of device will not be made to deteriorate.In addition, the reduction of the areas device JFET upper gate capacitance, reduces device
Negative differential capacity effect under low current open state avoids the electricity that shakes and thus bring of the device in opening process
Magnetic radiation problem improves the Performance And Reliability of device, and reduces the requirement to device gate drive circuit ability.The present invention carries
The production method of confession is compatible with tradition IGBT production methods.The present invention is suitable for from mid power to powerful high-voltage semi-conductor
Power device field.
Description of the drawings
Fig. 1 is traditional half cellular structural schematic diagram of planar gate IGBT device.
Fig. 2 is the first half cellular structural schematic diagram of planar gate IGBT device provided by the invention.
Fig. 3 is diagrammatic cross-section of the first half structure cell of planar gate IGBT device provided by the invention along AB lines.
Fig. 4 second of planar gate IGBT device, half cellular structural schematic diagrams provided by the invention.
Fig. 5 is diagrammatic cross-section of second of planar gate IGBT device, half structure cell provided by the invention along AB lines.
Fig. 6 is diagrammatic cross-section of the third half structure cell of planar gate IGBT device provided by the invention along AB lines.
Fig. 7 half cellular structural schematic diagrams of the 4th kind of planar gate IGBT device provided by the invention.
Fig. 8 is diagrammatic cross-section of the 4th kind of half structure cell of planar gate IGBT device provided by the invention along AB lines.
Fig. 9 half cellular structural schematic diagrams of the 5th kind of planar gate IGBT device provided by the invention.
Figure 10 is diagrammatic cross-section of the 5th kind of half structure cell of planar gate IGBT device provided by the invention along AB lines.
In Fig. 1 to Figure 10,1 is emitter metal, and 2 be P+ emitter region, and 3 be N+ emitter region, and 4 be p-type base area, and 5 be medium
Layer, 6 be gate electrode, and 7 be the drift regions N-, and 8 be N-type electric field trapping layer, and 9 be p-type collecting zone, and 10 be collector electrode metal, 11 for
Emitter connection surface electrode, 12 be dielectric layer, and 13 be N-type layer, and 14 be trench dielectric layer, and 15 be trench electrode, and 16 bury for p-type
Layer, 17 be N-type layer.
Specific implementation mode
Below in conjunction with attached drawing, the principle of the present invention and characteristic are described further, specific embodiments of the present invention
It is illustrated by taking the IGBT of 6500V voltage class as an example, the given examples are served only to explain the present invention, is not intended to limit the present invention
Range.
Embodiment 1：
A kind of planar gate IGBT, half structure cell and as shown in Figures 2 and 3 along the section of AB lines, including：From bottom to up
Back collector electrode metal 10, p-type collecting zone 9, N-type field stop layer 8 and the drift regions N- 7 being cascading；It is characterized in that,
Also there is N-type layer 13, the doping concentration of the N-type layer 13 to be more than the doping concentration of the drift regions N- 7 on 7 upper layer of the drift regions N-；
There is 13 upper layer both sides of the N-type layer p-type base area 4,4 upper layer of p-type base area there is mutually independent N+ emitter region 3 and P+ to send out
Penetrate area 2；Also there is in the N-type layer 13 of side the groove being made of first medium layer 14 and first electrode 15 along the longitudinal direction
Structure, the depth of the groove structure are more than the depth of N-type layer 13 and run through N-type layer 13 along device horizontal direction, p-type base area 4,
N+ emitter region 3 and P+ emitter region 2, side pass through first medium layer 14 and N-type layer 13, p-type base area 4, N+ emitter region 3, P+ hairs
It penetrates area 2 and the drift regions N- 7 to be in contact, bottom and the drift regions N- 7 are in contact；2 upper table mask of the N+ emitter region 3 and P+ emitter region
There are emitter metal 1, the upper table extendable in the longitudinal direction to first medium layer 14 and first electrode 15 of the emitter metal 1
Face；Semiconductor surface between the emitter metal 1 of both sides has compound gate structure, compound gate structure and emitter
There is spacing between metal 1；The compound gate structure includes second dielectric layer 5 and the grid on second dielectric layer 5
Electrode 6, second electrode 11 and third dielectric layer 12, the gate electrode 6, second electrode 11 and third dielectric layer 12 are being parallel to
The cellular center of MOS orientations is symmetrical；The lower surface of the second dielectric layer 5 and part N+ emitter region 3, p-type
Base area 4, N-type layer 13, first medium layer 14 are connected with the upper surface of first electrode 15；Along device longitudinal direction, second electrode 11
Device both ends are located at gate electrode 6, while along device horizontal direction, the both sides of second electrode 11 are surrounded by gate electrode 6, institute
It states and is isolated by third dielectric layer 12 between second electrode 11 and gate electrode 6；The underface of second electrode 11 is N-type layer 13, the
One dielectric layer 14 and first electrode 15；Perpendicular to MOS orientations, the second electrode 11 is in 13 upper surface of N-type layer
Length be less than device N-type layer 13 in bipolar carrier diffusion length, the second electrode 11 is with the gate electrode 6 parallel
It is more than it in the length perpendicular to MOS orientations in the length of MOS orientations；The second electrode 11 and
One electrode 15 is electrically connected with emitter metal 1.Formed half cellular be in the length for being parallel to MOS orientations
50-60 microns, the JFET sector widths between p-type base area 4 are 35-45 microns, and half cellular of formation is perpendicular to MOS raceway grooves
The length of length direction is 3-10 microns；The gate electrode of formation is 1-5 microns in the length perpendicular to MOS orientations；
The second electrode 11 of formation is located at the center of half dollar born of the same parents, symmetrical, length 30- in the direction for being parallel to MOS channel lengths
40 microns, second electrode 11 is 2-5 microns in the direction length perpendicular to MOS channel lengths；The depth of the N-type layer 13 of formation is big
0.5-1 microns of the depth in p-type base area 4；The groove width of first medium layer 14 and first electrode 15 composition of formation is~1 micro-
Rice, the gash depth are more than 0.5-1 microns of the depth of N-type layer 13.
Embodiment 2：
A kind of planar gate IGBT, half structure cell and as shown in Figure 4 and Figure 5 along the section of AB lines, in the base of embodiment 1
On plinth, also it is with a slice width degree in the N-type layer 13 between being parallel to p-type base area 4 described in MOS orientations
20-30 microns of p-type buried layer 16, the thickness of the p-type buried layer 16 are less than the thickness of p-type base area 4；Perpendicular to MOS ditch Taoist priests
Direction is spent, the p-type buried layer 16 is located at the opposite other end of the groove structure, and width is 1-5 microns.P-type buried layer 16
In the presence of influence of the N-type layer 13 to device electric breakdown strength is further shielded, high 13 concentration of N-type layer can be used；P-type buried layer simultaneously
16 presence also has electric field shielding effect to the second dielectric layer 5 of upper part, reduces the high electric field in second dielectric layer 5,
Improve the reliability of second dielectric layer 5.In device breakdown, 13 fully- depleted of N-type layer, p-type buried layer 16 is fully- depleted or part
It exhausts.
Embodiment 3：
A kind of planar gate IGBT, the section along AB lines is as shown in fig. 6, on the basis of embodiment 2, perpendicular to MOS
Orientation, the p-type buried layer 16 is discontinuous and is evenly distributed in N-type layer 13.Discontinuous and equally distributed p-type is buried
Layer 16 can provide better electric field shielding effect, and reduce the negative effect on state characteristic.
Embodiment 4：
A kind of planar gate IGBT, half structure cell and as shown in Figure 7 and Figure 8 along the section of AB lines, in the base of embodiment 3
On plinth, there are one layer of N-type layer 17, the N-type layer 17 to mix between the second dielectric layer 5 and p-type buried layer 16 and N-type layer 13
Miscellaneous concentration is more than the doping concentration of N-type layer 13.The introducing of N-type layer 17 further improves the forward conduction characteristic of device, more preferably
The introducing for compensating for second electrode 11 to the adverse effect of break-over of device characteristic.In device breakdown, N-type layer 17 is full consumption
To the greatest extent.
Embodiment 5：
A kind of planar gate IGBT, half structure cell and as shown in Figure 9 and Figure 10 along the section of AB lines, in embodiment 4
On the basis of, along device longitudinal direction, second electrode 11 runs through the entire half dollar cellular surface between gate electrode 6.11 face of second electrode
Long-pending increase further reduces the grid capacitance of device, especially grid-collector capacitance, reduces the switch speed of device
Degree, increases the switching loss of device.
Claims (6)
1. a kind of planar gate IGBT, including：The back collector electrode metal (10) that is cascading from bottom to up, p-type collecting zone
(9), N-type field stop layer (8) and the drift regions N- (7)；It is characterized in that, the drift regions N- (7) upper layer also has N-type layer
(13), the doping concentration of the N-type layer (13) is more than the doping concentration of the drift regions N- (7)；N-type layer (13) the upper layer both sides tool
There are p-type base area (4), p-type base area (4) upper layer that there is mutually independent N+ emitter region (3) and P+ emitter region (2)；Along vertical
Also have by first medium layer (14) and first electrode (15) group in MOS orientations, the N-type layer (13) of device one end
At groove structure, the depth of the groove structure is more than the depth of N-type layer (13) and passed through along MOS orientations are parallel to
N-type layer (13), p-type base area (4), N+ emitter region (3) and P+ emitter region (2) are worn, side passes through first medium layer (14) and N-type
Layer (13), p-type base area (4), N+ emitter region (3), P+ emitter region (2) and the drift regions N- (7) are in contact, bottom and the drift regions N-
(7) it is in contact；The N+ emitter region (3) and P+ emitter region (2) upper surface have emitter metal (1), the emitter metal
(1) along the upper surface for extending to first medium layer (14) and first electrode (15) perpendicular to MOS orientations；Positioned at both sides
Emitter metal (1) between semiconductor surface there is compound gate structure, compound gate structure and emitter metal (1) it
Between have spacing；The compound gate structure includes second dielectric layer (5) and the gate electrode on second dielectric layer (5)
(6), second electrode (11) and third dielectric layer (12), the gate electrode (6), second electrode (11) and third dielectric layer (12) exist
The cellular center for being parallel to MOS orientations is symmetrical；The lower surface of the second dielectric layer (5) emits with part N+
Area (3), p-type base area (4), N-type layer (13), first medium floor (14) are connected with the upper surface of first electrode (15)；Along perpendicular to
MOS orientations, one end of the embedded gate electrode (6) of second electrode (11), the second electrode (11) and gate electrode (6) it
Between pass through third dielectric layer (12) be isolated；The underface of second electrode (11) is N-type layer (13), first medium layer (14) and first
Electrode (15)；Perpendicular to MOS orientations, length of the second electrode (11) in N-type layer (13) upper surface is less than
Bipolar carrier diffusion length in device N-type layer (13), the second electrode (11) and the gate electrode (6) are being parallel to
The length of MOS orientations is more than it in the length perpendicular to MOS orientations；The second electrode (11) and
One electrode (15) is electrically connected with emitter metal (1).
2. a kind of planar gate IGBT according to claim 1, it is characterised in that：It is being parallel to MOS orientations, p
Also there is one layer of p-type buried layer (16), the thickness of the p-type buried layer (16) to be less than in the N-type layer (13) between type base area (4)
The thickness of p-type base area (4)；Along perpendicular to MOS orientations, the p-type buried layer (16) is located at the relatively described groove structure
One end and be not in contact with the groove structure.
3. a kind of planar gate IGBT according to claim 2, it is characterised in that：Perpendicular to MOS orientations, institute
It states p-type buried layer (16) discontinuously and is evenly distributed in N-type layer (13).
4. a kind of planar gate IGBT according to claim 3, it is characterised in that：It is buried with p-type in the second dielectric layer (5)
There are one layer of N-type layer (17), the doping concentration of the N-type layer (17) to be more than N-type layer (13) between layer (16) and N-type layer (13)
Doping concentration.
5. a kind of planar gate IGBT according to claim 4, it is characterised in that：The thickness of the first medium layer (14) is big
In second dielectric layer (5) thickness and its material can be the same or different.
6. a kind of production method of planar gate IGBT, includes the following steps：
The first step：That chooses certain thickness and concentration is lightly doped FZ silicon chips to form the drift regions N- (7) of device；It is carried on the back in silicon chip
The N-type field stop layer (8) that face passes through ion implanting N-type impurity and making devices of annealing；
Second step：Silicon chip is overturn and be thinned, passes through pre-oxidation, photoetching, etching, ion implanting and high annealing work in silicon chip surface
Skill, in the terminal structure of front side of silicon wafer making devices；
Third walks：Active area is etched, ion implanting N-type impurity is simultaneously annealed, and N-type layer (13) is made in front side of silicon wafer；
4th step：One layer of TEOS is deposited in silicon chip surface, after making window by lithography, groove silicon etching is carried out, etches groove, formed
Gash depth be more than the depth of N-type layer (13) and positioned at perpendicular to one end of MOS orientations；Etching groove is completed
Afterwards, by HF solution by the TEOS rinsed cleans on surface；
5th step：Form first medium layer (14) in the trench by thermal oxide；Then accumulation fills polysilicon, shape in the trench
At first electrode (15)；
6th step：By thermal oxide second dielectric layer (5) is formed on surface；Then the depositing polysilicon in second dielectric layer (5)
Layer, and photoetching, etching form gate electrode (6) and second electrode (11)；Along perpendicular to MOS orientations, second electrode
(11) and gate electrode (6) is located at device both ends, while second electrode (11) is located at the upper of the groove structure of the 5th step formation
Surface；Simultaneously along MOS orientations are parallel to, the both sides of second electrode (11) are surrounded by gate electrode (6)；
7th step：It using photoetching process, by ion implanting p type impurity and anneals, p-type is formed in N-type layer (13) upper layer both sides
Base area (4)；
8th step：Using photoetching process, by ion implanting N-type impurity, N+ emitter region (3) is formed on p-type base area (4) upper layer；
9th step：Using photoetching process, by ion implanting p type impurity, in p-type base area (4) upper layer shape P+ emitter region (2), P+
Emitter region (2) and N+ emitter region (3) are mutual indepedent；
Tenth step：Dielectric layer deposited, and photoetching, etching form third dielectric layer between second electrode (11) and gate electrode (6)
(12)；
11st step：Metal, and photoetching, etching are deposited, the device surface in gate electrode both sides forms metal emitting (1)；
12nd step：Silicon chip is overturn, silicon wafer thickness is thinned, in silicon chip back side implanting p-type impurity and anneals, in N-type field stop layer
(8) lower surface forms p-type collecting zone (9)；
13rd step：The back side deposits metal, and metal collector (10) is formed in p-type collecting zone (9) lower surface.
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| CN108461537B (en) * | 2018-02-05 | 2019-11-29 | 电子科技大学 | A kind of trench gate charge storage type IGBT and preparation method thereof |
| CN108321193B (en) * | 2018-02-05 | 2019-12-10 | 电子科技大学 | trench gate charge storage type IGBT and manufacturing method thereof |
| CN108493242B (en) * | 2018-05-31 | 2020-08-28 | 电子科技大学 | Carrier enhancement type IGBT device for optimizing internal electric field |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19608906C1 (en) * | 1996-03-07 | 1997-05-22 | Siemens Ag | Semiconductor component controlled by field effect esp. isolated gate bipolar transistor IGBT |
| US6091107A (en) * | 1997-01-21 | 2000-07-18 | Mitel Semiconductor Limited | Semiconductor devices |
| EP1469524A2 (en) * | 1991-08-08 | 2004-10-20 | Kabushiki Kaisha Toshiba | Insulated trench gate bipolar transistor |
| CN102148240A (en) * | 2011-03-10 | 2011-08-10 | 电子科技大学 | SOI-LIGBT (silicon on insulator-lateral insulated gate bipolar transistor) device with split anode structure |
-
2016
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1469524A2 (en) * | 1991-08-08 | 2004-10-20 | Kabushiki Kaisha Toshiba | Insulated trench gate bipolar transistor |
| DE19608906C1 (en) * | 1996-03-07 | 1997-05-22 | Siemens Ag | Semiconductor component controlled by field effect esp. isolated gate bipolar transistor IGBT |
| US6091107A (en) * | 1997-01-21 | 2000-07-18 | Mitel Semiconductor Limited | Semiconductor devices |
| CN102148240A (en) * | 2011-03-10 | 2011-08-10 | 电子科技大学 | SOI-LIGBT (silicon on insulator-lateral insulated gate bipolar transistor) device with split anode structure |
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