CN107785415B - SOI-RC-LIGBT device and preparation method thereof - Google Patents
SOI-RC-LIGBT device and preparation method thereof Download PDFInfo
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- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
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Abstract
The invention provides an SOI-RC-LIGBT device and a preparation method thereof, comprising an N-type substrate, a buried oxide layer, an N-type drift region, a trench gate structure, a P-type base region, an N-type drift region+Source region and P+The semiconductor device comprises a contact region, an emitter, an oxide layer, an N-type buffer region and a P-type collector region; an N-type strip is arranged on the surface of an N-type drift region between a P-type base region and an N-type buffer region, and a P-type buried layer is arranged in the drift region below the N-type strip; a dielectric groove structure is arranged between the right side of the N-type strip and the P-type buried layer, and the left side of the N-type buffer layer and the left side of the P-type collector region; an N + collector region is arranged between the N-type strip and the dielectric groove structure; the SOI-RC-LIGBT provided by the invention can eliminate the snapback phenomenon of the IGBT conduction characteristic, improve the breakdown voltage of the device, reduce the forward conduction voltage drop of the device, improve the turn-off speed, reduce the turn-off loss and improve the reverse recovery characteristic of the integrated freewheeling diode.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a reverse conducting type lateral insulated gate bipolar transistor (RC-LIGBT) device based On an SOI (silicon On insulator) technology and a preparation method thereof.
Background
The semiconductor power device is a basic electronic component for controlling and converting energy of a power electronic system, and the continuous development of the power electronic technology develops a wide application field for the semiconductor power device. The MOS type semiconductor power device marked by IGBT, VDMOS, CoolMOS is the mainstream of devices in the field of power electronics today, and among them, the most representative semiconductor power device belongs to the IGBT.
An IGBT (Insulated Gate Bipolar Transistor) is a voltage controlled MOS/BJT composite device. Structurally, the structure of the IGBT is very similar to that of the VDMOS, except that N of the VDMOS is used+The substrate is adjusted to be P+The substrate, but the introduced conductance modulation effect overcomes the contradiction between the intrinsic on-resistance and breakdown voltage of the VDMOS, so that the IGBT has the main advantages of both a bipolar power transistor and a power MOSFET: high input impedance, low input drive power, low on-state voltage, high current capacity, high switching speed, etc. Due to the unique and irreplaceable performance advantages of IGBTs, their self-propelled utility products have found wide application in many areas, such as: the new energy technology, advanced transportation means represented by motor cars and high-speed rails, hybrid electric vehicles, household appliances and the like.
As a power device, the IGBT with the longitudinal structure occupies a large area in an intelligent power integrated circuit, and the process is difficult to be compatible with other device processes in the circuit, so that the overall performance and reliability are influenced. The LIGBT (Lateral Insulated Gate Bipolar Transistor) can effectively solve the above problems. Transient substrate surge current in the process of isolating the LIGBT switch, dynamic and static cross influence among devices (including among a plurality of LIGBTs, between the LIGBTs and CMOS, between bipolar devices) and the like are combined, so that the LIGBT switch is difficult to be applied to an intelligent power integrated circuit which needs to integrate a plurality of LIGBT single chips. The SOI (silicon On insulator) process adopts medium isolation, basically has no substrate current leakage, eliminates the problems of parasitic effect and latch-up effect between devices On the reliability of a chip, effectively reduces the chip area occupied by the traditional PN junction isolation structure, is favorable for realizing higher performance, lower power consumption and higher speed, and is favorable for reducing the cost.
In the power system, the IGBT generally needs to be used with a Free Wheeling Diode (Free Wheeling Diode) to ensure the safety and stability of the system. Therefore, in a conventional IGBT module or a single-tube device, there is usually a FWD connected in anti-parallel therewith, which not only increases the overall production cost, but also during packagingThe overall performance is affected by parasitic effects from the metal interconnects used. To solve this problem, e.napoli et al proposed in 2002 that an IGBT capable of Reverse conduction, called RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor), is achieved by introducing N on the collector side+The method of the collector region realizes the integration of the IGBT and the diode. A conventional SOI-RC-LIGBT is shown in FIG. 1, in which a P-type base region, a drift region, an N-type buffer layer, and N+The collector region forms a parasitic diode structure that conducts current in the freewheel mode. But N is+The introduction of collector regions, wherein the channel region, the drift region, the N-type buffer layer and the N, adversely affects the forward conduction characteristics+The collector region forms a parasitic VDMOS structure, and electrons injected into the drift region from the channel are directly injected from N under the condition of low current+The collector region flows out, so that the collector junction cannot be opened, the conductance modulation effect cannot be formed in the drift region, and the device has VDMOS (vertical double-diffused metal oxide semiconductor) characteristics. When the electron current increases to a certain value, the collector junction is turned on, P+And injecting holes into the drift region by the collector region to form a conductance modulation effect, wherein the forward voltage drop is rapidly reduced along with the increase of current, so that a current-voltage curve presents a negative resistance (Snapback) phenomenon. This will cause the IGBT to not be fully turned on for parallel applications, and thus presents reliability issues.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention aims to suppress Snapback phenomenon of the conventional SOI-RC-LIGBT as shown in fig. 1, and to improve the stability of the whole system, and provides an SOI-RC-LIGBT device and a method for manufacturing the same.
In order to achieve the purpose, the technical scheme of the invention is as follows:
an SOI-RC-LIGBT device comprising: the N-type substrate, the buried oxide layer and the N-type drift region are arranged from bottom to top in sequence; a groove grid structure consisting of a grid dielectric layer and a grid electrode is arranged at one end in the N-type drift region, and the grid electrode is positioned in one side of the grid dielectric layer; the other side of the gate dielectric layer in the N-type drift region is provided with a P-type base region, and N is arranged above the inner part of the P-type base region+Source region and P+Contact zone, anThe P-type base region and N+The side surfaces of the source regions are all contacted with the side surfaces of the gate dielectric layers; said N is+Source region and P+An emitter is arranged above the contact region, and oxide layers are arranged above the gate dielectric layer and the gate electrode; an N-type buffer region is arranged at one end, far away from the groove grid structure, in the N-type drift region, and a P-type collector region is arranged above the inside of the N-type buffer region; an N-type strip is arranged on the surface of the N-type drift region between the P-type base region and the N-type buffer region, and a P-type buried layer is arranged in the drift region below the N-type strip; the P-type buried layer is not contacted with the P-type base region; a dielectric groove structure is arranged between the right side of the N-type strip and the P-type buried layer, and the left side of the N-type buffer layer and the left side of the P-type collector region; an N + collector region is arranged between the N-type strip and the dielectric groove structure; the upper surface of part of the N + collector region, the upper surfaces of the dielectric groove structure and the P type collector region are collectors; the depth of the dielectric groove structure is not less than the depth of the N-type strip and the P-type collector region; the concentration of the N-type strips and the concentration of the P-type buried layer are greater than that of the N-type drift region.
The invention introduces a composite structure formed by a P-type buried layer and a dielectric groove on the surface of a device, and the composite structure comprises a left MOS structure, an N-type drift region, an N-type strip and an N-type strip of the device+The LDMOS part formed by the collector region is separated from the LIGBT part formed by the MOS structure on the left side of the device, the N-type drift region, the N-type buffer layer and the P-type collector region, and the doping concentrations of the N-type strip, the P-type buried layer and the N-type drift region are improved through Triple RESURF action provided by the P-type buried layer and the buried oxide layer, the distribution of an electric field on the surface of the device is improved, and the breakdown voltage of the device is improved. When the device is in forward conduction, the channel is opened, and the voltage V between the collector and the emitter is reducedCEWhen the voltage is less than the turn-on voltage (0.7V) of the P-type collector region and the N-type buffer layer corresponding to the collector junction, electrons flow through the channel, the N-type drift region, the N-type strip and the N+And the collector region flows out of the collector electrode, and the corresponding unipolar conduction mode of the LDMOS is represented. The existence of the high-concentration N-type strip greatly reduces the on-resistance of the LDMOS, and large current is obtained under a certain collector current. When V isCEAfter increasing to the starting voltage of the collector junction, the P-type collector region starts to inject holes into the N-type drift region to form a conductivity modulation effect, namely LIThe GBT is turned on and exhibits a bipolar conduction pattern corresponding to the IGBT. The LDMOS and the LIGBT are separated by the P-type buried layer and the dielectric groove structure, so that a mixed conduction mode of the LDMOS and the LIGBT is formed, and V can be realized when the structure is in forward conductionCEThe Snapback phenomenon is completely eliminated. And is composed of P-type base region, N-type drift region, N-type strip and N+And an anti-parallel diode formed by the collector region realizes the reverse conduction performance of the LIGBT.
Preferably, the P-type buried layer is composed of a plurality of regions whose concentrations decrease sequentially from left to right.
Preferably, the N-type strips are composed of a plurality of regions whose concentration increases sequentially from left to right.
As a preferable mode, on the basis of the trench MOS structure composed of the trench gate structure and the P-type base region, the N + source region, and the P + contact region, a planar gate structure composed of a second gate dielectric layer and a second gate electrode and a planar MOS structure formed by the planar gate structure, the P-type base region, and the second N + source region are added to form a composite dual-gate structure composed of the planar gate structure and the trench gate structure.
Preferably, the depth of the dielectric groove structure is greater than the depths of the P-type buried layer and the N-type buffer region.
And the high-concentration N-type strip, the P-type buried layer and the N-type drift region are fully depleted before the device breaks down.
The structure of the invention is not only suitable for bulk silicon (Si), but also can be used for semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs) or gallium nitride (GaN); the structure is not limited to SOI technology, but can be used for bulk silicon and junction isolation technology.
In order to achieve the above object, the present invention further provides a method for manufacturing the SOI-RC-LIGBT device, which sequentially comprises the following steps:
preparing an SOI material, injecting and pushing phosphorus into an N-type buffer layer, etching a groove gate, growing a gate oxide layer, depositing and etching N + polysilicon, injecting and pushing boron into a P-type base region, injecting high-energy boron into a P-type buried layer, injecting and pushing arsenic into a surface N-type layer, injecting arsenic into an N + source region and an N + collector region, injecting and pushing boron into a P + contact region, etching a rectangular groove, depositing and etching silicon dioxide, injecting boron into a P-type collector region and annealing at a low temperature, depositing and refluxing BPSG, etching a contact hole, and depositing and etching an aluminum layer.
Preferably, the method for manufacturing the SOI-RC-LIGBT device further comprises the following steps:
the first step is as follows: preparing a silicon-on-insulator material, wherein the thickness of the substrate is 300-500 microns, and the doping concentration is 1014～1015Per cm3The thickness of the buried oxide layer on the substrate is 0.5-3 microns, the thickness of the SOI layer is 5-20 microns, and the doping of the SOI layer is 5e14cm-3～1e15cm-3；
The second step is that: photoetching, implanting N-type impurities into the right side area of the surface of the silicon wafer through ions, and annealing to manufacture an N-type buffer layer, wherein the thickness of the formed N-type buffer layer is 2-4 microns;
the third step: photoetching, etching a groove on the left side of the surface of the silicon wafer, growing a gate oxide layer on the surface of the silicon wafer through thermal oxidation, and depositing a gate electrode material; photoetching, etching the unnecessary gate electrode material and the gate oxide layer to form a gate electrode;
the fourth step: photoetching, injecting a P-type impurity into the left side of a drift region on the surface of the silicon wafer through ions, and annealing to manufacture a P-type base region, wherein the thickness of the formed P-type base region is 2-3 microns;
the fifth step: photoetching, implanting high-energy ions into a P-type impurity in the middle of a drift region on the surface of a silicon wafer to form a P-type buried layer, wherein the depth of the P-type buried layer from the surface is 0.5-1 micron, the thickness of the P-type buried layer is 0.5-1 micron, and the concentration of the P-type buried layer is 5e15cm-3～1e16cm-3；
And a sixth step: photoetching, implanting N-type impurities in the middle of the drift region on the surface of the silicon wafer by ions, and annealing to form N-type strip regions with the concentration of 5e15cm-3～1e16cm-3；
The seventh step: photoetching, and preparing N on the surface of a silicon wafer by ion implantation of N-type impurities+Source region and N+A collector region;
eighth step: photoetching, implanting P-type impurities on the surface of a silicon wafer through ions, and annealing to manufacture a P-type contact region, wherein the thickness of the formed N-type source region and the P-type contact region is about 0.2-0.3 microns;
the ninth step: photoetching, etching and filling a medium to form a medium groove, wherein the depth of the formed medium groove structure is 1-2 microns, and the width of the formed medium groove structure is 0.1-0.5 micron;
the tenth step: photoetching, implanting P-type impurities into the right region of the surface of the silicon wafer through ions, and annealing at low temperature to manufacture a P-type collector region, wherein the thickness of the formed P-type collector region is 0.3-0.5 microns;
the eleventh step: depositing, photoetching and etching the dielectric layer to form a dielectric layer;
the twelfth step: depositing, photoetching and etching metal to form a metal emitter and a metal collector on the surface of the device; thus preparing the SOI-RC-LIGBT device.
The working principle and the beneficial effects of the invention are as follows:
on the basis of the structure of the traditional SOI-RC-LIGBT, a composite structure formed by an N-type strip, a P-type buried layer and a dielectric groove structure is introduced on the surface of an N-type drift region of a device. The N-type strip, the P-type buried layer, the N-type drift region and the buried oxide layer form a Triple RESURF structure, so that when the device is in a blocking state, the distribution of an electric field on the surface of the device can be improved, the breakdown voltage of the device is improved, and the doping concentrations of the N-type strip, the P-type buried layer and the N-type drift region are improved. When the device is conducted in the forward direction, the invention introduces a P-type buried layer and a dielectric groove structure on the surface of the device, so that the device consists of a MOS structure on the left side of the device, an N-type drift region and an N+The LDMOS part formed by the collector region is separated from the LIGBT part formed by the MOS structure on the left side of the device, the N-type drift region, the N-type buffer layer and the P-type collector region. When the device is in forward conduction, the channel is opened, and the voltage V between the collector and the emitter is reducedCEWhen the voltage is less than the turn-on voltage (0.7V) of the P-type collector region and the N-type buffer layer corresponding to the collector junction, electrons flow through the channel, the N-type drift region, the N-type strip and the N+And the collector region flows out of the collector electrode, and the corresponding unipolar conduction mode of the LDMOS is represented. The existence of the high-concentration N-type strip greatly reduces the on-resistance of the LDMOS, and large current is obtained under a certain collector current. When V isCEAfter increasing to the starting voltage of the collector junction, the P-type collector region starts to inject into the N-type drift regionAnd holes form a conductivity modulation effect, and the LIGBT is conducted to show a bipolar conductivity mode corresponding to the IGBT. The LDMOS and the LIGBT are separated by the P-type buried layer and the dielectric groove structure, so that a mixed conduction mode of the LDMOS and the LIGBT is formed, and V can be realized when the structure is in forward conductionCEThe Snapback phenomenon is completely eliminated. Meanwhile, due to the existence of the high-concentration N-type strip, the LDMOS component in the whole collector current is increased, the excessive carrier injection in an N-type drift region under a certain current is reduced, and meanwhile, a small forward conduction voltage drop can be obtained under the whole collector voltage. When the device is turned off, due to the transverse expansion of the depletion layer of the P-type RESURF layer, the expansion speed of the depletion layer in the drift region is high, the turn-off speed of the device is improved, and the turn-off loss of the device is reduced; at the same time, from PbodyBase region, N-type drift region, N-type bar and N+And an anti-parallel diode formed by the collector region realizes the reverse conduction performance of the LIGBT. The presence of the P-type buried layer improves the reverse recovery characteristics of the diode when the anti-parallel diode freewheels.
FIG. 5 is a graph comparing the turn-on characteristics of a conventional SOI-RC-LIGBT and the SOI-RC-LIGBT of the present invention. As can be seen from the figure, in the forward conduction characteristic, the conventional SOI-RC-LIGBT without the N-type buffer layer has the Snapback phenomenon, and the concentration of the N-type buffer layer is 5e15cm-3The Snapback phenomenon of the traditional SOI-RC-LIGBT is more serious, and the concentration of the N-type buffer layer is 1e16cm-3The Snapback phenomenon of the traditional SOI-RC-LIGBT is more serious. The SOI-RC-LIGBT provided by the invention has the concentration of 5e15cm in N-type strips and P-type buried layers-3The concentration of the N-type buffer layer is 1e16cm-3Under the condition of (2), the Snapback phenomenon is completely eliminated. Meanwhile, on the aspect of reverse conduction characteristics, the conduction characteristics of the SOI-RC-LIGBT body-integrated diode provided by the invention are superior to those of the traditional SOI-RC-LIGBT body-integrated diode.
FIG. 6 is a graph comparing the breakdown characteristics of conventional SOI-RC-LIGBT and SOI-RC-LIGBT of the present invention. As can be seen from the figure, the breakdown voltage BV of the conventional SOI-RC-LIGBT without the N-type buffer layer is only 137V, and the concentration of the N-type buffer layer is 5e15cm-3The BV of the conventional SOI-RC-LIGBT is 169V, and the concentration of the N-type buffer layer is 1e16cm-3The BV of the traditional SOI-RC-LIGBT reaches 211V, and the concentration of the SOI-RC-LIGBT provided by the invention in an N-type strip and a P-type buried layer is 5e15cm-3The concentration of the N-type buffer layer is 1e16cm-3With a breakdown voltage BV of up to 273V, the BV increment is about 30% compared to a conventional SOI-RC-LIGBT with the same N-type buffer layer concentration.
FIG. 7 is a graph comparing the reverse recovery characteristics of conventional SOI-RC-LIGBT and SOI-RC-LIGBT body-integrated diodes of the present invention. It can be seen from the figure that the reverse recovery characteristics of the SOI-RC-LIGBT diode proposed by the present invention are softer than the conventional structure, and the oscillation problem in the reverse recovery process of the conventional structure is avoided.
In summary, the SOI-RC-LIGBT provided by the present invention improves the breakdown voltage of the device, reduces the forward conduction voltage drop of the device, improves the turn-off speed, and reduces the turn-off loss while eliminating the snapback phenomenon of the IGBT conduction characteristic. At the same time, the reverse recovery characteristics of the integrated freewheeling diode are improved.
Drawings
FIG. 1 is a schematic diagram of a conventional SOI-RC-LIGBT structure.
FIG. 2 is a schematic structural diagram of an SOI-RC-LIGBT according to embodiment 1 of the present invention.
FIG. 3 is a schematic structural diagram of an SOI-RC-LIGBT according to embodiment 4 of the present invention.
FIG. 4 is a schematic diagram of a process for preparing an SOI-RC-LIGBT according to the present invention.
FIG. 5 is a graph comparing the turn-on characteristics of a conventional SOI-RC-LIGBT and the SOI-RC-LIGBT of the present invention.
FIG. 6 is a graph comparing the breakdown characteristics of a conventional SOI-RC-LIGBT with the SOI-RC-LIGBT of the present invention.
FIG. 7 is a graph comparing the reverse recovery characteristics of conventional SOI-RC-LIGBT and SOI-RC-LIGBT body-integrated diodes of the present invention.
Wherein 1 is an oxide layer, and 2 is N+Source region, 3 is emitter, 4 is P+Contact zone, 5 is PA type base region 6 is a gate electrode, 7 is a gate dielectric layer, 8 is a buried oxide layer, 9 is an N type substrate, 10 is a surface oxide layer 2, 11 is a P type collector region, 12 is a collector, 13 is N+Collector region 14 is N-type buffer layer, 15 is N-type drift region, 16 is N-type strip, 17 is P-type buried layer, 18 is dielectric groove structure, and 2-1 is second N+And the source region 6-1 is a second gate electrode, and the source region 7-1 is a second gate dielectric layer.
In FIGS. 5 to 7, "Conventional SOI-RC-LIGBT" is Conventional SOI-RC-LIGBT, "New SOI-RC-LIGBT" is SOI-RC-LIGBT of the present invention, "Nbuffer" is the concentration of N-type buffer layer, and "BV" represents the breakdown voltage.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
An SOI-RC-LIGBT device comprising: the N-type substrate 9, the buried oxide layer 8 and the N-type drift region 15 are arranged from bottom to top in sequence; a groove gate structure consisting of a gate dielectric layer 7 and a gate electrode 6 is arranged at one end inside the N-type drift region 15, and the gate electrode 6 is positioned inside one side of the gate dielectric layer 7; a P-type base region 5 is arranged on the other side of the gate dielectric layer 7 in the N-type drift region 15, and N is arranged above the inner part of the P-type base region 5+Source regions 2 and P+Contact region 4, said P-type base region 5 and N+The side surfaces of the source region 2 are all contacted with the side surface of the gate dielectric layer 7; said N is+Source regions 2 and P+An emitter 3 is arranged above the contact region 4, and an oxide layer 1 is arranged above the gate dielectric layer 7 and the gate electrode 6; an N-type buffer region 14 is arranged at one end, far away from the trench gate structure, in the N-type drift region 15, and a P-type collector region 11 is arranged above the inside of the N-type buffer region 14; the method is characterized in that: an N-type strip 16 is arranged on the surface of the N-type drift region 15 between the P-type base region 5 and the N-type buffer region 14, and an N-type strip 16 is arranged below the N-type strip 16The square drift region is provided with a P-type buried layer 17; the P-type buried layer 17 is not in contact with the P-type base region 5; a dielectric groove structure 18 is arranged between the right side of the N-type strip 16 and the P-type buried layer 17, and the left side of the N-type buffer layer 14 and the left side of the P-type collector region 11; an N + collector region 13 is arranged between the N-type strip 16 and the dielectric groove structure 18; the upper surface of part of the N + collector region 13, the upper surfaces of the dielectric groove structure 18 and the P-type collector region 11 are collectors 12; the depth of the dielectric groove structure 18 is not less than the depth of the N-type strips 16 and the P-type collector region 11; the concentration of the N-type strips 16 and the P-type buried layer 17 is greater than that of the N-type drift region 15.
The depth of the dielectric groove structure 18 is larger than the depth of the P-type buried layer 17 and the N-type buffer region 14.
Specifically, the thickness of the N-type drift region 15 is 5-20 microns, and the doping is 5e14cm-3～1e15cm-3(ii) a The depth of the P-type buried layer 17 from the surface is 0.5-1 micron, the thickness is 0.5-1 micron, and the concentration is 5e15cm-3～1e16cm-3(ii) a The concentration of the N-shaped strips 16 is 5e15cm-3～1e16cm-3(ii) a The distance between the P-type buried layer 17 and the P-type base region 5 is 0.5-2 microns, the depth of the medium groove structure 18 is 1-2 microns, the width of the medium groove structure is 0.1-0.5 micron, and the junction depth of the P-type collector region 11 is 0.3-0.5 micron.
Example 2
This example is substantially the same as example 1, except that: the P-type buried layer 17 is composed of a plurality of regions whose concentrations decrease in order from left to right.
Example 3
This example is substantially the same as example 1, except that: the N-type strips 16 are composed of a plurality of regions whose concentration increases sequentially from left to right.
Example 4
This example is substantially the same as example 1, except that: on the basis of a groove MOS structure consisting of the groove grid structure, a P-type base region 5, an N + source region 2 and a P + contact region 4, a plane grid structure consisting of a second grid dielectric layer 7-1 and a second grid electrode 6-1 and a plane MOS structure consisting of the plane grid structure, the P-type base region 5 and the second N + source region 2-1 are added to form a composite double-grid structure consisting of the plane grid structure and the groove grid structure.
Example 5
The method of fabricating the SOI-RC-LIGBT device of embodiments 1 to 4, in turn, comprises the steps of:
preparing an SOI material, injecting and pushing phosphorus into an N-type buffer layer, etching a groove gate, growing a gate oxide layer, depositing and etching N + polysilicon, injecting and pushing boron into a P-type base region, injecting high-energy boron into a P-type buried layer, injecting and pushing arsenic into a surface N-type layer, injecting arsenic into an N + source region and an N + collector region, injecting and pushing boron into a P + contact region, etching a rectangular groove, depositing and etching silicon dioxide, injecting boron into a P-type collector region and annealing at a low temperature, depositing and refluxing BPSG, etching a contact hole, and depositing and etching an aluminum layer.
Example 6
The method of fabricating the SOI-RC-LIGBT device of embodiments 1-4, in turn, comprises the steps of:
the first step is as follows: preparing a silicon-on-insulator material, wherein the thickness of the substrate is 300-500 microns, and the doping concentration is 1014～1015Per cm3The thickness of the buried oxide layer on the substrate is 0.5-3 microns, the thickness of the SOI layer is 5-20 microns, and the doping of the SOI layer is 5e14cm-3～1e15cm-3；
The second step is that: photoetching, implanting N-type impurities into the right side area of the surface of the silicon wafer through ions, and annealing to manufacture an N-type buffer layer 14, wherein the thickness of the formed N-type buffer layer 14 is 2-4 microns;
the third step: photoetching, etching a groove on the left side of the surface of the silicon wafer, growing a gate oxide layer on the surface of the silicon wafer through thermal oxidation, and depositing a gate electrode material; photoetching, etching the unnecessary gate electrode material and the gate oxide layer to form a gate electrode;
the fourth step: photoetching, injecting a P-type impurity into the left side of a drift region on the surface of the silicon wafer through ions, and annealing to manufacture a P-type base region, wherein the thickness of the formed P-type base region is 2-3 microns;
the fifth step: photoetching, implanting P-type impurities into the drift region on the surface of the silicon wafer by high-energy ions to form a P-type buried layer, wherein the depth of the P-type buried layer from the surface is 0.5-1 micron, and the thickness is 0.5-E1 micron, concentration 5e15cm-3～1e16cm-3；
And a sixth step: photoetching, implanting N-type impurities in the middle of the drift region on the surface of the silicon wafer by ions, and annealing to form N-type strip regions with the concentration of 5e15cm-3～1e16cm-3；
The seventh step: photoetching, and preparing N on the surface of a silicon wafer by ion implantation of N-type impurities+Source region and N+A collector region;
eighth step: photoetching, implanting P-type impurities on the surface of a silicon wafer through ions, and annealing to manufacture a P-type contact region, wherein the thickness of the formed N-type source region and the P-type contact region is about 0.2-0.3 microns;
the ninth step: photoetching, etching and filling a medium to form a medium groove, wherein the depth of the formed medium groove structure 18 is 1-2 microns, and the width of the formed medium groove structure is 0.1-0.5 micron;
the tenth step: photoetching, implanting P-type impurities into the right region of the surface of the silicon wafer through ions, and annealing at low temperature to manufacture a P-type collector region, wherein the thickness of the formed P-type collector region is 0.3-0.5 microns;
the eleventh step: depositing, photoetching and etching the dielectric layer to form a dielectric layer;
the twelfth step: depositing, photoetching and etching metal to form a metal emitter and a metal collector on the surface of the device; thus preparing the SOI-RC-LIGBT device.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (5)
1. An SOI-RC-LIGBT device comprising: the N-type substrate (9), the buried oxide layer (8) and the N-type drift region (15) are arranged from bottom to top in sequence; a groove grid junction consisting of a grid dielectric layer (7) and a grid electrode (6) is arranged at one end in the N-type drift region (15)The grid electrode (6) is positioned inside one side of the grid dielectric layer (7); a P-type base region (5) is arranged on the other side of the gate dielectric layer (7) in the N-type drift region (15), and N is arranged above the inner part of the P-type base region (5)+Source region (2) and P+A contact region (4), the P-type base region (5) and N+The side surface of the source region (2) is contacted with the side surface of the gate dielectric layer (7); said N is+Source region (2) and P+An emitter (3) is arranged above the contact region (4), and an oxide layer (1) is arranged above the gate dielectric layer (7) and the gate electrode (6); an N-type buffer region (14) is arranged at one end, far away from the trench gate structure, in the N-type drift region (15), and a P-type collector region (11) is arranged above the inside of the N-type buffer region (14); the method is characterized in that: an N-type strip (16) is arranged on the surface of the N-type drift region (15) between the P-type base region (5) and the N-type buffer region (14), and a P-type buried layer (17) is arranged in the drift region below the N-type strip (16); the P-type buried layer (17) is not in contact with the P-type base region (5); a dielectric groove structure (18) is arranged between the right side of the N-type strip (16), the right side of the P-type buried layer (17), the left side of the N-type buffer layer (14) and the left side of the P-type collector region (11); an N + collector region (13) is arranged between the N-type strip (16) and the dielectric groove structure (18); the upper surface of part of the N + collector region (13), the upper surfaces of the dielectric groove structure (18) and the P-type collector region (11) are collectors (12); the depth of the dielectric groove structure (18) is not less than the depth of the N-type strips (16) and the P-type collector region (11); the concentration of the N-type strips (16) and the concentration of the P-type buried layer (17) are greater than that of the N-type drift region (15).
2. The SOI-RC-LIGBT device according to claim 1, wherein: the P-type buried layer (17) is composed of a plurality of regions with the concentration decreasing from left to right in sequence.
3. The SOI-RC-LIGBT device according to claim 1, wherein: the N-shaped strips (16) are composed of a plurality of areas with the concentration increasing from left to right in sequence.
4. The SOI-RC-LIGBT device according to claim 1, wherein: on the basis of a trench MOS structure consisting of the trench gate structure, a P-type base region (5), an N + source region (2) and a P + contact region (4), a planar gate structure consisting of a second gate dielectric layer (7-1) and a second gate electrode (6-1) and a planar MOS structure consisting of the planar gate structure, the P-type base region (5) and the second N + source region (2-1) are added to form a composite double-gate structure consisting of the planar gate structure and the trench gate structure.
5. The SOI-RC-LIGBT device according to claim 1, wherein: the depth of the dielectric groove structure (18) is larger than the depth of the P-type buried layer (17) and the N-type buffer region (14).
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| CN109192773B (en) * | 2018-09-05 | 2021-08-13 | 电子科技大学 | RC-IGBT device based on junction terminal |
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| CN109920840B (en) * | 2019-03-20 | 2022-02-11 | 重庆邮电大学 | L-shaped SiO2Composite RC-LIGBT device with isolation layer |
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| CN110473869B (en) * | 2019-08-30 | 2022-05-24 | 瑞森半导体科技(广东)有限公司 | LIGBT type ESD protection device with oxide layer |
| CN110610986B (en) * | 2019-10-09 | 2023-03-14 | 重庆邮电大学 | RC-IGBT device integrating transverse freewheeling diode by using junction terminal |
| CN111048585B (en) * | 2019-12-11 | 2021-06-11 | 四川大学 | Reverse conducting IGBT (insulated Gate Bipolar transistor) containing back groove type medium and floating space area |
| CN111403385B (en) * | 2020-03-02 | 2022-10-14 | 电子科技大学 | RC-LIGBT device with embedded Schottky diode |
| CN112510036B (en) * | 2020-10-27 | 2023-01-31 | 广东美的白色家电技术创新中心有限公司 | IGBT device and intelligent power module |
| CN113782592B (en) * | 2021-09-10 | 2023-08-29 | 重庆邮电大学 | RC-LIGBT device with substrate integrated with anti-parallel freewheeling diode |
| CN117457732B (en) * | 2023-12-22 | 2024-05-28 | 深圳天狼芯半导体有限公司 | SiC LIGBT with P-type space layer below grid electrode and preparation method |
| CN117457749B (en) * | 2023-12-22 | 2024-04-09 | 深圳天狼芯半导体有限公司 | SiC LMOS with P-type space layer below grid electrode and preparation method |
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