CN112510036B - IGBT device and intelligent power module - Google Patents

IGBT device and intelligent power module Download PDF

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CN112510036B
CN112510036B CN202011165931.9A CN202011165931A CN112510036B CN 112510036 B CN112510036 B CN 112510036B CN 202011165931 A CN202011165931 A CN 202011165931A CN 112510036 B CN112510036 B CN 112510036B
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igbt
body region
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substrate
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CN112510036A (en
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兰昊
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Midea Group Co Ltd
Guangdong Midea White Goods Technology Innovation Center Co Ltd
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Midea Group Co Ltd
Guangdong Midea White Goods Technology Innovation Center Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

The application discloses IGBT device and intelligent power module. The IGBT device includes: the IGBT device comprises a substrate, a first IGBT cellular cell, a second IGBT cellular cell and a first interlayer insulating layer, wherein the first IGBT cellular cell and the second IGBT cellular cell are sequentially stacked on the substrate and are isolated by the first interlayer insulating layer, and the first IGBT cellular cell and the second IGBT cellular cell share an emitting electrode, a collecting electrode and a gate electrode. By the mode, the voltage resistance and the current handling capacity of the IGBT device can be improved, the on-resistance is reduced, and the power consumption of the IGBT device can be reduced.

Description

IGBT device and intelligent power module
Technical Field
The application relates to the technical field of semiconductors, in particular to an IGBT device and an intelligent power module.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of a Bipolar Transistor (BJT) and an Insulated Gate field effect Transistor (MOSFET), and has the advantages of high input impedance of the MOSFET device and low conduction voltage drop of a power Transistor.
IGBTs can be generally classified into lateral IGBTs and vertical IGBTs. IGBTs based on SOI technology typically employ a lateral structure (SOI-LIGBT). With the development of semiconductor technology, SOI-LIGBT and its driving control circuit can be integrated together, and become an important research direction of current intelligent power module. Improving the performance of the SOI-LIGBT is also one of the key points of research.
The inventor of the application finds that the voltage resistance and the current handling capacity of the existing SOI-LIGBT are not strong enough in a long-term research and development process.
Disclosure of Invention
The technical problem that this application mainly solved is how to improve the withstand voltage performance and the current handling capacity of IGBT device, and then reduces the consumption of IGBT device.
In order to solve the technical problem, the application adopts a technical scheme that: an IGBT device is provided. The IGBT device includes: the IGBT device comprises a substrate, a first IGBT cellular cell, a second IGBT cellular cell and a first interlayer insulating layer, wherein the first IGBT cellular cell and the second IGBT cellular cell are sequentially stacked on the substrate and are isolated by the first interlayer insulating layer, and the first IGBT cellular cell and the second IGBT cellular cell share an emitting electrode, a collecting electrode and a gate electrode.
In order to solve the technical problem, the other technical scheme adopted by the application is as follows: an intelligent power module is provided. The intelligent power module is integrated with an IGBT device and a drive control circuit thereof, and the IGBT device is the IGBT device.
The beneficial effects of the embodiment of the application are that: the IGBT device of this application includes: the IGBT device comprises a substrate, a first IGBT cellular cell, a second IGBT cellular cell and a first interlayer insulating layer, wherein the first IGBT cellular cell and the second IGBT cellular cell are sequentially stacked on the substrate and are isolated by the first interlayer insulating layer, and the first IGBT cellular cell and the second IGBT cellular cell share an emitting electrode, a collecting electrode and a gate electrode. The IGBT device is provided with two IGBT cells, the two IGBT cells share an emitter, a collector and a gate electrode, namely the two IGBT cells are arranged in parallel, so that two parallel conducting channels are formed when the IGBT device is conducted, and compared with the existing IGBT device, the IGBT device has a wider conducting channel when being conducted; meanwhile, the first IGBT unit cell is arranged on the second IGBT unit cell in a laminated mode, a field plate effect is formed between the first IGBT unit cell and the second IGBT unit cell, the voltage-resisting capacity of the second IGBT unit cell can be improved, the second IGBT unit cell has a field plate effect on the first IGBT unit cell, and the voltage-resisting capacity of the first IGBT unit cell can be improved. Therefore, the voltage resistance and the current density of the IGBT device can be improved, the on-resistance is reduced, and the power consumption of the IGBT device can be reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an embodiment of an IGBT device according to the present application;
fig. 2 is a schematic structural diagram of an embodiment of the IGBT device of the present application;
FIG. 3 is a schematic structural diagram of an embodiment of an IGBT device of the present application;
FIG. 4 is a schematic structural diagram of an embodiment of an IGBT device of the present application;
fig. 5 is a schematic structural diagram of an embodiment of the smart power module of the present application.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be noted that the following examples are only illustrative of the present application, and do not limit the scope of the present application. Likewise, the following examples are only some examples and not all examples of the present application, and all other examples obtained by a person of ordinary skill in the art without any inventive step are within the scope of the present application.
The application firstly provides an IGBT device, as shown in fig. 1, fig. 1 is a schematic structural diagram of an embodiment of the IGBT device of the application. The IGBT device 10 of the present embodiment includes: the IGBT device comprises a substrate 20, a first IGBT cellular cell 30, a second IGBT cellular cell 40 and a first interlayer insulating layer 50, wherein the first IGBT cellular cell 30 and the second IGBT cellular cell 40 are sequentially arranged on the substrate 20 in a stacked mode, and the substrate 20 is used for supporting the first IGBT cellular cell 30 and the second IGBT cellular cell 40; and the first IGBT-cell 30 and the second IGBT-cell 40 are isolated by the first interlayer insulating layer 50, wherein the first IGBT-cell 30 and the second IGBT-cell 40 are in contact with the emitter 60, the collector 70, and the gate electrode 80, respectively, i.e., the first IGBT-cell 30 and the second IGBT-cell 40 share the emitter 60, the collector 70, and the gate electrode 80.
The Substrate 20 of the present embodiment may be a Direct-Copper-Bonded (DCB) Substrate or an Insulated-Metal-Substrate (IMS) Substrate; the first interlayer insulating layer 50 may be an oxide layer, for example, when the IGBT device is fabricated using a silicon wafer, the first interlayer insulating layer 50 may be SiO 2 And (3) a layer.
When the IGBT device 10 is turned on, the first IGBT-cell 30 forms a first conduction channel, and the second IGBT-cell 40 forms a second conduction channel.
Different from the prior art, the IGBT device 10 of the present embodiment is provided with the first IGBT cell 30 and the second IGBT cell 40, and the first IGBT cell 30 and the second IGBT cell 40 share the emitter 60, the collector 70, and the gate electrode 80, that is, the first IGBT cell 30 and the second IGBT cell 40 are arranged in parallel, so that two conducting channels arranged in parallel are formed when the IGBT device 10 is turned on, and therefore, compared with the existing IGBT device, the IGBT device 10 of the present embodiment has a wider conducting channel when turned on; meanwhile, the first IGBT unit cell 30 is stacked on the second IGBT unit cell 40, and a field plate function is provided between the first IGBT unit cell and the second IGBT unit cell, so that the withstand voltage capability of the second IGBT unit cell 40 can be improved, and the second IGBT unit cell 40 has a field plate function on the first IGBT unit cell 30, so that the withstand voltage capability of the first IGBT unit cell can be improved. Therefore, the present embodiment can improve the withstand voltage and current density of the IGBT device 10, reduce the on-resistance, and thus can reduce the power consumption of the IGBT device 10.
Optionally, as shown in fig. 1, the IGBT device 10 of the present embodiment further includes: the gate insulating layer 90, the gate insulating layer 90 and the second IGBT cell 40 are disposed in the same layer, and the gate electrode 80 is embedded in the gate insulating layer 90, that is, the gate electrode 80 is surrounded by the gate insulating layer 90.
As can be seen from the above analysis, the second IGBT cell 40 is stacked on the side of the first IGBT cell 30 facing away from the substrate 20, and therefore, the gate insulating layer 90 of the present embodiment is disposed in the same layer as the second IGBT cell 40, which not only can reduce the thickness of the IGBT device 10, but also can ensure that the first IGBT cell 30 and the second IGBT cell 40 share the gate electrode 80 disposed in the gate insulating layer 90.
The gate electrode 80 may be led out of the IGBT device 10 through a wire; in other embodiments, the gate electrode may also be disposed on a side of the second IGBT cell facing away from the first IGBT cell, so as to lead out the gate electrode.
The gate insulating layer 90 and the first interlayer insulating layer 50 of the present embodiment are semiconductor structure layers independent of each other; the process and material of the gate insulating layer 90 are the same as those of the first interlayer insulating layer 50, and the gate insulating layer 90 is in contact with the first interlayer insulating layer 50.
In another embodiment, as shown in fig. 2, the IGBT device 10 of the present embodiment differs from the IGBT device 10 of the embodiment of fig. 1 in that: the gate insulating layer 210 and the first interlayer insulating layer 220 of the present embodiment are integrally formed and formed by the same process.
Compared with the embodiment of fig. 1, the gate insulating layer 210 and the first interlayer insulating layer 220 are integrally formed, so that the process can be simplified and the cost can be saved.
With continuing reference to fig. 1, the IGBT device 10 of the present embodiment optionally further includes: a second interlayer insulating layer 110, the second interlayer insulating layer 110 being disposed between the substrate 20 and the first IGBT-cell 30. The second interlayer insulating layer 110 serves to isolate the substrate 20 from the semiconductor structure on the substrate 20.
The second interlayer insulating layer 110 of the present embodiment may be a buried oxide layer. The present embodiment may form the buried oxide layer by a Silicon-On-Insulator (SOI) process On an insulating substrate.
In an application scene, in an SOI process, high-energy and large-dose oxygen can be injected into silicon by adopting an oxygen injection isolation technology to form an oxygen buried layer; the buried oxide layer divides the original silicon wafer into two parts, the thin silicon wafer of the upper part is used for forming the semiconductor structures such as the first IGBT cell 30 and the second IGBT cell 40 of the embodiment, and the silicon wafer of the lower part is used for forming the substrate 20 of the embodiment.
In another application scenario, in the SOI process, two silicon wafers with oxide layers grown thereon may be bonded together, the two oxide layers are bonded together to form a buried oxide layer, the upper silicon wafer is used to form the semiconductor structures such as the first IGBT cell 30 and the second IGBT cell 40 of this embodiment, and the lower silicon wafer is used to form the substrate 20 of this embodiment.
Of course, in other application scenarios, other SOI processes may also be adopted to form the buried oxide layer of the present embodiment, for example, the smart cut technique.
In the embodiment, the buried oxide layer is formed by the SOI process, so that the latch-up effect of the IGBT device 10 can be improved, the parasitic effect of the IGBT device 10 can be reduced, a well does not need to be formed, the process can be simplified, the size of the IGBT device 10 can be reduced, and the IGBT device 10 and the intelligent power module can be miniaturized.
When the IGBT device 10 of this embodiment is made of a silicon wafer, the buried oxide layer may be SiO 2 And (3) a layer.
Alternatively, as shown in fig. 1, the first IGBT cell 30 of the present embodiment includes: a first drift region 301, a first body region 302, and a first emitter region 303; wherein the first body region 302 is in contact with one side of the first drift region 301; the first emitter region 303 is in contact with the first body region 302, and the first emitter region 303 is isolated from the first drift region 301 by the first body region 302.
Wherein the first body region 302 may be in direct contact with the first drift region 301 or in indirect contact through a conductive layer; the first emission region 303 may be in direct contact with the first body region 302 or in indirect contact through a conductive layer.
The first body region 302 of this embodiment is disposed in an L shape, and both inner side edges of the L-shaped first body region 302 are in contact with the first emitting region 303; the L-shaped first body region 302 can isolate the first emitter region 303 from the second interlayer insulating layer 110; this structure can prevent parasitic channels from being generated at the back of the first body region 302.
Further, the first drift region 301 of the present embodiment further extends between the first body region 302 and the second interlayer insulating layer 110, that is, both outer sides of the L-shaped first body region 302 are in contact with the first drift region 301; this structure can further improve the parasitic channel problem at the back of the first body region 302.
In other embodiments, to reduce the thickness of the first IGBT cell, the first emitter region may be in contact with the second interlayer insulating layer and/or the first body region may be in contact with the first drift region.
Further, as shown in fig. 1, the first IGBT cell 30 of the present embodiment further includes: a first buffer region 304 and a first collector region 305; wherein the first buffer region 304 is in contact with the other side of the first drift region 301; the first collector region 305 is in contact with the first buffer region 304, and the first buffer region 304 isolates the first collector region 305 from the first drift region 301.
Wherein the first buffer region 304 may be in direct contact with the first drift region 301 or in indirect contact through a conductive layer; the first collector region 305 may be in direct contact with the first buffer region 304 or in indirect contact through a conductive layer.
The first body region 302 and the first emitter region 303 of the present embodiment are disposed on one side of the first drift region 301, and are disposed on the same layer as the first drift region 301; the first buffer region 304 and the first collector region 305 are disposed on the other side of the first drift region 301 and on the same layer as the first drift region 301; this structure can reduce the thickness of the first IGBT cell 30.
Further, the first buffer region 304 of the present embodiment is disposed in an L shape, and the first drift region 301 further extends to a position between the first buffer region 304 and the second interlayer insulating layer 110, that is, two outer sides of the L-shaped first buffer region 304 are both in contact with the first drift region 301, and two inner sides of the L-shaped first buffer region 304 are both in contact with the first collector region 305; this structure can improve the parasitic channel problem at the back of the first buffer region 304.
In other embodiments, to reduce the thickness of the first IGBT cell, the first buffer region may be in contact with the second interlayer insulating layer.
In this embodiment, the first drift region 301 has a first doping type, the first emitter region 303 has the first doping type, the doping concentration of the first emitter region 303 is greater than that of the first drift region 301, the first body region 302 has a second doping type, and the first doping type is different from the second doping type; further, the first buffer region 304 of the present embodiment has a first doping type, and the first collector region 305 has a second doping type.
Specifically, as shown in fig. 1, the first doping type of the present embodiment is N-type doping, and the second doping type is P-type doping, that is, the first IGBT cell 30 is composed of an N-type doped drift region, an N-type doped emitter region, an N-type doped buffer region, a P-type doped body region, and a P-type doped collector region. The first IGBT cell 30 of the present embodiment has an NPN structure, and when the first IGBT cell 30 is turned on, an N channel is formed.
Further, the doping type of the substrate 20 is not limited in this embodiment, and the substrate 20 may be N-type doped or P-type doped.
Specifically, when the first IGBT cell 30 is turned on, the minority carrier injected by the emitter 60 is a hole, and the minority carrier injected by the collector 70 is an electron; when the voltage applied to the gate electrode 80 is greater than the threshold voltage, the emitter 60 injects high-concentration electrons into the N-type doped drift region through the N-type doped emitter region and the P-type doped body region, and forms an electron current through the N-type doped buffer region and the P-type doped collector region; meanwhile, the collector 70 injects high-concentration holes into the N-type doped drift region through the P-type doped collector region and the N-type doped buffer region, and combines with high-concentration electrons in the N-type doped drift region to form hole current. The sum of the electron current and the hole current constitutes the saturation current capability of the first IGBT cell 30.
In another embodiment, the first doping type is P-type doping, and the second doping type is N-type doping, i.e., the first IGBT cell is a PNP structure composed of a P-type doped drift region, a P-type doped emitter region, a P-type doped buffer region, an N-type doped body region, and an N-type doped collector region. When the first IGBT unit cell is conducted, a P channel is formed; specifically, when the first IGBT unit cell is turned on, the minority carrier injected by the emitter is an electron, and the minority carrier injected by the collector is a hole; when the voltage applied to the gate electrode is greater than the threshold voltage, the emitter injects high-concentration holes into the P-type doped drift region through the P-type doped emitter region and the N-type doped body region, and the holes are formed through the P-type doped buffer region and the N-type doped collector region; meanwhile, the collector injects high-concentration electrons into the P-type doped drift region through the N-type doped collector region and the P-type doped buffer region, and the high-concentration electrons are combined with high-concentration holes in the P-type doped drift region to form hole current. The sum of the electron current and the hole current constitutes the saturation current capability of the first IGBT cell.
Optionally, as shown in fig. 1, the first IGBT cell 30 of this embodiment further includes a third body region 306, the third body region 306 is in contact with the first body region 302 and the first emitter region 303, and is isolated from the first drift region 301 by the first body region 302, a doping type of the third body region 306 is the same as that of the first body region 302, and a doping concentration of the third body region 306 is greater than that of the first body region 302.
Wherein the third body region 306 may be in direct contact with the first body region 302 and the first emitter region 303 or indirectly through a conductive layer.
The first IGBT unit cell 30 of the present embodiment can provide a minority carrier extraction channel when the first IGBT unit cell 30 is turned off by providing the third body region 306, and thus the turn-off speed of the first IGBT unit cell 30 can be increased.
In another embodiment, as shown in fig. 3, the difference between the IGBT device 10 of the present embodiment and the IGBT device 10 of the embodiment of fig. 1 at least includes: the first IGBT-cell 30 of the present embodiment further includes: the body regions 330, 330 are in contact with the first buffer region 304, the first collector region 305, and the first interlayer insulating layer 50, respectively.
Compared with the embodiment of fig. 1, the first IGBT unit cell 30 of the present embodiment can provide the minority carrier extraction channel when the first IGBT unit cell 30 is turned off by providing the body region 330, so that the turn-off speed of the first IGBT unit cell 30 can be increased.
With continued reference to fig. 1, optionally, as shown in fig. 1, the second IGBT cell 40 of the present embodiment includes: a second drift region 401, a second body region 402, and a second emitter region 403; wherein the second body region 402 is in contact with one side of the second drift region 401; the second emitter region 403 is in contact with the second body region 402 and is isolated from the second drift region 401 by the second body region 402.
Wherein the second body region 402 may be in direct contact with the second drift region 401 or in indirect contact through a conductive layer; the second emission region 403 may be in direct contact with the second body region 402 or in indirect contact through a conductive layer.
The second body region 402 of the present embodiment is disposed in an L shape, and an inner side edge of the L-shaped second body region 402 contacts the second emitter region 403; an L-shaped second body region 402 capable of isolating the second emitter region 403 from the second drift region 401; this structure can prevent the creation of parasitic channels behind the second body region 402.
Further, the second drift region 401 of this embodiment further extends to between the second body region 402 and the first interlayer insulating layer 50, that is, both outer sides of the L-shaped second body region 402 are in contact with the second drift region 401, which can further improve the problem of parasitic channel at the back of the second body region 402.
In other embodiments, to reduce the thickness of the second IGBT-cell, the second emitter region may be in contact with the first interlayer insulating layer and/or the second body region may be in contact with the second drift region.
Alternatively, as shown in fig. 1, in the present embodiment, the orthographic projection of the first body region 302 on the substrate 20 is staggered in a direction away from the second drift region 401 compared with the orthographic projection of the second body region 402 on the substrate 20, and the gate electrode 80 is disposed adjacent to a side surface of the first body region 302 away from the substrate 20 and adjacent to a side surface of the second body region 402 away from the second drift region 401.
As can be seen from the above analysis, in order to reduce the thickness of the IGBT device 10 and ensure that the first IGBT cell 30 and the second IGBT cell 40 share the gate electrode 80, the gate insulating layer 90 and the second IGBT cell 40 are disposed in the same layer, and therefore, the first body region 302 and the second body region 402 of the present embodiment are disposed in a staggered manner, so that the electrical performance of the first IGBT cell 30 can be similar to the electrical performance of the second IGBT cell 40.
Further, as shown in fig. 1, the second IGBT cell 40 of the present embodiment further includes: a second buffer region 404 and a second collector region 405, wherein the second buffer region 404 is in contact with the other side of the second drift region 401; the second collector region 405 is in contact with the second buffer region 404 and is isolated from the second drift region 401 by the second buffer region 404.
Wherein the second buffer region 404 is in direct contact with the second drift region 401 or in indirect contact through a conductive layer; the second collector region 405 is in direct contact with the second buffer region 404 or indirectly through a conductive layer.
In the present embodiment, the second drift region 401 has a first doping type, the second emitter region 403 has the first doping type, the doping concentration of the second emitter region 403 is greater than the doping concentration of the second drift region 401, and the second body region 402 has the second doping type; further, the second buffer region 404 of the present embodiment has a first doping type, and the second collector region 405 has a second doping type.
Specifically, as shown in fig. 1, the second IGBT cell 40 of this embodiment is composed of an N-type doped drift region, an N-type doped emitter region, an N-type doped buffer region, a P-type doped body region, and a P-type doped collector region, that is, the second IGBT cell 40 of this embodiment is an NPN structure, and when the second IGBT cell 40 is turned on, an N channel is formed.
Specifically, when the second IGBT cell 40 is turned on, the minority carrier injected by the emitter 60 is a hole, and the minority carrier injected by the collector 70 is an electron; when the voltage applied to the gate electrode 80 is greater than the threshold voltage, the emitter 60 injects high-concentration electrons into the N-type doped drift region through the N-type doped emitter region and the P-type doped body region, and forms electron current through the N-type doped buffer region and the P-type doped collector region; meanwhile, the collector 70 injects high-concentration holes into the N-type doped drift region through the P-type doped collector region and the N-type doped buffer region, and combines with high-concentration electrons in the N-type doped drift region to form hole current. The sum of the electron current and the hole current constitutes the saturation current capability of the second IGBT cell 40.
In another embodiment, the first doping type is P-type doping, and the second doping type is N-type doping, i.e., the second IGBT cell is a PNP structure composed of a P-type doped drift region, a P-type doped emitter region, a P-type doped buffer region, an N-type doped body region, and an N-type doped collector region. When the first IGBT unit cell is conducted, a P channel is formed; specifically, when the second IGBT unit cell is turned on, the minority carrier injected by the emitter is an electron, and the minority carrier injected by the collector is a hole; when the voltage applied to the gate electrode is greater than the threshold voltage, the emitter injects high-concentration holes into the P-type doped drift region through the P-type doped emitter region and the N-type doped body region, and the holes are formed through the P-type doped buffer region and the N-type doped collector region; meanwhile, the collector injects high-concentration electrons into the P-type doped drift region through the N-type doped collector region and the P-type doped buffer region, and the high-concentration electrons are combined with high-concentration holes in the P-type doped drift region to form hole current. The sum of the electron current and the hole current constitutes the saturation current capability of the second IGBT cell.
The second IGBT-cell 40 of the present embodiment is the same doping type as the first IGBT-cell 30 so that the emitter 60, the collector 70, and the gate electrode 80 can be shared by both.
In the present embodiment, the second body region 402 and the second emitter region 403 are disposed on one side of the second drift region 401, and the second buffer region 404 and the second collector region 405 are disposed on the other side of the second drift region 401 and are disposed on the same layer as the second drift region 401, so that the thickness of the second IGBT cell 40 can be reduced.
In other embodiments, the second buffer region may further extend between the second collector region and the second drift region and/or the second drift region may further extend between the second buffer region and the second interlayer insulating layer.
The first emitter region 303 and the second emitter region 403 of the present embodiment are disposed on the same side, so that the first IGBT cell 30 and the second IGBT cell 40 share the emitter 60; the first collector region 305 and the second collector region 405 are disposed on the same side, so that the first IGBT cell 30 and the second IGBT cell 40 share the collector electrode 70.
The second drift region 401 of the second IGBT cell 40 of the present embodiment forms a field plate effect on the first drift region 301 of the first IGBT cell 30, and the voltage withstanding capability of the first IGBT cell 30 can be improved by adjusting the electric field distribution of the first drift region 301; similarly, the first drift region 301 of the first IGBT cell 30 forms a field plate effect on the second drift region 401 of the second IGBT cell 40, and the voltage withstanding capability of the second IGBT cell 40 can be improved by adjusting the electric field distribution of the second drift region 401.
Further, as shown in fig. 1, an orthographic projection of the first collector region 305 on the substrate 20 of the present embodiment is shifted in a direction away from the second drift region 401 compared to an orthographic projection of the second collector region 405 on the substrate 20. This structure can facilitate the same layer arrangement of the collector 70 and the second IGBT cell 40, and can reduce the thickness of the IGBT device 10.
Optionally, as shown in fig. 1, the second IGBT-cell 40 of this embodiment further includes a fourth body region 406, the fourth body region 406 is in contact with the second body region 402 and the second emitter region 403, and is isolated from the second drift region 401 by the second body region 402, the fourth body region 406 is of the same doping type as the second body region 402, and the doping concentration of the fourth body region 406 is greater than the doping concentration of the second body region 402.
Wherein the fourth body region 406 is in direct contact with the second body region 402 and the second emitter region 403 or is in indirect contact through a conductive layer.
The second IGBT unit cell 40 of the present embodiment can provide an minority carrier extraction channel when the second IGBT unit cell 40 is turned off by providing the fourth body region 406, and thus the turn-off speed of the second IGBT unit cell 40 can be increased.
In another embodiment, as shown in fig. 3, the IGBT device 10 of the present embodiment further includes, in distinction from the IGBT device 10 of the embodiment of fig. 1: the second IGBT cell 40 of the present embodiment further includes: the body region 440, the body region 440 is in contact with the second buffer region 404, the second collector region 405, and the first interlayer insulating layer 50, respectively.
Compared with the embodiment of fig. 1, the second IGBT unit cell 40 of the present embodiment can provide the minority carrier extraction channel when the second IGBT unit cell 40 is turned off by providing the body region 440, so that the turn-off speed of the second IGBT unit cell 40 can be increased.
Optionally, as shown in fig. 1, the emitter 60 of the present embodiment includes a first sub-electrode 61, the first sub-electrode 61 is disposed on a side of the gate electrode 80 facing away from the first drift region 301, and is in contact with a surface of a side of the first emitting region 303 facing away from the substrate 20; the emitter 60 further comprises a second sub-electrode 62, the second sub-electrode 62 is connected to the first sub-electrode 61, is disposed on a side of the gate electrode 80 facing away from the substrate 20, and is in surface contact with a side of the second emitter region 403 facing away from the substrate 20.
Wherein the first sub-electrode 61 is in direct contact with the first emission region 303 or in indirect contact with the first emission region 303 through a conductive layer; the second sub-electrode 62 is in direct contact with the second emission region 403 or in indirect contact through a conductive layer.
The first sub-electrode 61 of the present embodiment is disposed in the same layer as the second IGBT cell 40 so as to be in contact with the first emitter region 303 of the first IGBT cell 30; the second sub-electrode 62 is disposed on the second IGBT cell 40 so as to be in contact with the second emitter region 403 of the second IGBT cell 40, and so as to lead out the emitter 60.
Further, the first sub-electrode 61 is further in contact with a side surface of the third body region 306 facing away from the substrate 20, and the second sub-electrode 62 is further in contact with a side surface of the fourth body region 406 facing away from the substrate 20.
Alternatively, as shown in fig. 1, the first sub-electrode 61 and the second sub-electrode 62 of the present embodiment are integrally disposed, which can simplify the process and ensure that the electrical performance of the first IGBT cell 30 is similar to the electrical performance of the second IGBT cell 40; and the first sub-electrode 61 and the second sub-electrode 62 are connected in an L-shape, the size of the IGBT device 10 can be reduced.
In another embodiment, as shown in fig. 4, the IGBT device 10 of the present embodiment differs from the IGBT device 10 of the embodiment of fig. 1 at least in the following points: the first sub-electrode 61 of this embodiment may also extend to a side of the third body region 306 away from the first emitter region 303, and contact the third body region 306.
This structure allows the electrical performance of the first IGBT-cell 30 to be similar to the electrical performance of the second IGBT-cell 40.
With reference to fig. 1, the collector 70 of the present embodiment is optionally in contact with a surface of the first collector region 305 facing away from the substrate 20 and in contact with a surface of the second collector region 405 facing away from the second drift region 401.
Wherein the collector 70 is in direct contact with the first collector region 305 and the second collector region 405 or indirectly through a conductive layer.
The collector 70 and the second IGBT cell 40 of the present embodiment are disposed in the same layer, which can reduce the thickness of the IGBT device 10 and facilitate the extraction of the collector 70.
In another embodiment, as shown in fig. 4, the IGBT device 10 of the present embodiment further includes, in distinction from the IGBT device 10 of the embodiment of fig. 1: the collector electrode 70 of this embodiment may also extend to a side of the first collector region 305 away from the first buffer region 304, and contact the first collector region 305 and the first buffer region 304.
This structure allows the electrical performance of the first IGBT-cell 30 to be similar to the electrical performance of the second IGBT-cell 40.
Different from the prior art, the IGBT device 10 of the present embodiment has two IGBT cells, and the two IGBT cells share the emitter 60, the collector 70, and the gate electrode 80, that is, the two IGBT cells are arranged in parallel, so that two parallel conduction channels are formed when the IGBT device 10 is turned on, and therefore, compared with the existing IGBT device, the IGBT device 10 of the present embodiment has a wider conduction channel when turned on. Therefore, the present embodiment can improve the withstand voltage and current density of the IGBT device 10, reduce the on-resistance, and thus can reduce the power consumption of the IGBT device 10.
It should be noted that the shapes and positions of the semiconductor structures and the electrode structures of the layers of the IGBT device according to the embodiments of the present application may be appropriately changed according to the specific product design.
The IGBT device according to the above embodiment of the present application includes two IGBT unit cells to form two conducting channels, and in other embodiments, the number of the IGBT unit cells in the IGBT device is not limited, and the number of the IGBT unit cells may be two or more.
The present application further provides an intelligent power module, as shown in fig. 5, fig. 5 is a schematic structural diagram of an embodiment of the intelligent power module of the present application. The intelligent power module of the embodiment comprises: the IGBT device 10 and its drive control circuit 51, and the IGBT device 10 operates under drive control of the drive control circuit 51. Here, IGBT device 10 is IGBT device 10 according to the above embodiment, and details are not described here.
The intelligent power module is a semiconductor device consisting of a high-speed low-power-consumption IGBT, a grid drive and a corresponding protection circuit, and has the advantages of high current density, low saturation voltage and high voltage resistance of a high-power transistor and the advantages of high input impedance, high switching frequency and low driving power of a field effect transistor. Logic, control, detection and protection circuits are integrated in the intelligent power module, so that the intelligent power module is convenient to use, the size and development time of the system are reduced, and the reliability of the system is greatly enhanced; the intelligent power module can be used in the fields of household appliances, rail transit, electric power systems and the like.
Be different from prior art, this application IGBT device includes: the IGBT device comprises a substrate, a first IGBT cellular cell, a second IGBT cellular cell and a first interlayer insulating layer, wherein the first IGBT cellular cell and the second IGBT cellular cell are sequentially stacked on the substrate and are isolated by the first interlayer insulating layer, and the first IGBT cellular cell and the second IGBT cellular cell share an emitting electrode, a collecting electrode and a gate electrode. The IGBT device is provided with two IGBT cells, and the two IGBT cells use the emitter, the collector and the gate electrode, namely the two IGBT cells are arranged in parallel, so that two parallel conducting channels are formed when the IGBT device is conducted, and therefore compared with the existing IGBT device, the IGBT device has a wider conducting channel when being conducted; meanwhile, the first IGBT unit cell is arranged on the second IGBT unit cell in a stacked mode, a field plate effect is formed between the first IGBT unit cell and the second IGBT unit cell, the voltage-resisting capacity of the second IGBT unit cell can be improved, the second IGBT unit cell has a field plate effect on the first IGBT unit cell, and the voltage-resisting capacity of the first IGBT unit cell can be improved. Therefore, the voltage resistance and the current density of the IGBT device can be improved, the on-resistance is reduced, and the power consumption of the IGBT device can be reduced.
Furthermore, the IGBT device is formed by adopting the SOI process, the latch-up effect of the IGBT device can be improved, the parasitic effect of the IGBT device can be reduced, a well does not need to be manufactured, the process can be simplified, the size of the IGBT device is reduced, and the miniaturization of the IGBT device and the intelligent power module is facilitated.
The above description is only an embodiment of the present application, and not intended to limit the scope of the present application, and all equivalent mechanisms or equivalent processes performed by the present application and the contents of the appended drawings, or directly or indirectly applied to other related technical fields, are all included in the scope of the present application.

Claims (8)

1. An IGBT device is characterized by comprising a substrate, a first IGBT cellular cell, a second IGBT cellular cell and a first interlayer insulating layer, wherein the first IGBT cellular cell and the second IGBT cellular cell are sequentially stacked on the substrate and are isolated by the first interlayer insulating layer, and the first IGBT cellular cell and the second IGBT cellular cell share an emitter, a collector and a gate electrode;
the IGBT device further comprises a grid insulation layer, the grid insulation layer and the second IGBT unit cell are arranged on the same layer, and the grid electrode is embedded in the grid insulation layer;
the first IGBT cell includes:
a first drift region;
a first body region contacting one side of the first drift region;
a first emitter region in contact with the first body region and isolated from the first drift region by the first body region;
the second IGBT cell includes:
a second drift region;
a second body region contacting one side of the second drift region;
a second emitter region in contact with the second body region and isolated from the second drift region by the second body region;
the orthographic projection of the first body region on the substrate is staggered towards a direction far away from the second drift region compared with the orthographic projection of the second body region on the substrate, and the gate electrode is arranged adjacent to one side surface, away from the substrate, of the first body region and adjacent to one side surface, away from the second drift region, of the second body region.
2. The IGBT device according to claim 1, wherein the emitter comprises a first sub-electrode and a second sub-electrode, the first sub-electrode is arranged on one side of the gate electrode facing away from the first drift region and is in surface contact with one side of the first emitter region facing away from the substrate, and the second sub-electrode is connected with the first sub-electrode, is arranged on one side of the gate electrode facing away from the substrate and is in surface contact with one side of the second emitter region facing away from the substrate.
3. The IGBT device according to claim 2, wherein the first sub-electrode and the second sub-electrode are integrally provided and connected in an L shape.
4. The IGBT device of claim 2, wherein the first drift region, the first emitter region, the second drift region, and the second emitter region have a first doping type, and a doping concentration of the first emitter region is greater than a doping concentration of the first drift region, a doping concentration of the second emitter region is greater than a doping concentration of the second drift region, and the first body region and the second body region have a second doping type, the second doping type being different from the first doping type.
5. The IGBT device of claim 4, wherein the first IGBT unit cell further comprises a third body region in contact with the first body region and the first emitter region and isolated from the first drift region by the first body region, the third body region having the second doping type and having a doping concentration greater than that of the first body region, the first sub-electrode further in contact with a side surface of the third body region facing away from the substrate;
the second IGBT unit cell further comprises a fourth body region, the fourth body region is in contact with the second body region and the second emitter region and is isolated from the second drift region through the second body region, the fourth body region is of the second doping type, the doping concentration of the fourth body region is larger than that of the second body region, and the second sub-electrode is further in contact with one side surface, away from the substrate, of the fourth body region.
6. The IGBT device of claim 1, further comprising a second interlayer insulating layer disposed between the first IGBT cell and the substrate, wherein the first drift region further extends between the first body region and the second interlayer insulating layer, and/or the second drift region further extends between the second body region and the first interlayer insulating layer.
7. The IGBT device according to claim 1, wherein the first IGBT cell further comprises:
a first buffer region contacting the other side of the first drift region;
a first collector region in contact with the first buffer region and isolated from the first drift region by the first buffer region;
the second IGBT cell further includes:
a second buffer region contacting the other side of the second drift region;
a second collector region in contact with the second buffer region and isolated from the second drift region by the second buffer region;
compared with the orthographic projection of the second collector region on the substrate, the orthographic projection of the first collector region on the substrate is staggered towards the direction far away from the second drift region, and the collector electrode is in contact with one side surface of the first collector region far away from the substrate and in contact with one side surface of the second collector region far away from the second drift region.
8. A smart power module, the smart power module comprising: an IGBT device according to any one of claims 1 to 7 and a drive control circuit therefor.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165662A (en) * 2011-12-15 2013-06-19 爱思开海力士有限公司 Resistive memory device and method of manufacturing the same
CN105870178A (en) * 2016-04-26 2016-08-17 电子科技大学 Bi-directional insulated gate bipolar transistor (IGBT) device and fabrication method thereof
CN107785415A (en) * 2017-10-27 2018-03-09 电子科技大学 A kind of SOI RC LIGBT devices and preparation method thereof
CN110797305A (en) * 2019-10-22 2020-02-14 广东美的白色家电技术创新中心有限公司 Semiconductor device, preparation method thereof and electrical equipment

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110444586B (en) * 2019-08-21 2022-10-25 江苏中科君芯科技有限公司 Trench gate IGBT device with shunt area and preparation method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165662A (en) * 2011-12-15 2013-06-19 爱思开海力士有限公司 Resistive memory device and method of manufacturing the same
CN105870178A (en) * 2016-04-26 2016-08-17 电子科技大学 Bi-directional insulated gate bipolar transistor (IGBT) device and fabrication method thereof
CN107785415A (en) * 2017-10-27 2018-03-09 电子科技大学 A kind of SOI RC LIGBT devices and preparation method thereof
CN110797305A (en) * 2019-10-22 2020-02-14 广东美的白色家电技术创新中心有限公司 Semiconductor device, preparation method thereof and electrical equipment

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