CN109888007B - SOI LIGBT device with diode clamped carrier storage layer - Google Patents
SOI LIGBT device with diode clamped carrier storage layer Download PDFInfo
- Publication number
- CN109888007B CN109888007B CN201910316577.6A CN201910316577A CN109888007B CN 109888007 B CN109888007 B CN 109888007B CN 201910316577 A CN201910316577 A CN 201910316577A CN 109888007 B CN109888007 B CN 109888007B
- Authority
- CN
- China
- Prior art keywords
- region
- area
- type semiconductor
- gate
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Thin Film Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses an SOI LIGBT device with a diode clamp carrier storage layer, which is characterized in that a P-type semiconductor base region is divided into a plurality of regions, and two or three diodes connected in series are introduced into different regions, so that when the device is in reverse voltage resistance, the potential of a P-type electric field shielding region is increased to the conduction voltage drop of the two or three diodes, the diodes are conducted, the potential of the P-type electric field shielding region is clamped near the conduction voltage drop of the two or three diodes, the potential of an N-type carrier storage region is well shielded at a very low value by the P-type electric field shielding region, the voltage resistance of the device is borne by a reverse bias diode mainly composed of the P-type electric field shielding region and a surface voltage resistance region, and the contradiction between the breakdown voltage and the N-type carrier layer concentration is thoroughly broken.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a design of an SOI LIGBT device with a diode clamp carrier storage layer.
Background
Miniaturization and integration of power electronic systems are important research directions of power semiconductor devices. In an intelligent Power Integrated Circuit (SPIC) or a High Voltage Integrated Circuit (HVIC), low voltage circuits such as protection, control, detection, and driving and High voltage Power devices are Integrated on the same chip, which not only reduces the system volume, but also improves the system reliability. Meanwhile, in a working occasion with higher frequency, the requirement of the buffering and protecting circuit can be obviously reduced due to the reduction of the inductance of the lead wire of the system.
Lateral Insulated-Gate Bipolar Transistor (LIGBT) is one of the important power devices of SPIC or HVIC, and LIGBT based on SOI technology is widely used due to its excellent isolation characteristics. As a bipolar power device, LIGBT has the characteristics of high input impedance of MOSFET and high current density of BJT. However, the presence of a large number of non-equilibrium carriers in the drift region enhances the drift region conductance modulation effect while also increasing the turn-off loss of the device. Therefore, the Turn-off loss (Turn-off loss: E) of the device is optimizedoff) And an On-state voltage (On-state voltage d)rop：Von) The compromise relationship between the two is one of the keys in designing the LIGBT.
In order to obtain a better trade-off relationship between turn-off loss and turn-on Voltage drop, h.takahashi et al first proposed a Carrier storage layer technology in the article "Carrier Stored Trench-Gate Bipolar transistor (csbt) -a Novel power device for High Voltage Application" in 1996, and applied it to a vertical IGBT structure. As shown in fig. 1, an LIGBT structure with a carrier storage layer is introduced at the cathode side, so that more non-equilibrium carriers are accumulated in the drift region close to the cathode side, and the conductivity modulation effect of the drift region is further enhanced. Meanwhile, the injection efficiency of the cathode electron is improved, and the injection efficiency of the anode can be reduced, so that when the LIGBT is turned off, holes continuously injected by the anode are reduced, and the turn-off speed is improved. Therefore, the introduction of the carrier storage layer enables the LIGBT device to have better EoffAnd VonA compromise relationship.
However, in the LIGBT device having the Carrier storage Layer of the prior art, as the Carrier-Stored Layer Concentration (N) is variedcs) The breakdown voltage of the device (breakdown voltage: BV) will decrease accordingly. Therefore, how to solve the contradiction between the breakdown voltage and the concentration of the carrier storage layer is one of the keys in designing the LIGBT with the carrier storage layer.
Disclosure of Invention
The invention aims to solve the contradiction between the breakdown voltage and the concentration of a current carrier storage layer of the conventional LIGBT device with the current carrier storage layer, and provides an SOI LIGBT device with a diode clamping current carrier storage layer, which can break the contradiction between the breakdown voltage and the concentration of the current carrier layer, realize quick turn-off, improve a short-circuit safe working area and simultaneously be compatible with the conventional current carrier storage layer technology.
The technical scheme of the invention is as follows: an SOI LIGBT device with a diode clamped carrier storage layer includes a semiconductor substrate, a buried oxide layer region on the semiconductor substrate, and a semiconductor layer on the buried oxide layer region. The semiconductor layer comprises a P-type semiconductor base region, a gate region, an N-type carrier storage region, a surface voltage-resisting region, a P-type electric field shielding region, an N-type semiconductor buffer region and a P-type collector region, the P-type semiconductor base region and the gate region are located on one side of the semiconductor layer, the N-type semiconductor buffer region is located on the other side of the semiconductor layer, the N-type carrier storage region is located beside the P-type semiconductor base region, the P-type electric field shielding region is located beside the gate region, the surface voltage-resisting region is located among the N-type carrier storage region, the P-type electric field shielding region and the N-type semiconductor buffer region, and the P-.
Furthermore, the gate region comprises a planar gate region and a three-dimensional groove gate region, the planar gate region is composed of a gate dielectric layer, gate metal and a polycrystalline silicon gate region, the three-dimensional groove gate region is contacted with the P-type semiconductor base region, the three-dimensional groove gate region is composed of a deep groove extending into the semiconductor layer, and the deep groove comprises the gate dielectric layer, the polycrystalline silicon gate region which is positioned in the deep groove and is surrounded by the gate dielectric layer and the gate metal which covers part of the polycrystalline silicon gate region.
Further, the P-type semiconductor base region is divided into four different sub-regions by a three-dimensional trench gate region, wherein:
the first sub-region is used as a LIGBT channel base region, a heavily doped N-type semiconductor region and a heavily doped P-type semiconductor region are respectively arranged in the first sub-region, the heavily doped N-type semiconductor region is used as a source region of the LIGBT channel base region, the heavily doped P-type semiconductor region is used as an ohmic contact region of the LIGBT channel base region, and emitter metals are covered on part of the heavily doped N-type semiconductor region and part of the heavily doped P-type semiconductor region; the surface of the first sub-area is also provided with a plane gate area, a gate dielectric layer of the plane gate area covers part of the heavily doped N-type semiconductor area, the P-type semiconductor base area and part of the N-type carrier storage area, and the upper surface of the gate dielectric layer is sequentially covered with a polycrystalline silicon gate area and gate metal from bottom to top.
And a heavily doped N-type semiconductor region and a heavily doped P-type semiconductor region are respectively arranged in the second sub-region, the heavily doped N-type semiconductor region of the second sub-region is used as a cathode ohmic contact region of the first diode, the heavily doped P-type semiconductor region of the second sub-region is used as an anode ohmic contact region of the first diode, and the cathode ohmic contact region of the first diode is connected with the emitter metal.
And a heavily doped N-type semiconductor region and a heavily doped P-type semiconductor region are respectively arranged in the third sub-region, the heavily doped N-type semiconductor region of the third sub-region is used as a cathode ohmic contact region of the second diode, the heavily doped P-type semiconductor region of the third sub-region is used as an anode ohmic contact region of the second diode, and the cathode ohmic contact region of the second diode is connected with the anode ohmic contact region of the first diode through the first floating metal.
The fourth sub-area is connected with an anode ohmic contact area of the second diode through a second floating metal, the fourth sub-area is connected with the P-type electric field shielding area, the fourth sub-area and the P-type electric field shielding area surround one side portion, close to the surface voltage-resistant area, of the three-dimensional groove gate area, and the fourth sub-area and the P-type electric field shielding area jointly form an electric field shielding area.
Further, an ohmic contact region of the base region, a source region of the base region, a gate region, a P-type semiconductor base region, an N-type carrier storage region and emitter metal form an nMOS structure of the LIGBT together, and the nMOS structure, the P-type electric field shielding region, the first diode and the second diode form a first active region.
Further, the P-type semiconductor base region is divided into five different sub-regions by a stereoscopic slot gate region, wherein:
the first sub-region is used as a LIGBT channel base region, a heavily doped N-type semiconductor region and a heavily doped P-type semiconductor region are respectively arranged in the first sub-region, the heavily doped N-type semiconductor region is used as a source region of the LIGBT channel base region, the heavily doped P-type semiconductor region is used as an ohmic contact region of the LIGBT channel base region, and emitter metals are covered on part of the heavily doped N-type semiconductor region and part of the heavily doped P-type semiconductor region; the surface of the first sub-area is also provided with a plane gate area, a gate dielectric layer of the plane gate area covers part of the heavily doped N-type semiconductor area, the P-type semiconductor base area and part of the N-type carrier storage area, and the upper surface of the gate dielectric layer is sequentially covered with a polycrystalline silicon gate area and gate metal from bottom to top.
And a heavily doped N-type semiconductor region and a heavily doped P-type semiconductor region are respectively arranged in the second sub-region, the heavily doped N-type semiconductor region of the second sub-region is used as a cathode ohmic contact region of the first diode, the heavily doped P-type semiconductor region of the second sub-region is used as an anode ohmic contact region of the first diode, and the cathode ohmic contact region of the first diode is connected with the emitter metal.
And a heavily doped N-type semiconductor region and a heavily doped P-type semiconductor region are respectively arranged in the third sub-region, the heavily doped N-type semiconductor region of the third sub-region is used as a cathode ohmic contact region of the second diode, the heavily doped P-type semiconductor region of the third sub-region is used as an anode ohmic contact region of the second diode, and the cathode ohmic contact region of the second diode is connected with the anode ohmic contact region of the first diode through the first floating metal.
And a heavily doped N-type semiconductor region and a heavily doped P-type semiconductor region are respectively arranged in the fourth sub-region, the heavily doped N-type semiconductor region of the fourth sub-region is used as a cathode ohmic contact region of the third diode, the heavily doped P-type semiconductor region of the fourth sub-region is used as an anode ohmic contact region of the third diode, and the cathode ohmic contact region of the third diode is connected with the anode ohmic contact region of the second diode through a third floating metal.
The fifth sub-area is connected with an anode ohmic contact area of the third diode through a second floating metal, the fifth sub-area is connected with the P-type electric field shielding area, the fifth sub-area and the P-type electric field shielding area surround one side portion, close to the surface voltage-resistant area, of the three-dimensional groove gate area, and the fifth sub-area and the P-type electric field shielding area jointly form an electric field shielding area.
Further, an ohmic contact region of the base region, a source region of the base region, a gate region, a P-type semiconductor base region, an N-type carrier storage region and emitter metal form an nMOS structure of the LIGBT together, and the nMOS structure, the P-type electric field shielding region, the first diode, the second diode and the third diode form a first active region.
Furthermore, the upper surface of the P-type collector region is covered with collector metal, and the N-type semiconductor buffer region, the P-type collector region and the collector metal jointly form a second active region.
Furthermore, the surface voltage-withstanding region is formed by an N-type semiconductor layer, one side of the surface voltage-withstanding region is in contact with the three-dimensional groove gate region and the N-type carrier storage region, and the other side of the surface voltage-withstanding region is in contact with the N-type semiconductor buffer region.
Further, the surface voltage-resisting area is formed by an N-type semiconductor layer with linear gradient doping, and the doping of the N-type semiconductor layer is gradually increased from the position close to the first active area to the second active area.
The invention has the beneficial effects that: the invention provides a novel SOI LIGBT device with low on-state voltage drop, low turn-off loss and excellent short-circuit resistance. In the invention, the P-type semiconductor base region is divided into a plurality of regions, and two or three diodes connected in series are introduced into different regions, so that when the device is in reverse voltage resistance, the potential of the P-type electric field shielding region is increased to the conduction voltage drop of the two or three diodes, the diodes are conducted, and the potential of the P-type electric field shielding region is clamped near the conduction voltage drop of the two or three diodes, so that the potential of the N-type carrier storage region is well shielded at a very low value by the P-type electric field shielding region, and the voltage resistance of the device is mainly born by the reverse bias diode formed by the P-type electric field shielding region and the surface voltage resistance region, thereby thoroughly breaking the contradiction relation between the breakdown voltage and the N-type carrier layer concentration. The N-type carrier storage region doping can be increased by several orders of magnitude without breakdown at the reverse biased diode formed by the carrier storage region and the P-type semiconductor base region. The emitter injection efficiency of the LIGBT can be obviously improved, so that the conduction voltage drop of the LIGBT is reduced. And due to the improvement of the injection efficiency of the emitter, the LIGBT collector injection efficiency can be properly reduced, thereby improving the turn-off speed. Meanwhile, the plurality of diodes connected in series can clamp the drain voltage of the nMOS of the LIGBT of the first active region, namely the voltage of the N-type carrier storage region, so that the device has lower saturation current density, and the short-circuit safe working region is improved. In conclusion, the invention can reduce the LIGBT conduction voltage drop, improve the turn-off speed and improve the short-circuit safe working area on the basis of being compatible with the prior art.
Drawings
Fig. 1 is a schematic diagram of a conventional SOI LIGBT structure with a carrier storage layer in the prior art.
Fig. 2 is a schematic diagram of an SOI LIGBT structure with two diode clamps according to an embodiment of the present invention.
FIG. 3 is a top view of an SOI LIGBT structure with two diode clamps according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of an SOI LIGBT structure with three diode clamps according to a second embodiment of the present invention.
Fig. 5 is a top view of a SOI LIGBT structure with three diode clamps according to a second embodiment of the present invention.
FIG. 6 shows simulated V for conventional SOI LIGBT with carrier storage layer and SOI LIGBT with two diode clamps according to an embodiment of the present inventionon-EoffThe relationship is compared to the graph.
Description of reference numerals:
the structure comprises a semiconductor substrate 1, a buried oxide layer 2, a P-type semiconductor base region 3, a heavily doped N-type semiconductor region 4, a heavily doped P-type semiconductor region 5, a N-type carrier storage region 6, a surface voltage-withstanding region 7, a gate dielectric layer 8, a gate metal 9, an emitter metal 10, a first floating metal 11, a second floating metal 12, a P-type electric field shielding region 13, a polysilicon gate region 14, an N-type semiconductor buffer region 15, a P-type collector region 16, a collector metal 17 and a third floating metal 18.
Detailed Description
Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It is to be understood that the embodiments shown and described in the drawings are merely exemplary and are intended to illustrate the principles and spirit of the invention, not to limit the scope of the invention.
The first embodiment is as follows:
the embodiment of the invention provides an SOI LIGBT device with two diode clamps, which is collectively shown in FIGS. 2 to 3 and comprises a semiconductor substrate 1, a buried oxide layer region 2 positioned on the semiconductor substrate 1 and a semiconductor layer (SOI layer) positioned on the buried oxide layer region 2. The semiconductor layer comprises a P-type semiconductor base region 3, a gate region, an N-type carrier storage region 6, a surface voltage-withstanding region 7, a P-type electric field shielding region 13, an N-type semiconductor buffer region 15 and a P-type collector region 16, the P-type semiconductor base region 3 and the gate region are located on one side of the semiconductor layer, the N-type semiconductor buffer region 15 is located on the other side of the semiconductor layer, the N-type carrier storage region 6 is located beside the P-type semiconductor base region 3, the P-type electric field shielding region 13 is located beside the gate region, the surface voltage-withstanding region 7 is located among the N-type carrier storage region 6, the P-type electric field shielding region 13 and the N-type semiconductor buffer region 15, and the P-type collector. In the embodiment of the invention, the P-type semiconductor base region 3 can be in contact with the buried oxide layer region 2 or not; the P-type electric field shielding region 13 may or may not be in contact with the buried oxide layer region 2.
The gate region comprises a plane gate region and a three-dimensional groove gate region, the plane gate region is composed of a gate dielectric layer 8, gate metal 9 and a polycrystalline silicon gate region 14, the three-dimensional groove gate region is in contact with the P-type semiconductor base region 3, the three-dimensional groove gate region is composed of a deep groove extending into the semiconductor layer, and the deep groove comprises the gate dielectric layer 8, the polycrystalline silicon gate region 14 located in the deep groove and surrounded by the gate dielectric layer 8 and the gate metal 9 covering part of the polycrystalline silicon gate region 14.
In the embodiment of the present invention, the P-type semiconductor base region 3 is divided into four different sub-regions by a three-dimensional trench gate region, wherein:
the first sub-region is used as a LIGBT channel base region, a heavily doped N-type semiconductor region 4 and a heavily doped P-type semiconductor region 5 are respectively arranged in the first sub-region, the heavily doped N-type semiconductor region 4 is used as a source region of the LIGBT channel base region, the heavily doped P-type semiconductor region 5 is used as an ohmic contact region of the LIGBT channel base region, and emitter metal 10 covers part of the heavily doped N-type semiconductor region 4 and part of the heavily doped P-type semiconductor region 5. The surface of the first sub-area is also provided with a plane gate area, a gate dielectric layer 8 of the plane gate area covers part of the heavily doped N-type semiconductor area 4, the P-type semiconductor base area 3 and part of the N-type carrier storage area 6, and the upper surface of the gate dielectric layer 8 is sequentially covered with a polysilicon gate area 14 and a gate metal 9 from bottom to top.
And a heavily doped N-type semiconductor region 4 and a heavily doped P-type semiconductor region 5 are respectively arranged in the second sub-region, the heavily doped N-type semiconductor region 4 of the second sub-region is used as a cathode ohmic contact region of the first diode, the heavily doped P-type semiconductor region 5 of the second sub-region is used as an anode ohmic contact region of the first diode, and the cathode ohmic contact region of the first diode is connected with the emitter metal 10.
The third sub-area is internally provided with a heavily doped N-type semiconductor area 4 and a heavily doped P-type semiconductor area 5 respectively, the heavily doped N-type semiconductor area 4 of the third sub-area is used as a cathode ohmic contact area of the second diode, the heavily doped P-type semiconductor area 5 of the third sub-area is used as an anode ohmic contact area of the second diode, and the cathode ohmic contact area of the second diode is connected with the anode ohmic contact area of the first diode through the first floating metal 11, namely the second diode is connected with the first diode in series.
The fourth sub-area is connected with an anode ohmic contact area of the second diode through a second floating metal 12, the fourth sub-area is connected with a P-type electric field shielding area 13, the fourth sub-area and the P-type electric field shielding area 13 surround one side part of the three-dimensional groove gate area close to the surface voltage-resisting area 7, and the fourth sub-area and the P-type electric field shielding area 13 jointly form an electric field shielding area.
The ohmic contact region of the base region, the source region of the base region, the gate region, the P-type semiconductor base region 3, the N-type carrier storage region 6 and the emitter metal 10 form an nMOS structure of the LIGBT together, and the nMOS structure, the P-type electric field shielding region 13, the first diode and the second diode form a first active region.
The upper surface of the P-type collector region 16 is covered with a collector metal 17, and the N-type semiconductor buffer region 15, the P-type collector region 16 and the collector metal 17 together form a second active region.
The surface voltage-withstanding region 7 is formed of an N-type semiconductor layer, one side of which is in contact with the three-dimensional trench gate region and the N-type carrier storage region 6, and the other side of which is in contact with the N-type semiconductor buffer region 15. In the embodiment of the present invention, the surface voltage-withstanding region 7 is formed by an N-type semiconductor layer with linear graded doping, and the doping of the N-type semiconductor layer gradually increases from the region close to the first active region to the second active region.
Example two:
the embodiment of the invention provides an SOI LIGBT device with three diode clamps, which is collectively shown in fig. 4-5 and comprises a semiconductor substrate 1, a buried oxide layer region 2 positioned on the semiconductor substrate 1 and a semiconductor layer (SOI layer) positioned on the buried oxide layer region 2. The semiconductor layer comprises a P-type semiconductor base region 3, a gate region, an N-type carrier storage region 6, a surface voltage-withstanding region 7, a P-type electric field shielding region 13, an N-type semiconductor buffer region 15 and a P-type collector region 16, the P-type semiconductor base region 3 and the gate region are located on one side of the semiconductor layer, the N-type semiconductor buffer region 15 is located on the other side of the semiconductor layer, the N-type carrier storage region 6 is located beside the P-type semiconductor base region 3, the P-type electric field shielding region 13 is located beside the gate region, and the surface voltage-withstanding region 7 is located among the N-type carrier storage region 6, the P-type electric field shielding region 13. The P-type collector region 16 is disposed on the top side of the N-type semiconductor buffer region 15. In the embodiment of the invention, the P-type semiconductor base region 3 can be in contact with the buried oxide layer region 2 or not; the P-type electric field shielding region 13 may or may not be in contact with the buried oxide layer region 2.
The gate region comprises a plane gate region and a three-dimensional groove gate region, the plane gate region is composed of a gate dielectric layer 8, gate metal 9 and a polycrystalline silicon gate region 14, the three-dimensional groove gate region is in contact with the P-type semiconductor base region 3, the three-dimensional groove gate region is composed of a deep groove extending into the semiconductor layer, and the deep groove comprises the gate dielectric layer 8, the polycrystalline silicon gate region 14 located in the deep groove and surrounded by the gate dielectric layer 8 and the gate metal 9 covering part of the polycrystalline silicon gate region 14.
In the embodiment of the present invention, the P-type semiconductor base region 3 is divided into five different sub-regions by a three-dimensional trench gate region, wherein:
the first sub-region is used as a LIGBT channel base region, a heavily doped N-type semiconductor region 4 and a heavily doped P-type semiconductor region 5 are respectively arranged in the first sub-region, the heavily doped N-type semiconductor region 4 is used as a source region of the LIGBT channel base region, the heavily doped P-type semiconductor region 5 is used as an ohmic contact region of the LIGBT channel base region, and emitter metal 10 covers part of the heavily doped N-type semiconductor region 4 and part of the heavily doped P-type semiconductor region 5. The surface of the first sub-area is also provided with a plane gate area, a gate dielectric layer 8 of the plane gate area covers part of the heavily doped N-type semiconductor area 4, the P-type semiconductor base area 3 and part of the N-type carrier storage area 6, and the upper surface of the gate dielectric layer 8 is sequentially covered with a polysilicon gate area 14 and a gate metal 9 from bottom to top.
And a heavily doped N-type semiconductor region 4 and a heavily doped P-type semiconductor region 5 are respectively arranged in the second sub-region, the heavily doped N-type semiconductor region 4 of the second sub-region is used as a cathode ohmic contact region of the first diode, the heavily doped P-type semiconductor region 5 of the second sub-region is used as an anode ohmic contact region of the first diode, and the cathode ohmic contact region of the first diode is connected with the emitter metal 10.
The third sub-area is internally provided with a heavily doped N-type semiconductor area 4 and a heavily doped P-type semiconductor area 5 respectively, the heavily doped N-type semiconductor area 4 of the third sub-area is used as a cathode ohmic contact area of the second diode, the heavily doped P-type semiconductor area 5 of the third sub-area is used as an anode ohmic contact area of the second diode, and the cathode ohmic contact area of the second diode is connected with the anode ohmic contact area of the first diode through the first floating metal 11, namely the second diode is connected with the first diode in series.
The fourth sub-area is internally provided with a heavily doped N-type semiconductor area 4 and a heavily doped P-type semiconductor area 5 respectively, the heavily doped N-type semiconductor area 4 of the fourth sub-area is used as a cathode ohmic contact area of the third diode, the heavily doped P-type semiconductor area 5 of the fourth sub-area is used as an anode ohmic contact area of the third diode, and the cathode ohmic contact area of the third diode is connected with the anode ohmic contact area of the second diode through a third floating metal 18, namely the third diode is connected with the second diode in series.
The fifth sub-area is connected with an anode ohmic contact area of the third diode through a second floating metal 12, the fifth sub-area is connected with a P-type electric field shielding area 13, the fifth sub-area and the P-type electric field shielding area 13 surround one side part of the three-dimensional groove gate area close to the surface voltage-resisting area 7, and the fifth sub-area and the P-type electric field shielding area 13 jointly form an electric field shielding area.
The ohmic contact region of the base region, the source region of the base region, the gate region, the P-type semiconductor base region 3, the N-type carrier storage region 6 and the emitter metal 10 form an nMOS structure of the LIGBT together, and the nMOS structure, the P-type electric field shielding region 13, the first diode, the second diode and the third diode form a first active region.
The upper surface of the P-type collector region 16 is covered with a collector metal 17, and the N-type semiconductor buffer region 15, the P-type collector region 16 and the collector metal 17 together form a second active region.
The surface voltage-withstanding region 7 is formed of an N-type semiconductor layer, one side of which is in contact with the three-dimensional trench gate region and the N-type carrier storage region 6, and the other side of which is in contact with the N-type semiconductor buffer region 15. In the embodiment of the present invention, the surface voltage-withstanding region 7 is formed by an N-type semiconductor layer with linear graded doping, and the doping of the N-type semiconductor layer gradually increases from the region close to the first active region to the second active region.
Based on the two embodiments, the working principle of the invention is described in detail below with reference to the drawings of the specification:
compared with the traditional SOI LIGBT with a carrier storage layer, the invention mainly introduces a series diode and a P-type electric field shielding region 13. Referring to fig. 2 and 4, when the device operates under the reverse voltage-withstanding condition, the potential of the P-type electric field shielding region 13 rises with the rise of the collector voltage, and when the potential of the P-type electric field shielding region 13 rises to about 1.4V or 2.1V, i.e., the sum of the conduction voltage drops of two or three diodes connected in series (actually, since only the leakage current flows, the voltage should be less than 1.4V or 2.1V), the potential of the P-type electric field shielding region 13 will not rise any more. Meanwhile, a part of the surface voltage-resistant region 7 between the N-type carrier storage region 6 and the P-type electric field shielding region 13 is quickly fully depleted due to small thickness and low doping concentration. Thereafter, the reverse bias voltage of the PN junction formed by the P-type semiconductor base region 3 and the N-type carrier storage region 6 in the first sub-region does not substantially increase rapidly with the increase of the collector voltage, which is mainly borne by the reverse biased diode formed by the P-type electric field shielding region 13 and the surface voltage-withstanding region 7. In other words, the SOI LIGBT proposed by the present invention is mainly subjected to reverse bias by the PN junction formed by the P-type electric field shielding region 13 and the surface voltage-withstanding region 7, rather than the PN junction formed by the P-type semiconductor base region 3 and the N-type carrier storage region 6 in the conventional SOI LIGBT structure. Therefore, the doping concentration of the N-type carrier storage region 6 in the invention is no longer limited by the breakdown voltage of the device, so that the carrier storage layer can be heavily doped to improve the electron injection efficiency of the emitter.
When the device works in a forward conduction state, a large number of non-equilibrium carriers are gathered near the first active region due to the fact that the N-type carrier storage region 6 has high doping concentration, and conductivity modulation of the surface voltage-resisting region 7 is enhancedThe effect is that the on-state voltage drop (V) of the device is reduced significantlyon). On the other hand, since the series diode clamps the potential of the P-type electric field shielding region 13, the nMOS of the LIGBT has a very low drain voltage, thereby reducing the saturation current density of the device and increasing the safe operating region. For the turn-off characteristic, since the injection efficiency of the emitter is improved, the injection efficiency of the collector holes can be properly reduced to obtain the same on-state voltage drop, so that when the turn-off is performed, high-concentration carriers of the emitter are rapidly extracted by a strong electric field, and after the hole injection efficiency of the collector is reduced, the continuous injection of the holes is greatly reduced, so that the device has better Von-EoffA compromise relationship.
In the embodiment of the invention, the structural parameters of the adopted simulation device are mainly set as that the thickness of an SOI layer is 1.5 mu m, the thickness of a buried oxide layer region 2 is 3 mu m, the length of the device is 35 mu m, and the concentration of an N-type carrier storage region 6 is 1 × 1019cm-3The surface voltage-resistant area 7 adopts transverse gradient doping to obtain Von-EoffSimulation results are shown in fig. 6, and it can be seen from fig. 6 that the SOI LIGBT device with two diode clamps provided by the first embodiment of the present invention has better V than the conventional structure of the prior arton-EoffCompromise Curve, at 300K, same VonDown, EoffThe reduction is 26.5%.
The key point of the technology of the invention is that the P-type semiconductor base region 3 of the LIGBT is divided into a plurality of sub-regions by a three-dimensional groove grid region, a plurality of diodes which are connected in series are arranged in some sub-regions, the potential of the N-type carrier storage region 6 is shielded at a very low value by the diodes which are connected in series and the other P-type electric field shielding region 13 which is positioned at one side of the three-dimensional groove grid region close to the surface voltage-resistant region 7, so that the doping concentration of the carrier storage layer can be greatly improved, the diode formed by the N-type carrier storage region 6 and the P-type semiconductor base region 3 is not broken down when the device is voltage-resistant, the conduction voltage drop of the LIGBT can be greatly reduced, and the. And because the potential of the carrier storage layer is shielded at a very low value, the saturation current density of the LIGBT is improved, thereby greatly improving the short-circuit safe working area of the LIGBT.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (7)
1. The SOI LIGBT device with the diode-clamped carrier storage layer is characterized by comprising a semiconductor substrate (1), a buried oxide layer region (2) located on the semiconductor substrate (1) and a semiconductor layer located on the buried oxide layer region (2);
the semiconductor layer comprises a P-type semiconductor base region (3), a gate region, an N-type carrier storage region (6), a surface voltage-resisting region (7), a P-type electric field shielding region (13), an N-type semiconductor buffer region (15) and a P-type collector region (16), wherein the P-type semiconductor base region (3) and the gate region are located on one side of the semiconductor layer, the N-type semiconductor buffer region (15) is located on the other side of the semiconductor layer, the N-type carrier storage region (6) is located beside the P-type semiconductor base region (3), the P-type electric field shielding region (13) is located beside the gate region, the surface voltage-resisting region (7) is located among the N-type carrier storage region (6), the P-type electric field shielding region (13) and the N-type semiconductor buffer region (15), and the P-type collector region (16) is arranged on one side of;
the gate region comprises a plane gate region and a three-dimensional groove gate region, the plane gate region is composed of a gate dielectric layer (8), gate metal (9) and a polycrystalline silicon gate region (14), the three-dimensional groove gate region is contacted with the P-type semiconductor base region (3), the three-dimensional groove gate region is composed of deep grooves which go deep into the semiconductor layer, and the deep grooves comprise gate dielectric layers (8), polycrystalline silicon gate regions (14) which are positioned in the deep grooves and surrounded by the gate dielectric layers (8) and gate metal (9) which covers part of the polycrystalline silicon gate regions (14);
the P-type semiconductor base region (3) is divided into four different sub-regions by a three-dimensional groove grid region, wherein:
the first sub-area is used as a LIGBT channel base area, a heavily doped N-type semiconductor area (4) and a heavily doped P-type semiconductor area (5) are respectively arranged in the first sub-area, the heavily doped N-type semiconductor area (4) is used as a source area of the LIGBT channel base area, the heavily doped P-type semiconductor area (5) is used as an ohmic contact area of the LIGBT channel base area, and emitter metal (10) covers part of the heavily doped N-type semiconductor area (4) and part of the heavily doped P-type semiconductor area (5); the surface of the first sub-area is also provided with a planar gate area, a gate dielectric layer (8) of the planar gate area covers part of the heavily doped N-type semiconductor area (4), the P-type semiconductor base area (3) and part of the N-type carrier storage area (6), and the upper surface of the gate dielectric layer (8) is sequentially covered with a polycrystalline silicon gate area (14) and gate metal (9) from bottom to top;
a heavily doped N-type semiconductor region (4) and a heavily doped P-type semiconductor region (5) are respectively arranged in the second sub-region, the heavily doped N-type semiconductor region (4) of the second sub-region is used as a cathode ohmic contact region of the first diode, the heavily doped P-type semiconductor region (5) of the second sub-region is used as an anode ohmic contact region of the first diode, and the cathode ohmic contact region of the first diode is connected with the emitter metal (10);
a heavily doped N-type semiconductor region (4) and a heavily doped P-type semiconductor region (5) are respectively arranged in the third sub-region, the heavily doped N-type semiconductor region (4) of the third sub-region is used as a cathode ohmic contact region of the second diode, the heavily doped P-type semiconductor region (5) of the third sub-region is used as an anode ohmic contact region of the second diode, and the cathode ohmic contact region of the second diode is connected with the anode ohmic contact region of the first diode through a first floating metal (11);
the fourth sub-area is connected with an anode ohmic contact area of the second diode through a second floating metal (12), the fourth sub-area is connected with the P-type electric field shielding area (13), the fourth sub-area and the P-type electric field shielding area (13) surround one side part of the three-dimensional groove gate area close to the surface voltage-resistant area (7), and the fourth sub-area and the P-type electric field shielding area (13) jointly form an electric field shielding area.
2. The SOI LIGBT device with the diode-clamped carrier storage layer is characterized by comprising a semiconductor substrate (1), a buried oxide layer region (2) located on the semiconductor substrate (1) and a semiconductor layer located on the buried oxide layer region (2);
the semiconductor layer comprises a P-type semiconductor base region (3), a gate region, an N-type carrier storage region (6), a surface voltage-resisting region (7), a P-type electric field shielding region (13), an N-type semiconductor buffer region (15) and a P-type collector region (16), wherein the P-type semiconductor base region (3) and the gate region are located on one side of the semiconductor layer, the N-type semiconductor buffer region (15) is located on the other side of the semiconductor layer, the N-type carrier storage region (6) is located beside the P-type semiconductor base region (3), the P-type electric field shielding region (13) is located beside the gate region, the surface voltage-resisting region (7) is located among the N-type carrier storage region (6), the P-type electric field shielding region (13) and the N-type semiconductor buffer region (15), and the P-type collector region (16) is arranged on one side of;
the gate region comprises a plane gate region and a three-dimensional groove gate region, the plane gate region is composed of a gate dielectric layer (8), gate metal (9) and a polycrystalline silicon gate region (14), the three-dimensional groove gate region is contacted with the P-type semiconductor base region (3), the three-dimensional groove gate region is composed of deep grooves which go deep into the semiconductor layer, and the deep grooves comprise gate dielectric layers (8), polycrystalline silicon gate regions (14) which are positioned in the deep grooves and surrounded by the gate dielectric layers (8) and gate metal (9) which covers part of the polycrystalline silicon gate regions (14);
the P-type semiconductor base region (3) is divided into five different sub-regions by a three-dimensional trench gate region, wherein:
the first sub-area is used as a LIGBT channel base area, a heavily doped N-type semiconductor area (4) and a heavily doped P-type semiconductor area (5) are respectively arranged in the first sub-area, the heavily doped N-type semiconductor area (4) is used as a source area of the LIGBT channel base area, the heavily doped P-type semiconductor area (5) is used as an ohmic contact area of the LIGBT channel base area, and emitter metal (10) covers part of the heavily doped N-type semiconductor area (4) and part of the heavily doped P-type semiconductor area (5); the surface of the first sub-area is also provided with a planar gate area, a gate dielectric layer (8) of the planar gate area covers part of the heavily doped N-type semiconductor area (4), the P-type semiconductor base area (3) and part of the N-type carrier storage area (6), and the upper surface of the gate dielectric layer (8) is sequentially covered with a polycrystalline silicon gate area (14) and gate metal (9) from bottom to top;
a heavily doped N-type semiconductor region (4) and a heavily doped P-type semiconductor region (5) are respectively arranged in the second sub-region, the heavily doped N-type semiconductor region (4) of the second sub-region is used as a cathode ohmic contact region of the first diode, the heavily doped P-type semiconductor region (5) of the second sub-region is used as an anode ohmic contact region of the first diode, and the cathode ohmic contact region of the first diode is connected with the emitter metal (10);
a heavily doped N-type semiconductor region (4) and a heavily doped P-type semiconductor region (5) are respectively arranged in the third sub-region, the heavily doped N-type semiconductor region (4) of the third sub-region is used as a cathode ohmic contact region of the second diode, the heavily doped P-type semiconductor region (5) of the third sub-region is used as an anode ohmic contact region of the second diode, and the cathode ohmic contact region of the second diode is connected with the anode ohmic contact region of the first diode through a first floating metal (11);
a heavily doped N-type semiconductor region (4) and a heavily doped P-type semiconductor region (5) are respectively arranged in the fourth sub-region, the heavily doped N-type semiconductor region (4) of the fourth sub-region is used as a cathode ohmic contact region of a third diode, the heavily doped P-type semiconductor region (5) of the fourth sub-region is used as an anode ohmic contact region of the third diode, and the cathode ohmic contact region of the third diode is connected with the anode ohmic contact region of the second diode through a third floating metal (18);
the fifth sub-area is connected with an anode ohmic contact area of a third diode through a second floating metal (12), the fifth sub-area is connected with a P-type electric field shielding area (13), the fifth sub-area and the P-type electric field shielding area (13) surround one side part, close to the surface voltage-resistant area (7), of the three-dimensional groove gate area, and the fifth sub-area and the P-type electric field shielding area (13) jointly form an electric field shielding area.
3. The SOI LIGBT device according to claim 1, characterized in that the ohmic contact area of the LIGBT channel base region, the source area of the LIGBT channel base region, the gate area, the P-type semiconductor base region (3), the N-type carrier storage region (6), the emitter metal (10) together form an nMOS structure of LIGBT, the nMOS structure and the P-type electric field shielding region (13), the first diode and the second diode constituting the first active region.
4. The SOI LIGBT device according to claim 2, characterized in that the ohmic contact area of the LIGBT channel base region, the source area of the LIGBT channel base region, the gate area, the P-type semiconductor base region (3), the N-type carrier storage region (6), the emitter metal (10) together form an nMOS structure of LIGBT, the nMOS structure and the P-type electric field shielding region (13), the first diode, the second diode and the third diode constituting the first active region.
5. SOI LIGBT device according to any of claims 3 or 4, wherein the upper surface of the P-type collector region (16) is covered with a collector metal (17), and the N-type semiconductor buffer region (15), the P-type collector region (16) and the collector metal (17) together form a second active region.
6. SOI LIGBT device according to claim 5, characterized in that the surface voltage withstand region (7) is formed by an N-type semiconductor layer, which is in contact with the three-dimensional trench gate region and the N-type carrier storage region (6) on one side and with the N-type semiconductor buffer region (15) on the other side.
7. The SOI LIGBT device according to claim 6, wherein the surface voltage withstanding region (7) is formed by an N-type semiconductor layer with a linear graded doping, the doping of which is gradually increased from near the first active region to the second active region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910316577.6A CN109888007B (en) | 2019-04-19 | 2019-04-19 | SOI LIGBT device with diode clamped carrier storage layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910316577.6A CN109888007B (en) | 2019-04-19 | 2019-04-19 | SOI LIGBT device with diode clamped carrier storage layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109888007A CN109888007A (en) | 2019-06-14 |
| CN109888007B true CN109888007B (en) | 2020-08-18 |
Family
ID=66937900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910316577.6A Active CN109888007B (en) | 2019-04-19 | 2019-04-19 | SOI LIGBT device with diode clamped carrier storage layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109888007B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110504305B (en) * | 2019-08-06 | 2021-02-05 | 电子科技大学 | SOI-LIGBT device with self-biased pmos clamp carrier storage layer |
| CN110504312B (en) * | 2019-08-29 | 2020-09-15 | 电子科技大学 | Transverse IGBT with short circuit self-protection capability |
| CN111403385B (en) * | 2020-03-02 | 2022-10-14 | 电子科技大学 | RC-LIGBT device with embedded Schottky diode |
| CN111816698B (en) * | 2020-08-31 | 2021-06-08 | 电子科技大学 | Power device integrated with Zener diode and collector PMOS structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5959345A (en) * | 1997-11-28 | 1999-09-28 | Delco Electronics Corporation | Edge termination for zener-clamped power device |
| CN106505101A (en) * | 2016-10-19 | 2017-03-15 | 东南大学 | A kind of high current silicon-on-insulator lateral insulated-gate bipolar transistor device |
| CN107482058A (en) * | 2017-09-25 | 2017-12-15 | 电子科技大学 | A kind of thin SOI LIGBT devices with carrier accumulation layer |
| CN109103186A (en) * | 2018-08-14 | 2018-12-28 | 电子科技大学 | A kind of integrated hetero-junctions freewheeling diode silicon carbide tank gate MOSFET |
-
2019
- 2019-04-19 CN CN201910316577.6A patent/CN109888007B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5959345A (en) * | 1997-11-28 | 1999-09-28 | Delco Electronics Corporation | Edge termination for zener-clamped power device |
| CN106505101A (en) * | 2016-10-19 | 2017-03-15 | 东南大学 | A kind of high current silicon-on-insulator lateral insulated-gate bipolar transistor device |
| CN107482058A (en) * | 2017-09-25 | 2017-12-15 | 电子科技大学 | A kind of thin SOI LIGBT devices with carrier accumulation layer |
| CN109103186A (en) * | 2018-08-14 | 2018-12-28 | 电子科技大学 | A kind of integrated hetero-junctions freewheeling diode silicon carbide tank gate MOSFET |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109888007A (en) | 2019-06-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109888007B (en) | SOI LIGBT device with diode clamped carrier storage layer | |
| CN109427869B (en) | Semiconductor device with a plurality of transistors | |
| CN110400840B (en) | RC-LIGBT device for inhibiting voltage folding phenomenon | |
| CN111146274B (en) | Silicon carbide groove IGBT structure and manufacturing method thereof | |
| CN112928156B (en) | Floating p-column reverse-conducting type grooved gate super-junction IGBT | |
| CN111834449B (en) | Quick turn-off RC-IGBT device with back double MOS structure | |
| CN112038401A (en) | Insulated gate bipolar transistor structure and preparation method thereof | |
| CN110137250B (en) | High-speed IGBT device with ultralow conduction voltage drop | |
| CN109686788B (en) | Trench gate IGBT device with carrier storage layer | |
| CN110504305B (en) | SOI-LIGBT device with self-biased pmos clamp carrier storage layer | |
| CN111403385B (en) | RC-LIGBT device with embedded Schottky diode | |
| KR20100085508A (en) | Trench insulated gate bipolar trangistor | |
| CN112271208A (en) | Silicon carbide single-gate double-channel thyristor transport IGBT and manufacturing method thereof | |
| CN109686787B (en) | IGBT device clamped by diode and provided with carrier storage layer | |
| CN113054012B (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
| CN112928155B (en) | Groove gate super junction IGBT of floating p column | |
| CN111834450B (en) | SOI LIGBT device integrated with Zener diode | |
| US9318599B2 (en) | Power semiconductor device | |
| CN109888006B (en) | Low-power-consumption silicon-on-insulator transverse insulated gate bipolar transistor | |
| US9209287B2 (en) | Power semiconductor device | |
| CN115117161A (en) | Semiconductor device with a plurality of semiconductor chips | |
| CN112736134A (en) | Silicon carbide PNPN thyristor injection type IGBT device | |
| CN112018172A (en) | Insulated gate bipolar transistor, intelligent power device and electronic product | |
| CN111276537A (en) | Reverse conducting RC-LIGBT device with polycrystalline silicon voltage-resistant layer | |
| CN113193043B (en) | Trench gate IGBT device with diode clamping carrier storage layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |