CN112038401A - Insulated gate bipolar transistor structure and preparation method thereof - Google Patents
Insulated gate bipolar transistor structure and preparation method thereof Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
Abstract
The invention provides an insulated gate bipolar transistor structure and a preparation method thereof. The method comprises the following steps: the collector structure comprises a bottom collector, a P + + collector region positioned above the bottom collector and an N + buffer layer positioned above the P + + collector region; the drift region is positioned above the N + buffer layer, wherein a super junction structure is arranged in the drift region, and the super junction structure is formed by a plurality of first doping upright columns and a plurality of second doping upright columns which are sequentially and alternately arranged along the third dimension z direction; and the surface structure is positioned above the drift region, wherein the surface structure comprises a P base region, a floating P base region, a trench grid arranged in the P base region, a P + emitter region, an N + emitter region and a top emitter arranged above the floating P base region, the trench grid, the P + emitter region and the N + emitter region, and the P + emitter region and the N + emitter region are alternately arranged in a third z direction perpendicular to the plane. The IGBT structure can inhibit the reduction effect of the bias induced barrier of the collector electrode and improve the working capacity of the device.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to an Insulated Gate Bipolar Transistor (IGBT) structure and a preparation method thereof.
Background
The Insulated Gate Bipolar Transistor (IGBT) combines the advantages of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a Bipolar Junction Transistor (BJT), has the characteristics of voltage drive, high input impedance and high switching speed of the MOSFET device, and has the characteristics of reduced breakover voltage and strong current drive capability of the BJT, so that the IGBT is widely applied to the fields of energy conversion, locomotive traction, industrial frequency conversion, automotive electronics, consumer electronics and the like, and is one of important core devices in the field of power electronics.
Fig. 1 shows a conventional trench gate IGBT structure, which includes three electrodes: a bottom collector C (10), a top emitter E (8), and a gate G (9). It includes inside it: the transistor comprises an NMOS (N-channel metal oxide semiconductor) consisting of an N + emitter region 1, a P-type base region 2 and an N-drift region 4, a wide-base-region bipolar junction transistor PNP consisting of a top P + emitter region 3, the P-type base region 2, the N-drift region 4, an N + buffer region 5 and a bottom P + + collector region 6, and a middle floating P-type base region 2 a. The device gate structure is composed of a trench gate electrode 9 and a gate dielectric layer 7. When the voltage of the grid electrode 9 is higher than the threshold voltage of the device, the NMOS is conducted, the current enters the N-drift region 4 from the N + emitter region 1, the base electrode driving current is provided for the PNP transistor with the wide base region below, and the PNP transistor is started to conduct the device; when the voltage of the grid 9 is lower than the threshold voltage, the NMOS is turned off, and no current is injected into the N-drift region any more, so that the device is turned off.
However, when the IGBT structure is turned on, a hole current easily enters the channel inversion region, so that conductance modulation occurs in the channel region, a collector bias induced barrier lowering (CIBL) effect is generated, the threshold voltage of the device is lowered, the current of the saturated collector is increased, and the short-circuit operation of the device is failed; and when the device is switched on, a large number of carriers are stored in the drift region, so that the switching-off process of the device is relatively slow.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides the IGBT structure which can inhibit the collector bias induced barrier lowering (CIBL) effect, improve the short-circuit working capacity of the device, simultaneously improve the turn-off speed of the device and reduce the turn-off power consumption.
According to an aspect of the present invention, there is provided an Insulated Gate Bipolar Transistor (IGBT) structure including: a collector structure comprising a bottom collector, a P + + collector region above the bottom collector, and an N + buffer layer above the P + + collector region; the drift region is positioned above the collector electrode structure, a super junction structure is arranged in the drift region, and the super junction structure is formed by a plurality of first doping upright columns and a plurality of second doping upright columns which are sequentially and alternately arranged along the third dimension z direction; and a surface structure located above the drift region, wherein the surface structure includes a P base region, a floating P base region, a trench gate and P + and N + emitter regions disposed in the P base region, and a top emitter disposed above the floating P base region, the trench gate and the P + and N + emitter regions, wherein the P + and N + emitter regions are alternately disposed in the third z-direction perpendicular to the plane.
Furthermore, the first doped column is a P-type column, and the second doped column is an N-type column.
Further, each N-type pillar in the drift region corresponds to an N + emitter region, and each P-type pillar corresponds to a P + emitter region.
Further, the insulated gate bipolar transistor structure further includes: the isolation dielectric layer is arranged below the top emitter; and the gate dielectric surrounds the trench gate.
Further, the N + emitter region, the P base region, and the N-type pillar form an input NMOS structure.
According to another aspect of the present invention, there is provided a method of manufacturing an Insulated Gate Bipolar Transistor (IGBT) structure, including: preparing a substrate; forming a drift region on the front surface of the substrate, wherein the drift region is provided with a super junction structure, and the super junction structure is formed by a plurality of first doping upright columns and a plurality of second doping upright columns which are sequentially and alternately arranged along a third dimension z direction; forming a surface structure over the drift region, the surface structure including a P base region, a floating P base region, a trench gate and P + and N + emitter regions disposed in the P base region, and a top emitter disposed over the floating P base region, the trench gate and the P + and N + emitter regions, wherein the P + emitter regions alternate with the N + emitter regions in a third z-direction perpendicular to the plane. And forming an N + buffer layer and a P + + collector region positioned below the N + buffer layer on the back surface of the substrate in an ion implantation mode, and forming a bottom collector positioned below the P + + collector region through a metallization process.
Furthermore, the first doped column is a P-type column, and the second doped column is an N-type column.
Further, each N-type pillar corresponds to an N + emitter region, and each P-type pillar corresponds to a P + emitter region.
Further, the method further comprises: forming an isolation dielectric layer below the top emitter; a gate dielectric is formed surrounding the trench gate.
Further, float-zone single crystal silicon may be selected as the substrate material.
Further, multiple times of epitaxial ion implantation or trench etching and epitaxial filling techniques may be employed to form the drift region.
Further, the surface structure can be manufactured by adopting a groove process.
Further, the manufacturing of the surface structure further comprises: performing epitaxy and ion implantation on the drift region to form the P base region; etching the P base region by the groove to form a longitudinal strip-shaped groove, then carrying out gate oxidation to form the gate medium, and then filling a groove electrode to form the groove gate; depositing the isolation medium layer above the trench gate and part of the P base region, and then performing ion implantation by using a mask plate to form the P + emitter regions and the N + emitter regions which are longitudinally and alternately arranged on two sides; and depositing a metal layer on the surface to form the top emitter, and finishing the preparation of the surface structure.
According to the IGBT structure, the P + emitter region is placed in the third dimension direction perpendicular to the plane, the super-junction structure is formed in the third dimension direction of the drift region, hole current is extracted by the super-junction P-type upright column to enter the P + emitter region, the bias induced barrier lowering (CIBL) effect of an IGBT collector electrode is inhibited, and the short circuit working capacity of a device is improved. In addition, the transverse electric field in the super junction drift region enhances the carrier extraction effect in the turn-off process, improves the turn-off speed of the device and reduces the turn-off power consumption.
Drawings
The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 is a prior art trenched IGBT structure.
Fig. 2 is an IGBT structure according to an embodiment of the invention.
Fig. 3 is an IGBT structure according to an embodiment of the invention after top and bottom metal layers are removed.
Fig. 4 is a cross-sectional view of the IGBT structure according to an embodiment of the invention in the yz direction.
Fig. 5 is a prior art IGBT channel region potential distribution diagram.
Fig. 6 is a potential diagram of a channel region of an IGBT structure according to an embodiment of the invention.
Fig. 7 is a graph illustrating short-circuit operation characteristics of an IGBT according to an embodiment of the present invention.
Fig. 8 is a comparison graph of turn-off characteristics of IGBTs according to an embodiment of the present invention.
Fig. 9 to 12 are schematic diagrams of main steps of manufacturing an IGBT structure according to an embodiment of the invention.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact.
Furthermore, spatial relationship terms, such as "below", "lower", "above", "upper", and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such.
The present invention provides an IGBT structure, comprising:
the collector structure comprises a bottom collector, a P + + collector region positioned above the bottom collector and an N + buffer layer positioned above the P + + collector region;
the drift region is positioned above the N + buffer layer, wherein a super junction structure is arranged in the drift region, and the super junction structure is formed by a plurality of first doping upright columns and a plurality of second doping upright columns which are sequentially and alternately arranged along the third dimension z direction;
and the surface structure is positioned above the drift region, wherein the surface structure comprises a P base region, a floating P base region, a trench grid arranged in the P base region, a P + emitter region, an N + emitter region and a top emitter arranged above the floating P base region, the trench grid, the P + emitter region and the N + emitter region, and the P + emitter region and the N + emitter region are alternately arranged in a third z direction perpendicular to the plane.
According to the IGBT structure, the super-junction structure is formed in the third dimension direction of the drift region, hole current is extracted by the super-junction P-type stand column to directly enter the P + emitter region, conductivity modulation of the channel region is weakened, the bias induced barrier lowering (CIBL) effect of an IGBT collector electrode is further inhibited, and the short circuit working capacity of a device is improved. In addition, the transverse electric field in the super junction drift region enhances the carrier extraction effect in the turn-off process, improves the turn-off speed of the device and reduces the turn-off power consumption.
In order to better understand the above technical solutions, the above technical solutions will be described in detail with reference to specific embodiments.
Fig. 2 is an IGBT structure according to an embodiment of the invention, the structure comprising three electrodes: a bottom collector C (29), a top emitter E (27), and a trench gate G (28). In the figure, a P base region 17, a floating P base region 17a, a gate dielectric 26, an isolation dielectric layer 26a, an N + buffer layer 24 and a P + + collector region 25 have the same structure as that of a common trench gate IGBT. According to another embodiment of the present invention, an isolation dielectric layer 26a is disposed below the top emitter 27, and a gate dielectric 26 surrounds the trench gate 28.
Fig. 3 is an IGBT structure according to an embodiment of the invention after the top and bottom metal layers (top emitter 27 and bottom collector 29) have been removed. Unlike a normal IGBT, the IGBT of the present invention places P + emitter regions (12, 14, 16), which originally lie in the xy plane, in the third z-direction, alternately with N + emitter regions (11, 13, 15); n-type columns (18, 20, 22) and P-type columns (19, 21, 23) are alternately arranged in the drift region along the z direction in sequence to form a super junction structure, and each N-type column and each P-type column in the drift region correspond to one top N + emitter region and one top P + emitter region respectively. According to one embodiment of the present invention, the N + emitter regions (11, 13, 15), the P base region 17 and the N-type pillars (18, 20, 22) form an input NMOS structure.
Fig. 4 is a cross-sectional view of the IGBT structure according to an embodiment of the invention in the yz direction. The P-type columns (19, 21, 23) in the super junction drift region can directly extract the hole current injected from the bottom to the top P + emitter regions (12, 14, 16), so that the hole current is prevented from entering a channel region, and the collector bias induced barrier lowering (CIBL) effect is suppressed.
According to one embodiment of the present invention, the IGBT shown in fig. 2 has three operating states:
when a negative bias is applied between the bottom collector 29 and the top emitter 27, a PN junction formed by the P + + collector region 25 and the N + buffer layer 24 is reversely biased, so that no current flows between the bottom collector 29 and the top emitter 27, and the IGBT structure is in a reverse blocking state;
forward bias is applied between the bottom collector 29 and the top emitter 27, and when the voltage of the trench gate 28 is smaller than the threshold voltage, the NMOS structure is turned off, electron current cannot be injected from the N + emitter region (11, 13, 15) to the N-type pillars (18, 20, 22), and the PNP transistor in the lower wide base region cannot be turned on, and at this time, no current still flows between the bottom collector 29 and the top emitter 27 of the IGBT structure, and the IGBT structure is in a forward blocking state;
③ when a forward bias is applied between the bottom collector 29 and the top emitter 27 and the trench gate 28 voltage is greater than the threshold voltage, the NMOS structure is turned on and current is injected from the N + emitter region (11, 13, 15) to the N-type pillar (18, 20, 22) through the NMOS conduction channel. The injected electron current is used as the base trigger current of the PNP transistor with the wide base region below, the strong injection of holes is promoted to occur at the PN junction formed by the P + + collector region 25 and the N + buffer layer 24, the PNP transistor is started, and the IGBT is in a forward conduction state at the moment.
As shown in fig. 1, during the turn-on process of the conventional IGBT in the prior art, a hole current enters the NMOS channel region, so that the conductivity modulation occurs in the channel region, and further, the voltage of the collector electrode 10 directly affects the potentials of the P base region 2 and the N + emitter region 1. Fig. 5 shows a potential distribution of a channel region of a general IGBT in the related art. With the gradual increase of the voltage of the collector electrode, the potentials of the P base region and the N + emitter region are increased, and a collector electrode bias induced barrier lowering (CIBL) effect is generated, so that the threshold voltage is lowered, the saturation current is increased, and the short-circuit operation failure of the device is caused. In the IGBT structure according to the embodiment of the invention, the hole current injected from the bottom directly flows into the P + emitter regions (12, 14, 16) through the P-type pillars (19, 21, 23) in the super junction drift region, so that the channel region conductivity modulation effect is greatly weakened, and the influence of the collector bias on the potentials of the P base region and the N + emitter region is weakened. Fig. 6 shows an IGBT channel region potential distribution according to an embodiment of the present invention, and as the collector voltage gradually increases, the P base region and the N + emitter region potentials are almost kept constant, so that the collector offset induced barrier lowering (CIBL) effect is greatly suppressed, and the device short circuit operation capability is improved. Fig. 7 is a short-circuit operating characteristic curve of an IGBT according to an embodiment of the present invention. Compared with the common IGBT, the short-circuit working time of the IGBT is longer.
In addition, the IGBT drift region adopts a super junction structure, and a transverse electric field is formed in the IGBT drift region, so that the extraction effect of stored carriers in the turn-off process is accelerated, the turn-off speed of a device is improved, and the turn-off power consumption is reduced. Fig. 8 shows the comparison of the turn-off characteristics of the IGBT according to an embodiment of the present invention (the dotted line is the normal IGBT, and the solid line is the IGBT according to the present invention), and the turn-off speed of the IGBT structure according to the present invention is significantly faster than that of the normal IGBT structure.
Fig. 9 to 12 are schematic diagrams illustrating main steps of manufacturing an IGBT structure according to an embodiment of the present invention. The IGBT structure can be realized by adopting an FS IGBT process, and the super-junction drift region can adopt a groove etching and epitaxial filling technology, a multi-step epitaxial ion implantation technology, a multi-time high-energy ion implantation technology and the like. The process implementation steps are briefly described below:
the method comprises the following steps: preparing a substrate, wherein zone-melting monocrystalline silicon can be selected as a substrate material;
step two: forming a drift region on the front surface of the substrate by adopting technologies such as multiple times of epitaxial ion implantation or groove etching and epitaxial filling, wherein the drift region is provided with a super junction structure which is a plurality of first doping upright columns and a plurality of second doping upright columns which are sequentially and alternately arranged along the third dimension z direction;
step three: and forming a surface structure above the drift region by adopting a groove process, wherein the surface structure comprises a P base region, a floating P base region, a groove grid electrode, a P + emitter region, an N + emitter region and a top emitter electrode, wherein the groove grid electrode, the P + emitter region and the N + emitter region are arranged in the P base region, and the top emitter electrode is arranged above the floating P base region, the groove grid electrode, the P + emitter region and the N + emitter region, and the P + emitter region and the N + emitter region are alternately arranged in a third dimension z direction perpendicular to the plane.
Fig. 11a to 11d further show schematic diagrams of the main steps of making the surface structure, in particular:
(a) performing epitaxy and ion implantation on the drift region to form a P base region;
(b) etching the P base region by the groove to form a longitudinal strip-shaped groove, then carrying out gate oxidation to form a gate medium, and then filling a groove electrode to form a groove gate;
(c) depositing an isolation medium layer above the trench gate and part of the P base region, then performing ion implantation by using a mask, and forming P + emitter regions and N + emitter regions which are longitudinally and alternately arranged on two sides;
(d) and depositing a metal layer on the surface to form a top emitter, and finishing the preparation of the surface structure.
Step four: and forming an N + buffer layer and a P + + collector region positioned below the N + buffer layer on the back surface of the substrate in an ion implantation mode, and forming a bottom collector positioned below the P + + collector region through a metallization process.
According to the IGBT structure formed by the invention, the P + emitter region is placed in the third dimension direction perpendicular to the plane, the super-junction structure is formed in the third dimension direction of the drift region, the super-junction P-type upright post is used for extracting hole current to directly enter the P + emitter region, the channel region conductance modulation is weakened, the bias induced barrier lowering (CIBL) effect of an IGBT collector electrode is further inhibited, and the short circuit working capacity of a device is improved. In addition, the transverse electric field in the super junction drift region enhances the carrier extraction effect in the turn-off process, improves the turn-off speed of the device and reduces the turn-off power consumption.
The components of several embodiments are discussed above so that those skilled in the art may better understand the various aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (13)
1. An insulated gate bipolar transistor structure, comprising:
a collector structure comprising a bottom collector, a P + + collector region above the bottom collector, and an N + buffer layer above the P + + collector region;
the drift region is positioned above the N + buffer layer, a super junction structure is arranged in the drift region, and the super junction structure is a plurality of first doping upright columns and a plurality of second doping upright columns which are sequentially and alternately arranged along a third dimension z direction;
a surface structure located over the drift region, wherein the surface structure includes a P base region, a floating P base region, a trench gate and P + and N + emitter regions disposed in the P base region, and a top emitter disposed over the floating P base region, the trench gate and the P + and N + emitter regions, wherein the P + emitter regions alternate with the N + emitter regions in the third z-direction perpendicular to the plane.
2. The igbt structure of claim 1, wherein the first doped column is a P-type column and the second doped column is an N-type column.
3. The igbt structure according to claim 1 and claim 2, wherein each of the N-type pillars in the drift region corresponds to one of the N + emitter regions, and each of the P-type pillars corresponds to one of the P + emitter regions.
4. The igbt structure according to claim 1, further comprising:
the isolation dielectric layer is arranged below the top emitter;
and the gate dielectric surrounds the trench gate.
5. The igbt structure according to claim 1, wherein the N + emitter region, the P base region, and the N-type pillar constitute an input NMOS structure.
6. A method of making an insulated gate bipolar transistor structure, comprising:
preparing a substrate;
forming a drift region on the front surface of the substrate, wherein the drift region is provided with a super junction structure, and the super junction structure is formed by a plurality of first doping upright columns and a plurality of second doping upright columns which are sequentially and alternately arranged along a third dimension z direction;
forming a surface structure over the drift region, the surface structure including a P base region, a floating P base region, a trench gate and P + and N + emitter regions disposed in the P base region, and a top emitter disposed over the floating P base region, the trench gate and the P + and N + emitter regions, wherein the P + emitter regions alternate with the N + emitter regions in the third z-direction perpendicular to the plane;
forming an N + buffer layer and a P + + collector region below the N + buffer layer on the back surface of the substrate in an ion implantation mode, and forming a bottom collector below the P + + collector region through a metallization process.
7. The method of claim 6, wherein the first doped column is a P-type column and the second doped column is an N-type column.
8. The method according to claim 6 or 7, wherein each of the N-type pillars in the drift region corresponds to one of the N + emitter regions, and each of the P-type pillars corresponds to one of the P + emitter regions.
9. The method of manufacturing an igbt structure according to claim 6, further comprising:
forming an isolation dielectric layer below the top emitter;
and forming a gate dielectric surrounding the trench gate.
10. The method for manufacturing the IGBT structure according to claim 6, wherein a zone-melting monocrystalline silicon is selected as the substrate material.
11. The method of claim 6, wherein the drift region is formed by multiple epitaxial ion implantation or trench etching and epitaxial filling.
12. The method of claim 6, wherein the surface structure is formed by a trench process.
13. The method for manufacturing the igbt structure according to any one of claims 6 to 12, wherein the fabricating the surface structure further includes:
performing epitaxy and ion implantation on the drift region to form the P base region;
etching the P base region by the groove to form a longitudinal strip-shaped groove, then carrying out gate oxidation to form the gate medium, and then filling a groove electrode to form the groove gate;
depositing the isolation medium layer above the trench gate and part of the P base region, and then performing ion implantation by using a mask plate to form the P + emitter regions and the N + emitter regions which are longitudinally and alternately arranged on two sides;
and depositing a metal layer on the surface to form the top emitter, and finishing the preparation of the surface structure.
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