CN112928155A - Groove gate super junction IGBT of floating p column - Google Patents
Groove gate super junction IGBT of floating p column Download PDFInfo
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Abstract
The invention provides a super-junction IGBT (Insulated Gate Bipolar Transistor), wherein a second conductive type semiconductor region in a voltage-resisting layer is floating, the bottom of a groove-shaped grid structure is surrounded by a heavily doped second conductive type semiconductor region, the super-junction IGBT has low conduction voltage drop, and the heavily doped second conductive type semiconductor region at the bottom of the groove-shaped grid structure can obviously reduce impact ionization when holes flow through the bottom of the groove-shaped grid structure, so that the reduction of breakdown voltage is avoided.
Description
Technical Field
The invention belongs to a semiconductor device, in particular to a power semiconductor device.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a medium-high voltage power semiconductor switching device. Because a large number of non-equilibrium carriers need to be stored in the body to realize the conductance modulation of the voltage-resisting layer (high-resistance region) during conduction, the turn-off speed of the IGBT is slower than that of a unipolar power semiconductor device. Therefore, the IGBT has a contradictory relationship between on-voltage drop and off-power consumption. A Super Junction (SJ) is a voltage-resistant structure in which n columns and p columns are alternately arranged, and it enables the n columns and the p columns to obtain a higher breakdown voltage even at a higher doping concentration, and is generally applied to a unipolar power semiconductor device. In fact, the super junction can also be applied to the IGBT, and the IGBT is helped to improve the contradiction relation between the on-state voltage drop and the off-state power consumption. When the IGBT adopts a super-junction voltage-resistant structure, a pn junction formed by the n column/p column can be quickly depleted in the turn-off process, and the turn-off speed is increased (or the turn-off power consumption is reduced). However, in the ordinary super junction IGBT, the conductivity modulation effect (or carrier storage effect) of the n-pillar and the p-pillar in the on-state is poor, mainly because the p-pillar easily collects holes and rapidly extracts the collected holes to the emitter, which makes it difficult to effectively store the holes in the n-pillar and the p-pillar, and increases the on-state voltage drop. If the p column floats, the holes enter the p column and then flow to the emitter electrode difficultly in the conduction state, the potential of the p column is raised, the p column is restrained from collecting the holes, the conductivity modulation effect of the n column and the p column is enhanced, and the conduction voltage drop is reduced. However, the breakdown voltage of the super junction IGBT structure of the ordinary floating p-pillar may be reduced.
Disclosure of Invention
Compared with the common super-junction IGBT, the super-junction IGBT device provided by the invention can enhance the storage effect of minority carriers in a body, reduce the conduction voltage drop and simultaneously not reduce the breakdown voltage.
Referring to fig. 3 to 6, the present invention provides a super junction insulated gate bipolar transistor device, wherein a cell structure of the super junction insulated gate bipolar transistor device includes: the transistor comprises a collector structure (composed of 10 and 20), a voltage-withstanding layer (composed of 31 and 32) positioned on the collector structure, a base region (composed of 41 and 43) of a second conductive type and a well region 42 of the second conductive type positioned on the voltage-withstanding layer, a heavily doped emitter region 44 of the first conductive type in contact with at least part of the base region, and a groove-shaped gate structure (composed of 47 and 49) which is in contact with the emitter region 44, the base region (composed of 41 and 43) and the voltage-withstanding layer (composed of 31 and 32) and is used for controlling a switch, and is characterized in that:
the current collection structure (composed of 10 and 20) is composed of a collector region 10 of a second conductivity type and a buffer region 20 of a first conductivity type, wherein the lower surface of the buffer region 20 is in contact with the upper surface of the collector region 10; the lower surface of the collector region 10 is covered with a collector conductor 1 and is connected to a collector C through a lead;
the voltage-resistant layer (composed of 31 and 32) is composed of a first conductivity type semiconductor region 31 and a second conductivity type semiconductor region 32 which are alternately arranged, and the side surface of the first conductivity type semiconductor region 31 in the super-junction voltage-resistant layer and the side surface of the second conductivity type semiconductor region 32 in the super-junction voltage-resistant layer are in contact with each other; the voltage-resistant layer (made up of 31 and 32) is in direct contact with the buffer region 20 or in indirect contact through an auxiliary layer 30 of the first conductivity type;
the lower surface of the base region (composed of 41 and 43) is in contact with the first conductive type semiconductor region 31 in the voltage-proof layer through a first conductive type carrier storage layer 33; the upper surface of the base region (composed of 41 and 43) is at least partially covered with an emitter conductor 2 and is connected to an emitter E through a lead; at least one heavily doped region 43 of the base region (consisting of 41 and 43) is in direct contact with the emitter conductor 2 so as to form an ohmic contact;
the upper surface of the emitter region 44 is covered with an emitter conductor 2 and connected to the emitter E by a wire;
the lower surface of the well region 42 is in direct contact with the second conductivity type semiconductor region 32 in the voltage-resistant layer; the well region 42 and the base region (composed of 41 and 43) are isolated from each other through a first type of emitter-connected trench gate structure (composed of 46 and 48) and/or the trench gate structure (composed of 47 and 49) for controlling the switch;
the trench gate structure (consisting of 47 and 49) for controlling the switch comprises a first insulating dielectric layer 49 and a first conductor region 47 surrounded by the first insulating dielectric layer; the first insulating medium layer 49 is in direct contact with the emitter region 44, the base region (formed by 41 and 43), the carrier storage layer 33, and the first conductivity type semiconductor region 31 in the voltage-withstanding layer, or in direct contact with the emitter region 44, the base region (formed by 41 and 43), the well region 42, the carrier storage layer 33, the first conductivity type semiconductor region 31 in the voltage-withstanding layer, and the second conductivity type semiconductor region 32 in the voltage-withstanding layer; the upper surface of the first conductor region 47 is covered with a gate conductor 3 and is connected to the gate G through a wire;
the first emitter-connected trench gate structure (made up of 46 and 48) includes a second insulating dielectric layer 48 and a second conductor region 46 surrounded by the second insulating dielectric layer; the second insulating medium layer 48 is in direct contact with the base region (composed of 41 and 43), the well region 42, the carrier storage layer 33, the first conductivity type semiconductor region 31 in the voltage-resistant layer, and the second conductivity type semiconductor region 32 in the voltage-resistant layer; the upper surface of the second conductor region 46 is covered with an emitter conductor 2 and is connected to the emitter E through a wire;
the bottom of the groove-shaped gate structure (composed of 47 and 49) for controlling the switch and the bottom of the first emitter-connected groove-shaped gate structure (composed of 46 and 48) are respectively surrounded by the heavily doped semiconductor region 35 of the second conductivity type; the heavily doped semiconductor region 35 of the second conductivity type is in direct contact with the voltage-resistant layer (made up of 31 and 32);
the first and second conductor regions 47, 46 are comprised of heavily doped polycrystalline semiconductor material; when the first conduction type is n type, the second conduction type is p type; when the first conductivity type is p-type, the second conductivity type is n-type.
Referring to fig. 7-9, a trench gate structure (composed of 50 and 51) of the second type for connecting the emitter is included above the semiconductor region 31 of the first conductivity type in the voltage-resistant layer and/or the semiconductor region 32 of the second conductivity type in the voltage-resistant layer; the second type of emitter-connected trench gate structure includes a third insulating medium layer 51 and a third conductor region 50 surrounded by the third insulating medium layer, the third insulating medium layer 51 is in direct contact with the base region (composed of 41 and 43), the carrier storage layer 33 and the first conductivity type semiconductor region 31 in the voltage-withstanding layer, or in direct contact with the well region 42 and the second conductivity type semiconductor region 32 in the voltage-withstanding layer, and the upper surface of the third conductor region 50 is covered with an emitter conductor 2 and is connected to the emitter E through a wire; the bottom of the second emitter-connected trench gate structure (made of 50 and 51) is also surrounded by the heavily doped semiconductor region 35 of the second conductivity type.
Referring to fig. 10, the doping concentration of the well region 42 is higher than the doping concentration of the second-conductivity-type semiconductor region 32 in the voltage-resistant layer, or equal to or equivalent to the doping concentration of the second-conductivity-type semiconductor region 32 in the voltage-resistant layer.
Referring to fig. 11, the doping concentration of the carrier storage layer 33 is higher than the doping concentration of the first-conductivity-type semiconductor region 31 in the voltage-resistant layer, or equal to or comparable to the doping concentration of the first-conductivity-type semiconductor region 31 in the voltage-resistant layer.
Referring to fig. 12 to 13, the doping concentration of the auxiliary layer 30 is lower than the doping concentration of the first-conductivity-type semiconductor region 31 in the voltage-withstanding layer, or equal to or equivalent to the doping concentrations of the first-conductivity-type semiconductor region 31 and the carrier storage layer 33 in the voltage-withstanding layer.
Referring to fig. 14 to 16, the doping concentration of the buffer region 20 is higher than the doping concentration of the auxiliary layer 30, or equal to or equivalent to the doping concentrations of the auxiliary layer 30 and the first-conductivity-type semiconductor region 31 in the voltage-withstanding layer, or equal to or equivalent to the doping concentrations of the auxiliary layer 30, the first-conductivity-type semiconductor region 31 in the voltage-withstanding layer, and the carrier storage layer 33.
Drawings
FIG. 1(a) is a schematic diagram of a common super junction IGBT structure;
FIG. 1(b) is a schematic diagram of a common semi-super junction IGBT structure;
FIG. 2(a) is a schematic diagram of a super junction IGBT structure of a common floating p column;
FIG. 2(b) is a schematic diagram of a semi-super junction IGBT structure of a common floating p column;
FIG. 3 shows a super junction IGBT, wherein a p-type well region is arranged above a p column, the p-type well region is isolated from a p-type base region through a first trench gate structure connected with an emitter, and the bottom of the trench gate structure is p-type+A zone enclosure;
FIG. 4 shows a semi-super-junction IGBT of the present invention, in which a p-type well region is disposed above a p-pillar, and the p-type well region is connected to an emitter via a first trenchThe grid structure is isolated from the p-type base region, and the bottom of the groove-shaped grid structure is p+A zone enclosure;
FIG. 5 shows another semi-super-junction IGBT of the present invention, in which a p-type well region is disposed above the p-pillar, the p-type well region is isolated from the p-type base region by a trench gate structure of a control switch, and the bottom of the trench gate structure is p-type+A zone enclosure;
FIG. 6 shows another semi-super-junction IGBT of the present invention, in which a p-type well region is disposed above the p-pillar, the p-type well region is isolated from the p-type base region by a trench gate structure of a control switch and a first trench gate structure connected to an emitter, and the bottom of the trench gate structure is p-type+A zone enclosure;
FIG. 7 shows a further semi-super junction IGBT according to the invention with a second emitter-connected trench gate structure above the p-pillar according to FIG. 4;
FIG. 8 shows a further semi-super junction IGBT according to the invention with a second emitter-connected trench gate structure above the p-pillar according to FIG. 5;
FIG. 9 shows a further semi-super junction IGBT according to the invention with a second emitter-connected trench gate structure above both the p-pillar and the n-pillar according to FIG. 5;
FIG. 10 shows a further semi-superjunction IGBT according to FIG. 4, with the p-well region and p-pillar doped to the same concentration, with the p-well region forming part of the p-pillar;
FIG. 11 is a view showing still another semi-super junction IGBT according to FIG. 4, in which the n-type carrier storage layer is formed as a part of the n-column, and the doping concentration of the n-type carrier storage layer is the same as that of the n-column;
FIG. 12 shows a semi-super junction IGBT according to the invention, wherein the doping concentration of the n-type auxiliary layer and the n-column are the same according to FIG. 4;
FIG. 13 shows a semi-super junction IGBT according to the invention, wherein the doping concentrations of the n-type auxiliary layer, the n-column and the n-type carrier storage layer are the same according to FIG. 4;
FIG. 14 shows a further semi-superjunction IGBT according to FIG. 4, with the n-type buffer region and the n-type auxiliary layer doped at the same concentration, with the n-type buffer layer forming part of the n-type auxiliary layer;
FIG. 15 shows a semi-super junction IGBT according to the invention, wherein the doping concentrations of the n-type buffer region, the n-type auxiliary layer and the n-column are the same according to FIG. 4;
FIG. 16 shows a semi-super junction IGBT according to the invention, wherein the doping concentrations of the n-type buffer region, the n-type auxiliary layer, the n-type carrier storage layer and the n-column are the same according to FIG. 4;
FIG. 17 forward conduction of the three half super junction IGBTs of FIG. 4, FIG. 2(b) and FIG. 1(b)I-VA curve;
FIG. 18 forward breakdown of three half super junction IGBTs of FIGS. 4, 2(b) and 1(b)I-VCurve line.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1(a) is a schematic diagram of a common super junction IGBT structure, and fig. 1(b) is a schematic diagram of a common semi-super junction IGBT structure. Compared with the super-junction IGBT, the semi-super-junction IGBT has one more n-type auxiliary layer (n-assist layer 30) for bearing partial applied voltage between the n column (n-pillar region 31) and the p column (p-pillar region 32) and the n-type buffer region (n-buffer region 20), wherein the doping concentration of the n-type auxiliary layer (n-assist layer 30) can be lower than or equal to that of the n region (n-pillar region 31). When a voltage exceeding the threshold voltage is applied to the gate (G), the base region (formed by p-base region 41 and p)+Region 43) forms an electron channel near the interface with the trench gate structure (comprised of 47 and 49) used to control the switch; if a positive voltage exceeding 0.7V is applied to the collector (C), electrons pass from the emitter (E) through the emitter region (n) under the influence of the electric field+Region 44) and electron channels into the n-pillar (n-pillar region 31), n-type assist layer (n-assist layer 30), n-type buffer region (n-buffer region 20), and then injected into the collector region (p-collector region 10); then, holes enter the collector region (p-collector region 10) from the collector (C), and are injected into the n-type buffer region (n-buffer region 20), the n-type assist layer (n-assist layer 30), and the n-column (n-pilar region 31), so that the device is turned on. Since the pn junction formed by the p-pillar (p-pillar region 32), the n-pillar (n-pillar region 31) and the n-type auxiliary layer (n-assist layer 30) is reverse biased, holes are easily collected by the p-pillar (p-pillar region 32) and enter the base region (formed by the p-base region 41 and the p-base region 30)+Region 43) and thus current carrying in vivoThe sub-memory effect (conductance modulation effect) is weak and the turn-on voltage is high.
Fig. 2(a) is a schematic diagram of a super junction IGBT structure of a common floating p column, and fig. 2(b) is a schematic diagram of a semi-super junction IGBT structure of a common floating p column. In FIG. 2, over the p-pillar (p-pilar region 32) is a p-well region (p-w region 42), and the p-well region (p-w region 42) is not connected to an electrode. The p-type well region (p-w region 42) is connected with the base region (composed of p-base region 41 and p-base region) through a first emitter-connected trench gate structure (composed of 46 and 48)+Region 43) is formed, the p-type well region (p-w region 42) is a floating region. Because the p-type well region (p-w region 42) has no hole passage flowing to the emitter E, in the forward conduction state, holes are accumulated in the p column (p-pilar region 32) after entering the p column (p-pilar region 32), the potential of the p column (p-pilar region 32) is increased, the p column/n column junction becomes a forward biased junction, the concentration of non-equilibrium carriers near the p column/n column junction is higher, the in-vivo conductivity modulation effect is enhanced, and the conduction voltage drop is reduced.
In fig. 2, an n-type carrier storage layer (n-cs layer 33) is used. Although there is no hole path due to the p-type well region (p-w region 42), if there is no n-type carrier storage layer (n-cs layer 33), the holes of the n-pillar (n-pilar region 31) can flow to the base region (formed by p-base region 41 and p-base region 41) more smoothly+Region 43) so that the conductivity modulation effect in the top region of the n-pillar (n-pilar region 31) is weak, which increases the on-state voltage drop to some extent. When an n-type carrier storage layer (n-cs layer 33) with the doping concentration higher than that of the n column (n-pilar region 31) is introduced, the n-type carrier storage layer (n-cs layer 33) can inhibit holes from entering the base region (formed by the p-base region 41 and the p column region 31)+Region 43) to enhance the conductivity modulation effect in the top region of the n-pillar (n-pilar region 31) to further reduce the turn-on voltage drop.
Although the super junction IGBT of the ordinary floating p-pillar and the half super junction IGBT of the ordinary floating p-pillar shown in fig. 2 can reduce the turn-on voltage drop, the breakdown voltage thereof is lower than that of the ordinary super junction IGBT and the ordinary half super junction IGBT shown in fig. 1. In the forward blocking state, the bottom of the p-pillar (p-pilar region 32), the n-pillar (n-p)The ill-bar region 31) top and the side interface of the p-pillar (p-pillar region 32)/n-pillar (n-pillar region 31) are subjected to high electric fields. The holes generated by impact ionization caused by high electric field at the top of the n column (n-pilar region 31) flow into the base region (formed by p-base region 41 and p-base region+Region 43) while electrons generated by impact ionization flow toward collector C, which does not significantly affect the breakdown voltage. However, holes generated by impact ionization caused by high electric fields at the bottom of the p-pillar (p-pillar region 32) and at the side of the p-pillar (p-pillar region 32) flow upward through the p-pillar (p-pillar region 32). Since the p-well region (p-w region 42) does not provide a hole path, the holes generated by these impact ionization must flow into the p-base region (formed by p-base region 41 and p-base region) through the bottom of the first emitter-connected trench gate structure (formed by 46 and 48) that isolates the p-well region from the p-base region+Zone 43). The high electric field exists at the bottom of the first emitter-connected trench gate structure (composed of 46 and 48), and when holes flow through the bottom of the first emitter-connected trench gate structure (composed of 46 and 48), the holes generated by impact ionization are increased again, the impact ionization effect is increased, and the breakdown voltage is reduced remarkably because the p column (p-pilar region 32) is floated.
The main purpose of the invention is to improve the defect of low breakdown voltage of the super-junction IGBT of the common floating p column and the semi-super-junction IGBT of the common floating p column shown in fig. 2, and simultaneously keep the advantage of low conduction voltage drop.
FIG. 3 is a schematic diagram of a super junction IGBT structure with floating p-pillar according to the invention, wherein the bottom of the trench type gate structure (composed of 47 and 49) for controlling the switch and the bottom of the first emitter-connected trench type gate structure (composed of 46 and 48) are respectively heavily doped with a p-type region (p)+Region 35). In the blocking state, a heavily doped p-type region (p)+Region 35) is substantially not depleted, so the electric field at the bottom of the trenched gate structure (comprised of 47 and 49) for controlling the switch and the first emitter-connected trenched gate structure (comprised of 46 and 48) is relatively low and the high electric field is shifted to the heavily doped p-type region (p)+Region 35) and a voltage-withstanding layer (composed of an n-pilar region 31 and a p-pilar region 32)On the contact surface of the contact element. Thus, holes generated by impact ionization at the bottom of the p-pillar (p-pillar region 32) and at the side of the p-pillar (p-pillar region 32) do not undergo impact ionization again while flowing through the bottom of the first emitter-connected trench gate structure (composed of 46 and 48) and/or the trench gate structure (composed of 47 and 49) for controlling the switch, and the breakdown voltage of the device is not affected by the floating of the p-pillar (p-pillar region 32).
In FIG. 4, the main difference from the structure of FIG. 3 is that there is an n-type auxiliary layer (n-assist layer 30) between the n-type buffer region (n-buffer region 20) and the voltage-withstanding layer (composed of n-pilar region 31 and p-pilar region 32). The doping concentration of the n-type auxiliary layer (n-assit layer 30) and the n-pillar (n-pillar region 31) may be the same or comparable, or even much lower than the doping concentration of the n-pillar (n-pillar region 31).
In FIG. 5, the main difference from the structure of FIG. 4 is that the p-well region (p-w region 42) is separated from the base region (p-base region 41 and p) by a trench gate structure (consisting of 47 and 49) for controlling the switch+Region 43) is formed.
In fig. 6, the main difference from the structure of fig. 5 is that the p-well region (p-w region 42) is connected to the base region (p-base region 41 and p-base region) via the trench gate structure (consisting of 47 and 49) for controlling the switches and the first emitter-connected trench gate structure (consisting of 46 and 48)+Region 43) is formed.
In fig. 7, the main difference from the structure of fig. 4 is that there is also a second emitter-connected trench gate structure (consisting of 50 and 51) over the p-pillar (p-pilar region 32). When the density of the groove type grid structure is increased, the heavily doped p type region (p) at the bottom of the groove type grid structure is relieved+Region 35) of the field.
In fig. 8, the main difference from the structure of fig. 5 is that there is also a second emitter-connected trench gate structure (consisting of 50 and 51) over the p-pillar (p-pilar region 32).
In fig. 9, the main difference from the structure of fig. 5 is that there is a second emitter-connected trench gate structure (consisting of 50 and 51) over both the p-pillar (p-pilar region 32) and the n-pillar (n-pilar region 31).
The main difference between the structure of fig. 10 and that of fig. 4 is that the p-well region (p-w region 42) and the p-pillar (p-pillar region 32) have the same doping concentration, and the p-well region (p-w region 42) and the p-pillar (p-pillar region 32) become the same region.
The main difference between the structures of fig. 11 and fig. 4 is that the doping concentration of the n-type carrier storage layer (n-cs layer 33) is the same as that of the n-column (n-pilar region 31), and the n-type carrier storage layer (n-cs layer 33) and the n-column (n-pilar region 31) become the same region.
The main difference between the structure of fig. 12 and fig. 4 is that the doping concentration of the n-type assist layer (n-assist layer 30) is the same as that of the n-pillar (n-pillar region 31), and the n-type assist layer (n-assist layer 30) and the n-pillar (n-pillar region 31) become the same region.
The main difference between the structures of fig. 13 and 12 is that the doping concentration of the n-type carrier storage layer (n-cs layer 33) is also the same as the doping concentrations of the n-pillar (n-pilar region 31) and the n-type auxiliary layer (n-assist layer 30). In this case, the n-type carrier storage layer (n-cs layer 33), the n-type assist layer (n-assist layer 30), and the n-pillar (n-pilar region 31) become the same region.
The main difference between the structure of fig. 14 and that of fig. 4 is that the doping concentration of the n-type buffer region (n-buffer region 20) is the same as that of the n-type auxiliary layer (n-assist layer 30), and the n-type buffer region (n-buffer region 20) and the n-type auxiliary layer (n-assist layer 30) become the same region.
The main difference between the structures of fig. 15 and 14 is that the doping concentration of the n-pillar (n-pilar region 31) is also the same as the doping concentrations of the n-type buffer region (n-buffer region 20) and the n-type auxiliary layer (n-assist layer 30). In this case, the n-pillar (n-pillar region 31), the n-type buffer region (n-buffer region 20), and the n-type auxiliary layer (n-assist layer 30) become the same region.
The main difference between the structures of fig. 16 and 14 is that the doping concentration of the n-type carrier storage layer (n-cs layer 33) is also the same as the doping concentrations of the n-pillar (n-pilar region 31), the n-type buffer region (n-buffer region 20), and the n-type auxiliary layer (n-assist layer 30). In this case, the n-type carrier storage layer (n-cs layer 33), the n column (n-pillar region 31), the n-type buffer region (n-buffer region 20), and the n-type auxiliary layer (n-assist layer 30) become the same region.
To illustrate the superiority of the IGBT of the present invention, the half-super-junction IGBT structure of the present invention in fig. 4 is taken as an example to be compared with the simulation calculation of the half-super-junction IGBT of the ordinary half-super-junction IGBT in fig. 1(b) and the half-super-junction IGBT of the ordinary floating p-pillar in fig. 2 (b). The 3 kinds of IGBTs are all made of Si materials, a symmetrical super-junction structure is adopted, minority carrier lifetime and minority carrier lifetime of electrons and holes are both 5 mu s, the width of a half cell is 6 mu m, and SiO is adopted as insulating medium layers (48 and 49)2The thickness of the film is 0.1 μm, and the thickness and doping concentration of the n-pillar (n-pillar region 31) and the p-pillar (p-pillar region 32)N pillarRespectively 70 μm and 3X 1015 cm-3The thickness and doping concentration of the n-type assist layer (n-assist layer 30) were 20 μm and 5 × 10, respectively13 cm-3The n-type buffer region (n-buffer region 20) has a thickness of 2 μm and a doping concentration of 5X 10 at the peak, respectively16 cm-3The peak values of the thickness and the doping concentration of the collector region (p-collector region 10) are 1 μm and 3 × 10, respectively18 cm-3The thickness of the n-type carrier storage layer (n-cs layer 33) was 1.5 μm, and the doping concentration of the n-type carrier storage layer (n-cs layer 33)N csAdopt 3X 1016 cm-3With a uniformly doped p-type well region (p-w region 42) and p-type base region (p-base region 41 and p)+Region 43) are each 1.5 μm thick, and the peak doping concentration of the p-type well region (p-w region 42) is 2.5 × 1017 cm-3The peak doping concentration of the p-base region 41 in the p-type base region is 2.5 × 1017 cm-3。
Fig. 17 is the forward conduction of the three types of half super junction IGBTs shown in fig. 4, 2(b), and 1(b)I-VCurve of the grid voltageV G= 15V. Forward conduction of the fig. 4 structure of the present inventionI-VForward conduction of the curve with the structure of FIG. 2(b)I-VThe curves almost coincide, and the conduction voltage drop of both are significantly lower than that of the ordinary half super junction IGBT shown in fig. 1 (b). At 100A/cm2At on current density ofThe turn-on voltage for the fig. 4 structure and the fig. 2(b) structure is only about 1V, whereas the turn-on voltage for the fig. 1(b) structure reaches 2V.
Fig. 18 is the forward breakdown of the three types of half super junction IGBTs shown in fig. 4, 2(b), and 1(b)I-VCurve of the grid voltageV G= 0V. Forward breakdown of the fig. 4 structure of the present inventionI-VForward breakdown of the curve with the structure of FIG. 1(b)I-VThe curves almost coincide and the breakdown voltage of both is significantly higher than that of the half super junction IGBT with the ordinary floating p-pillar shown in fig. 2 (b). The breakdown voltage for the structure of fig. 4 and the structure of fig. 1(b) is about 1400V, while the breakdown voltage for the structure of fig. 2(b) is only about 1130V.
In the above description of many embodiments of the present invention, the n-type semiconductor material can be regarded as a first conductive type semiconductor material, and the p-type semiconductor material can be regarded as a second conductive type semiconductor material. Obviously, according to the principle of the present invention, the n-type and the p-type in the embodiments can be interchanged without affecting the content of the present invention. It is obvious to a person skilled in the art that many other embodiments are possible within the inventive idea without going beyond the claims of the invention.
Claims (6)
1. A super junction insulated gate bipolar transistor device, the cellular structure of which comprises: the collector structure, be located voltage-withstanding layer on the collector structure, be located second conductivity type's base region and second conductivity type's well region on the voltage-withstanding layer, with the heavily doped first conductivity type's emitter region that the base region has at least partial contact, with the emitter region, the base region and the equal contact of voltage-withstanding layer is used for control switch's cell type grid structure, its characterized in that:
the current collection structure is composed of a collector region of a second conduction type and a buffer region of a first conduction type, and the lower surface of the buffer region is in contact with the upper surface of the collector region; the lower surface of the collector region is covered with a collector conductor and is connected to a collector through a lead;
the voltage-resistant layer is composed of semiconductor regions of a first conductivity type and semiconductor regions of a second conductivity type which are alternately arranged, and the side surface of the semiconductor region of the first conductivity type in the super-junction voltage-resistant layer is contacted with the side surface of the semiconductor region of the second conductivity type in the super-junction voltage-resistant layer; the voltage-proof layer is in direct contact with the buffer area or in indirect contact with the buffer area through an auxiliary layer of a first conduction type;
the lower surface of the base region is in contact with the first-conductivity-type semiconductor region in the voltage-resisting layer through a first-conductivity-type carrier storage layer; at least part of the upper surface of the base region is covered with an emitter conductor and is connected to the emitter through a lead; at least one heavily doped region in the base region is in direct contact with the emitter conductor so as to form ohmic contact;
the upper surface of the emitting region is covered with an emitter conductor and is connected to the emitter through a lead;
the lower surface of the well region is in direct contact with the second-conductivity-type semiconductor region in the voltage-resisting layer; the well region and the base region are mutually isolated through a first groove-shaped grid structure connected with an emitter and/or the groove-shaped grid structure used for controlling a switch;
the groove-shaped grid structure for controlling the switch comprises a first insulating medium layer and a first conductor region surrounded by the first insulating medium layer; the first insulating medium layer is in direct contact with the first conductive type semiconductor regions in the emitter region, the base region, the carrier storage layer and the voltage-resisting layer, or is in direct contact with the first conductive type semiconductor regions in the emitter region, the base region, the well region, the carrier storage layer, the voltage-resisting layer and the second conductive type semiconductor regions in the voltage-resisting layer; the upper surface of the first conductor region is covered with a grid conductor and is connected to the grid through a lead;
the first emitter-connected groove-shaped gate structure comprises a second insulating medium layer and a second conductor region surrounded by the second insulating medium layer; the second insulating medium layer is in direct contact with the base region, the well region, the carrier storage layer, the first conductive semiconductor region in the voltage-resisting layer and the second conductive semiconductor region in the voltage-resisting layer; an emitter conductor covers the upper surface of the second conductor region and is connected to the emitter through a lead;
the bottom of the groove-shaped grid structure for controlling the switch and the bottom of the first groove-shaped grid structure connected with the emitter are respectively surrounded by heavily doped semiconductor regions of the second conductivity type; the heavily doped semiconductor region of the second conductivity type is in direct contact with the voltage-resisting layer;
the first conductor region and the second conductor region are composed of heavily doped polycrystalline semiconductor material; when the first conduction type is n type, the second conduction type is p type; when the first conductivity type is p-type, the second conductivity type is n-type.
2. The super junction insulated gate bipolar transistor device of claim 1, wherein:
a groove-shaped grid structure connected with an emitter of the second type is arranged above the semiconductor region of the first conductivity type in the voltage-resisting layer and/or the semiconductor region of the second conductivity type in the voltage-resisting layer; the second type of trench gate structure connected with the emitter comprises a third insulating medium layer and a third conductor region surrounded by the third insulating medium layer, the third insulating medium layer is in direct contact with the first conductivity type semiconductor regions in the base region, the carrier storage layer and the voltage-withstanding layer or in direct contact with the second conductivity type semiconductor regions in the well region and the voltage-withstanding layer, and an emitter conductor covers the upper surface of the third conductor region and is connected to the emitter through a wire; the bottom of the second emitter-connected trench gate structure is surrounded by the heavily doped semiconductor region of the second conductivity type.
3. The super junction insulated gate bipolar transistor device of claim 1, wherein:
the doping concentration of the well region is higher than that of the second-conductivity-type semiconductor region in the voltage-resisting layer, or is equal to or equivalent to that of the second-conductivity-type semiconductor region in the voltage-resisting layer.
4. The super junction insulated gate bipolar transistor device of claim 1, wherein:
the doping concentration of the carrier storage layer is higher than that of the first-conductivity-type semiconductor region in the voltage-resisting layer or equal to or equivalent to that of the first-conductivity-type semiconductor region in the voltage-resisting layer.
5. The super junction insulated gate bipolar transistor device of claim 1, wherein:
the doping concentration of the auxiliary layer is lower than that of the first-conductivity-type semiconductor region in the voltage-proof layer, or equal to or equivalent to that of the first-conductivity-type semiconductor region in the voltage-proof layer and that of the carrier storage layer.
6. The super junction insulated gate bipolar transistor device of claim 1, wherein:
the doping concentration of the buffer region is higher than that of the auxiliary layer, or equal to or equivalent to that of the first-conductivity-type semiconductor region in the auxiliary layer and the voltage-withstanding layer, or equal to or equivalent to that of the first-conductivity-type semiconductor region in the auxiliary layer, the first-conductivity-type semiconductor region in the voltage-withstanding layer and the carrier storage layer.
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