CN108198851B - Super-junction IGBT with carrier storage effect - Google Patents

Super-junction IGBT with carrier storage effect Download PDF

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CN108198851B
CN108198851B CN201711445708.8A CN201711445708A CN108198851B CN 108198851 B CN108198851 B CN 108198851B CN 201711445708 A CN201711445708 A CN 201711445708A CN 108198851 B CN108198851 B CN 108198851B
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CN108198851A (en
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黄铭敏
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Sichuan University
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Sichuan University
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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/1004—Base region of bipolar transistors
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

The invention provides a super-junction IGBT (Insulated Gate Bipolar Transistor), wherein a second conductive type Semiconductor region in a voltage-withstanding layer is connected with an emitter through a Bipolar Transistor with an open base, the Bipolar Transistor with the open base and the second conductive type Semiconductor region in the voltage-withstanding layer are isolated from a base region through a groove-shaped Gate structure, the Bipolar Transistor with the open base and the groove-shaped Gate structure also form a MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) with a floating substrate, and an electrode of the groove-shaped Gate structure can be connected with the Gate or the emitter. When conducting in the forward direction, the bipolar transistor with the open base can help to enhance the carrier storage effect in the voltage-resisting area, so that the conducting voltage drop is reduced.

Description

Super-junction IGBT with carrier storage effect
Technical Field
The invention belongs to a semiconductor device, in particular to a power semiconductor device.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a widely used power semiconductor device. The super junction is a voltage-resistant structure with n column regions and p column regions arranged alternately, and can enable the n column regions and the p column regions to obtain higher breakdown voltage under the condition of higher doping concentration. When the super junction is applied to an IGBT (i.e., a super junction IGBT), the pn junction formed by the n-column region/p-column region can be depleted more rapidly during turn-off, and thus the super junction IGBT can attain a faster turn-off speed (or lower turn-off power consumption) as compared with a normal IGBT. However, in an on state, minority holes injected from the p-type collector region to the n-column region are easily collected by the p-column region, enter the p-type base region, and flow into the emitter, so that the storage effect of the minority holes in the voltage-withstanding region (especially the top of the voltage-withstanding region) is weak, which increases the on-state voltage drop (or increases the on-state power consumption).
Disclosure of Invention
Compared with the traditional super-junction IGBT, the super-junction IGBT device provided by the invention has the advantages that the storage effect of minority carriers in a voltage-withstanding region is stronger, and the conduction voltage drop is lower.
The invention provides a super junction insulated gate bipolar transistor device, the cellular structure of which comprises: a voltage-withstanding layer (formed by 31 and 41), a collector structure (formed by 10 and 20) contacted with one surface of the voltage-withstanding layer (formed by 31 and 41), a base region 50 of a second conduction type contacted with the other surface of the voltage-withstanding layer (formed by 31 and 41), an emitter region 51 of a first conduction type heavily doped and contacted with at least part of the base region 50, a gate structure (formed by 53 and 60) contacted with the emitter region 51, the base region 50 and the voltage-withstanding layer (formed by 31 and 41) and used for controlling the on and off of a device, a collector C formed by a conductor 1 covering the collector structure (formed by 10 and 20), an emitter E formed by a conductor 2 covering the emitter region 51 and the base region 50, and a gate G formed by a conductor 3 of the gate structure (formed by 53 and 60) used for controlling the on and off of the device, the method is characterized in that:
the base region 50 covered by the emitter E is at least partially a semiconductor region 52 of the second conductivity type heavily doped so as to form an ohmic contact;
the collector structure (composed of 10 and 20) is composed of at least one collector region 10 of the second conductivity type and at least one buffer region 20 of the first conductivity type, the buffer region 20 is in contact with the voltage-resistant layer (composed of 31 and 41), and the collector region 10 is in direct contact with the collector C;
the voltage-resistant layer (composed of 31 and 41) is composed of at least one first conductivity type semiconductor region 31 and at least one second conductivity type semiconductor region 41, the first conductivity type semiconductor region 31 in the voltage-resistant layer and the second conductivity type semiconductor region 41 in the voltage-resistant layer are in contact with each other, and the contact surface formed by the voltage-resistant layer is vertical or approximately vertical to the buffer region 20 and the base region 50 and/or the gate structure (composed of 53 and 60);
the voltage-resistant layer (composed of 31 and 41) and the buffer region 20 can be in direct contact, or can be in indirect contact through an auxiliary layer 21 of the first conductivity type;
the gate structure (composed of 53 and 60) for controlling the on and off of the device comprises at least one insulating medium layer 60 and at least one conductor region 53, wherein the insulating medium layer 60 is in direct contact with the emitter region 51, the base region 50 and the voltage-resistant layer (composed of 31 and 41); said conductor region 53 being in direct contact with said insulating dielectric layer 60 and being isolated from other semiconductor regions by said insulating dielectric layer 60, said conductor region 53 being in direct contact with said gate G;
the second conductive type semiconductor region 41 in the voltage-resistant layer is not in direct contact with the base region 50, but is isolated from the base region 50 through the gate structure (composed of 53 and 60) for controlling the on and off of the device, or is isolated from the base region 50 through the gate structure (composed of 53 and 60) for controlling the on and off of the device and the trench-type gate structure (composed of 55 and 60) connected with the emitter;
the trench gate structure (composed of 55 and 60) connected with the emitter comprises at least one insulating dielectric layer 60 and at least one conductor region 55, wherein the insulating dielectric layer 60 is in direct contact with the base region 50 and the voltage-resistant layer (composed of 31 and 41), and the insulating dielectric layer 60 and the voltage-resistant layer can be in direct contact with or not in direct contact with the emitter region 51; the conductor region (53 or 55) is in direct contact with the insulating medium layer 60 and is isolated from other semiconductor regions by the insulating medium layer 60, a conductor 2 is covered on the conductor region 55, and the conductor 2 is connected with the emitter E by a lead;
the insulating medium layer 60 is made of insulating medium materials, and the conductor region (53 or 55) in the gate structure is made of heavily doped polycrystalline semiconductor materials or/and metal materials or/and other conductor materials;
the second conductive semiconductor region 41 in the voltage-resistant layer is connected with the emitter E through a bipolar transistor with an open base; the bipolar transistor with the open base is composed of a second conductive type semiconductor region 41, a first conductive type semiconductor region 43 and a heavily doped second conductive type semiconductor region 54 in the voltage-resisting layer; the first conductivity type semiconductor region 43 is in direct contact with both the second conductivity type semiconductor region 41 in the voltage-proof layer and the heavily doped second conductivity type semiconductor region 54, and isolates the second conductivity type semiconductor region 41 in the voltage-proof layer from the heavily doped second conductivity type semiconductor region 54; the bipolar transistor with the open base is isolated from the base region 50 through the gate structure (composed of 53 and 60) for controlling the on and off of the device, or isolated from the base region 50 through the gate structure (composed of 53 and 60) for controlling the on and off of the device and the groove-shaped gate structure (composed of 55 and 60) connected with the emitter; the trench-type gate structure (composed of 55 and 60) for connecting the emitter and the gate structure (composed of 53 and 60) for controlling the on and off of the device are in direct contact with the second-conductivity-type semiconductor region 41, the first-conductivity-type semiconductor region 43 and the heavily-doped second-conductivity-type semiconductor region 54 in the voltage-withstanding layer, so that a metal-insulator-semiconductor field effect transistor structure with a floating substrate 43 is also formed; the heavily doped semiconductor region 54 of the second conductivity type is covered with a conductor 2 to form an ohmic contact, and the conductor 2 is connected with the emitter E through a wire;
the cell shape of the super junction insulated gate bipolar transistor device can be a strip shape, a hexagon shape, a rectangle shape and the like, and the arrangement mode of the first conductivity type semiconductor region 31 and the second conductivity type semiconductor region 41 in the voltage-resistant layer can be a strip shape, a hexagon shape, a circle shape, a rectangle shape and the like;
when the first conduction type is N type, the second conduction type is P type; and when the first conduction type is a P type, the second conduction type is an N type.
Further, the first conductivity type semiconductor region 31 in the voltage-resistant layer may be in direct contact with the base region 50, or may be in contact with the base region through a first conductivity type carrier storage layer 32; the highest doping concentration of the carrier storage layer 32 is higher than the doping concentration of the first conductivity type semiconductor region 31 in the voltage-resistant layer.
Further, the bottom of the gate structure (composed of 53 and 60) for controlling the on and off of the device and the bottom of the emitter-connected trench-type gate structure (composed of 55 and 60) are both surrounded by a heavily doped semiconductor region 42 of the second conductivity type; the heavily doped second-conductivity-type semiconductor region 42 is in direct contact with both the second-conductivity-type semiconductor region 41 in the voltage-resistant layer and the first-conductivity-type semiconductor region 31 in the voltage-resistant layer, and is not in direct contact with the base region 50.
Further, the first conductivity type semiconductor region 31 in the voltage-resistant layer contains at least one lightly doped first conductivity type semiconductor region 33; the lightly doped semiconductor region 33 of the first conductivity type is not in direct contact with the semiconductor region 41 of the second conductivity type in the voltage-resistant layer; the bottom of the lightly doped semiconductor region 33 of the first conductivity type is in direct contact with the buffer region 20 or in direct contact with the auxiliary layer 21 of the first conductivity type; the top of the lightly doped first conductive type semiconductor region 33 may be in direct contact with the base region 50 or the carrier storage layer 32, or may be surrounded by the first conductive type semiconductor region 31 in the voltage-proof layer.
Further, when the first conductivity type is N-type, the total charge of effective donor impurities in the semiconductor region 31 of the first conductivity type in the voltage-withstanding layer and the total charge of effective acceptor impurities in the semiconductor region 41 of the second conductivity type in the voltage-withstanding layer are relatively different by no more than 70%; when the first conductivity type is P-type, the relative difference between the total charge of the effective acceptor impurities in the first conductivity type semiconductor region 31 in the voltage-resisting layer and the total charge of the effective donor impurities in the second conductivity type semiconductor region 41 in the voltage-resisting layer is not more than 70%.
Further, when the first conductivity type is N-type, the total charge of effective donor impurities of the first conductivity type semiconductor region 31 in the voltage-resistant layer and the lightly doped first conductivity type semiconductor region 33 in the voltage-resistant layer and the total charge of effective acceptor impurities of the second conductivity type semiconductor region 41 in the voltage-resistant layer are different by no more than 70% relatively; when the first conductivity type is P-type, the total effective acceptor impurity charges of the first conductivity type semiconductor region 31 in the voltage-resistant layer and the lightly doped first conductivity type semiconductor region 33 in the voltage-resistant layer are different from the total effective donor impurity charges of the second conductivity type semiconductor region 41 in the voltage-resistant layer by no more than 70%.
Further, the semiconductor region 43 of the first conductivity type in the open-base bipolar transistor (composed of 41, 43, and 54) has a suitable effective dopant amount;
the appropriate effective dopant amount may enable the first conductivity type semiconductor region 43 of the bipolar transistor with the open base to punch through to form a second conductivity type carrier path at a device forward conduction voltage in a range of 1 to 20 volts, or enable the substrate-floating metal-insulator-semiconductor field effect transistor (composed of 41, 43, 54, 60 and 55) to conduct to form a second conductivity type carrier path at a device forward conduction voltage in a range of 1 to 20 volts;
when the second conduction type is a P type, the current carrier of the second conduction type is a hole; when the second conduction type is N type, the current carrier of the second conduction type is electron; the effective dopant amount refers to an integral of an effective doping concentration along a vertical direction, that is, an effective doping impurity total number per unit area.
Further, the semiconductor region 43 of the first conductivity type of the open-base bipolar transistor has a suitable effective dopant amount, which is 1 × 1011cm-2To 1 × 1014cm-2In between, the highest doping concentration of the semiconductor region 43 of the first conductivity type of said open-base bipolar transistor is 1 × 1014cm-3To 1 × 1018cm-3Between the ranges.
Drawings
FIG. 1(a) is a schematic diagram of a conventional super junction IGBT structure;
FIG. 1(b) is a schematic diagram of a conventional semi-super junction IGBT structure;
FIG. 2 shows a super-junction IGBT, wherein a p-column region is isolated from a base region p-base by a trench-type gate structure, the p-column region is connected with an emitter E by a pnp tube (or a substrate floating p-MISFET) with an open-circuit base, and the trench-type gate structure is connected with a gate G;
FIG. 3 shows a semi-super-junction IGBT, in which a p-pillar region is isolated from a base region p-base by a trench-type gate structure, the p-pillar region is connected to an emitter E by a pnp transistor (or a substrate-floating p-MISFET) with an open-circuited base, and the trench-type gate structure is connected to a gate G;
FIG. 4(a) shows a super-junction IGBT, in which a p-pillar region is isolated from a base region p-base by a trench-type gate structure, the p-pillar region is connected with an emitter E by a pnp transistor (or a substrate-floating p-MISFET) with an open base, the trench-type gate structure is connected with a gate G, and the trench-type gate structure is connected with the emitter E;
FIG. 4(b) shows another semi-super-junction IGBT, in which the p-pillar region is isolated from the base region p-base by a trench-type gate structure, the p-pillar region is connected to the emitter E by a pnp transistor (or substrate-floating p-MISFET) with open-base, there is a trench-type gate structure connected to the gate G, and there is a trench-type gate structure connected to the emitter E;
fig. 5(a) shows a super junction IGBT according to fig. 2, in which a more heavily doped carrier storage layer n-cs is provided between the n-pillar region and the base region p-base;
FIG. 5(b) shows a further semi-super junction IGBT according to FIG. 3, having a more heavily doped carrier storage layer n-cs between the n-pillar region and the base region p-base;
fig. 6(a) shows a super junction IGBT according to the invention, which has a more heavily doped carrier storage layer n-cs between the n-pillar region and the base region p-base, according to fig. 4 (a);
FIG. 6(b) shows a further semi-super junction IGBT according to the invention, according to FIG. 4(b), with a more heavily doped carrier storage layer n-cs between the n-pillar region and the base region p-base;
FIG. 7(a) shows another super junction IGBT according to the invention, according to FIG. 2, with a p-type trench gate structure at the bottom+A zone;
FIG. 7(b) shows a further semi-super junction IGBT according to the invention according to FIG. 3, having a p-type trench gate structure at the bottom+A zone;
FIG. 8(a) shows another super junction IGBT according to the invention, which has a trench gate structure with a p at the bottom, according to FIG. 4(a)+A zone;
FIG. 8(b) shows another semi-super junction IGBT according to the invention, which has a p-type trench gate structure at the bottom+A zone;
FIG. 9(a) shows another super junction IGBT according to the invention, which has a trench gate structure with a p at the bottom, according to FIG. 5(a)+A zone;
FIG. 9(b) shows another semi-super junction IGBT according to the invention, according to FIG. 5(b), with a p-type gate structure at the bottom+A zone;
FIG. 10(a) shows another super junction IGBT according to the invention, which has a trench gate structure with a p at the bottom, according to FIG. 6(a)+A zone;
FIG. 10(b) shows another semi-super junction IGBT according to the present invention, which has a p-type trench gate structure at the bottom+A zone;
fig. 11(a) shows a super junction IGBT according to fig. 2, wherein a lightly doped n-region is provided in the n-column region, and the top of the n-region is directly contacted with the base region p-base;
FIG. 11(b) shows a further semi-superjunction IGBT according to the invention, according to FIG. 3, having a lightly doped n-region in the n-pillar region, the top of the n-region being in direct contact with the base region p-base;
fig. 12(a) shows a super junction IGBT according to the invention, which has a lightly doped n-region in the n-column region, and the top of the n-region is directly contacted with the base region p-base according to fig. 4 (a);
FIG. 12(b) shows a further semi-super junction IGBT according to the invention, with a lightly doped n-region in the n-pillar region, with the top of the n-region in direct contact with the base region p-base, according to FIG. 4 (b);
fig. 13(a) shows a super junction IGBT according to fig. 2, wherein a lightly doped n-region is provided in the n-pillar region, and the top of the n-region is surrounded by the n-pillar region;
FIG. 13(b) shows a further semi-superjunction IGBT according to FIG. 3, having a lightly doped n-region in the n-pillar region, the top of the n-region being surrounded by the n-pillar region;
fig. 14(a) shows a further super junction IGBT according to the invention having a lightly doped n-region in the n-pillar region, the top of the n-region being surrounded by the n-pillar region, according to fig. 4 (a);
FIG. 14(b) shows a further semi-superjunction IGBT according to the invention, having a lightly doped n-region in the n-pillar region, surrounded on top by the n-pillar region, according to FIG. 4 (b);
fig. 15(a) shows a super junction IGBT according to the invention having a lightly doped n-region in the n-column region, the n-region being surrounded on top by a carrier storage layer n-cs according to fig. 5 (a);
FIG. 15(b) shows a further semi-superjunction IGBT according to the invention, according to FIG. 5(b), having a lightly doped n-region in the n-column region, surrounded on top by a carrier storage layer n-cs;
fig. 16(a) shows a super junction IGBT according to still another embodiment of the present invention, according to fig. 6(a), having a lightly doped n-region in the n-column region, the n-region being surrounded on top by a carrier storage layer n-cs;
FIG. 16(b) shows a further semi-superjunction IGBT according to the invention, having a lightly doped n-region in the n-column region, surrounded on top by a carrier storage layer n-cs according to FIG. 6 (b);
fig. 17I-V curves of the half super junction IGBT of the present invention in fig. 3 and the conventional half super junction IGBT in fig. 1 (b);
fig. 18 shows the carrier concentration distribution in the body of the half-super-junction IGBT of the invention in fig. 3 and the conventional half-super-junction IGBT in fig. 1 (b).
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1(a) shows a schematic diagram of a conventional super junction IGBT structure, and fig. 1(b) shows a schematic diagram of a conventional semi-super junction IGBT structure. Compared with the super-junction IGBT, the semi-super-junction IGBT has an auxiliary layer (n-assist region 21) for bearing part of applied voltage between the n-column region (n-pillar region 31) and the buffer region (n-pillar region 41) and between the buffer region (n-region 20), wherein the doping concentration of the auxiliary layer can be lower than or equal to that of the n-column region (n-pillar region 31). When a gate voltage exceeding a threshold voltage is applied to the gate (G), the surface of the base region (p-base region 50) under the gate dielectric (60) is inverted to form an electron channel that connects the emitter region (n)+Region 51) is in communication with the n-pillar region (n-pilar region 31); if a positive voltage exceeding 0.7V is applied to the collector (C), electrons pass from the emitter (E) through the emitter region (n) under the influence of the electric field+Region 51), the electron channel enters the n column region (n-pilar region 31), and then enters the buffer region (n region 20) and the collector region (p region 10); thus, holes enter the collector region (p region 10) from the collector electrode (C), pass through the buffer region (n region 20), the n-pillar region (n-pillar region 31), and the like,The p-pillar region (p-pilar region 41) eventually enters the emitter (E) and the device turns on. Since the PN junction formed by the p-pillar region (p-pillar region 41) and the n-pillar region (n-pillar region 31) is a reverse biased junction, holes entering the n-pillar region (n-pillar region 31) are easily collected by the p-pillar region (p-pillar region 41), so that the hole concentration in the n-pillar region (n-pillar region 31) is relatively low, the electron concentration at the same position is relatively low, and the voltage drop in this part of the region is relatively high. The main purpose of the present invention is to enhance the storage effect of minority carriers in the p-pillar region (p-pillar region 41) and the n-pillar region (n-pillar region 31), thereby reducing the on-state voltage drop.
The technique of the present invention is applicable to any one of a super-junction and a semi-super-junction IGBT.
In fig. 2, the p-pillar region (p-pilar region 41) is not in direct contact with the base region (p-base region 50), but is isolated from the base region (p-base region 50) by a trench gate structure (consisting of 53 and 60) which is used for both isolation and control on and off, and the emitter (E) is connected to the p-pillar region (p-pilar region 41) by an open-base pnp transistor consisting of the p-pillar region (p-pilar region 41), an n-region (n-region 43) and a heavily doped p-pillar region (p-base region 50)+Region (p)+Region 54) with p-pillar region (p-pilar region 41), n-region (n-region 43), and heavily doped p+Region (p)+Region 53) are in direct contact with the trench gate structure (formed of 53 and 60) and thus also form a p-MISFET (Metal-Insulator-Semiconductor Field Effect Transistor). At a lower forward conduction voltage, both the pnp transistor with open-base and the p-MISFET are in an off state, so that after the hole enters the p-pillar region (p-pillar region 41), the hole does not pass and raises the potential of the p-pillar region (p-pillar region 41), so that the potential of the p-pillar region (p-pillar region 41) is about 0.7V higher than the potential of the base region (p-base region 50). Thus, the PN junction formed by the p-pillar region (p-pillar region 41) and the n-pillar region (n-pillar region 31) becomes a forward bias PN junction, holes running to the vicinity of the p-pillar region (p-pillar region 41) are not easy to be collected, and holes running to the vicinity of the base region (p-base region 50) are collected by the base region (p-base region 50). Thus, holes and electrons are in the p-column region (p-pilar region 41) and nThe storage effect of the column region (n-pilar region 31) is enhanced and the on-state voltage drop is reduced. When the forward conduction voltage continues to increase, the potential of the p-pillar region (p-pilar region 41) also increases, the depletion region of the base region (n region 43) of the pnp transistor with open-base continuously expands toward the p-pillar region (p-pilar region 41), and finally the pnp transistor is penetrated, and a part of holes flow away from the pnp transistor channel.
In FIG. 3, the main difference from the structure of FIG. 2 is that an auxiliary layer (n-assit region 21) is located between the buffer region (n region 20) and the n pillar region (n-pillar region 31) and the p pillar region (p region-pillar 41), and the auxiliary layer (n-assit region 21) can bear a part of the applied voltage. The doping concentration of the auxiliary layer (n-assit region 21) and the n-pillar region (n-pillar region 31) may be the same or different, and may even be much lower than the doping concentration of the n-pillar region (n-pillar region 31). The thickness of the auxiliary layer (n-assit region 21) may be smaller than the thickness of the n-pillar region (n-pillar region 31), may be comparable to the thickness of the n-pillar region (n-pillar region 31), and may be even larger than the thickness of the n-pillar region (n-pillar region 31).
In fig. 4(a), the main difference from the structure of fig. 2 is that the trench gate structure for isolation (consisting of 53 and 60, and consisting of 55 and 60) is not necessarily connected only to the gate (G) but also to the emitter (E). In the on state, as the forward conduction voltage increases, the potential of the p column region (p-pilar region 41) is continuously increased, inversion occurs near the interface of the base region (n region 43) of the pnp transistor with open base and the insulating layer (60) of the trench type gate structure for isolation, the p-MISFET is turned on to provide a hole path, or the pnp transistor with open base is punched to provide a hole path.
In FIG. 4(b), the main difference from the structure of FIG. 4(a) is that there is an auxiliary layer (n-assit region 21) between the buffer region (n region 20) and the n pillar region (n-pillar region 31) and the p pillar region (p-pillar region 41).
In fig. 5(a), the main difference from the structure of fig. 2 is that the base region (p-base region 50) is not in direct contact with the n-pillar region (n-pilar region 31), but is in indirect contact via a carrier storage layer (n-cs layer 32). The carrier storage layer (n-cs layer 32) can suppress the entry of holes into the base region (p-base region 50), thereby further enhancing the carrier storage effect in vivo.
In FIG. 5(b), the main difference from the structure of FIG. 5(a) is that there is an auxiliary layer (n-assit region 21) between the buffer region (n region 20) and the n pillar region (n-pillar region 31) and the p pillar region (p-pillar region 41).
In fig. 6(a), the main difference from the structure of fig. 5(a) is that the trench gate structure for isolation (consisting of 53 and 60, and consisting of 55 and 60) is not necessarily connected only to the gate (G) but also to the emitter (E).
In FIG. 6(b), the main difference from the structure of FIG. 6(a) is that there is an auxiliary layer (n-assit region 21) between the buffer region (n region 20) and the n pillar region (n-pillar region 31) and the p pillar region (p-pillar region 41).
In fig. 7(a), the main difference from the structure of fig. 2 is that the bottom of the trench gate structure (consisting of 53 and 60, and consisting of 55 and 60) is heavily doped with p+And region 42 is surrounded.
In FIG. 7(b), the main difference from the structure of FIG. 7(a) is that there is an auxiliary layer (n-assit region 21) between the buffer region (n region 20) and the n pillar region (n-pillar region 31) and the p pillar region (p-pillar region 41).
In fig. 8(a), the main difference from the structure of fig. 7(a) is that the trench gate structure for isolation (consisting of 53 and 60, and consisting of 55 and 60) is not necessarily connected only to the gate (G) but also to the emitter (E).
In FIG. 8(b), the main difference from the structure of FIG. 8(a) is that there is an auxiliary layer (n-assit region 21) between the buffer region (n region 20) and the n pillar region (n-pillar region 31) and the p pillar region (p-pillar region 41).
In fig. 9(a), the main difference from the structure of fig. 5(a) is that the bottom of the trench gate structure (consisting of 53 and 60, and consisting of 55 and 60) is heavily doped with p+And region 42 is surrounded.
In FIG. 9(b), the main difference from the structure of FIG. 9(a) is that there is an auxiliary layer (n-assit region 21) between the buffer region (n region 20) and the n pillar region (n-pillar region 31) and the p pillar region (p-pillar region 41).
In fig. 10(a), the main difference from the structure of fig. 9(a) is that the trench gate structure for isolation (consisting of 53 and 60, and consisting of 55 and 60) is not necessarily connected only to the gate (G) but also to the emitter (E).
In FIG. 10(b), the main difference from the structure of FIG. 10(a) is that there is an auxiliary layer (n-assit region 21) between the buffer region (n region 20) and the n pillar region (n-pillar region 31) and the p pillar region (p-pillar region 41).
In fig. 11(a), the main difference from the structure of fig. 2 is that there is a lightly doped n-type drift region (n-region 33) in the middle of the n-pillar region (n-pilar region 31). It should be noted that the doping concentration of the n-type drift region (n-region 33) is usually much less than that of the n-column region (n-pilar region 31), and the process of forming the n-column region (n-pilar region 31) in the structure may be a deep trench etching and a deep trench sidewall ion implantation on a substrate material of the lightly doped n-type drift region (n-region 33). The n-pillar region (n-pilar region 31) typically produced by this process has a relatively small width and a relatively high doping concentration.
In fig. 11(b), the main difference from the structure of fig. 11(a) is that there is an auxiliary layer (n-assist region 21) between the voltage-proof layer (composed of n-pillar region 31 and p-pillar region 41) and the lightly doped n-type drift region (n-region 33) and the buffer region (n-region 20), and the bottom of the p-pillar region (p-pillar region 41) is surrounded by the n-pillar region (n-pillar region 31). It should be noted that, in a special case, the doping concentration of the auxiliary layer (n-assit region 21) may be the same as the doping concentration of the lightly doped n-type drift region (n-region 33), and the auxiliary layer (n-assit region 21) is substantially the same as the lightly doped n-type drift region (n-region 33).
In fig. 12(a), the main difference from the structure of fig. 11(a) is that the trench gate structure for isolation (consisting of 53 and 60, and consisting of 55 and 60) is not necessarily connected only to the gate (G) but also to the emitter (E).
In FIG. 12(b), the main difference from the structure of FIG. 12(a) is that there is an auxiliary layer (n-assit region 21) between the buffer region (n region 20) and the n pillar region (n-pillar region 31) and the p pillar region (p-pillar region 41).
In fig. 13(a), the main difference from the structure of fig. 11(a) is that the top of the lightly doped n-type drift region (n-region 33) is surrounded by an n-pillar region (n-pilar region 31).
In FIG. 13(b), the main difference from the structure of FIG. 13(a) is that there is an auxiliary layer (n-assit region 21) between the buffer region (n region 20) and the n pillar region (n-pillar region 31) and the p pillar region (p-pillar region 41).
In fig. 14(a), the main difference from the structure of fig. 13(a) is that the trench gate structures (composed of 53 and 60, and composed of 55 and 60) for isolation are not necessarily all connected to the gate (G) but may be connected to the emitter (E).
In FIG. 14(b), the main difference from the structure of FIG. 14(a) is that there is an auxiliary layer (n-assit region 21) between the buffer region (n region 20) and the n pillar region (n-pillar region 31) and the p pillar region (p-pillar region 41).
In fig. 15(a), the main difference from the structure of fig. 5(a) is that there is a lightly doped n-type drift region (n-region 33) in the middle of the n-pillar region (n-pilar region 31).
In FIG. 15(b), the main difference from the structure of FIG. 15(a) is that there is an auxiliary layer (n-assit region 21) between the buffer region (n region 20) and the n pillar region (n-pillar region 31) and the p pillar region (p-pillar region 41).
In fig. 16(a), the main difference from the structure of fig. 15(a) is that the trench gate structure for isolation (consisting of 53 and 60, and consisting of 55 and 60) is not necessarily connected only to the gate (G) but also to the emitter (E).
In FIG. 16(b), the main difference from the structure of FIG. 16(a) is that there is an auxiliary layer (n-assit region 21) between the buffer region (n region 20) and the n pillar region (n-pillar region 31) and the p pillar region (p-pillar region 41).
To illustrate the superiority of the super junction IGBT of the present invention over the conventional super junction IGBT (fig. 1(a) and 1(b)), the half super junction IGBT structure in fig. 3 is taken as an example here to compare with the conventional half super junction IGBT in fig. 1(b) for numerical simulation calculation. The numerical simulation adopts the MEDICI simulation software. The set-up in the simulation is as follows, the structures of fig. 1(b) and 3 both use Si material, the simulation uses half cells (right part of central symmetry axis of fig. 1(b) and 3), the minority carrier lifetime of electrons and holes is 5 μ s, the width of half cells is 4 μm, the conductor region 53 uses n-poly with thickness of 2.4 μm, the insulating layer 60 uses SiO-poly2The thickness of the substrate is 0.1 μm, and the thickness and doping concentration of the base region (p-base region 50) are 1.5 μm and 3 × 10 respectively17cm-3Emitting region (n)+Region 51) has a width, thickness and doping concentration of 0.75 μm, 0.5 μm and 4 × 10, respectively19cm-3The thickness and doping concentration of the n-pillar region (n-pillar region 31) and the p-pillar region (p-pillar region 41) are 51 μm and 3 × 1015cm-3The thickness and doping concentration profile of the auxiliary layer (n-assist region 21) was 40 μm and 8 × 1013cm-3The buffer region (n-region 20) has a thickness and a doping concentration peak of 2 μm and 5 × 10, respectively16cm-3The peak values of the thickness and the doping concentration of the collector region (p region 10) are 1 μm and 1 × 1018cm-3. The width of the base region (p-base region 50) in fig. 1(b) is 2.5 μm, and the width of the conductor region 53 is 1.4 μm; the base region (p-base region 50) in fig. 3 has a width of 1.75 μm and the conductor region 53 has a width of 1.4 μm. The breakdown voltage of the half super junction IGBT shown in fig. 1(b) and fig. 3 is 1415V through simulation.
Fig. 17 is a forward conduction I-V curve of the half super junction IGBT of the present invention in fig. 3 and the conventional half super junction IGBT in fig. 1(b), both of which apply a gate voltage of 15V. It can be obtained from the figure that the concentration is 100A/cm2Next, the turn-on voltage drop of the IGBT of the present invention in fig. 3(b) is 1.05V, which is about 0.85V lower than the turn-on voltage drop (1.90V) of the conventional half super junction IGBT in fig. 1 (b).
Fig. 18 is a hole concentration and electron concentration distribution along x 0 μm (i.e., central symmetry axis) in the case where the turn-on voltage is 1.2V for the half super junction IGBT of the present invention in fig. 3 and the conventional half super junction IGBT in fig. 1 (b). As can be seen from the figure, the storage effect of carriers in the n-column region (n-pilar region 31) of the half super junction IGBT of the present invention in fig. 3 is significantly stronger than that in the conventional half super junction IGBT in fig. 1(b), which is also the reason why the half super junction IGBT of the present invention in fig. 3 has a lower turn-on voltage drop than the conventional half super junction IGBT in fig. 1 (b).
In the above description of many embodiments of the present invention, the N-type semiconductor material may be regarded as a first conductive type semiconductor material, and the P-type semiconductor material may be regarded as a second conductive type semiconductor material. Obviously, according to the principle of the present invention, the N-type and the P-type in the embodiment can be interchanged without affecting the content of the present invention. It is obvious to a person skilled in the art that many other embodiments are possible within the inventive idea without departing from the claims of the invention.

Claims (10)

1. A super junction insulated gate bipolar transistor device, the cellular structure of which comprises: the device comprises a pressure-resistant layer, a current collection structure contacted with one surface of the pressure-resistant layer, a base region of a second conductive type contacted with the other surface of the pressure-resistant layer, a heavily-doped emitter region of a first conductive type at least partially contacted with the base region, a grid structure which is contacted with the emitter region, the base region and the pressure-resistant layer and used for controlling the conduction and the disconnection of a device, a collector covered on a conductor of the current collection structure, an emitter covered on the emitter region and the conductor of the base region, and a grid covered on a conductor of the grid structure used for controlling the conduction and the disconnection of the device, and is characterized in that:
at least part of the base region covered by the emitter is a heavily doped semiconductor region of the second conductivity type so as to form ohmic contact;
the current collection structure is composed of at least one current collection region of a second conduction type and at least one buffer region of a first conduction type, the buffer region is in contact with the voltage-resisting layer, and the current collection region is in direct contact with the collector;
the voltage-resisting layer is composed of at least one first-conductivity-type semiconductor region and at least one second-conductivity-type semiconductor region, the first-conductivity-type semiconductor region in the voltage-resisting layer is mutually contacted with the second-conductivity-type semiconductor region in the voltage-resisting layer, and a contact surface formed by the first-conductivity-type semiconductor region and the second-conductivity-type semiconductor region is vertical or approximately vertical to the top plane of the buffer region and vertical or approximately vertical to the base region and the bottom plane of the gate structure;
the voltage-resistant layer is in direct contact with the buffer area or is in indirect contact with the buffer area through an auxiliary layer of a first conduction type;
the grid structure for controlling the on and off of the device comprises at least one insulating medium layer and at least one conductor region, wherein the insulating medium layer is directly contacted with the emitter region, the base region and the voltage-resistant layer; the conductor region is in direct contact with the insulating medium layer and is isolated from the emitter region, the base region and the voltage-resistant layer through the insulating medium layer, and the conductor region is in direct contact with the grid electrode;
the semiconductor region of the second conduction type in the pressure-resistant layer is not directly contacted with the base region, but is isolated from the base region through the gate structure for controlling the on and off of the device, or isolated from the base region through the gate structure for controlling the on and off of the device and the groove-shaped gate structure connected with the emitter;
the groove-shaped grid structure connected with the emitter comprises at least one insulating medium layer and at least one conductor region, wherein the insulating medium layer is directly contacted with the base region and the voltage-resistant layer, and is directly contacted with or not directly contacted with the emitter region; the conductor region is directly contacted with the insulating medium layer and is isolated from the base region and the voltage-resistant layer through the insulating medium layer, a conductor covers the conductor region, and the conductor is connected with the emitter through a lead;
the insulating medium layer is made of insulating medium materials, and the conductor region in the grid structure is made of heavily-doped polycrystalline semiconductor materials or/and metal materials;
the second-conductivity-type semiconductor region in the voltage-resisting layer is connected with the emitter through a bipolar transistor with an open-circuit base; the bipolar transistor with the open base is composed of a second conductive type semiconductor region, a first conductive type semiconductor region and a heavily doped second conductive type semiconductor region in the voltage-resisting layer; the semiconductor region of the first conductivity type is in direct contact with the semiconductor region of the second conductivity type in the pressure-resistant layer and the semiconductor region of the heavily doped second conductivity type, and the semiconductor region of the second conductivity type in the pressure-resistant layer is isolated from the semiconductor region of the heavily doped second conductivity type; the bipolar transistor with the open base is isolated from the base region through the grid structure for controlling the on and off of the device, or isolated from the base region through the grid structure for controlling the on and off of the device and the groove-shaped grid structure connected with the emitter; the groove-shaped gate structure connected with the emitter and the gate structure used for controlling the on-off of the device are in direct contact with the second-conductivity-type semiconductor region, the first-conductivity-type semiconductor region and the heavily-doped second-conductivity-type semiconductor region in the voltage-resisting layer, so that a metal-insulator-semiconductor field effect transistor structure with a floating substrate is formed; a conductor is covered on the heavily-doped second conduction type semiconductor region to form ohmic contact, and the conductor is connected with the emitter through a wire;
the cell shape of the super junction insulated gate bipolar transistor device is strip-shaped or hexagonal or rectangular, and the arrangement mode of the first conductivity type semiconductor region and the second conductivity type semiconductor region in the voltage-resisting layer is strip-shaped or hexagonal or circular or rectangular; when the first conduction type is N type, the second conduction type is P type; and when the first conduction type is a P type, the second conduction type is an N type.
2. The super junction insulated gate bipolar transistor device of claim 1, wherein:
the first conductive type semiconductor region in the voltage-proof layer is in direct contact with the base region or is in contact with the base region through a first conductive type carrier storage layer; the highest doping concentration of the carrier storage layer is higher than that of the first-conductivity-type semiconductor region in the voltage-proof layer.
3. The super junction insulated gate bipolar transistor device of claim 1, wherein:
the bottom of the gate structure for controlling the device to be switched on and off and the bottom of the groove-shaped gate structure connected with the emitter are both surrounded by a heavily doped semiconductor region of the second conductivity type; the heavily-doped second-conductivity-type semiconductor region is in direct contact with both the second-conductivity-type semiconductor region in the voltage-resistant layer and the first-conductivity-type semiconductor region in the voltage-resistant layer, and is not in direct contact with the base region.
4. The super junction insulated gate bipolar transistor device of claim 2, wherein:
the bottom of the gate structure for controlling the device to be switched on and off and the bottom of the groove-shaped gate structure connected with the emitter are both surrounded by a heavily doped semiconductor region of the second conductivity type; the heavily-doped second-conductivity-type semiconductor region is in direct contact with both the second-conductivity-type semiconductor region in the voltage-resistant layer and the first-conductivity-type semiconductor region in the voltage-resistant layer, and is not in direct contact with the base region.
5. The super junction insulated gate bipolar transistor device of claim 1, wherein:
the semiconductor region of the first conductivity type in the voltage-resisting layer contains at least one lightly doped semiconductor region of the first conductivity type; the lightly doped semiconductor region of the first conductivity type is not in direct contact with the semiconductor region of the second conductivity type in the voltage-resistant layer; the bottom of the lightly doped semiconductor region of the first conductivity type is in direct contact with the buffer region or in direct contact with the auxiliary layer of the first conductivity type; the top of the lightly doped first conductive type semiconductor region is in direct contact with the base region or is surrounded by the first conductive type semiconductor region in the voltage-proof layer.
6. The super junction insulated gate bipolar transistor device of claim 2, wherein:
the semiconductor region of the first conductivity type in the voltage-resisting layer contains at least one lightly doped semiconductor region of the first conductivity type; the lightly doped semiconductor region of the first conductivity type is not in direct contact with the semiconductor region of the second conductivity type in the voltage-resistant layer; the bottom of the lightly doped semiconductor region of the first conductivity type is in direct contact with the buffer region or in direct contact with the auxiliary layer of the first conductivity type; the top of the lightly doped semiconductor region of the first conductivity type is in direct contact with the carrier storage layer.
7. The super junction insulated gate bipolar transistor device of claim 1, wherein:
when the first conductivity type is N type, the relative difference between the total charge of effective donor impurities in the semiconductor region of the first conductivity type in the voltage-resisting layer and the total charge of effective acceptor impurities in the semiconductor region of the second conductivity type in the voltage-resisting layer is not more than 70%; when the first conduction type is P type, the relative difference between the total charge of effective acceptor impurities in the semiconductor region of the first conduction type in the voltage-resisting layer and the total charge of effective donor impurities in the semiconductor region of the second conduction type in the voltage-resisting layer is not more than 70%.
8. The super junction insulated gate bipolar transistor device of claim 5, wherein:
when the first conductivity type is an N type, the relative difference between the total effective donor impurity charges of the first conductivity type semiconductor region in the voltage-resisting layer and the lightly doped first conductivity type semiconductor region in the voltage-resisting layer and the total effective acceptor impurity charges of the second conductivity type semiconductor region in the voltage-resisting layer is not more than 70%; when the first conductivity type is P-type, the total charge of effective acceptor impurities of the first conductivity type semiconductor region in the voltage-resisting layer and the lightly doped first conductivity type semiconductor region in the voltage-resisting layer is not more than 70% different from the total charge of effective donor impurities of the second conductivity type semiconductor region in the voltage-resisting layer.
9. The super junction insulated gate bipolar transistor device of claim 1, wherein:
a suitable effective dopant amount in a semiconductor region of the first conductivity type of the open base bipolar transistor;
the proper effective doping dosage enables the first conduction type semiconductor region of the bipolar transistor with the open base to punch through in the range of 1 to 20 volts of forward conduction voltage of the device to form a second conduction type carrier path, or enables the substrate-floating metal-insulator-semiconductor field effect transistor to conduct in the range of 1 to 20 volts of forward conduction voltage of the device to form a second conduction type carrier path;
when the second conduction type is a P type, the current carrier of the second conduction type is a hole; when the second conduction type is N type, the current carrier of the second conduction type is electron; the effective dopant amount refers to an integral of an effective doping concentration along a vertical direction, that is, an effective doping impurity total number per unit area.
10. The super junction insulated gate bipolar transistor device of claim 9, wherein:
the bipolar transistor with the open base is provided with a proper effective doping dose in the semiconductor region of the first conduction type, and the proper effective doping dose is 1 × 1011cm-2To 1 × 1014cm-2In the range, the highest doping concentration of the first conduction type semiconductor region of the bipolar transistor with the open base is 1 × 1014cm-3To 1 × 1018cm-3Between the ranges.
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