CN109148572B - Reverse blocking type FS-IGBT - Google Patents
Reverse blocking type FS-IGBT Download PDFInfo
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- CN109148572B CN109148572B CN201810737634.3A CN201810737634A CN109148572B CN 109148572 B CN109148572 B CN 109148572B CN 201810737634 A CN201810737634 A CN 201810737634A CN 109148572 B CN109148572 B CN 109148572B
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- 230000000903 blocking effect Effects 0.000 title claims abstract description 28
- 230000005684 electric field Effects 0.000 claims abstract description 38
- 238000003860 storage Methods 0.000 claims abstract description 33
- 239000004020 conductor Substances 0.000 claims description 98
- 239000004065 semiconductor Substances 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 8
- 230000001413 cellular effect Effects 0.000 claims description 6
- 210000004027 cell Anatomy 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 239000000370 acceptor Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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Abstract
The invention provides a Reverse Blocking type Field Stop Insulated Gate Bipolar Transistor (RB FS-IGBT) device, wherein a carrier storage region and a groove-shaped Gate structure connected with a Gate are arranged at the top of a drift region, and a Field Stop region and a groove-shaped Gate structure connected with a collector are arranged at the bottom of the drift region. In a forward blocking state, the high electric field of the carrier storage region is shielded by the groove-shaped grid structure connected with the grid, and the electric field at the bottom of the drift region is blocked by the field blocking region; in a reverse blocking state, the high electric field of the cut-off region is shielded by the groove-shaped grid structure connected with the collector, and the electric field at the top of the drift region is cut off by the carrier storage region.
Description
Technical Field
The invention belongs to a semiconductor device, in particular to a semiconductor power device.
Background
A Reverse Blocking Insulated Gate Bipolar Transistor (RB-IGBT) is an IGBT having a Reverse Blocking capability. The reverse blocking type insulated gate bipolar transistor (RB-IGBT) can form a bidirectional switch, is applied to a 3-level frequency converter circuit, is favorable for reducing conduction power consumption, and improves the efficiency of an inverter. However, since the reverse blocking withstanding voltage is considered, the general RB-IGBT adopts a Non-Punch Through (NPT) type structure rather than a Field Stop (FS) type structure, which has an adverse effect on both forward conduction voltage drop and turn-off power consumption. In addition, a normal RB-IGBT generally requires one p throughout the entire chip+The region serves as a reverse voltage-resistant terminal structure, which brings about a number of difficulties in the manufacturing process.
Disclosure of Invention
Compared with the common RB-IGBT, the RB-IGBT device provided by the invention has the advantages that the electric Field distribution of forward blocking and reverse blocking is Field Stop (FS) type electric fields, and the terminal structure can bear higher forward blocking voltage and reverse blocking voltage.
The invention provides a reverse blocking type insulated gate bipolar transistor device, wherein a cellular structure of the device comprises: a drift region 21 of a lightly doped first conductivity type, a collector structure (composed of 10 and 20) in contact with a bottom plane of the drift region 21, a base region (composed of 30 and 31) of a second conductivity type in contact with a top plane of the drift region 21, an emitter region 32 of the heavily doped first conductivity type in contact with at least part of the base region (composed of 30 and 31), a trench gate structure (composed of 33 and 34) for controlling a switch in contact with each of the emitter region 32, the base region (composed of 30 and 31) and the drift region 21, a trench gate structure (composed of 11 and 12) for shielding a reverse high electric field in contact with each of the collector structure (composed of 10 and 20) and the drift region 21, a collector C formed of a conductor 1 overlying the collector structure (composed of 10 and 20) and the trench gate structure (composed of 11 and 12) for shielding a reverse high electric field, emitter E formed by conductor 2 overlying said emitter region 32 and said base region (constituted by 30 and 31), and gate G formed by conductor 3 overlying said trenched gate structure (constituted by 33 and 34) for controlling the switches, characterized in that (with reference to fig. 1-2):
the drift region 21 is in indirect contact with the base region (formed from 30 and 31) via a carrier storage region 22 of the first conductivity type, the doping concentration of the carrier storage region 22 being higher than the doping concentration of the drift region 21;
the collector structure (made of 10 and 20) is made of at least one collector region 10 of the second conductivity type and at least one field stop region 20 of the first conductivity type, the bottom plane of the field stop region 20 being in direct contact with the collector region 10 of the second conductivity type, the top plane of the field stop region 20 being in direct contact with the bottom plane of the drift region 21, the collector region 10 being in direct contact with the collector conductor 1;
the trench gate structure (composed of 11 and 12) for shielding the reverse high electric field penetrates into the bottom region of the drift region 21 from the bottom plane of the collector region 10, the trench gate structure (composed of 11 and 12) for shielding the reverse high electric field comprises at least one insulating medium layer 12 and at least one conductor region 11, the insulating medium layer 12 is in direct contact with the collector region 10, the field stop region 20 and the drift region 21, the conductor region 11 is in direct contact with the insulating medium layer 12 and is isolated from other semiconductor regions through the insulating medium layer 12, and the conductor region 11 is in direct contact with the collector conductor 1;
the trench-type gate structure (composed of 33 and 34) for controlling the switch is deep into the top region of the drift region 21 from the top plane of the emitter region 32, the trench-type gate structure (composed of 33 and 34) comprises at least one insulating medium layer 34 and at least one conductor region 33, the insulating medium layer 34 is in direct contact with the emitter region 32, the base region (composed of 30 and 31), the carrier storage region 22 and the drift region 21, the conductor region 33 is in direct contact with the insulating medium layer 34 and is isolated from other semiconductor regions through the insulating medium layer 34, and the conductor region 33 is in direct contact with the gate conductor 3;
on the side of the emitter E, besides the groove-shaped gate structure (composed of 33 and 34) for controlling the switch, a groove-shaped gate structure (composed of 34 and 35) for shielding a forward high electric field can be contained; the trench-type gate structure (composed of 34 and 35) for shielding the forward high electric field extends from the top plane of the base region (composed of 30 and 31) to the top region of the drift region 21, the trench-type gate structure (composed of 34 and 35) comprises at least one insulating medium layer 34 and at least one conductor region 35, the insulating medium layer 34 is in direct contact with the base region (composed of 30 and 31), the carrier storage region 22 and the drift region 21, the conductor region 35 is in direct contact with the insulating medium layer 34 and is isolated from other semiconductor regions through the insulating medium layer 34, and the conductor region 35 is in direct contact with the emitter conductor 2; at least one heavily doped region 31 of the base region (consisting of 30 and 31) can be in direct contact with the emitter conductor 2 so as to form an ohmic contact; the conductor regions (11, 33, 35) in the trench-type gate structure are made of heavily doped polycrystalline semiconductor material or/and other conductor materials.
Referring to fig. 3-4, the periphery of the cell region formed by the plurality of cells of the reverse blocking-type igbt device further has a terminal region, and the upper and lower surfaces of the terminal region each include at least one trench-type gate structure (formed by 34 and 35 and formed by 11 and 12) connected with a field plate and a plurality of floating field limiting rings (36, 37, 38 and 13, 14, 15) of the second conductivity type, the trench-type gate structure (formed by 34 and 35 and formed by 11 and 12) connected with a field plate being next to the cell region and located between the cell region and the floating field limiting rings (36, 37, 38 and 13, 14, 15); on the upper surface of the terminal region, the trench gate structure (composed of 34 and 35) connected with the field plate extends from the top plane of the base region (composed of 30 and 31) to the top region of the drift region 21, the trench gate structure (composed of 34 and 35) comprises at least one insulating medium layer 34 and at least one conductor region 35, the insulating medium layer 34 is directly contacted with the base region (composed of 30 and 31), the carrier storage region 22 and the drift region 21, the conductor region 35 is directly contacted with the insulating medium layer 34 and is isolated from other semiconductor regions through the insulating medium layer 34, the conductor region 35 is directly contacted with the emitter conductor 2, the upper surface of the semiconductor region in the terminal region is covered with an insulating medium layer 38, and the emitter conductor 2 covers part of the insulating medium layer 39 as the field plate 2, the starting point of the field plate 2 is positioned at a position between the groove-shaped gate structure (composed of 34 and 35) connected with the field plate and the terminal point of the field plate is positioned at a position between the groove-shaped gate structure (composed of 34 and 35) connected with the field plate and one floating field limiting ring 36 closest to the cellular region;
on the lower surface of the termination region, the trench gate structure (composed of 11 and 12) connected with the field plate extends from the bottom plane of the collector region 10 to the bottom region of the drift region 21, the trench gate structure (composed of 11 and 12) comprises at least one insulating dielectric layer 12 and at least one conductor region 11, the insulating dielectric layer 12 is in direct contact with the collector region 10, the field stop region 20 and the drift region 21, the conductor region 11 is in direct contact with the insulating dielectric layer 12 and is isolated from other semiconductor regions by the insulating dielectric layer 12, the conductor region 11 is in direct contact with the collector conductor 1, the lower surface of the semiconductor region in the termination region is covered with an insulating dielectric layer 16, the collector conductor 1 covers part of the insulating dielectric layer 16 as the field plate 1, the starting point of the field plate 1 is located on the trench gate structure (composed of 11 and 12) connected with the field plate and the ending point is located on the field plate connected with the field plate A trench gate structure (consisting of 11 and 12) and one of the floating field limiting rings 13 nearest to the cell region;
the upper and lower surfaces of the termination region may also each have at least one cut-off ring (40, 17) of the first conductivity type, the cut-off rings (40, 17) being located at the periphery of the floating field limiting rings (36, 37, 38 and 13, 14, 15).
Referring to fig. 5-6, the field plates (1, 2) can be stepped field plates, with the thickness of the insulating layer dielectric (39, 16) under the field plates (1, 2) increasing stepwise as the distance from the trench gate structure (34 and 35, 11 and 12) to which the field plates are connected increases.
Referring to fig. 7-8, each floating field limiting ring (36, 37, 38 and 13, 14, 15) is connected with a respective floating field plate (7, 8, 9 and 4, 5, 6), the starting point of the floating field plate (7, 8, 9 and 4, 5, 6) is located at the respective floating field limiting ring (36, 37, 38 and 13, 14, 15) and the end point is located at a distance from the respective floating field limiting ring (36, 37, 38 and 13, 14, 15), and the floating field plate is not connected with other floating field plates.
Referring to fig. 9-10, at the upper surface of the termination region, there may be at least one equipotential trench gate structure (composed of 34 and 35) between the trench gate structure (composed of 34 and 35) connected with the field plate and the floating field limiting ring (36, 37, 38); the equipotential trench gate structure (composed of 34 and 35) penetrates from the top plane of the termination region into the top region of the drift region 21, the trench gate structure (comprised of 34 and 35) includes at least one insulating dielectric layer 34 and at least one conductor region 35, the insulating dielectric layer 34 is in direct contact with the drift region 21, the conductor region 35 is in direct contact with the insulating dielectric layer 34 and is isolated from other semiconductor regions by the insulating dielectric layer 34, the conductor region 35 is in direct contact with the emitter conductor 2, and the region between the trench-type gate structure (composed of 34 and 35) with the field plate connected thereto and the equipotential trench-type gate structure (composed of 34 and 35) and the region between the two equipotential trench-type gate structures (composed of 34 and 35) can be the drift region 21 and also can be the semiconductor region 19 with a doping type or/and a doping concentration different from the drift region;
at the lower surface of the terminal region, at least one equipotential trench gate structure may be provided between the trench gate structure (composed of 11 and 12) connected with the field plate and the floating field limiting ring (13, 14, 15), the equipotential trench gate structure (composed of 11 and 12) extends from the bottom plane of the terminal region into the bottom region of the drift region 21, the trench gate structure (composed of 11 and 12) includes at least one insulating dielectric layer 12 and at least one conductor region 11, the insulating dielectric layer 12 is in direct contact with the drift region 21, the conductor region 11 is in direct contact with the insulating dielectric layer 12 and is isolated from other semiconductor regions by the insulating dielectric layer 12, the conductor region 11 is in direct contact with the field plate conductor 1, the region between the trench gate structure (composed of 11 and 12) connected with the equipotential trench gate structure (composed of 11 and 12) and two equipotential trench gate structures (11 and 12), (c) 11 and 12) may be the drift region 21 and may also be a semiconductor region 18 of a different doping type or/and doping concentration than the drift region.
Referring to fig. 11, on the upper surface of the termination region, the regions between the trench gate structure (composed of 34 and 35) to which the field plate is connected and the equipotential trench gate structure (composed of 34 and 35) and between the two equipotential trench gate structures (composed of 34 and 35) are the base region 30, the carrier storage region 22 and the drift region 21, and the base region 30 is in contact with the emitter conductor 2;
on the lower surface of the termination region, the region between the trench gate structure (composed of 11 and 12) to which the field plate is connected and the equipotential trench gate structure (composed of 11 and 12) and the region between the two equipotential trench gate structures (composed of 11 and 12) are the collector region 10 and the field stop region 20, and the collector region 10 is in contact with the collector conductor 1.
Drawings
FIG. 1 is a RB FS-IGBT of the present invention having a trench gate structure for shielding a reverse high electric field;
FIG. 2 is a schematic view of still another RB FS-IGBT of the present invention, which has a trench type gate structure for shielding a reverse high electric field and a trench type gate structure for shielding a forward high electric field;
FIG. 3 shows that according to FIG. 1, the terminal region of the RB FS-IGBT terminal structure of the present invention has a trench gate structure connected with a field plate and a floating field limiting ring;
FIG. 4 shows that according to FIG. 1, the terminal region of the RB FS-IGBT terminal structure of the present invention comprises a trench gate structure connected with a field plate, a floating field limiting ring and a stop ring;
FIG. 5 shows a terminal structure of a RB FS-IGBT according to the present invention, wherein the field plate is a step field plate, according to FIG. 3;
FIG. 6 shows a terminal structure of a RB FS-IGBT according to the present invention, wherein the field plate is a step field plate;
FIG. 7 shows a terminal structure of an RB FS-IGBT according to the present invention, wherein a field limiting ring is connected with a floating field plate;
FIG. 8 shows a terminal structure of an RB FS-IGBT according to the present invention, wherein a field limiting ring is connected to a floating field plate;
FIG. 9 shows, according to FIG. 4, a equipotential trench gate structure is formed between a trench gate structure connected with a field plate and a field limiting ring, and a drift region is formed in a region between the trench gate structure connected with the field plate and the equipotential trench gate structure;
FIG. 10 shows a terminal structure of an RB FS-IGBT according to the present invention, wherein an equipotential trench gate structure is formed between a trench gate structure connected with a field plate and a field limiting ring, and a region between the trench gate structure connected with the field plate and the equipotential trench gate structure is a semiconductor region with a doping type or/and a doping concentration different from that of the drift region;
FIG. 11 shows a terminal structure of RB FS-IGBT according to the present invention, wherein the region between the trench gate structure connected with the field plate and the equipotential trench gate structure is a base region, a carrier storage region and a drift region, and the emitter conductor is in direct contact with the base region, according to FIG. 10;
FIG. 12 shows a forward withstand voltage I-V curve and a reverse withstand voltage I-V curve of the RB FS-IGBT of FIG. 6 according to the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
The invention mainly aims to provide an FS-IGBT with reverse blocking capability.
Fig. 1 is a schematic structural diagram of a reverse blocking FS-IGBT cell according to the present invention, which includes two types of trench gate structures. One is a trench gate structure (composed of 33 and 34) for controlling the switch, and the other is a trench gate structure (composed of 11 and 12) for shielding the reverse high electric field, wherein the insulating dielectric layers (34 and 12) can be SiO2The dielectric layer, the conductor region (33) of the trench gate structure for controlling the switch and the conductor region (11) of the trench gate structure for shielding the reverse high electric field may be a heavily doped n-type or p-type polysilicon material. The trench gate structure (composed of 33 and 34) for controlling the switch is deep into the drift region (n-region 21) and is connected with the emitter region (n + region 32), the base region (composed of p-base region 30 and p-base region)+Region 31), carrier storage region (n-cs region 22) and drift region (n-region 21) are all in contact, and a conductor region (33) of a trench gate structure (consisting of 33 and 34) for controlling the switch is connected to the gate (G). The groove-shaped grid structure (composed of 11 and 12) for shielding the reverse high electric field is deeply arranged in the drift region (n-region 21), is contacted with the collector region (p-collector region 10), the field stop region (n-fs region 20) and the drift region (n-region 21), and the conductor region (11) of the groove-shaped grid structure (composed of 11 and 12) for shielding the reverse high electric field is connected with the collector (C). Note that the base region (formed by p-base regions 30 and p)+Region 31) of the substrate is formed by a heavily doped region (p)+Region 31) is to form a good ohmic contact with the emitter (E), a heavily doped region (p-base region 30) in the base region when the doping concentration at the surface of the base region is sufficiently high+Region 31) is not required.
In the forward blocking state (gate voltage V)GLess than threshold voltage VTHVoltage V between collector and emitterCE>0) Most of the consumptionThe electric lines of force generated by ionized donors in the drift region (n-region 21) are absorbed by negative charges in a conductor region (33) of a groove-shaped gate structure (composed of 33 and 34) used for controlling the switch, but are only absorbed by ionized acceptors of a base region (p-base region 30) rarely, so that a pn junction formed by the base region (p-base region 30) and a carrier storage region (n-cs region 22) cannot bear a high electric field, namely the groove-shaped gate structure (composed of 33 and 34) used for controlling the switch shields the high electric field at the pn junction formed by the base region (p-base region 30) and the carrier storage region (n-cs region 22), and the carrier storage region (n-cs region 22) is prevented from being subjected to avalanche breakdown. With VCEWhen the depletion region of the drift region (n-region 21) is expanded to the field stop region (n-fs region 20), the field stop region (n-fs region 20) stops the electric field from continuously expanding to the collector region (p-collector region 10), and punch-through breakdown is avoided.
In reverse blocking state (V)G<VTH，VCE<0) Most of the electric lines of force generated by the ionization donors in the depleted drift region (n-region 21) are absorbed by negative charges in the conductor region (11) of the trench-type gate structure (composed of 11 and 12) for shielding a reverse high electric field, and are only rarely absorbed by the ionization acceptors of the collector region (p-collector region 10), so that the pn junction formed by the collector region (p-collector region 10) and the field stop region (n-fs region 20) cannot bear the high electric field, that is, the trench-type gate structure (composed of 11 and 12) for shielding the reverse high electric field shields the high electric field at the pn junction formed by the collector region (p-collector region 10) and the field stop region (n-fs region 20), and avoids the breakdown of the field stop region (n-fs region 20). With reverse bias VCEWhen the depletion region of the drift region (n-region 21) is expanded to the carrier storage region (n-cs region 22), the carrier storage region (n-cs region 22) stops the electric field and continues to expand to the base region (p-base region 30), and punch-through breakdown is avoided.
In the forward conducting state (V)G>VTH，VCE>0.7V), inversion occurs at the interface of the base region (p-base region 30) and an insulating medium layer (34) of a groove type grid structure (composed of 33 and 34) for controlling the switch to form an electron channel, and electrons are emitted from an emitting region (n)+Zone 32) throughThe electrons enter a carrier storage region (n-cs region 22), a drift region (n-region 21) and a field stop region (n-fs region 20) through an electron channel, and finally enter a collector region (p-collector region 10) to cause a large number of holes to be injected into the drift region (n-region 21) from the collector region (p-collector region 10). Because the doping concentration of the carrier storage region (n-cs region 22) is higher than that of the drift region (n-region 21), the carrier storage region (n-cs region 22) can play a role in preventing holes from entering the base region (p-base region 30), so that the carrier storage effect (or conductance modulation effect) in the drift region (n-region 21) is enhanced, the conduction voltage drop is reduced, and the excellent compromise relationship between the conduction voltage drop and the turn-off power consumption is obtained.
In fig. 2, the main difference from the structure of fig. 1 is that there is also a trench-type gate structure (composed of 34 and 35) in the cell for shielding the forward high electric field. The trench gate structure (composed of 34 and 35) for shielding the forward high electric field differs from the trench gate structure (composed of 33 and 34) for controlling the switch in that the former conductor region (35) is connected to the emitter (E) and the latter conductor region (33) is connected to the gate (G). In the forward blocking state, the groove-shaped gate structure (composed of 34 and 35) for shielding the forward high electric field and the groove-shaped gate structure (composed of 33 and 34) for controlling the switch play similar roles, namely the groove-shaped gate structures are used for shielding the high electric field at the pn junction formed by the base region (p-base region 30) and the carrier storage region (n-cs region 22) and preventing the carrier storage region (n-cs region 22) from avalanche breakdown.
Fig. 3 shows a termination structure of a reverse blocking FS-IGBT applicable to the present invention, the left half of the drawing is a cell region composed of reverse blocking FS-IGBT cells, and the right half of the drawing is a termination region. On both upper and lower planes of the terminal region, there are a trench gate structure (composed of 34 and 35 and composed of 11 and 12) connected with a field plate and a plurality of p-type floating field limiting rings (p-ring 36, p-ring 37, p-ring 38, p-ring 13, p-ring 14, p-ring 15), wherein the trench gate structure (composed of 34 and 35 and composed of 11 and 12) connected with the field plate is close to the cell region, and the plurality of p-type floating field limiting rings (p-ring 36, p-ring 37, p-ring 38, p-ring 13, p-ring 14, p-ring 15) are located at the periphery of the trench gate structure (composed of 34 and 35 and composed of 11 and 12) connected with the field plate. On the upper surface, a conductor region (35) of a trench gate structure (composed of 34 and 35) connected with a field plate is connected with an emitter conductor (2), the emitter conductor (2) is covered on an insulating layer medium (39) to be used as the field plate, and a distance is reserved between the edge of the field plate (2) and a p-type floating field limiting ring (p-ring 36) closest to a cellular region. On the lower surface, a conductor region (11) of a trench gate structure (composed of 11 and 12) connected with a field plate is connected with a collector conductor (1), the collector conductor (1) is covered under an insulating layer medium (16) to be used as the field plate, and a distance is reserved between the edge of the field plate (1) and a p-type floating field limiting ring (p-ring 13) closest to a cellular region.
In fig. 4, the main difference from the structure of fig. 3 is that an n-type stop ring (n-ring 40 and n-ring 17) is further provided on the outer periphery of the p-type floating-field limiting rings (p-ring 36, p-ring 37, p-ring 38, p-ring 13, p-ring 14, and p-ring 15). The n-type cut-off rings (n-ring 40 and n-ring 17) function to cut off the electric field and ensure that the drift region (n-region 21) at the periphery of the n-type cut-off rings (n-ring 40 and n-ring 17) is a neutral region in both the forward blocking state and the reverse blocking state.
In fig. 5, the main difference from the structure of fig. 3 is that the field plates (1 and 2) are stepped, the insulating layer dielectric (39 and 16) under the field plates is thinner near the trench gate structures (34 and 35 and 11 and 12) to which the field plates are connected, and the insulating layer dielectric (39 and 16) under the field plates is thicker far from the trench gate structures (34 and 35 and 11 and 12) to which the field plates are connected.
In fig. 6, the main difference from the structure of fig. 5 is that an n-type stop ring (n-ring 40 and n-ring 17) is further provided on the outer periphery of the p-type floating-field limiting rings (p-ring 36, p-ring 37, p-ring 38, p-ring 13, p-ring 14, and p-ring 15).
In fig. 7, the main difference from the structure of fig. 3 is that floating field plates (7, 8, 9, 4, 5, 6) are connected to p-type floating field limiting rings (p-ring 36, p-ring 37, p-ring 38, p-ring 13, p-ring 14, p-ring 15), the floating field plates (7, 8, 9, 4, 5, 6) are formed of conductors, and the floating field plates (7, 8, 9, 4, 5, 6) of each floating field limiting ring (p-ring 36, p-ring 37, p-ring 38, p-ring 13, p-ring 14, p-ring 15) are not connected to (the floating field plates of) the adjacent floating field limiting ring.
In fig. 8, the main difference from the structure of fig. 7 is that an n-type stop ring (n-ring 40 and n-ring 17) is further provided on the outer periphery of the p-type floating-field limiting rings (p-ring 36, p-ring 37, p-ring 38, p-ring 13, p-ring 14, and p-ring 15).
In fig. 9, the main difference from the structure of fig. 4 is that there is an equipotential trench gate structure (composed of 34 and 35 and composed of 11 and 12) between the trench gate structure (composed of 34 and 35 and composed of 11 and 12) connected with the field plate and the floating field limiting rings (p-ring 36, p-ring 37, p-ring 38 and p-ring 13, p-ring 14, p-ring 15). Between the trench gate structure with the field plates attached (consisting of 34 and 35 and consisting of 11 and 12) and the equipotential trench gate structure (consisting of 34 and 35 and consisting of 11 and 12) is the drift region (n-region 21). Conductor regions (35 and 11) of equipotential groove-shaped gate structures (composed of 34 and 35 and composed of 11 and 12) are connected with conductor regions (35 and 11) of groove-shaped gate structures (composed of 34 and 35 and composed of 11 and 12) connected with field plates through conductors (2 and 1), and the field plates (2 and 1) extend to the periphery of the equipotential groove-shaped gate structures (composed of 34 and 35 and composed of 11 and 12).
In fig. 10, the main difference from the structure of fig. 9 is that there may be a plurality of equipotential trench gate structures (composed of 34 and 35 and composed of 11 and 12) between the trench gate structure connected to the field plate (composed of 34 and 35 and composed of 11 and 12) and the floating field limiting ring (p-ring 36, p-ring 37, p-ring 38 and p-ring 13, p-ring 14, p-ring 15), and there may be a semiconductor region (19) different in doping from the drift region (n-region 21) between the trench gate structure connected to the field plate (composed of 34 and 35 and composed of 11 and 12) and the equipotential trench gate structures (composed of 34 and 35 and composed of 11 and 12) and between the two equipotential trench gate structures (composed of 34 and 35 and composed of 11 and 12).
In fig. 11, the main difference from the structure of fig. 9 is that between the trench gate structure (composed of 34 and 35 and composed of 11 and 12) to which the field plate is connected and the equipotential trench gate structure (composed of 34 and 35 and composed of 11 and 12) are the base region (p-base region 30), the carrier storage region (n-cs region 22) and the drift region (n-region 21), and the base region (p-base region 30) between the trench gate structure (composed of 34 and 35 and composed of 11 and 12) to which the field plate is connected and the equipotential trench gate structure (composed of 34 and 35 and composed of 11 and 12) is in contact with the collector conductor (2).
In order to illustrate the superiority of the RB FS-IGBT of the invention, a structure with a target withstand voltage of 1200V is designed and verified by simulation by taking the RB FS-IGBT structure of the invention in FIG. 6 as an example. In the simulation, the width of the cellular region is 12 μm, the width of the terminal region is 450 μm, the length of the step field plate is 251 μm, the distance from the first field limiting ring (p-ring 36) to the stop ring (n-ring 40) is 200 μm, and the insulating dielectric layers (34, 12, 39 and 16) are made of SiO2The width and depth of the trench gate structure (composed of 34 and 35, and composed of 11 and 12) are 2 μm and 5 μm, respectively, and the thickness and doping concentration of the drift region (n-region 21) are 134 μm and 4 × 10, respectively13cm-3The thickness and doping concentration peaks of the field stop region (n-fs region 20) were 1.5 μm and 4X 10, respectively16cm-3The peak values of the thickness and the doping concentration of the carrier storage region (n-cs region 22) were 1.5 μm and 4X 10, respectively16cm-3The peak values of the thickness and the doping concentration of the collector region (p-collector region 10) are 1.5 μm and 2 × 10 respectively19cm-3。
FIG. 12 is a forward withstand voltage I-V curve and a reverse withstand voltage I-V curve of the RB FS-IGBT of the present invention shown in FIG. 6, wherein a gate voltage V isG0V, and the abscissa is the applied voltage V between the collector and emitterCEOrdinate is the current I between collector and emitterCE. As can be seen from the figure, the RB FS-IGBT provided by the invention has both high forward blocking capability and high reverse blocking capability, the forward breakdown voltage is about 1240V, and the reverse breakdown voltage is about 1390V.
In the above description of many embodiments of the present invention, the n-type semiconductor material can be regarded as a first conductive type semiconductor material, and the p-type semiconductor material can be regarded as a second conductive type semiconductor material. Obviously, according to the principle of the present invention, the n-type and the p-type in the embodiments can be interchanged without affecting the content of the present invention. It is obvious to a person skilled in the art that many other embodiments are possible within the inventive idea without going beyond the claims of the invention.
Claims (6)
1. A reverse blocking type insulated gate bipolar transistor device comprises a unit cell structure which comprises: a drift region of a lightly doped first conductivity type, a collector structure in contact with a bottom plane of the drift region, a base region of the second conductivity type in contact with the top plane of the drift region, a heavily doped emitter region of the first conductivity type in contact with at least part of the base region, a trench gate structure in contact with the emitter region, the base region, and the drift region for controlling a switch, with the current collection structure with the drift region all contacts be used for shielding reverse high electric field's cell type grid structure, cover in the current collection structure with be used for shielding reverse high electric field's collector conductor's that the cell type grid structure's collector conductor formed collector, cover in the emitter region with the emitter conductor of base region forms emitter, cover in be used for the control switch's cell type grid structure's that the grid conductor forms, its characterized in that:
the drift region is indirectly contacted with the base region through a carrier storage region of a first conduction type, and the doping concentration of the carrier storage region is higher than that of the drift region;
the collector structure is composed of at least one collector region of a second conductivity type and at least one field stop region of a first conductivity type, the bottom plane of the field stop region is in direct contact with the collector region of the second conductivity type, the top plane of the field stop region is in direct contact with the bottom plane of the drift region, and the collector region is in direct contact with the collector conductor;
the groove-shaped grid structure for shielding the reverse high electric field extends into the bottom region of the drift region from the bottom plane of the collector region, the groove-shaped grid structure comprises at least one insulating dielectric layer and at least one conductor region, the insulating dielectric layer is directly contacted with the collector region, the field stop region and the drift region, the conductor region is directly contacted with the insulating dielectric layer and is isolated from the collector region, the field stop region and the drift region through the insulating dielectric layer, and the conductor region is directly contacted with the collector conductor;
the groove-shaped gate structure for controlling the switch extends into the top area of the drift region from the top plane of the emitter region, the groove-shaped gate structure comprises at least one insulating medium layer and at least one conductor region, the insulating medium layer is directly contacted with the emitter region, the base region, the carrier storage region and the drift region, the conductor region is directly contacted with the insulating medium layer and is isolated from the emitter region, the base region, the carrier storage region and the drift region through the insulating medium layer, and the conductor region is directly contacted with the gate conductor;
on one side of the emitter, the groove-shaped grid structure used for controlling the switch is contained, and the groove-shaped grid structure used for shielding a forward high electric field or the groove-shaped grid structure not used for shielding the forward high electric field is also contained; the groove-shaped grid structure for shielding the forward high electric field extends from the top plane of the base region to the top region of the drift region, the groove-shaped grid structure comprises at least one insulating medium layer and at least one conductor region, the insulating medium layer is directly contacted with the base region, the carrier storage region and the drift region, the conductor region is directly contacted with the insulating medium layer and is isolated from the base region, the carrier storage region and the drift region through the insulating medium layer, and the conductor region is directly contacted with the emitter conductor;
at least one heavily doped region in the base region is in direct contact with the emitter conductor so as to form an ohmic contact; the conductor region in the trench gate structure is composed of a heavily doped polycrystalline semiconductor material.
2. A reverse blocking-type igbt device according to claim 1, wherein:
a terminal region is arranged at the periphery of a cell region formed by a plurality of cells of the reverse blocking type insulated gate bipolar transistor device, the upper surface and the lower surface of the terminal region respectively comprise at least one groove type gate structure connected with a field plate and a plurality of floating field limiting rings of a second conduction type, and the groove type gate structure connected with the field plate is close to the cell region and is positioned between the cell region and the floating field limiting rings;
on the upper surface of the terminal region, the trench gate structure connected with the field plate extends from the top plane of the base region to the top region of the drift region, the trench gate structure comprises at least one insulating medium layer and at least one conductor region, the insulating medium layer is in direct contact with the base region, the carrier storage region and the drift region, the conductor region is in direct contact with the insulating medium layer and is isolated from the base region, the carrier storage region and the drift region through the insulating medium layer, the conductor region is in direct contact with the emitter conductor, the upper surface of the semiconductor region in the terminal region is covered with one insulating medium layer, the emitter conductor covers part of the insulating medium layer as the field plate, the starting point of the field plate is located in the trench gate structure connected with the field plate, and the ending point of the field plate is located between the trench gate structure connected with the field plate and one floating field limiting ring nearest to the cellular region A location;
on the lower surface of the terminal region, the trench gate structure connected with the field plate extends from the bottom plane of the collector region to the bottom region of the drift region, the trench gate structure comprises at least one insulating medium layer and at least one conductor region, the insulating medium layer is in direct contact with the collector region, the field stop region and the drift region, the conductor region is in direct contact with the insulating medium layer and is isolated from the collector region, the field stop region and the drift region through the insulating medium layer, the conductor region is in direct contact with the collector conductor, the lower surface of the semiconductor region in the terminal region is covered with an insulating medium layer, the collector conductor covers part of the insulating medium layer to serve as the field plate, the starting point of the field plate is located in the trench gate structure connected with the field plate, and the ending point of the field plate is located at a certain position between the trench gate structure connected with the field plate and the floating field limiting ring closest to the cellular region Placing;
and the upper surface and the lower surface of the terminal area do not contain a stop ring of the first conductivity type or contain at least one stop ring of the first conductivity type, and the stop rings are positioned on the periphery of the floating field limiting ring.
3. A reverse blocking-type igbt device according to claim 2, wherein: the field plate is a step-shaped field plate, and the thickness of the insulating medium layer below the field plate is increased along with the increase of the distance from the groove-shaped grid structure connected with the field plate.
4. A reverse blocking-type igbt device according to claim 2, wherein: each floating field limiting ring is connected with a respective floating field plate, the starting point of each floating field plate is located at the respective floating field limiting ring, the terminal point of each floating field plate is located at a position which is a certain distance away from the respective floating field limiting ring, and the floating field plates are not connected with other floating field plates.
5. A reverse blocking-type igbt device according to claim 2, wherein:
at least one equipotential groove-shaped gate structure is arranged on the upper surface of the terminal region between the groove-shaped gate structure connected with the field plate and the floating field limiting ring; the equipotential groove-shaped gate structure penetrates into the top region of the drift region from the top plane of the terminal region, the groove-shaped gate structure comprises at least one insulating medium layer and at least one conductor region, the insulating medium layer is in direct contact with the drift region, the conductor region is in direct contact with the insulating medium layer and is isolated from the drift region through the insulating medium layer, the conductor region is in direct contact with the emitter conductor, and the region between the groove-shaped gate structure connected with the field plate and the equipotential groove-shaped gate structure and the region between the two equipotential groove-shaped gate structures are the drift region or semiconductor regions with different doping types or/and different doping concentrations from the drift region;
at least one equipotential groove-shaped gate structure is arranged on the lower surface of the terminal region and between the groove-shaped gate structure connected with the field plate and the floating field limiting ring, the equipotential trench gate structure penetrates from the bottom plane of the termination region into the bottom region of the drift region, the trench gate structure includes at least one insulating dielectric layer and at least one conductor region, the insulating dielectric layer being in direct contact with the drift region, the conductor region is in direct contact with the insulating dielectric layer and is isolated from the drift region by the insulating dielectric layer, the conductor region is in direct contact with the collector conductor, and the region between the trench-type gate structure with the field plate connected and the equipotential trench-type gate structure and the region between the two equipotential trench-type gate structures are the drift region or semiconductor regions with different doping types or/and doping concentrations from the drift region.
6. A reverse blocking-type igbt device according to claim 5, wherein:
on the upper surface of the terminal region, the region between the trench gate structure connected with the field plate and the equipotential trench gate structure and the region between the two equipotential trench gate structures are the base region, the carrier storage region and the drift region, and the base region is in contact with the emitter conductor;
and on the lower surface of the terminal region, the region between the groove-shaped grid structure connected with the field plate and the equipotential groove-shaped grid structure and the region between the two equipotential groove-shaped grid structures are the collector region and the field stop region, and the collector region is in contact with the collector conductor.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003318399A (en) * | 2002-04-25 | 2003-11-07 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method therefor |
| CN107293579A (en) * | 2017-06-29 | 2017-10-24 | 四川大学 | A kind of superjunction IGBT with low conduction voltage drop |
| CN107464842A (en) * | 2017-08-03 | 2017-12-12 | 电子科技大学 | A kind of superjunction with colelctor electrode groove is against conductivity type IGBT |
| CN108198851A (en) * | 2017-12-27 | 2018-06-22 | 四川大学 | A kind of superjunction IGBT with enhancing carrier storage effect |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2003318399A (en) * | 2002-04-25 | 2003-11-07 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method therefor |
| CN107293579A (en) * | 2017-06-29 | 2017-10-24 | 四川大学 | A kind of superjunction IGBT with low conduction voltage drop |
| CN107464842A (en) * | 2017-08-03 | 2017-12-12 | 电子科技大学 | A kind of superjunction with colelctor electrode groove is against conductivity type IGBT |
| CN108198851A (en) * | 2017-12-27 | 2018-06-22 | 四川大学 | A kind of superjunction IGBT with enhancing carrier storage effect |
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