CN113035939B - Reverse-conducting super-junction IGBT (insulated Gate Bipolar translator) with isolated p-top region - Google Patents
Reverse-conducting super-junction IGBT (insulated Gate Bipolar translator) with isolated p-top region Download PDFInfo
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Abstract
The invention provides a Reverse Conducting super-junction IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) device, wherein a top region of a second Conducting type with lower resistivity is arranged above a semiconductor region of the second Conducting type in a voltage-resisting layer, and the top region is isolated from a base region of the second Conducting type through a groove-shaped Gate structure and comprises a back groove-shaped insulating medium region, the side surface of the back groove-shaped insulating medium region is surrounded by a floating region of the second Conducting type, and the top of the back groove-shaped insulating medium region is surrounded by a stopping ring of a first Conducting type. The device has lower conduction voltage drop and can eliminate the voltage retracing phenomenon along with the current.
Description
Technical Field
The invention belongs to a semiconductor device, in particular to a power semiconductor device.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a medium-high voltage power semiconductor switching device. A Super Junction (SJ) is a voltage-withstanding layer structure in which n columns and p columns are alternately arranged, and can enable the n columns and the p columns to obtain higher breakdown voltage under higher doping concentration. When the IGBT adopts a super-junction voltage-withstanding layer structure, a pn junction formed by the n column/p column can be quickly exhausted in the turn-off process, so that the turn-off speed is increased (or the turn-off power consumption is reduced). However, in the ordinary super junction IGBT, the conductivity modulation effect (or carrier storage effect) of the n-pillar and the p-pillar in the on-state is poor, mainly because the p-pillar easily collects holes and smoothly extracts the collected holes to the emitter, which makes it difficult to effectively store the holes in the n-pillar and the p-pillar, increasing the on-state voltage drop. In addition, an IGBT is usually used in combination with an antiparallel diode in application. In order to reduce parasitic effects and improve integration, a Reverse diode may also be integrated in the IGBT, which is called a Reverse Conducting IGBT (RC-IGBT). However, the conventional RC-IGBT generates a voltage-back (Snap-back) phenomenon with current, which is disadvantageous for reliable operation of the device.
Disclosure of Invention
Compared with the common reverse-conducting super-junction IGBT, the reverse-conducting super-junction IGBT device provided by the invention has lower conduction voltage drop and eliminates the phenomenon that voltage is folded along with current.
Referring to fig. 2 to 6, the present invention provides an inverse conduction type super junction insulated gate bipolar transistor device, wherein a cell structure of the device comprises: a current collection structure (composed of 10, 11, and 20), a lightly doped auxiliary layer 30 of the first conductivity type located above the current collection structure (composed of 10, 11, and 20), a super junction voltage withstanding layer (composed of 31 and 32) located above the auxiliary layer 30, a base region (composed of 41 and 43) of the second conductivity type located above the super junction voltage withstanding layer (composed of 31 and 32), and a top region (composed of 42 and 45) of the second conductivity type, a heavily doped emitter region 44 of the first conductivity type in contact with at least part of the base region (composed of 41 and 43), and a trench type gate structure (composed of 47 and 49) for controlling a switch in contact with the emitter region 44, the base region (composed of 41 and 43), and the super junction voltage withstanding layer (composed of 31 and 32), characterized in that:
the collection structure (made up of 10, 11 and 20) is made up of at least one collector region 10 of the second conductivity type, at least one collector region 11 of the first conductivity type and at least one buffer region 20 of the first conductivity type; the lower surface of the buffer region 20 is in direct contact with both the collector region 10 of the second conductivity type and the collector region 11 of the first conductivity type, and the upper surface of the buffer region 20 is in direct contact with the auxiliary layer 30;
the cell structure comprises a back groove-shaped insulating medium region 12, and the back groove-shaped insulating medium region 12 extends into the auxiliary layer 30; the side surface of the back groove-type insulating medium region 12 is in direct contact with the collector region 10 of the second conductivity type, the collector region 11 of the first conductivity type and the buffer region 20, and the collector region 10 of the second conductivity type and the collector region 11 of the first conductivity type are isolated from each other by the back groove-type insulating medium region 12; the side surface of the back groove-shaped insulating medium region 12 is indirectly contacted with the auxiliary layer 30 through a floating space region 21 of a second conduction type, and the top of the back groove-shaped insulating medium region 12 is indirectly contacted with the auxiliary layer 30 through a stop ring 22 of a first conduction type; collector conductors 1 are covered on the lower surfaces of the collector region 11 of the first conductivity type, the collector region 10 of the second conductivity type and the back groove-shaped insulating medium region 12 and are connected to a collector C through a lead;
the super junction voltage-withstanding layer (composed of 31 and 32) is composed of at least one first conductivity type semiconductor region 31 and at least one second conductivity type semiconductor region 32, the first conductivity type semiconductor region 31 of the super junction voltage-withstanding layer and the second conductivity type semiconductor region 32 of the super junction voltage-withstanding layer are in contact with each other, and a contact surface formed by the semiconductor region is vertical or approximately vertical to the upper surface of the auxiliary layer 30, the base region (composed of 41 and 43) and the lower surface of the top region (composed of 42 and 45); the lower surface of the super junction voltage-resistant layer (composed of 31 and 32) is in direct contact with the auxiliary layer 30;
the lower surface of the base region (composed of 41 and 43) is in contact with the first-conductivity-type semiconductor region 31 of the super-junction voltage-resistant layer through a first-conductivity-type carrier storage layer 33; the upper surface of the base region (composed of 41 and 43) is at least partially covered with an emitter conductor 2 and is connected to an emitter E through a lead; at least one heavily doped region 43 of the base region (consisting of 41 and 43) is in direct contact with the emitter conductor 2 so as to form an ohmic contact;
the upper surface of the emitter region 44 is covered with an emitter conductor 2 and connected to the emitter E by a wire;
the lower surface of the top region (composed of 42 and 45) is in direct contact with the second conductivity-type semiconductor region 32 of the super junction voltage-resistant layer, and the resistivity of the top region (composed of 42 and 45) in the vertical direction is higher than the resistivity of the second conductivity-type semiconductor region 32 of the super junction voltage-resistant layer in the vertical direction; the upper surface of the top region (consisting of 42 and 45) is at least partially covered with an emitter conductor 2 and is connected to the emitter E by a wire; at least one heavily doped region 45 in the top region (consisting of 42 and 45) is in direct contact with the emitter conductor 2 so as to form an ohmic contact;
the top region (composed of 42 and 45) and the base region (composed of 41 and 43) are isolated from each other through a first type of emitter-connected trench gate structure (composed of 46 and 48) and/or the trench gate structure (composed of 47 and 49) for controlling the switch;
the groove-type gate structure (composed of 47 and 49) for controlling the switch comprises an insulating medium layer 49 and a conductor region 47 surrounded by the insulating medium layer; the insulating dielectric layer 49 of the trench-type gate structure for controlling the switch is in direct contact with the emitter region 44, the base region (composed of 41 and 43), the carrier storage layer 33 and the first conductivity-type semiconductor region 31 of the super junction voltage-withstanding layer, or in direct contact with the emitter region 44, the base region (composed of 41 and 43), the top region (composed of 42 and 45), the carrier storage layer 33, the first conductivity-type semiconductor region 31 of the super junction voltage-withstanding layer and the second conductivity-type semiconductor region 32 of the super junction voltage-withstanding layer; the upper surface of the conductor region 47 of the groove-shaped grid structure for controlling the switch is covered with a grid conductor 3 and is connected to the grid G through a lead;
the first emitter-connected trench gate structure (consisting of 46 and 48) comprises an insulating dielectric layer 48 and a conductor region 46 surrounded by the insulating dielectric layer; the insulating medium layer 48 of the first emitter-connected trench gate structure is in direct contact with the base region (composed of 41 and 43), the top region (composed of 42 and 45), the carrier storage layer 33, the first conductivity type semiconductor region 31 of the super junction voltage-withstanding layer, and the second conductivity type semiconductor region 32 of the super junction voltage-withstanding layer; the upper surface of the first emitter-connected groove-shaped grid structure conductor region 46 is covered with an emitter conductor 2 and is connected to the emitter E through a wire;
the conductor regions (46 and 47) in the trench gate structure are composed of heavily doped polycrystalline semiconductor material; when the first conduction type is n type, the second conduction type is p type; when the first conductivity type is p-type, the second conductivity type is n-type.
Referring to fig. 7-9, a second emitter-connected trench gate structure (composed of 46 and 48) is included above the semiconductor region 31 of the first conductivity type of the super junction voltage-resistant layer and/or the semiconductor region 32 of the second conductivity type of the super junction voltage-resistant layer; the second type of emitter-connected trench gate structure (composed of 46 and 48) includes an insulating dielectric layer 48 and a conductor region 46 surrounded by the insulating dielectric layer, the insulating dielectric layer 48 directly contacts with the base region (composed of 41 and 43), the carrier storage layer 33 and the first conductivity type semiconductor region 31 of the super junction voltage-withstanding layer, or directly contacts with the top region (composed of 42 and 45) and the second conductivity type semiconductor region 32 of the super junction voltage-withstanding layer, and the upper surface of the conductor region 46 is covered with an emitter conductor 2 and is connected to the emitter E through a wire.
Referring to fig. 10, the doping concentration and thickness of the region of the buffer region 20 in contact with the collector region 10 of the second conductivity type are required to be such that applying a high positive voltage between the collector C and the emitter E will not cause an electric field to pass through to the collector region 10 of the second conductivity type; the doping concentration of the region of the buffer region 20 in contact with the collector region 11 of the first conductivity type is equal to or comparable to the doping concentration of the auxiliary layer 30.
Referring to fig. 11, the doping concentration of the carrier storage layer 33 is higher than the doping concentration of the first conductivity type semiconductor region 31 of the super junction voltage-withstanding layer, or equal to or equivalent to the doping concentration of the first conductivity type semiconductor region 31 of the super junction voltage-withstanding layer.
Drawings
FIG. 1 is a schematic diagram of a common reverse conducting super junction IGBT structure;
FIG. 2 shows a reverse conducting super junction IGBT, wherein a p-type top region is isolated from a p-type base region through a first emitter-connected trench gate structure, and the upper surface of the p-type top region is p+Region, emitter conductor covering p+A region upper surface;
FIG. 3 shows another reverse conducting super junction IGBT, in which the p-type top region is isolated from the p-type base region by a first emitter-connected trench gate structure, and the upper surface of the p-type top region is p+A region, an emitter conductor overlying an upper surface of the p-type top region;
FIG. 4 shows another reverse conducting super junction IGBT, in which the p-type top region is isolated from the p-type base region by a first emitter-connected trench gate structure, and the upper surface of the p-type top region is p+Region, emitter conductor covering p+A region upper surface;
FIG. 5 shows another reverse conducting super-junction IGBT, in which the p-type top region is isolated from the p-type base region by the trench-type gate structure of the control switch, and p is a unitThe upper surface of the top region of the type is p+Region, emitter conductor covering p+A region upper surface;
FIG. 6 shows another reverse conducting super-junction IGBT, in which the p-type top region is isolated from the p-type base region by the trench-type gate structure of the control switch and the first emitter-connected trench-type gate structure, and the upper surface of the p-type top region is p+Region, emitter conductor covering p+A region upper surface;
FIG. 7 shows a further reverse conducting super junction IGBT according to the invention with a second emitter-connected trench gate structure above the p-pillar according to FIG. 2;
FIG. 8 shows another reverse conducting super junction IGBT according to the invention with a second trench gate structure over the n-pillar to connect the emitter according to FIG. 5;
FIG. 9 shows a further reverse conducting super junction IGBT according to the invention, with a second trench gate structure connecting the emitters above both the n-pillar and the p-pillar, according to FIG. 5;
fig. 10 shows a further reverse conducting super junction IGBT according to fig. 2, in which the buffer region in contact with the collector region of the first conductivity type has the same doping concentration as the auxiliary layer, making it a part of the auxiliary layer;
fig. 11 is a view showing another reverse conducting type super junction IGBT according to fig. 2, in which the doping concentration of the carrier storage layer is equal to the doping concentration of the first conduction type region of the super junction voltage-withstanding layer, so that the carrier storage layer becomes a part of the first conduction type region of the super junction voltage-withstanding layer;
FIG. 12 forward conduction of the conventional reverse conducting super-junction IGBT of FIG. 1 and the reverse conducting super-junction IGBT of FIG. 2I-VCurve line.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a common reverse conducting super junction IGBT structure, in which a super junction voltage-withstanding layer is composed of an n-pillar (n-pillar region 31) and a p-pillar (p-pillar region 32) and is used for bearing a main applied voltage, a lightly doped n-type auxiliary layer (n-assist layer 30) also bears a part of the applied voltage, and an n-type buffer region (n-buffer region 20) plays a role of a cut-off electric field. In the reverse directionIn the on state, the gate (G) is shorted to the emitter (E), which applies a positive voltage with respect to the collector (C). When the voltage exceeds 0.7V, the base region (p-b region 41 and p)+Region 43) and p-pillar (p-pillar region 32) inject holes into the n-pillar (n-pillar region 31) and n-type assist layer (n-assist layer 30). At the same time, an n-type collector region (n)+Region 11) provides electrons that are injected into the base region (p-b region 41 and p) through the n-pillar (n-pilar region 31) and the n-type assist layer (n-assist layer 30)+Region 43) and p-pillar (p-pilar region 32), the reverse diode is conducting. In the forward conduction state, a positive voltage is applied to the gate (G) with respect to the emitter (E), and when the voltage exceeds a threshold voltage, an electron channel is formed in the vicinity of the interface between the base region (p-b region 41) and the insulating layer (49). At this time, the collector (C) is applied with a positive voltage with respect to the emitter (E), and electrons pass from the emitter (E) through the emitter region (n) by the action of the electric field+Region 44) and electron channel into the n-pillar (n-pillar region 31), n-assist layer (n-assist layer 30), n-buffer region (n-buffer region 20), and then into the n-collector region (n-collector region)+Region 11) the device is in MOSFET conduction mode. When the positive voltage of the collector (C) relative to the emitter (E) continues to increase, the current continuously increases, electrons transversely flow through the n-type buffer region (n-buffer region 20) to generate a potential difference of more than 0.7V on the n-type buffer region (n-buffer region 20), the p-type collector region (p-collector region 10) starts to inject holes into the n-type buffer region (n-buffer region 20), and the device is converted into an IGBT conducting mode. Since the unbalanced carriers can be stored in the n-type auxiliary layer (n-assist layer 30), the n-pillar (n-pillar region 31), and the p-pillar (p-pillar region 32) in the IGBT on mode, a conductivity modulation effect occurs in the body, and the resistance of the device decreases, which causes a voltage folding-back phenomenon with current. Further, when the device enters the IGBT conducting mode, since the pn junction of the p-pillar (p-pillar region 32) and the n-pillar (n-pillar region 31) is reverse biased, holes in the n-pillar (n-pillar region 31) easily enter the p-pillar (p-pillar region 32) and pass through the base regions (p-b region 41 and p-pillar region 31)+Region 43) is collected by the emitter (E). This results in a reduced storage effect of non-equilibrium carriers in the n-pillar (n-pillar region 31) and the p-pillar (p-pillar region 32), leading to a reduction in the storage effect of non-equilibrium carriersThe pressure drop through increases.
The main purpose of the invention is to improve the defects of the common reverse-conducting super-junction IGBT shown in FIG. 1 that the voltage is folded back along with the current and the conduction voltage drop is high.
FIG. 2 is a schematic diagram of a reverse conducting super junction IGBT cell structure of the present invention, which is mainly different from the conventional reverse conducting super junction IGBT shown in FIG. 1 in that (1) a base region (p-b region 41 and p-p region 32) is introduced above a p column (p-pilar region 32)+Region 43) isolated p-type top region (formed by p-top region 42 and p)+Region 45) that provides a greater resistance to the passage of holes from the p-pillar (p-pilar region 32) to the emitter (E), thereby enhancing the conductivity modulation effect in the on-state; (2) an n-type carrier storage layer (n-cs layer 33) is added to further enhance the conductivity modulation effect in an on state; (3) the back groove type insulating medium region (12), a p-type floating region (p region 21) and an n-type stop ring (n-ring region 22) are introduced into the back surface, so that the phenomenon that voltage is folded along with current is eliminated.
At zero bias, depletion of the n-type assist layer (n-assist region 30) between two adjacent p-type floating regions (p regions 21) occurs due to the built-in potential, e.g., 0.7V, between the p-type floating region (p region 21) and the n-type assist layer (n-assist layer 30). When the pitch of the adjacent two p-type floating regions (p regions 21) is sufficiently small, the n-type auxiliary layer (n-assist region 30) between them can be completely depleted, which allows the n-type collector region (n-assist region 30) to be reached from the neutral region of the n-type auxiliary layer+Region 11) is closed.
In the forward conduction state, when a positive voltage applied between the gate (G) and the emitter (E) is greater than a threshold voltage of the trench gate structure (composed of 47 and 49) for controlling the switch, an electron accumulation layer channel is formed near an interface between the base region (p-b region 41) and the trench gate structure (composed of 47 and 49) for controlling the switch, and the emitter region (n) is formed+Region 44) to the n-pillar (n-pilar region 31). Electrons pass from the emitter (E) through the emitter region (n) due to a positive voltage applied between the collector (C) and the emitter (E)+Region 44) and electron accumulation layer channel into the n-pillar(n-pilar region 31) and an n-type auxiliary layer (n-assist layer 30). From the neutral region of the n-type auxiliary layer (n-assist layer 30) to the n-type collector region (n)+Region 11) is turned off, electrons that have entered the n-type auxiliary layer (n-assist layer 30) enter the p-type collector region (p-collector region 10), thereby causing holes to be injected from the p-type collector region (p-collector region 10) into the n-type auxiliary layer (n-assist layer 30), and the device directly enters the IGBT conduction mode, so that the voltage folding back phenomenon with current is eliminated.
Further, above the p-pillar (p-pilar region 32) is a p-type top region (composed of p-top region 42 and p-pillar region)+Region 45) with a p-type top region in the vertical direction (consisting of p-top region 42 and p)+Region 45) is higher than the p-pillar (p-pilar region 32) and the p-type top region (composed of p-top region 42 and p-pillar region 32)+Region 45) is connected to the base region (formed by p-base regions 41 and p) by a first emitter-connected trench gate structure (formed by 46 and 48)+Region 43) is formed. In the forward conduction state, holes enter the p-pillar (p-pilar region 32) and pass up the p-type top region (formed by p-top region 42 and p-pillar region)+Region 45) towards the emitter (E). Due to the p-type top region (formed by p-top region 42 and p)+Region 45) is higher than the p-pillar (p-pilar region 32), the p-type top region (composed of p-top region 42 and p-pillar region)+Region 45) the voltage drop caused by the hole current is not negligible and the potential of the p-pillar (p-pilar region 32) is thus raised. When the p-type top region (composed of p-top region 42 and p)+Region 45) is sufficiently high, the potential of the p-pillar (p-pilar region 32) can be raised to 0.7V, and then the p-pillar/n-pillar junction becomes a forward biased junction, the concentration of non-equilibrium carriers near the p-pillar/n-pillar junction is higher, the in-vivo conductivity modulation effect is enhanced, and the conduction voltage drop is reduced. To form a p-type top region (composed of p-top region 42 and p)+Region 45) has a higher resistivity than the p-pillar (p-pilar region 32). Removing heavily doped region (p) in p-type top region+Region 45) (p-top region 42) may have a gaussian doping profile in the vertical direction and a much lower doping concentration at the interface with the p-pillar (p-pilar region 32)Average doping concentration of the p-pillar (p-pilar region 32).
Still further, in fig. 2, an n-type carrier storage layer (n-cs layer 33) is employed. Albeit due to the p-type top region (formed by p-top region 42 and p)+Region 45) causes a difficulty in flowing holes to the p-pillar (p-pillar region 32), but if the n-type carrier storage layer (n-cs layer 33) is not provided, holes in the n-pillar (n-pillar region 31) can flow more smoothly to the base region (formed by the p-b region 41 and the p-pillar region 32)+Region 43) so that the conductivity modulation effect in the top region of the n-pillar (n-pilar region 31) is weak, which increases the on-state voltage drop to some extent. When an n-type carrier storage layer (n-cs layer 33) with the doping concentration higher than that of the n column (n-pilar region 31) is introduced, the n-type carrier storage layer (n-cs layer 33) can inhibit holes from entering the base region (formed by the p-b region 41 and the p-c region)+Region 43) to enhance the conductivity modulation effect in the top region of the n-pillar (n-pilar region 31) to further reduce the turn-on voltage drop.
In addition, a p-type top region (defined by p-top region 42 and p)+Region 45) is a heavily doped region (p)+Zone 45). The heavily doped region (p)+Region 45) for connecting the emitter conductor (2) to the p-type top region (formed by p-top region 42 and p)+Region 45) forms a good ohmic contact. Of course, overlying the p-type top region (formed by p-top region 42 and p)+Region 45) does not necessarily have to cover only the heavily doped region (p)+Region 45), or a portion thereof may be overlaid in the p-type top region to remove the heavily doped region (p)+Region 45) (p-top region 42).
In FIG. 3, the main difference from the structure of FIG. 2 is the p-type top region (formed by p-top region 42 and p-top region)+Region 45) is not all heavily doped (p)+Region 45) and overlies the p-type top region (defined by p-top region 42 and p)+Region 45) does not cover the heavily doped region (p) either only+Zone 45).
In FIG. 4, the main difference from the structure of FIG. 3 is that the p-type top region is covered (by p-top region 42 and p-top region)+ Zone 45 formed)The emitter conductor (2) only covers the heavily doped region (p)+Zone 45).
In FIG. 5, the main difference from the structure of FIG. 2 is the p-type top region (formed by p-top region 42 and p-top region)+Region 45) with the base region (formed by p-b regions 41 and p) by controlling the trench gate structure of the switch (formed by 47 and 49)+Region 43) is formed.
In FIG. 6, the main difference from the structure of FIG. 5 is that the p-type top region (formed by p-top region 42 and p-top region)+Region 45) is connected to the base region (formed by p-b regions 41 and p) via the trench gate structure (formed by 47 and 49) of the control switch and the first emitter-connected trench gate structure (formed by 46 and 48)+Region 43) is formed.
In fig. 7, the main difference from the structure of fig. 2 is that there is also a second emitter-connected trench gate structure (consisting of 46 and 48) over the p-pillar (p-pilar region 32). When the density of the groove type grid structure is increased, the electric field concentration effect at the bottom of the groove type grid structure is favorably relieved.
In fig. 8, the main difference from the structure of fig. 5 is that there is also a second emitter-connected trench gate structure (consisting of 46 and 48) over the n-pillar (n-pilar region 31).
In fig. 9, the main difference from the structure of fig. 8 is that there is a second emitter-connected trench gate structure (consisting of 46 and 48) over both the p-pillar (p-pilar region 32) and the n-pillar (n-pilar region 31).
The main difference between the structure of fig. 10 and that of fig. 2 is that the doping concentration of the region of the n-type buffer region (n-buffer region 20) in contact with the n-type collector region is equal to the doping concentration of the n-type auxiliary layer (n-assist layer 30), making it a part of the auxiliary layer.
The main difference between the structures of fig. 11 and fig. 2 is that the n-type carrier storage layer (n-cs layer 33) and the n-pillar (n-pilar region 31) have the same doping concentration, and the n-type carrier storage layer (n-cs layer 33) is a part of the n-pillar (n-pilar region 31).
For the purpose of illustrating the superiority of the reverse-conducting super-junction IGBT of the present invention, the reverse-conducting super-junction IGBT of the present invention shown in fig. 2 is used hereinFor example, the structure of the conduction-type super-junction IGBT is compared with the common reverse conduction-type super-junction IGBT in the figure 1 through simulation calculation. The structures in fig. 1 and fig. 2 both adopt Si materials, a symmetrical super junction structure is adopted, minority carrier lifetimes of electrons and holes are both 5 μ s, and a half cell width is 6 μm; the insulating medium layers (48 and 49) adopt SiO2The thickness of the film is 0.1 mu m; the insulating medium region (12) adopts SiO2The width and the depth of the film are respectively 1 μm and 5 μm; the thickness and doping concentration of the n-pillar (n-pillar region 31) and the p-pillar (p-pillar region 32)N pillarRespectively 70 μm and 3X 1015 cm-3(ii) a The thickness, the highest concentration and the lowest concentration of the region (p-top region 42) of the p-type top region excluding the heavily doped region were 2.8 μm and 1X 10, respectively15 cm-3And 1X 1014 cm-3(ii) a The thickness and doping concentration of the n-type auxiliary layer (n-assist layer 30) were 20 μm and 5 × 10, respectively13 cm-3(ii) a The n-type buffer region (n-buffer region 20) in the structure of FIG. 2 has peak values of thickness and doping concentration of 2 μm and 5X 10, respectively16 cm-3(ii) a In the structure of FIG. 1, the thickness of the n-type buffer region (n-buffer region 20) is 2 μm, and the peak doping concentration of the n-type buffer region (n-buffer region 20) adopts 3 different concentrations (3 × 10)14 cm-3，5×1014 cm-3，1×1015 cm-3) (ii) a The width, thickness and doping concentration peak of the p-type collector region (p-collector region 10) were 3.5 μm, 1 μm and 1 × 10, respectively18 cm-3(ii) a n type collector region (n)+Region 11) has a width, thickness and doping concentration peak of 1.5 μm, 1 μm and 1X 10, respectively18 cm-3(ii) a The peak concentration at the interface of the n-type termination ring (n-ring region 22) and the back groove-type insulating medium region (12) is 3 × 1018 cm-3The diffusion length is 0.3 μm; the peak concentration at the interface of the p-type floating empty region (p region 21) and the back groove-type insulating medium region (12) is 2 multiplied by 1016 cm-3The diffusion length is 0.4 μm; the thickness of the n-type carrier storage layer (n-cs layer 33) was 1.5 μm, and the doping concentration of the n-type carrier storage layer (n-cs layer 33)N csAdopt 3X 1016 cm-3Is uniformly doped.
FIG. 12 is a forward conduction of the structure of FIG. 2 and the structure of FIG. 1I-VCurve of the grid voltageV G= 15V. Conduction drop (current density ofJ C = 150 A/cm2Lower) is only 1.4V, while the conduction drop of the structure of fig. 1 has reached 4.5V. In addition, the structure of FIG. 2 has no voltage-dependent current foldback, while the structure of FIG. 1 has a doping concentration peak in the n-type buffer region (n-buffer region 20) as low as 3 × 1014 cm-3The voltage is still folded back along with the current. If the structure of FIG. 1 is to ensure sufficient withstand voltage, the peak doping concentration of the n-type buffer region (n-buffer region 20) is increased to 1016 cm-3The thickness of the n-type auxiliary layer (n-assist layer 30) is either increased in order to prevent electric field from passing through to the p-type collector region (p-collector region 10). In the former case, if the voltage folding phenomenon along with the current is to be eliminated, the width of the p-type collector region (p-collector region 10) is greatly increased, so that the resistance of the n-type buffer region (n-buffer region 20) in the lateral direction is greatly increased, but this may cause the current to be more concentrated in a narrow region in the vertical direction of the n-type buffer region (n-buffer region 20) during reverse conduction, which is not favorable for reliability. In the latter case, an increase in the on-voltage and an increase in the off-power consumption are caused due to an increase in the thickness of the n-type auxiliary layer (n-assist layer 30). The structure of fig. 2 therefore has a significant advantage over the structure of fig. 1.
In the above description of many embodiments of the present invention, the n-type semiconductor material can be regarded as a first conductive type semiconductor material, and the p-type semiconductor material can be regarded as a second conductive type semiconductor material. Obviously, according to the principle of the present invention, the n-type and the p-type in the embodiments can be interchanged without affecting the content of the present invention. It is obvious to a person skilled in the art that many other embodiments are possible within the inventive idea without going beyond the claims of the invention.
Claims (4)
1. A reverse conducting type super junction insulated gate bipolar transistor device comprises a unit cell structure which comprises: the semiconductor device comprises a current collection structure, an auxiliary layer, a super-junction voltage-withstanding layer, a base region, a top region, a heavily doped emitter region and a groove-shaped gate structure, wherein the auxiliary layer is located above the current collection structure and is of a lightly doped first conductive type, the super-junction voltage-withstanding layer is located above the auxiliary layer, the base region is located above the super-junction voltage-withstanding layer and is of a second conductive type, the heavily doped emitter region is at least partially contacted with the base region, and the groove-shaped gate structure is contacted with the emitter region, the base region and the super-junction voltage-withstanding layer and is used for controlling a switch, and the semiconductor device is characterized in that:
the current collection structure is composed of at least one collector region of a second conduction type, at least one collector region of a first conduction type and at least one buffer region of a first conduction type; the lower surface of the buffer area is in direct contact with the collector area of the second conduction type and the collector area of the first conduction type, and the upper surface of the buffer area is in direct contact with the auxiliary layer;
the cellular structure comprises a back groove-shaped insulating medium region which extends into the auxiliary layer; the side face of the back groove-type insulating medium region is in direct contact with the collector region of the second conduction type, the collector region of the first conduction type and the buffer region, and the collector region of the second conduction type and the collector region of the first conduction type are isolated from each other by the back groove-type insulating medium region; the side surface of the back groove-shaped insulating medium region is in contact with the auxiliary layer through a second conductive type floating space region, and the top of the back groove-shaped insulating medium region is in contact with the auxiliary layer through a first conductive type stopping ring; collector conductors are covered on the lower surfaces of the collector region of the first conduction type, the collector region of the second conduction type and the back groove-shaped insulating medium region and are connected to collectors through wires;
the super-junction voltage-withstanding layer is composed of at least one first-conductivity-type semiconductor region and at least one second-conductivity-type semiconductor region, the first-conductivity-type semiconductor region of the super-junction voltage-withstanding layer is in contact with the second-conductivity-type semiconductor region of the super-junction voltage-withstanding layer, and a contact surface formed by the semiconductor region is perpendicular to the upper surface of the auxiliary layer and the lower surfaces of the base region and the top region; the lower surface of the super junction voltage-resistant layer is in direct contact with the auxiliary layer;
the lower surface of the base region is in contact with the first-conductivity-type semiconductor region of the super-junction voltage-resisting layer through a first-conductivity-type carrier storage layer; the base region is not in direct contact with the second conductive type semiconductor region in the super junction voltage-resisting layer; at least part of the upper surface of the base region is covered with an emitter conductor and is connected to the emitter through a lead; at least one heavily doped region in the base region is in direct contact with the emitter conductor so as to form ohmic contact;
the upper surface of the emitting region is covered with an emitter conductor and is connected to the emitter through a lead;
the lower surface of the top region is in direct contact with the semiconductor region of the second conduction type of the super junction voltage-resisting layer, and the resistivity of the top region in the vertical direction is higher than that of the semiconductor region of the second conduction type of the super junction voltage-resisting layer in the vertical direction; the upper surface of the top area is at least partially covered with an emitter conductor and is connected to the emitter through a lead; at least one heavily doped region in the top region in direct contact with the emitter conductor so as to form an ohmic contact;
the top region and the base region are mutually isolated through a first groove-shaped grid structure connected with an emitter and/or the groove-shaped grid structure used for controlling a switch;
the groove-shaped grid structure for controlling the switch comprises an insulating medium layer and a conductor region surrounded by the insulating medium layer; the insulating medium layer of the groove-shaped grid structure for controlling the switch is in direct contact with the first conductive type semiconductor regions of the emitter region, the base region, the carrier storage layer and the super-junction voltage-resisting layer, or in direct contact with the first conductive type semiconductor regions of the emitter region, the base region, the top region, the carrier storage layer, the super-junction voltage-resisting layer and the second conductive type semiconductor regions of the super-junction voltage-resisting layer; the upper surface of a conductor region of the groove-shaped grid structure for controlling the switch is covered with a grid conductor and is connected to the grid through a lead;
the first groove-shaped grid structure connected with the emitter comprises an insulating medium layer and a conductor region surrounded by the insulating medium layer; the insulating medium layer of the first type of emitter-connected groove-shaped gate structure is in direct contact with the base region, the top region, the carrier storage layer, the first conduction type semiconductor region of the super-junction voltage-resisting layer and the second conduction type semiconductor region of the super-junction voltage-resisting layer; the upper surface of a conductor region of the first type of the groove-shaped grid structure connected with the emitter is covered with an emitter conductor and is connected to the emitter through a lead;
the conductor region in the groove-shaped gate structure is made of heavily doped polycrystalline semiconductor materials; when the first conduction type is n type, the second conduction type is p type; when the first conductivity type is p-type, the second conductivity type is n-type.
2. The device of claim 1, wherein:
a second groove-shaped grid structure connected with an emitter is arranged above the first conduction type semiconductor region of the super junction voltage-resisting layer and/or the second conduction type semiconductor region of the super junction voltage-resisting layer; the second groove-shaped grid structure connected with the emitter comprises an insulating medium layer and a conductor region surrounded by the insulating medium layer, the insulating medium layer is in direct contact with the base region, the carrier storage layer and the first conduction type semiconductor region of the super-junction voltage-resisting layer or in direct contact with the top region and the second conduction type semiconductor region of the super-junction voltage-resisting layer, and an emitter conductor covers the upper surface of the conductor region and is connected to the emitter through a lead.
3. The device of claim 1, wherein:
the doping concentration of the region of the buffer region, which is in contact with the collector region of the first conductivity type, is equal to the doping concentration of the auxiliary layer.
4. The device of claim 1, wherein:
the doping concentration of the carrier storage layer is higher than that of the first-conductivity-type semiconductor region of the super-junction voltage-resisting layer or equal to that of the first-conductivity-type semiconductor region of the super-junction voltage-resisting layer.
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