CN115148783A - Reverse-conducting super-junction IGBT (insulated Gate Bipolar transistor) with high-resistance p-top region - Google Patents

Reverse-conducting super-junction IGBT (insulated Gate Bipolar transistor) with high-resistance p-top region Download PDF

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CN115148783A
CN115148783A CN202110351484.4A CN202110351484A CN115148783A CN 115148783 A CN115148783 A CN 115148783A CN 202110351484 A CN202110351484 A CN 202110351484A CN 115148783 A CN115148783 A CN 115148783A
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马瑶
黄铭敏
杨治美
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Sichuan University
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Sichuan University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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  • Bipolar Transistors (AREA)

Abstract

The invention provides a Reverse Conducting super junction Insulated Gate Bipolar Transistor (IGBT) device, wherein a top area of a second Conducting type with higher resistivity is arranged above a semiconductor area of the second Conducting type in a super junction voltage-resisting layer, and the device comprises a back groove type insulating medium area, the side surface of which is surrounded by a floating area of the second Conducting type, and the top of which is surrounded by a stopping ring of a first Conducting type. The device has lower conduction voltage drop and can eliminate the voltage retracing phenomenon along with the current.

Description

Reverse-conducting super-junction IGBT (insulated Gate Bipolar transistor) with high-resistance p-top region
Technical Field
The invention belongs to a semiconductor device, in particular to a power semiconductor device.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a medium-high voltage power semiconductor switching device. A Super Junction (SJ) is a voltage-withstanding layer structure in which n columns and p columns are alternately arranged, and can enable the n columns and the p columns to obtain higher breakdown voltage under higher doping concentration. When the IGBT adopts a super-junction voltage-withstanding layer structure, a pn junction formed by the n column/p column can be quickly depleted in the turn-off process, so that the turn-off speed is increased (or the turn-off power consumption is reduced). However, in the common super junction IGBT, the conductivity modulation effect (or carrier storage effect) of the n column and the p column in the on state is poor, mainly because the p column easily collects holes and smoothly extracts the collected holes to the emitter, which makes it difficult to effectively store the holes in the n column and the p column, and increases the on-state voltage drop. In addition, an IGBT is usually used in combination with an antiparallel diode in application. In order to reduce parasitic effects and improve integration, a Reverse diode may also be integrated in the IGBT, which is called a Reverse Conducting IGBT (RC-IGBT). However, the conventional RC-IGBT generates a voltage-back (Snap-back) phenomenon with current, which is disadvantageous for reliable operation of the device.
Disclosure of Invention
Compared with the common reverse-conducting super-junction IGBT, the reverse-conducting super-junction IGBT device provided by the invention has lower conduction voltage drop and eliminates the phenomenon that voltage is folded along with current.
Referring to fig. 2 to 5, the present invention provides an inverse conduction type super junction insulated gate bipolar transistor device, wherein a cell structure of the device includes: a current collecting structure (composed of 10, 11, and 20), a lightly doped auxiliary layer 30 of the first conductivity type located above the current collecting structure (composed of 10, 11, and 20), a super junction voltage withstanding layer (composed of 31 and 32) located above the auxiliary layer 30, a base region (composed of 41 and 43) of the second conductivity type located above the super junction voltage withstanding layer (composed of 31 and 32), and a top region (composed of 42 and 45) of the second conductivity type, a heavily doped emitter region 44 of the first conductivity type in contact with at least part of the base region (composed of 41 and 43), and a trench type gate structure (composed of 47 and 49) for controlling a switch in contact with the emitter region 44, the base region (composed of 41 and 43), and the super junction voltage withstanding layer (composed of 31 and 32), characterized in that:
the collection structure (made up of 10, 11 and 20) is made up of at least one collector region 10 of the second conductivity type, at least one collector region 11 of the first conductivity type and at least one buffer region 20 of the first conductivity type; the lower surface of the buffer region 20 is in direct contact with both the collector region 10 of the second conductivity type and the collector region 11 of the first conductivity type, and the upper surface of the buffer region 20 is in direct contact with the auxiliary layer 30;
the cell structure comprises a back groove-shaped insulating medium region 12, and the back groove-shaped insulating medium region 12 extends into the auxiliary layer 30; the side surface of the back surface groove type insulating medium region 12 is in direct contact with the collector region 10 of the second conduction type, the collector region 11 of the first conduction type and the buffer region 20, and the collector region 10 of the second conduction type and the collector region 11 of the first conduction type are isolated from each other by the back surface groove type insulating medium region 12; the side surface of the back groove-shaped insulating medium region 12 is indirectly contacted with the auxiliary layer 30 through a floating space region 21 of the second conductivity type, and the top of the back groove-shaped insulating medium region 12 is indirectly contacted with the auxiliary layer 30 through a stop ring 22 of the first conductivity type; collector conductors 1 are covered on the lower surfaces of the collector region 11 of the first conductivity type, the collector region 10 of the second conductivity type and the back groove-shaped insulating medium region 12 and are connected to a collector C through a lead;
the super junction voltage-withstanding layer (composed of 31 and 32) is composed of first conductivity type semiconductor regions 31 and second conductivity type semiconductor regions 32 which are alternately arranged, and the side surfaces of the first conductivity type semiconductor regions 31 in the super junction voltage-withstanding layer and the side surfaces of the second conductivity type semiconductor regions 32 in the super junction voltage-withstanding layer are in contact with each other; the lower surface of the super junction voltage-resistant layer (composed of 31 and 32) is in direct contact with the auxiliary layer 30;
the lower surface of the base region (composed of 41 and 43) is in direct contact with the semiconductor region 31 of the first conductivity type in the super junction voltage-resistant layer; the upper surface of the base region (composed of 41 and 43) is at least partially covered with an emitter conductor 2 and is connected to an emitter E through a lead; at least one heavily doped region 43 in the base region (consisting of 41 and 43) is in direct contact with the emitter conductor 2 so as to form an ohmic contact;
the upper surface of the emitter region 44 is covered with an emitter conductor 2 and connected to the emitter E by a wire;
the lower surface of the top region (composed of 42 and 45) is in direct contact with the semiconductor region 32 of the second conductivity type in the super junction voltage-resistant layer, and the resistivity of the top region (composed of 42 and 45) in the vertical direction is higher than the resistivity of the semiconductor region 32 of the second conductivity type in the super junction voltage-resistant layer in the vertical direction; the upper surface of the top region (consisting of 42 and 45) is at least partially covered with an emitter conductor 2 and is connected to the emitter E by a wire; at least one heavily doped region 45 in the top region (consisting of 42 and 45) is in direct contact with the emitter conductor 2 so as to form an ohmic contact;
the heavily doped region 45 in the top region is indirectly contacted with the heavily doped region 43 in the base region through the semiconductor region 31 of the first conductivity type in the super junction voltage-resistant layer, or the heavily doped region 45 in the top region is directly contacted with the heavily doped region 43 in the base region to form a communicated heavily doped region 43; the region 42 in the top region, from which the heavily doped region is removed, is in indirect contact with the region 41 in the base region, from which the heavily doped region is removed, through the semiconductor region 31 of the first conductivity type in the super junction voltage-resistant layer;
the trench gate structure (consisting of 47 and 49) for controlling the switch comprises a first insulating dielectric layer 49 and a first conductor region 47 surrounded by the first insulating dielectric layer; the first insulating medium layer 49 is in direct contact with the emitter region 44, the base region (composed of 41 and 43) and the semiconductor region 31 of the first conductivity type in the super junction voltage-resisting layer; the upper surface of the first conductor region 47 is covered with a gate conductor 3 and is connected to the gate G through a wire;
the first conductor region 47 is composed of a heavily doped polycrystalline semiconductor material; when the first conduction type is n type, the second conduction type is p type; when the first conductivity type is p-type, the second conductivity type is n-type.
Referring to fig. 6, a trench gate structure (composed of 46 and 48) connected to an emitter is included above the second conductivity type semiconductor region 32 in the voltage-proof layer; the emitter-connected trench gate structure (composed of 46 and 48) comprises a second insulating dielectric layer 48 and a second conductor region 46 surrounded by the second insulating dielectric layer, wherein the second insulating dielectric layer 48 is in direct contact with the top region (composed of 42 and 45) and the second conductivity type semiconductor region 32 in the super junction voltage-withstanding layer, and the upper surface of the second conductor region 46 is covered with an emitter conductor 2 and is connected to the emitter E through a wire.
Drawings
FIG. 1 is a schematic diagram of a common reverse conducting super junction IGBT structure;
FIG. 2 shows a reverse conducting super junction IGBT of the invention, which comprises a p-type top region with resistivity higher than that of p column, p in the p-type top region + The region not being adjacent to p in the p-type base region + Region-connected emitter conductor covered in p + A zone;
FIG. 3 shows yet another reverse conducting super junction IGBT of the invention having a p-type top region with higher resistivity than the p-pillar, p in the p-type top region + P in region and p-type base region + Zone connected as a p + Region, emitter conductor overlying p + A zone;
FIG. 4 is yet another reverse conducting super junction IGBT of the present invention having a p-type top region with higher resistivity than the p-pillar, p in the p-type top region + P in region and p-type base region + Zone connected as a p + Region, emitter conductor overlying p + Removing p in the region and p-type top region + A region of a zone;
FIG. 5 is yet another reverse conducting super junction IGBT of the present invention having a p-type top region with higher resistivity than the p-pillar, p in the p-type top region + P in region and p-type base region + Zone connected as a p + Region, p-type top region upper surface portion is p + Region with emitter conductor overlying p + Removing p in regions not overlying p-type top regions + A region of a zone;
FIG. 6 shows a further reverse conducting super junction IGBT according to the invention with a trench gate structure over the p-pillar to connect the emitter according to FIG. 3;
fig. 7 shows forward conduction of the conventional reverse-conducting super-junction IGBT shown in fig. 1 and the reverse-conducting super-junction IGBT of the present invention shown in fig. 2I-VCurve line.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a conventional reverse conducting super-junction IGBT structure, in which a super-junction voltage-withstanding layer is composed of an n-pillar (n-pillar region 31) and a p-pillar (p-pillar region 32) for withstanding a main applied voltage, and a lightly doped n-type auxiliary layer (n-assist layer 30) also bearsThe n-type buffer region (n-buffer region 20) acts to cut off the electric field when a voltage is applied. In the reverse conducting state, the gate (G) is short-circuited with the emitter (E) which applies a positive voltage with respect to the collector (C). When the voltage exceeds 0.7V, the p-type base region (p-b region 41 and p) + Region 43) and p-pillar (p-pillar region 32) inject holes into the n-pillar (n-pillar region 31) and n-type assist layer (n-assist layer 30). At the same time, an n-type collector region (n) + Region 11) provides electrons that are injected into the p-type base region (p-b region 41 and p-type assist layer (n-assist layer 30) through the n-pillar (n-pilar region 31) and the n-type assist layer (n-assist layer 30) + Region 43) and p-pillar (p-pillar region 32), the reverse diode is conducting. In the forward conduction state, the gate (G) applies a positive voltage with respect to the emitter (E), and when this voltage exceeds a threshold voltage, the p-type base regions (p-b region 41 and p) + Region 43) forms an electron channel near the interface with the trench gate structure (comprised of 47 and 49) of the control switch. At this time, a positive voltage is applied to the collector electrode (C) with respect to the emitter electrode (E), and electrons pass from the emitter electrode (E) through the n-type emitter region (n) by the action of an electric field + Region 44) and electron channel into the n-pillar (n-pillar region 31), n-assist layer (n-assist layer 30), n-buffer region (n-buffer region 20), and then into the n-collector region (n-collector region) + Region 11) the device is in MOSFET conduction mode. When the positive voltage of the collector (C) relative to the emitter (E) continues to increase, the current continues to increase, electrons flow laterally through the n-type buffer region (n-buffer region 20) and generate a potential difference exceeding 0.7V across the n-type buffer region (n-buffer region 20), the p-type collector region (p-collector region 10) begins to inject holes into the n-type buffer region (n-buffer region 20), and the device transitions to the IGBT on mode. Since the unbalanced carriers can be stored in the n-type auxiliary layer (n-assist layer 30), the n-pillar (n-pillar region 31), and the p-pillar (p-pillar region 32) in the IGBT on mode, a conductivity modulation effect occurs in the body, and the resistance of the device decreases, which causes a voltage folding-back phenomenon with current. Further, when the device enters the IGBT conducting mode, since the pn junction of the p pillar (p-pillar region 32) and the n pillar (n-pillar region 31) is reverse biased, holes in the n pillar (n-pillar region 31) easily enter the p pillar (p-pillar region 32) and pass through the p-type base region(p-b region 41 and p + Region 43) is collected by the emitter (E). This results in a reduced storage effect of non-equilibrium carriers in the n column (n-pillar region 31) and the p column (p-pillar region 32), and an increased on-state voltage drop.
The invention mainly aims to overcome the defects that the common reverse conduction type super-junction IGBT shown in figure 1 has a voltage retracing phenomenon along with current and has high conduction voltage drop.
FIG. 2 is a schematic diagram of a reverse conducting super junction IGBT cell structure of the present invention, which is mainly different from the ordinary reverse conducting super junction IGBT shown in FIG. 1 in that (1) a p-type top region (composed of a p-top region 42 and a p-pillar region 32) with higher resistivity is introduced above a p-pillar (p-pillar region 32) + Region 45) and a p-type top region (consisting of p-top region 42 and p) + Region 45) from which the heavily doped region was removed (p-b region 41) and the p-type base region (p-b region 41 and p) + Region 43) with n pillars (n-pillar region 31) between them, the path for holes to flow from the p pillars (p-pillar region 32) to the emitter (E) is more resistive, thereby enhancing the conductivity modulation effect in the on-state; (2) A back groove type insulating medium region (12), a p-type floating region (p region 21) and an n-type stop ring (n-ring region 22) are introduced into the back surface, and the phenomenon that voltage is folded along with current is eliminated.
At zero bias, depletion of the n-type auxiliary layer (n-assist region 30) between two adjacent p-type floating regions (p regions 21) occurs due to the built-in potential between the p-type floating region (p region 21) and the n-type auxiliary layer (n-assist layer 30), e.g., 0.7V. When the pitch of the adjacent two p-type floating regions (p regions 21) is sufficiently small, the n-type auxiliary layer (n-assist region 30) between them can be completely depleted, which allows the n-type collector region (n-assist region 30) to be reached from the neutral region of the n-type auxiliary layer + Region 11) is turned off.
In the forward conduction state, when a positive voltage applied between the gate (G) and the emitter (E) is greater than a threshold voltage of a trench-type gate structure (composed of 47 and 49) for controlling a switch, the p-type base regions (p-b region 41 and p-b region) + Region 43) and a trench gate structure (consisting of 47 and 49) for controlling the switch, an electron accumulation layer channel, an emitter region（n + Region 44) to the n-pillar (n-pilar region 31). Electrons pass from the emitter (E) through the emitter region (n) due to a positive voltage applied between the collector (C) and the emitter (E) + Region 44) and electron accumulation layer channel into the n-pillar (n-pilar region 31) and n-type assist layer (n-assist layer 30). From the neutral region of the n-type auxiliary layer (n-assist layer 30) to the n-type collector region (n) + Region 11) is turned off, electrons that have entered the n-type auxiliary layer (n-assist layer 30) enter the p-type collector region (p-collector region 10), thereby causing holes to be injected from the p-type collector region (p-collector region 10) into the n-type auxiliary layer (n-assist layer 30), and the device directly enters the IGBT conduction mode, so that the voltage folding back phenomenon with current is eliminated.
Further, above the p-pillar (p-pillar region 32) is a p-type top region (composed of p-top region 42 and p-pillar region) + Region 45) with a p-type top region in the vertical direction (consisting of p-top region 42 and p) + Region 45) is higher than the p-pillar (p-pilar region 32) and the p-type top region (composed of p-top region 42 and p-pillar region 32) + Region 45) is connected to the p-type base region (formed by p-base region 41 and p-pillar region 31) via an n-pillar + Region 43) is formed. In the forward conduction state, holes enter the p-pillar (p-pilar region 32) and pass up the p-type top region (formed by p-top region 42 and p-pillar region) + Region 45) towards the emitter (E). Due to the p-type top region (formed by p-top region 42 and p) + Region 45) is higher than the p-pillar (p-pilar region 32), the p-type top region (composed of p-top region 42 and p-pillar region) + Region 45) the voltage drop caused by the hole current is not negligible and the potential of the p-pillar (p-pillar region 32) is therefore raised. When the p-type top region (composed of p-top region 42 and p) + Region 45) is sufficiently high, the potential of the p pillar (p-pillar region 32) is raised to 0.7V, and the p pillar/n pillar junction (pn junction formed by p-pillar region 32 and n-pillar region 31) becomes a positive bias junction, so that the concentration of non-equilibrium carriers in the vicinity of the p pillar/n pillar junction (pn junction formed by p-pillar region 32 and n-pillar region 31) is higher, the conductivity modulation effect in the body is enhanced, and the conduction voltage drop is reduced.
It should be noted that the above-mentioned top region of p-type in the vertical direction (composed of p-top region 42 and p-top region) + Region 45) refers to the entire p-type top region (formed by p-top region 42 and p) + Region 45) from bottom to top, rather than the p-type top region (comprised of p-top region 42 and p-top region) + Region 45) in the vertical direction. Of course, when the p-type top region (formed by p-top region 42 and p) + Region 45) have a doping concentration in the horizontal direction that is much lower than the doping concentration of the other regions, the p-type top region (formed by p-top region 42 and p-top region) + Region 45) is located in a region where the doping concentration in the horizontal direction is lowest for the resistance with the greatest conduction in the vertical direction, which will significantly affect the entire p-type top region (formed by p-top region 42 and p-top region) + Region 45) resistivity in the vertical direction. Therefore, in order to make the p-type top region (from p-top region 42 and p) + Region 45) has a higher resistivity than the p-pillars (p-pillar region 32), and the heavily doped region (p) is removed in the p-type top region (p-pillar region) + Region 45) (p-top region 42) may have a gaussian doping profile in the vertical direction and the doping concentration at the interface with the p-pillars (p-pillar region 32) is much lower than the average doping concentration of the p-pillars (p-pillar region 32).
In addition, a p-type top region (defined by p-top region 42 and p) + Region 45) is a heavily doped region (p) + Zone 45). The heavily doped region (p) + Region 45) for connecting emitter conductor 2 to the p-type top region (formed by p-top region 42 and p) + Region 45) form a good ohmic contact. Of course, overlying the p-type top region (formed by p-top region 42 and p + Region 45) does not necessarily have to cover only the heavily doped region (p) + Region 45), or a portion thereof may be overlaid in the p-type top region to remove the heavily doped region (p) + Region 45) (p-top region 42). Furthermore, a p-type top region (formed by p-top region 42 and p) + Region 45) of the substrate is heavily doped (p) + Region 45) may also be associated with the p-type base region (formed by p-base region 41 and p) + Region 43) of the substrate is heavily doped (p) + Zone 43) are connected.
In FIG. 3, the main difference from the structure of FIG. 2 is the p-type top region (formed by p-top region 42 and p-top region) + Region 45) of the substrate + Region 45) and p-type base region (formed by p-base region 41 and p) + Region 43) of the substrate is heavily doped (p) + Region 43) is connected to a p-type heavily doped region (p) + Zone 43).
In FIG. 4, the main difference from the structure of FIG. 3 is that the p-type top region (formed by p-top region 42 and p-top region) + Region 45) is a region (p-top region 42) where the heavily doped region is removed, and emitter conductor 2 overlies the p-type heavily doped region (p-top region) + Region 43) and a region in the p-type top region (p-top region 42) where the p-type heavily doped region is removed.
In fig. 5, the main difference with the structure of fig. 4 is that the emitter conductor 2 covers a heavily p-doped region (p) + Region 43) but does not overlie the region in the p-type top region where the p-type heavily doped region is removed (p-top region 42).
In fig. 6, the main difference from the structure of fig. 3 is that there is also a trench gate structure (consisting of 46 and 48) over the p-pillar (p-pilar region 32) that connects the emitter. When the density of the trench type gate structures (composed of 46 and 48, and composed of 47 and 49) is increased, it is helpful to alleviate the electric field concentration effect at the bottom of the trench type gate structures.
In order to illustrate the superiority of the reverse-conducting super-junction IGBT according to the present invention, the structure of the reverse-conducting super-junction IGBT according to the present invention shown in fig. 2 is used as an example to compare with the conventional reverse-conducting super-junction IGBT shown in fig. 1. The structures in fig. 1 and fig. 2 both adopt Si materials, and adopt a symmetrical super junction voltage-resistant structure, the minority carrier lifetime of electrons and holes is 5 μ s, and the width of half a cell is 6 μm; the insulating medium layers (48 and 49) adopt SiO 2 The thickness of the film is 0.1 mu m; the insulating medium region (12) adopts SiO 2 With a width and depth of 1 μm and 5 μm, respectively; the thickness and doping concentration of the n-pillar (n-pillar region 31) and the p-pillar (p-pillar region 32)N pillar Respectively 70 μm and 3X 10 15 cm -3 (ii) a The thickness of the region (p-top region 42) in the p-type top region excluding the heavily doped region,The highest concentration and the lowest concentration are respectively 3 μm and 7 × 10 14 cm -3 And 1X 10 14 cm -3 (ii) a The thickness and doping concentration of the n-type assist layer (n-assist layer 30) were 20 μm and 5 × 10, respectively 13 cm -3； The n-type buffer region (n-buffer region 20) has a thickness and a doping concentration peak of 2 μm and 5 × 10, respectively 16 cm -3 (ii) a The width, thickness and doping concentration peak of the p-type collector region (p-collector region 10) were 3.5 μm,1 μm and 1 × 10, respectively 18 cm -3 (ii) a n type collector region (n) + Region 11) has a width, thickness and doping concentration peak of 1.5 μm,1 μm and 1X 10, respectively 18 cm -3 (ii) a The peak concentration at the interface of the n-type stop ring (n-ring region 22) and the back groove type insulating medium region (12) is 3 multiplied by 10 18 cm -3 The diffusion length is 0.3 μm; the peak concentration at the interface of the p-type floating empty region (p region 21) and the back groove-type insulating medium region (12) is 2 multiplied by 10 16 cm -3 The diffusion length was 0.4. Mu.m.
FIG. 7 is a forward conduction of the structure of FIG. 2 and the structure of FIG. 1I-VCurve of the grid voltageV G = 15V. Conduction drop (current density ofJ C = 100 A/cm 2 Lower) is only 1.5V, while the conduction voltage drop for the structure of fig. 1 is 3.5V. In addition, the structure of FIG. 2 has no voltage-dependent current folding phenomenon, while the peak doping concentration of the n-type buffer region (n-buffer region 20) in the structure of FIG. 1 is only 3 × 10 14 cm -3 (much less than the peak doping concentration of the n-buffer region 20 in the structure of fig. 2), but there is still a voltage-to-current foldback. If the structure of FIG. 1 is to ensure sufficient withstand voltage, the peak doping concentration of the n-type buffer region (n-buffer region 20) is increased to 10 16 cm -3 The thickness of the n-type auxiliary layer (n-assist layer 30) is either of an order or increased to prevent electric field from passing through to the p-type collector region (p-collector region 10). For the case of increasing the doping concentration peak of the n-type buffer region (n-buffer region 20), if the voltage folding phenomenon along with the current is to be eliminated, the width of the p-type collector region (p-collector region 10) is to be greatly widened so as to greatly increase the resistance of the n-type buffer region (n-buffer region 20) in the lateral direction, but this will cause the reverse conduction to occurThe current is more concentrated in a narrow region in the vertical direction of the n-type buffer region (n-buffer region 20), which is disadvantageous in reliability. In the case of increasing the thickness of the n-type auxiliary layer (n-assist layer 30), a further increase in on-voltage and an increase in off-power consumption are caused due to the increase in the thickness of the n-type auxiliary layer (n-assist layer 30). The structure of fig. 2 therefore has a significant advantage over the structure of fig. 1.
In the above description of many embodiments of the present invention, the n-type semiconductor material can be regarded as a first conductive type semiconductor material, and the p-type semiconductor material can be regarded as a second conductive type semiconductor material. Obviously, according to the principle of the present invention, the n-type and the p-type in the embodiments can be interchanged without affecting the content of the present invention. It is obvious to a person skilled in the art that many other embodiments are possible within the inventive idea without going beyond the claims of the invention.

Claims (2)

1. A reverse conducting super junction insulated gate bipolar transistor device comprises a unit cell structure, wherein the unit cell structure comprises: the semiconductor device comprises a current collection structure, an auxiliary layer, a super-junction voltage-withstanding layer, a base region, a top region, a heavily doped emitter region and a groove-shaped gate structure, wherein the auxiliary layer is located above the current collection structure and is of a lightly doped first conductive type, the super-junction voltage-withstanding layer is located above the auxiliary layer, the base region is located above the super-junction voltage-withstanding layer and is of a second conductive type, the heavily doped emitter region is at least partially contacted with the base region, and the groove-shaped gate structure is contacted with the emitter region, the base region and the super-junction voltage-withstanding layer and is used for controlling a switch, and the semiconductor device is characterized in that:
the current collection structure is composed of at least one collector region of a second conduction type, at least one collector region of a first conduction type and at least one buffer region of a first conduction type; the lower surface of the buffer area is in direct contact with the collector area of the second conduction type and the collector area of the first conduction type, and the upper surface of the buffer area is in direct contact with the auxiliary layer;
the cellular structure comprises a back groove-shaped insulating medium region which extends into the auxiliary layer; the side surface of the back surface groove-type insulating medium region is in direct contact with the collector region of the second conduction type, the collector region of the first conduction type and the buffer region, and the collector region of the second conduction type and the collector region of the first conduction type are isolated from each other by the back surface groove-type insulating medium region; the side surface of the back groove-shaped insulating medium region is in contact with the auxiliary layer through a second conductive type floating space region, and the top of the back groove-shaped insulating medium region is in contact with the auxiliary layer through a first conductive type stopping ring; collector conductors are covered on the lower surfaces of the collector region of the first conduction type, the collector region of the second conduction type and the back groove-shaped insulating medium region and are connected to collectors through wires;
the super-junction voltage-withstanding layer is composed of semiconductor regions of a first conductivity type and semiconductor regions of a second conductivity type which are alternately arranged, and the side surfaces of the semiconductor regions of the first conductivity type in the super-junction voltage-withstanding layer and the side surfaces of the semiconductor regions of the second conductivity type in the super-junction voltage-withstanding layer are in contact with each other; the lower surface of the super junction voltage-resistant layer is in direct contact with the auxiliary layer;
the lower surface of the base region is in direct contact with a first-conductivity-type semiconductor region in the super-junction voltage-resistant layer; at least part of the upper surface of the base region is covered with an emitter conductor and is connected to the emitter through a lead; at least one heavily doped region in the base region is in direct contact with the emitter conductor so as to form ohmic contact;
the upper surface of the emitting region is covered with an emitter conductor and is connected to the emitter through a lead;
the lower surface of the top region is in direct contact with the semiconductor region of the second conduction type in the super junction voltage-resisting layer, and the resistivity of the top region in the vertical direction is higher than that of the semiconductor region of the second conduction type in the super junction voltage-resisting layer in the vertical direction; the upper surface of the top area is at least partially covered with an emitter conductor and is connected to the emitter through a lead; at least one heavily doped region in the top region in direct contact with the emitter conductor so as to form an ohmic contact;
the heavily doped region in the top region is indirectly contacted with the heavily doped region in the base region through a first conductive type semiconductor region in the super junction voltage-resisting layer, or the heavily doped region in the top region is directly contacted with the heavily doped region in the base region to form a communicated heavily doped region; the region of the top region, from which the heavy doping region is removed, is in indirect contact with the region of the base region, from which the heavy doping region is removed, through a first conductivity type semiconductor region in the super junction voltage-resistant layer;
the groove-shaped grid structure for controlling the switch comprises a first insulating medium layer and a first conductor region surrounded by the first insulating medium layer; the first insulating medium layer is in direct contact with the emitter region, the base region and the first conductive type semiconductor region in the super junction voltage-resisting layer; the upper surface of the first conductor region is covered with a grid conductor and is connected to the grid through a lead;
the first conductor region is composed of a heavily doped polycrystalline semiconductor material; when the first conduction type is n type, the second conduction type is p type; when the first conductivity type is p-type, the second conductivity type is n-type.
2. The device of claim 1, wherein:
a groove-shaped grid structure connected with an emitter is arranged above the second-conductivity-type semiconductor region in the super-junction voltage-resisting layer; the groove-shaped grid structure connected with the emitter comprises a second insulating medium layer and a second conductor region surrounded by the second insulating medium layer, the second insulating medium layer is in direct contact with the top region and a second conduction type semiconductor region in the super junction voltage-resisting layer, and an emitter conductor covers the upper surface of the second conductor region and is connected to the emitter through a wire.
CN202110351484.4A 2021-03-31 2021-03-31 Reverse-conducting super-junction IGBT (insulated Gate Bipolar transistor) with high-resistance p-top region Pending CN115148783A (en)

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