CN110911481B - Reverse conducting IGBT (insulated Gate Bipolar translator) containing floating space area and termination ring - Google Patents
Reverse conducting IGBT (insulated Gate Bipolar translator) containing floating space area and termination ring Download PDFInfo
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- CN110911481B CN110911481B CN201911212951.4A CN201911212951A CN110911481B CN 110911481 B CN110911481 B CN 110911481B CN 201911212951 A CN201911212951 A CN 201911212951A CN 110911481 B CN110911481 B CN 110911481B
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The invention provides a Reverse Conducting Insulated Gate Bipolar Transistor (RC-IGBT) device, which comprises a back groove type Gate structure. And the top of the back groove type grid structure is provided with a termination ring of a first conduction type, and two sides of the back groove type grid structure are in direct contact with a floating zone of a second conduction type. The stop ring is used for reducing an electric field near the top of the back groove type grid structure, and the floating space area is used for inhibiting a snap-back phenomenon.
Description
Technical Field
The invention belongs to a semiconductor device, in particular to a semiconductor power device.
Background
A Reverse Conducting Insulated Gate Bipolar Transistor (RC-IGBT) is a device in which an IGBT and an antiparallel diode are integrated into one chip. The reverse conducting insulated gate bipolar transistor (RC-IGBT) can improve the integration level, reduce the parasitic inductance and reduce the packaging cost. However, the conventional RC-IGBT generates a phenomenon in which a current varies with a voltage flyback (Snap-back), which adversely affects power consumption and reliability of the device. The inventor's prior chinese patent application (application number: 2018103973557) proposed a reverse conducting IGBT with a back side trench gate in which heavily doped p-type polysilicon is used. However, this structure requires a smaller back-side trench gate pitch in order to completely suppress the fold-back phenomenon, and the effect of suppressing the fold-back phenomenon is also easily affected by the gate oxide charge in the back-side trench gate structure.
Disclosure of Invention
The invention aims to provide a reverse conducting type insulated gate bipolar transistor (RC-IGBT) device, compared with a common RC-IGBT, the RC-IGBT device eliminates a Snap-back phenomenon, and the influence of the space between back groove type grid structures and grid oxide charges on the effect of restraining the Snap-back phenomenon is small.
The invention provides a reverse conducting type insulated gate bipolar transistor device, wherein a cellular structure of the device comprises: a reverse conducting type insulated gate bipolar transistor device, the cellular structure of which comprises: a drift region 21 of a lightly doped first conductivity type, a collector structure (composed of 10, 11 and 20) in contact with a bottom plane of the drift region 21, a base region (composed of 30 and 32) of a second conductivity type in contact with a top plane of the drift region 21, an emitter region 31 of the heavily doped first conductivity type in contact with at least part of the base region (composed of 30 and 32), a trench gate structure (composed of 33 and 34) for controlling a switch in contact with all of the emitter region 31, the base region (composed of 30 and 32) and the drift region 21, a collector C formed of a conductor 1 covering the collector structure (composed of 10, 11 and 20), an emitter E formed of a conductor 2 covering the emitter region 31 and the base region (composed of 30 and 32), a gate G formed of a conductor 3 covering the trench gate structure (composed of 33 and 34) for controlling a switch, characterized in that (see fig. 1-5):
the collection structure (made up of 10, 11 and 20) is made up of at least one collector region 10 of the second conductivity type, at least one collector region 11 of the first conductivity type and at least one buffer region 20 of the first conductivity type; the bottom plane of the buffer region 20 is in direct contact with both the collector region 10 of the second conductivity type and the collector region 11 of the first conductivity type, and the top plane of the buffer region 20 is in direct contact with the bottom plane of the drift region 21;
the collector region 10 of the second conductivity type is isolated from the collector region 11 of the first conductivity type by at least one first kind of back side trench gate structure (consisting of 12 and 35); the top of the first type of back side trench gate structure (composed of 12 and 35) is in direct contact with the termination ring 22 of the first conductivity type, and two sides of the first type of back side trench gate structure (composed of 12 and 35) are in direct contact with the floating region 24 of the second conductivity type; the first kind of back side trench gate structure (consisting of 12 and 35) is not in direct contact with the drift region 21 but in indirect contact with the drift region 21 through the floating regions 24 of the second conductivity type and the stop ring 22 of the first conductivity type; the first type of back-side trench gate structure (comprised of 12 and 35) includes at least one first insulating dielectric layer 35 and at least one first conductor region 12, the first insulating dielectric layer 35 is in direct contact with the collector region 10 of the second conductivity type, the collector region 11 of the first conductivity type, the buffer region 20, the floating region 24 of the second conductivity type, and the stop ring 22 of the first conductivity type, the first conductor region 12 is in direct contact with the first insulating dielectric layer 35 and is isolated from the collector region 10 of the second conductivity type, the collector region 11 of the first conductivity type, the buffer region 20, the floating region 24 of the second conductivity type and the stop ring 22 of the first conductivity type by the first insulating dielectric layer 35, and the first conductor region 12 is made of a heavily doped polycrystalline semiconductor material or metal; the collector region 10 of the second conductivity type, the collector region 11 of the first conductivity type and the first conductor region 12 are in direct contact with the collector C;
the cell structure comprises a second type of back groove type grid structure (composed of 12 and 35) or does not comprise the second type of back groove type grid structure (composed of 12 and 35); the top of the second type of back side trench gate structure (composed of 12 and 35) is in direct contact with the termination ring 22 of the first conductivity type, and both sides of the second type of back side trench gate structure (composed of 12 and 35) are in direct contact with the floating region 24 of the second conductivity type; the second type of back side trench gate structure (consisting of 12 and 35) is not in direct contact with the drift region 21 but in indirect contact with the drift region 21 through the floating regions 24 of the second conductivity type and the stop ring 22 of the first conductivity type; the second type of back side trench gate structure (comprised of 12 and 35) includes at least one second insulating dielectric layer 14 and at least one second conductor region 13, the second insulating dielectric layer 14 is in direct contact with the collector region 11 of the first conductivity type, the buffer region 20, the floating region 24 of the second conductivity type and the termination ring 22 of the first conductivity type without being in direct contact with the collector region 10 of the second conductivity type, the second conductor region 13 is in direct contact with the second insulating dielectric layer 14 and is isolated from the collector region 11 of the first conductivity type, the buffer region 20, the floating region 24 of the second conductivity type and the termination ring 22 of the first conductivity type by the second insulating dielectric layer 14, the second conductor region 13 is made of a heavily doped polycrystalline semiconductor material or metal, and the second conductor region 13 is in direct contact with the collector C;
the cell structure comprises a third back groove type grid structure (composed of 12 and 35) or does not comprise the third back groove type grid structure (composed of 12 and 35); the top of the third type of back side trench gate structure (composed of 12 and 35) is in direct contact with the termination ring 22 of the first conductivity type, and both sides of the third type of back side trench gate structure (composed of 12 and 35) are in direct contact with the floating region 24 of the second conductivity type; the third kind of back side trench gate structure (composed of 12 and 35) is not in direct contact with the drift region 21 but in indirect contact with the drift region 21 through the floating region 24 of the second conductivity type and the stop ring 22 of the first conductivity type; the third type of back side trench gate structure (comprised of 12 and 35) includes at least one third insulating dielectric layer 16 and at least one third conductor region 15, the third insulating dielectric layer 16 is in direct contact with the collector region 10 of the second conductivity type, the buffer region 20, the floating region 24 of the second conductivity type and the termination ring 22 of the first conductivity type without being in direct contact with the collector region 11 of the first conductivity type, the third conductor region 15 is in direct contact with the third insulating dielectric layer 16 and is isolated from the collector region 10 of the second conductivity type, the buffer region 20, the floating region 24 of the second conductivity type and the termination ring 22 of the first conductivity type by the third insulating dielectric layer 16, the third conductor region 15 is made of a heavily doped polycrystalline semiconductor material or metal, the third conductor region 15 being in direct contact with the collector C;
the groove-type gate structure (composed of 33 and 34) for controlling the switch comprises at least one fourth insulating medium layer 34 and at least one fourth conductor region 33, wherein the fourth insulating medium layer 34 is in direct contact with the emitter region 31, the base region (composed of 30 and 32) and the drift region 21, the fourth conductor region 33 is in direct contact with the fourth insulating medium layer 34 and is isolated from the emitter region 31, the base region (composed of 30 and 32) and the drift region 21 through the fourth insulating medium layer 34, the fourth conductor region 33 is composed of heavily doped polycrystalline semiconductor material or metal, and the fourth conductor region 33 is in direct contact with the gate G;
at least one heavily doped region 32 of the base region (consisting of 30 and 32) is in direct contact with the emitter E so as to form an ohmic contact.
Referring to fig. 6 to 8, the drift region 21 is not in direct contact with the base region (composed of 30 and 32) but in indirect contact with the base region (composed of 30 and 32) through a carrier storage layer 23 of the first conductivity type; the doping concentration of the carrier storage layer 23 is higher than that of the drift region 21; the fourth insulating medium layer 34 is in direct contact with the carrier storage layer 23.
Referring to fig. 9-11, the regions of the buffer region 20 in contact with both the collector region 11 of the first conductivity type and the drift region 21 are replaced by the drift region 21, making the regions of the buffer region 20 in contact with both the collector region 11 of the first conductivity type and the drift region 21 a part of the drift region 21; the region of the buffer 20 in contact with both the collector region 11 of the first conductivity type and the floating region 24 of the second conductivity type is replaced with the floating region 24 of the second conductivity type, and the region of the buffer 20 in contact with both the collector region 11 of the first conductivity type and the floating region 24 of the second conductivity type becomes a part of the floating region 24 of the second conductivity type.
Referring to fig. 12, the cell structure includes a first trench gate structure (composed of 37 and 36) connected to an emitter E; the first trench gate structure (composed of 37 and 36) connected with the emitter E comprises at least one fifth insulating medium layer 37 and at least one fifth conductor region 36, the fifth insulating medium layer 37 is in direct contact with the base region (composed of 30 and 32) and the drift region 21, the fifth conductor region 36 is in direct contact with the fifth insulating medium layer 37 and is isolated from the base region (composed of 30 and 32) and the drift region 21 through the fifth insulating medium layer 37, the fifth conductor region 36 is composed of heavily doped polycrystalline semiconductor material or metal, and the fifth conductor region 36 is in direct contact with the emitter E.
Referring to fig. 13, the cell structure includes a second trench gate structure (composed of 38 and 39) connected to the emitter E; the second trench gate structure (composed of 38 and 39) connected with the emitter E comprises at least one sixth insulating medium layer 39 and at least one sixth conductor region 38, the sixth insulating medium layer 39 is in direct contact with the base region (composed of 30 and 32), the carrier storage layer 23 and the drift region 21, the sixth conductor region 38 is in direct contact with the sixth insulating medium layer 39 and is isolated from the base region (composed of 30 and 32), the carrier storage layer 23 and the drift region 21 through the sixth insulating medium layer 39, the sixth conductor region 38 is made of heavily doped polycrystalline semiconductor material or metal, and the sixth conductor region 38 is in direct contact with the emitter E.
Referring to fig. 1 to 13, under a zero volt applied between the collector C and the emitter E, the drift region 21 between the adjacent two floating regions 24 of the second conductivity type in direct contact with the first type of back side trench gate structure (composed of 12 and 35) is completely depleted, the drift region 21 between the adjacent two floating regions 24 of the second conductivity type in direct contact with the second type of back side trench gate structure (composed of 13 and 14) is completely depleted, and the drift region 21 between the adjacent floating regions 24 of the second conductivity type in direct contact with the first type of back side trench gate structure (composed of 12 and 35) and the floating regions 24 of the second conductivity type in direct contact with the second type of back side trench gate structure (composed of 13 and 14) is completely depleted.
Referring to fig. 1 to 13, the total number of effective impurity dopings in the floating-out region 24 of the second conductive type is smaller than the total number of effective impurity dopings in the buffer region 20; the total number of effective impurity dopings in the floating-out region 24 of the second conductivity type is smaller than the total number of effective impurity dopings in the termination region 22 of the first conductivity type.
Drawings
FIG. 1 is a RC-IGBT of the present invention having a first back side trench gate structure;
FIG. 2 is a further RC-IGBT of the present invention having a first back side trench gate structure and a second back side trench gate structure;
FIG. 3 is a schematic diagram of another RC-IGBT according to the present invention, which has a second type of back trench gate structure between the first type of back trench gate structures and has no second type of back trench gate structure between the first type of back trench gate structures;
FIG. 4 is a schematic diagram of yet another RC-IGBT of the present invention having a first, a second and a third back trench gate structure;
FIG. 5 shows another RC-IGBT of the present invention, which has two second back trench gate structures between two first back trench gate structures;
FIG. 6 shows a further RC-IGBT according to the present invention with a carrier storage layer between the base region and the drift region according to FIG. 1;
FIG. 7 shows a further RC-IGBT according to the present invention with a carrier storage layer between the base region and the drift region according to FIG. 2;
FIG. 8 is a view showing another RC-IGBT according to the present invention, in which a carrier storage layer is disposed between the base region and the drift region, according to FIG. 4;
FIG. 9 shows a further RC-IGBT according to the present invention, in which the buffer region has a portion in contact with the collector region and the drift region of the first conductivity type and a portion in contact with the collector region and the floating gate region of the first conductivity type;
FIG. 10 shows a further RC-IGBT according to the present invention, in which the buffer region has a part of the drift region in contact with the collector region and the drift region of the first conductivity type, and the buffer region has a part of the floating region in contact with the collector region and the floating region of the first conductivity type, according to FIG. 2;
FIG. 11 is a view showing another RC-IGBT according to the present invention, in which the buffer region has a region in contact with the collector region and the drift region of the first conductive type as a part of the drift region, and the buffer region has a region in contact with the collector region and the floating gate region of the first conductive type as a part of the drift region, according to FIG. 4;
FIG. 12 is a further RC-IGBT of the present invention having a first trench gate structure connected to the emitter according to FIG. 1;
FIG. 13 is a further RC-IGBT of the present invention having a second trench gate structure for emitter connection according to FIG. 6;
FIG. 14 is a reverse I-V curve for the RC-IGBT of the present invention in FIG. 1 and a forward I-V curve for the RC-IGBT of the present invention and a comparative structure in FIG. 1.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
The main purpose of the present invention is to suppress the Snap-back phenomenon of an RC-IGBT.
Fig. 1 is a schematic diagram of an RC-IGBT cell structure according to the present invention, which includes two types of trench gate structures. One is a trench gate structure (composed of the fourth conductor region 33 and the fourth insulating medium layer 34) connected with the gate (G) and used for controlling the switch, and the other is a first back trench gate structure (composed of the first conductor region 12 and the first insulating medium layer 35) connected with the collector (C), wherein the first insulating medium layer (35) and the fourth insulating medium layer (34) can be SiO2The dielectric layer, the fourth conductor region (33) may be a heavily doped n-type or p-type polysilicon material, and the first conductor region (12) may be a heavily doped n-type or p-type polysilicon material. The top of the first type of back side trench gate structure (composed of 12 and 35) is in direct contact with a termination ring (n-ring region 22) of the first conductivity type, and both sides of the first type of back side trench gate structure (composed of 12 and 35) are in direct contact with a floating region (p-float region 24) of the second conductivity type and are not in direct contact with the drift region (n-region 21). The first type of back-side trench gate structure (consisting of 12 and 35) connects the collector region of the second conductivity type (p-collector region 10) with the collector region of the first conductivity type (n)+The zones 11) are isolated from each other. The first type of back trench gate structure (formed by 12 and 35) extends deep into the drift region (n-region 21) and is connected to the collector region of the second conductivity type (p-collector region 10) and the collector region of the first conductivity type (n-collector region)+Region 11), buffer region (n-buffer region 20), floating region of the second conductivity type (p-float region 24), and termination ring of the first conductivity type (n-ring region 22) are all in contact. Note that the base region (formed by p-base regions 30 and p)+Region 32) is formed) of a heavily doped region (p)+Region 32) is a heavily doped region (p-base region 30) in the base region when the doping concentration at the surface of the base region is sufficiently high to form a good ohmic contact with the emitter (E)+Region 32) is not required.
At zero bias, depletion of the drift region (n-region 21) between two adjacent floating regions of the second conductivity type (p-float regions 24) occurs due to the built-in potential, e.g., 0.7V, between the floating regions of the second conductivity type (p-float regions 24) and the drift region (n-region 21). When the distance between two adjacent floating regions (p-float regions 24) of the second conductivity type is sufficiently small, the drift region (n-region 21) between them can be completely depleted, which allows the drift region (n-region 21) to go from the neutral region to the collector region (n) of the first conductivity type+Region 11) is closed. Further, when a positive voltage applied between the gate (G) and the emitter (E) is greater than a threshold voltage of a trench type gate structure (composed of 33 and 34) for controlling a switch, the base region (composed of p-base region 30 and p)+Region 32) and a trench gate structure (composed of 33 and 34) for controlling the switch, an emitter region (n)+Region 31) to the drift region (n-region 21). If a positive voltage is applied between the collector (C) and the emitter (E), electrons pass from the emitter (E) through the emitter region (n)+Region 31) and electron accumulation layer channel into the drift region (n-region 21). From the neutral region of the drift region (n-region 21) to the collector region (n) of the first conductivity type+Region 11) is turned off, electrons entering the drift region (n-region 21) may enter the collector region of the second conductivity type (p-collector region 10), thereby causing holes to be injected from the collector region of the second conductivity type (p-collector region 10) into the drift region (n-region 21), and finally the device is turned on.
In fig. 2, the main difference from the structure of fig. 1 is that there is also a second kind of back trench gate structure (consisting of 13 and 14) in the cell. The second type of back side trench gate structure (composed of 13 and 14) is different from the first type of back side trench gate structure (composed of 12 and 35) in that the former is not in contact with the collector region (p-collector region 10) of the second conductivity type. The second type of back side trench gate structure (consisting of 13 and 14) acts in conjunction with the first type of back sideThe trench gate structures (formed by 12 and 35) all function in the same way by depleting the drift region (n-region 21) by the potential difference between the floating region (p-float region 24) of the second conductivity type and the drift region (n-region 21) in contact with them to increase the current from the drift region (n-region 21) to the collector region (n-region 21) of the first conductivity type+Resistance on the electron path of region 11); the difference between the two is mainly the difference in position, and the second type of back side trench gate structure (composed of 12 and 35) is located between the two first type of back side trench gate structures (composed of 12 and 35) and is not in contact with the collector region (p-collector region 10) of the second conductivity type. From the foregoing discussion, it is known that, in order to avoid the snapback phenomenon, the width of the drift region (n-region 21) between the two floating regions (p-float regions 24) of the second conductivity type is limited, such as to be less than or equal to 3 μm; in fig. 1, only the first type of back-side trench gate structure (consisting of 12 and 35), the collector region of the first conductivity type (n)+The width of the region 11) is also limited, for example, 3 μm or less. After adding a second back-side trench gate structure (consisting of 13 and 14) in fig. 2, a collector region of the first conductivity type (n) in one cell+Region 11) can be increased, the collector region (n) of the first conductivity type+The ratio of the areas of the region 11) and the second conductive type collector region (p-collector region 10) can be increased.
In fig. 3, there are two first type back side trench gate structures (consisting of 12 and 35) with the second type back side trench gate structure (consisting of 13 and 14) in between, and there are two first type back side trench gate structures (consisting of 12 and 35) with no second type back side trench gate structure (consisting of 13 and 14) in between. Therefore, after the second type of back groove type grid structure (composed of 13 and 14) is added, the collector region (n) of the first conduction type can be flexibly adjusted+Region 11) to the area of the collector region of the second conductivity type (p-collector region 10).
In fig. 4, the main difference from the structure of fig. 3 is that there is a third kind of back trench gate structure (consisting of 15 and 16) in the cell. The third type of back side trench gate structure (consisting of 15 and 16) differs from the first type of back side trench gate structure (consisting of 12 and 35) in that the former is not the same as the second typeCollector region of one conductivity type (n)+Zone 11) are in contact.
In fig. 5, the main difference from the structure of fig. 3 is that there are two first type back side trench gate structures (consisting of 12 and 35) and there are two second type back side trench gate structures (consisting of 13 and 14) in between.
In FIG. 6, the main difference from the structure of FIG. 1 is that the base region (formed by p-base region 30 and p)+Region 32) and the drift region (n-region 21) has an n-type carrier storage layer (n-cs region 23). The doping concentration of the n-type carrier storage layer (n-cs region 23) is higher than that of the drift region (n-region 21), and the in-vivo carrier storage effect or the conductivity modulation effect can be enhanced, so that the conduction voltage drop is reduced.
In FIG. 7, the main difference from the structure of FIG. 2 is that the base region (formed by p-base region 30 and p)+Region 32) and the drift region (n-region 21) has an n-type carrier storage layer (n-cs region 23).
In FIG. 8, the main difference from the structure of FIG. 4 is that the base region (formed by p-base region 30 and p)+Region 32) and the drift region (n-region 21) has an n-type carrier storage layer (n-cs region 23).
In fig. 9, the main difference from the structure of fig. 1 is that a collector region (n) of the first conductivity type is included in a buffer region (n-buffer region 20)+The doping concentration of the region where the region 11) and the drift region (n-region 21) are in contact with each other is the same as the doping concentration of the drift region (n-region 21), so that the buffer region (n-buffer region 20) of the structure of fig. 1 is in contact with the collector region (n) of the first conductivity type+Region 11) and drift region (n-region 21) become a part of drift region (n-region 21); a collector region (n) of the first conductivity type in the buffer region (n-buffer region 20)+The doping concentration of the region 11) and the floating region (p-float region 24) in contact with each other is the same as the doping concentration of the floating region (p-float region 24), so that the buffer region (n-buffer region 20) of the structure of fig. 1 is in contact with the collector region (n) of the first conductivity type+Region 11) and the float region (p-float region 24) are in contact with each other, and the area becomes a part of the float region (p-float region 24).
In FIG. 10, the main difference from the structure of FIG. 2 is that in the buffer area (n-buffer area 20)With collector region (n) of the first conductivity type+The doping concentration of the region where the region 11) and the drift region (n-region 21) are in contact with each other is the same as the doping concentration of the drift region (n-region 21), so that the buffer region (n-buffer region 20) of the structure of fig. 2 is in contact with the collector region (n) of the first conductivity type+Region 11) and drift region (n-region 21) become a part of drift region (n-region 21); a collector region (n) of the first conductivity type in the buffer region (n-buffer region 20)+The doping concentration of the region 11) and the floating region (p-float region 24) in contact with each other is the same as the doping concentration of the floating region (p-float region 24), so that the buffer region (n-buffer region 20) of the structure of fig. 2 is in contact with the collector region (n) of the first conductivity type+Region 11) and the float region (p-float region 24) are in contact with each other, and the area becomes a part of the float region (p-float region 24).
In fig. 11, the main difference from the structure of fig. 4 is that a collector region (n) of the first conductivity type is included in a buffer region (n-buffer region 20)+The doping concentration of the region where the region 11) and the drift region (n-region 21) are in contact with each other is the same as the doping concentration of the drift region (n-region 21), so that the buffer region (n-buffer region 20) of the structure of fig. 4 is in contact with the collector region (n) of the first conductivity type+Region 11) and drift region (n-region 21) become a part of drift region (n-region 21); a collector region (n) of the first conductivity type in the buffer region (n-buffer region 20)+The doping concentration of the region 11) and the floating region (p-float region 24) in contact with each other is the same as the doping concentration of the floating region (p-float region 24), so that the buffer region (n-buffer region 20) of the structure of fig. 4 is in contact with the collector region (n) of the first conductivity type+Region 11) and the float region (p-float region 24) are also part of the float region (p-float region 24).
In fig. 12, the main difference from the structure of fig. 1 is that the cell further includes a first emitter-connected trench gate structure (consisting of 37 and 36). The first emitter-connected trench gate structure (composed of 37 and 36) differs from the trench gate structure (composed of 33 and 34) for controlling the switch in that the former conductor region (36) is connected to the emitter (E).
In fig. 13, the main difference from the structure of fig. 6 is that the cell further includes a second emitter-connected trench gate structure (composed of 38 and 39).
In order to illustrate the superiority of the RC-IGBT of the present invention, the RC-IGBT structure of the present invention in fig. 1 is taken as an example for simulation calculation here. Half of the cells (width 8 μm) of the structure of fig. 1 were used in the simulation; si material is adopted; the minority carrier lifetime of both electrons and holes is 10 mus; the insulating medium layers (34 and 35) adopt SiO2The thickness of which is 0.1 μm, and the thickness and doping concentration of the drift region (n-region 21) are 105 μm and 6X 10, respectively13cm-3(ii) a The thickness and doping concentration of the buffer region (n-buffer region 20) were 1.4 μm and 5X 10, respectively16cm-3(ii) a The width and the depth of a groove type grid structure (composed of 33 and 34) for controlling a switch and a first back groove type grid structure (composed of 35 and 12) are respectively 1 mu m and 5 mu m, and the first conductor region (12) adopts heavily doped p-type polycrystalline silicon; the peak concentration at the interface between the termination ring (n-ring region 22) of the first conductivity type and the first type of back side trench gate structure is 1 × 1017cm-3The diffusion length is 0.3 μm; the peak concentration at the interface of the second conductivity type floating region (p-float region 24) and the first back side trench gate structure is 3 × 1016cm-3The diffusion length is 0.3 μm; collector region of the second conductivity type (p-collector region 10) and collector region of the first conductivity type (n)+Region 11) has a thickness and doping concentration of 0.6 μm and 3 × 10, respectively18cm-3Collector region of the first conductivity type (n)+Region 11) has a width of 2 μm and the collector region of the second conductivity type (p-collector region 10) has a width of 3 μm. The simulation results show that the breakdown voltage of the structure of fig. 1 is 1424V. Whereas if the termination ring of the first conductivity type (n-ring region 22) in the structure of fig. 1 were removed, the breakdown voltage would be 1324V. This is mainly because the introduction of the termination ring (n-ring region 22) of the first conductivity type can avoid the electric field concentration effect at the top corner of the first type of back trench gate structure.
FIG. 14 is a reverse conducting I-V curve for the RC-IGBT of the present invention in FIG. 1, and a forward conducting I-V curve for the RC-IGBT of the present invention and a comparative structure in FIG. 1, wherein the comparative structure differs from the structure of FIG. 1 only in the absence of a termination ring of the first conductivity type (n-ring region 2)2) And a floating region (p-float region 24) of the second conductivity type. D in FIG. 14iRepresents the interfacial charge areal density on the first dielectric layer (35). As can be seen from the figure, the RC-IGBT of the invention has the capability of conducting in two directions. The inventive RC-IGBT is less prone to the snapback phenomenon than the comparative structure under the same back side trench gate pitch condition because the floating region of the second conductivity type (p-float region 24) reduces the width of the drift region (n-region 21) between the two back side trench gates. In addition, the RC-IGBT of the invention is also less prone to the phenomenon of folding back than the comparative structure in the presence of interface charges on the first insulating dielectric layer (35), because the floating regions (p-float regions 24) of the second conductivity type attenuate the influence of the interface charges on the first insulating dielectric layer (35) on the depletion region in the drift region (n-region 21).
In the above description of many embodiments of the present invention, the n-type semiconductor material can be regarded as a first conductive type semiconductor material, and the p-type semiconductor material can be regarded as a second conductive type semiconductor material. Obviously, according to the principle of the present invention, the n-type and the p-type in the embodiments can be interchanged without affecting the content of the present invention. It is obvious to a person skilled in the art that many other embodiments are possible within the inventive idea without going beyond the claims of the invention.
Claims (7)
1. A reverse conducting type insulated gate bipolar transistor device, the cellular structure of which comprises: the drift region of lightly doped first conduction type, with the collection electric structure that the bottom plane of drift region contacted, with the base region of second conduction type that the top plane of drift region contacted, with the emitter region of heavily doped first conduction type that the base region has at least partial contact, with emitter region, base region and the drift region all contact be used for the control switch's cell type grid structure, cover in the collector electrode that the conductor of collection electric structure formed, cover in the emitter region with the emitter electrode that the conductor of base region formed, cover in the grid that the conductor that is used for the control switch's cell type grid structure formed, its characterized in that:
the current collection structure is composed of at least one collector region of a second conduction type, at least one collector region of a first conduction type and at least one buffer region of a first conduction type; the bottom plane of the buffer region is in direct contact with the collector region of the second conduction type and the collector region of the first conduction type, and the top plane of the buffer region is in direct contact with the bottom plane of the drift region;
the collector region of the second conduction type is mutually isolated from the collector region of the first conduction type through at least one first back groove type grid structure; the top of the first type of back groove type grid structure is directly contacted with a termination ring of a first conduction type, and two sides of the first type of back groove type grid structure are directly contacted with a floating zone of a second conduction type; the first type of back groove type gate structure is not in direct contact with the drift region but in contact with the drift region through the floating space region of the second conductivity type and the termination ring of the first conductivity type; the first back groove type grid structure comprises at least one first insulating medium layer and at least one first conductor region, the first insulating medium layer is directly contacted with the collector region of the second conduction type, the collector region of the first conduction type, the buffer region, the floating region of the second conduction type and the stop ring of the first conduction type, the first conductor region is directly contacted with the first insulating medium layer and is separated from the collector region of the second conduction type, the collector region of the first conduction type, the buffer region, the floating region of the second conduction type and the stop ring of the first conduction type through the first insulating medium layer, and the first conductor region is made of heavily doped polycrystalline semiconductor materials or metals; the collector region of the second conductivity type, the collector region of the first conductivity type, and the first conductor region are in direct contact with the collector electrode;
the cell structure comprises a second type of back groove type grid structure or does not comprise the second type of back groove type grid structure; the top of the second back groove type grid structure is directly contacted with a termination ring of a first conduction type, and two sides of the second back groove type grid structure are directly contacted with a floating zone of a second conduction type; the second type of back groove type gate structure is not in direct contact with the drift region but in contact with the drift region through the floating space region of the second conductivity type and the termination ring of the first conductivity type; the second type of back groove type gate structure comprises at least one second insulating medium layer and at least one second conductor region, the second insulating medium layer is in direct contact with the collector region of the first conduction type, the buffer region, the floating region of the second conduction type and the termination ring of the first conduction type but not in direct contact with the collector region of the second conduction type, the second conductor region is in direct contact with the second insulating medium layer and is isolated from the collector region of the first conduction type, the buffer region, the floating region of the second conduction type and the termination ring of the first conduction type through the second insulating medium layer, the second conductor region is made of heavily doped polycrystalline semiconductor material or metal, and the second conductor region is in direct contact with the collector;
the cell structure comprises a third back groove type grid structure or does not comprise the third back groove type grid structure; the top of the third back groove type grid structure is directly contacted with a termination ring of the first conduction type, and two sides of the third back groove type grid structure are directly contacted with a floating zone of the second conduction type; the third back groove type grid structure is not in direct contact with the drift region but is in contact with the drift region through the floating space region of the second conduction type and the termination ring of the first conduction type; the third back groove-type gate structure comprises at least one third insulating medium layer and at least one third conductor region, the third insulating medium layer is in direct contact with the collector region of the second conduction type, the buffer region, the floating region of the second conduction type and the termination ring of the first conduction type but not in direct contact with the collector region of the first conduction type, the third conductor region is in direct contact with the third insulating medium layer and is isolated from the collector region of the second conduction type, the buffer region, the floating region of the second conduction type and the termination ring of the first conduction type through the third insulating medium layer, the third conductor region is made of heavily-doped polycrystalline semiconductor material or metal, and the third conductor region is in direct contact with the collector;
the groove-shaped grid structure for controlling the switch comprises at least one fourth insulating medium layer and at least one fourth conductor region, the fourth insulating medium layer is directly contacted with the emitter region, the base region and the drift region, the fourth conductor region is directly contacted with the fourth insulating medium layer and is isolated from the emitter region, the base region and the drift region through the fourth insulating medium layer, the fourth conductor region is made of heavily-doped polycrystalline semiconductor materials or metals, and the fourth conductor region is directly contacted with the grid;
at least one heavily doped region in the base region is in direct contact with the emitter to form an ohmic contact.
2. The igbt device of claim 1, wherein:
the drift region is not in direct contact with the base region but in indirect contact with the base region through a carrier storage layer of the first conductivity type; the doping concentration of the carrier storage layer is higher than that of the drift region; the fourth insulating medium layer is in direct contact with the carrier storage layer.
3. The igbt device of claim 1, wherein:
the drift region is arranged in the buffer region, and the region in contact with both the collector region and the drift region of the first conduction type in the buffer region is replaced by the drift region, so that the region in contact with both the collector region and the drift region of the first conduction type in the buffer region becomes a part of the drift region; and replacing the region of the buffer region, which is in contact with both the collector region of the first conductivity type and the floating region of the second conductivity type, with the floating region of the second conductivity type, so that the region of the buffer region, which is in contact with both the collector region of the first conductivity type and the floating region of the second conductivity type, becomes a part of the floating region of the second conductivity type.
4. The igbt device of claim 1, wherein: the cell structure comprises a first groove type grid structure connected with an emitter; the first groove-shaped grid structure connected with the emitter comprises at least one fifth insulating medium layer and at least one fifth conductor region, the fifth insulating medium layer is directly contacted with the base region and the drift region, the fifth conductor region is directly contacted with the fifth insulating medium layer and is isolated from the base region and the drift region through the fifth insulating medium layer, the fifth conductor region is made of heavily doped polycrystalline semiconductor materials or metals, and the fifth conductor region is directly contacted with the emitter.
5. The igbt device of claim 2, wherein:
the cell structure comprises a second groove-shaped grid structure connected with an emitter; the second type of emitter-connected trench gate structure comprises at least one sixth insulating dielectric layer and at least one sixth conductor region, the sixth insulating dielectric layer is in direct contact with the base region, the carrier storage layer and the drift region, the sixth conductor region is in direct contact with the sixth insulating dielectric layer and is isolated from the base region, the carrier storage layer and the drift region through the sixth insulating dielectric layer, the sixth conductor region is made of heavily-doped polycrystalline semiconductor materials or metal, and the sixth conductor region is in direct contact with the emitter.
6. The igbt device of claim 1, wherein:
under the condition that zero volt is applied between the collector and the emitter, the drift region between two adjacent floating empty regions of the second conduction type directly contacted with the first back groove type grid structure is completely depleted, the drift region between two adjacent floating empty regions of the second conduction type directly contacted with the second back groove type grid structure is completely depleted, and the drift region between two adjacent floating empty regions of the second conduction type directly contacted with the first back groove type grid structure and the floating empty regions of the second conduction type directly contacted with the second back groove type grid structure is completely depleted.
7. The igbt device of claim 1, wherein:
the total number of effective doping impurities in the floating space region of the second conduction type is smaller than that of the effective doping impurities in the buffer region; the total number of effective doping impurities in the floating space region of the second conduction type is smaller than that in the termination region of the first conduction type.
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| CN112928156B (en) * | 2021-04-07 | 2022-04-12 | 四川大学 | Floating p-column reverse-conducting type grooved gate super-junction IGBT |
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