CN112652658B - Trench gate super junction IGBT (insulated Gate Bipolar transistor) with isolated p-top region - Google Patents
Trench gate super junction IGBT (insulated Gate Bipolar transistor) with isolated p-top region Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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Abstract
The invention provides a super-junction IGBT (Insulated Gate Bipolar Transistor), wherein a top region of a second conductive type with higher resistivity is arranged above a semiconductor region of the second conductive type in a voltage-proof layer, the top region is isolated from a base region of the second conductive type through a groove-shaped Gate structure, and a current carrier storage layer of the first conductive type is arranged between the semiconductor region of the first conductive type in the voltage-proof layer and the base region. In the forward conduction state, a voltage drop is generated on the top region, so that the potential of the second-conductivity-type semiconductor region in the voltage-resisting layer is increased, and the conduction voltage drop is reduced.
Description
Technical Field
The invention belongs to a semiconductor device, in particular to a power semiconductor device.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a medium-high voltage power semiconductor switching device. Because a large number of non-equilibrium carriers need to be stored in the body to realize the conductance modulation of the voltage-resisting layer (high-resistance region) during conduction, the turn-off speed of the IGBT is slower than that of a unipolar power semiconductor device. Therefore, the IGBT has a contradictory relationship between on-voltage drop and off-power consumption. A Super Junction (SJ) is a voltage-resistant structure in which n columns and p columns are alternately arranged, and it enables the n columns and the p columns to obtain a higher breakdown voltage even at a higher doping concentration, and is generally applied to a unipolar power semiconductor device. In fact, the super junction can also be applied to the IGBT, and the IGBT is helped to improve the contradiction relation between the on-state voltage drop and the off-state power consumption. When the IGBT adopts a super-junction voltage-resistant structure, a pn junction formed by the n column/p column can be quickly depleted in the turn-off process, and the turn-off speed is increased (or the turn-off power consumption is reduced). However, in the ordinary super junction IGBT, the conductivity modulation effect (or carrier storage effect) of the n-pillar and the p-pillar in the on-state is poor, mainly because the p-pillar easily collects holes and rapidly extracts the collected holes to the emitter, which makes it difficult to effectively store the holes in the n-pillar and the p-pillar, and increases the on-state voltage drop.
Disclosure of Invention
Compared with the common super-junction IGBT, the super-junction IGBT device provided by the invention can enhance the storage effect of minority carriers in a body and reduce the conduction voltage drop.
The invention provides a super junction insulated gate bipolar transistor device, the cellular structure of which comprises: the circuit comprises a current collection structure (composed of 10 and 20), a voltage-resisting layer (composed of 31 and 32) positioned on the current collection structure, a base region (composed of 41 and 43) of a second conduction type and a top region (composed of 42 and 45) of the second conduction type positioned on the voltage-resisting layer, a heavily doped emitter region 44 of the first conduction type in contact with at least part of the base region, and a groove-shaped gate structure (composed of 47 and 49) which is in contact with the emitter region 44, the base region (composed of 41 and 43) and the voltage-resisting layer (composed of 31 and 32) and used for controlling a switch, and is characterized in that: (refer to FIGS. 2 to 7):
the current collection structure (composed of 10 and 20) is composed of at least one collector region 10 of the second conductivity type and at least one buffer region 20 of the first conductivity type, wherein the lower surface of the buffer region 20 is in contact with the upper surface of the collector region 10; the lower surface of the collector region 10 is covered with a collector conductor 1 and is connected to a collector C through a lead;
the voltage-resisting layer (composed of 31 and 32) is composed of at least one first conductivity type semiconductor region 31 and at least one second conductivity type semiconductor region 32, the first conductivity type semiconductor region 31 of the voltage-resisting layer and the second conductivity type semiconductor region 32 of the voltage-resisting layer are contacted with each other, and the contact surface formed by the contact surface is vertical or approximately vertical to the upper surface of the current collecting structure (composed of 10 and 20) and the lower surfaces of the base region (composed of 41 and 43) and the top region (composed of 42 and 45); the voltage-resistant layer (made up of 31 and 32) is in direct contact with the buffer region 20 or in indirect contact through an auxiliary layer 30 of the first conductivity type;
the lower surface of the base region (composed of 41 and 43) is in contact with the first conductivity type semiconductor region 31 of the voltage-proof layer through a first conductivity type carrier storage layer 33; the upper surface of the base region (composed of 41 and 43) is at least partially covered with an emitter conductor 2 and is connected to an emitter E through a lead; at least one heavily doped region 43 of the base region (consisting of 41 and 43) is in direct contact with the emitter conductor 2 so as to form an ohmic contact;
the upper surface of the emitter region 44 is covered with an emitter conductor 2 and connected to the emitter E by a wire;
the lower surface of the top region (composed of 42 and 45) is in direct contact with the second conductivity-type semiconductor region 32 of the voltage-resistant layer, and the resistivity of the top region (composed of 42 and 45) in the vertical direction is higher than the resistivity of the second conductivity-type semiconductor region 32 of the voltage-resistant layer in the vertical direction; the upper surface of the top region (consisting of 42 and 45) is at least partially covered with an emitter conductor 2 and is connected to the emitter E by a wire; at least one heavily doped region 45 in the top region (consisting of 42 and 45) is in direct contact with the emitter conductor 2 so as to form an ohmic contact;
the top region (composed of 42 and 45) and the base region (composed of 41 and 43) are isolated from each other through a first type of emitter-connected trench gate structure (composed of 46 and 48) and/or the trench gate structure (composed of 47 and 49) for controlling the switch;
the groove-type gate structure (composed of 47 and 49) for controlling the switch comprises an insulating medium layer 49 and a conductor region 47 surrounded by the insulating medium layer; the insulating medium layer 49 of the trench-type gate structure for controlling the switch is in direct contact with the emitter region 44, the base region (formed by 41 and 43), the carrier storage layer 33 and the first conductivity-type semiconductor region 31 of the voltage-withstanding layer, or in direct contact with the emitter region 44, the base region (formed by 41 and 43), the top region (formed by 42 and 45), the carrier storage layer 33, the first conductivity-type semiconductor region 31 of the voltage-withstanding layer and the second conductivity-type semiconductor region 32 of the voltage-withstanding layer; the upper surface of the conductor region 47 of the groove-shaped grid structure for controlling the switch is covered with a grid conductor 3 and is connected to the grid G through a lead;
the first emitter-connected trench gate structure (comprised of 46 and 48) includes an insulating dielectric layer 48 and a conductor region 46; the insulating medium layer 48 of the first emitter-connected trench gate structure is in direct contact with the base region (formed by 41 and 43), the top region (formed by 42 and 45), the carrier storage layer 33, the first conductivity-type semiconductor region 31 of the voltage-withstanding layer, and the second conductivity-type semiconductor region 32 of the voltage-withstanding layer; the upper surface of the emitter-connected groove-shaped grid structure conductor region 46 is covered with an emitter conductor 2 and is connected to the emitter E through a lead;
the conductor regions (46 and 47) in the trench gate structure are composed of heavily doped polycrystalline semiconductor material; when the first conduction type is n type, the second conduction type is p type; when the first conductivity type is p-type, the second conductivity type is n-type.
Referring to fig. 8-10, a trench gate structure (composed of 46 and 48) of the second type for connecting the emitter is included above the semiconductor region 31 of the first conductivity type of the voltage-resistant layer and/or the semiconductor region 32 of the second conductivity type of the voltage-resistant layer; the second type of emitter-connected trench gate structure includes an insulating dielectric layer 48 and a conductor region 46, the insulating dielectric layer 48 directly contacts the base region (formed by 41 and 43), the carrier storage layer 33, and the voltage-withstanding layer, or directly contacts the top region (formed by 42 and 45) and the voltage-withstanding layer, and the second type of conductivity semiconductor region 32, and the upper surface of the conductor region 46 is covered with an emitter conductor 2 and is connected to the emitter E through a wire.
Referring to fig. 11 to 14, in the extending direction of the trench type gate structure (composed of 47 and 49) for controlling the switch, the emitting region 44 is a connected emitting region 44 or a plurality of emitting regions 44 which are not connected to each other; in the extending direction of the first emitter-connected trench gate structure (composed of 46 and 48), the heavily doped region 45 in the top region is a connected heavily doped region 45 or a plurality of heavily doped regions 45 which are not connected to each other.
Referring to fig. 15, in the extending direction of the first emitter-connected trench gate structure (composed of 46 and 48), the heavily doped region 45 in the top region is a plurality of heavily doped regions 45 which are not connected to each other, and the emitter conductor 2 covering the top region covers only the heavily doped region 45 in the top region.
Referring to fig. 16, the doping concentration of the carrier storage layer 33 is higher than the doping concentration of the first conductive type semiconductor region 31 of the voltage-proof layer, or equal to or equivalent to the doping concentration of the first conductive type semiconductor region 31 of the voltage-proof layer.
Referring to fig. 17 to 18, the doping concentration of the auxiliary layer 30 is lower than the doping concentration of the first conductivity type semiconductor region 31 of the voltage-proof layer, or equal to or equivalent to the doping concentrations of the first conductivity type semiconductor region 31 of the voltage-proof layer and the carrier storage layer 33.
Referring to fig. 19 to 21, the doping concentration of the buffer region 20 is higher than the doping concentration of the auxiliary layer 30, or equal to or equivalent to the doping concentrations of the auxiliary layer 30 and the first conductivity type semiconductor region 31 of the voltage-withstanding layer, or equal to or equivalent to the doping concentrations of the auxiliary layer 30, the first conductivity type semiconductor region 31 of the voltage-withstanding layer, and the carrier storage layer 33.
Referring to fig. 22, the bottom of the trench type gate structure (composed of 46 and 48, and composed of 47 and 49) is surrounded by the heavily doped second conductive type semiconductor region 35; the heavily doped semiconductor region 35 of the second conductivity type is in direct contact with the voltage-resistant layer (made up of 31 and 32).
Drawings
FIG. 1(a) is a schematic diagram of a common super junction IGBT structure;
FIG. 1(b) is a schematic diagram of a common semi-super junction IGBT structure;
FIG. 2 shows a super junction IGBT of the present invention, which only contains a p-type top region with a resistivity higher than that of a p-pillar, the p-type top region is isolated from the p-type base region by a first trench gate structure connected to an emitter, and the upper surface of the p-type top region is p+Region, emitter conductor covering p+A region upper surface;
FIG. 3 shows a semi-super junction IGBT of the present invention, which only contains a p-type top region with a resistivity higher than that of a p-pillar, the p-type top region is isolated from the p-type base region by a first trench gate structure connected to an emitter, and the upper surface of the p-type top region is p+Region, emitter conductor covering p+A region upper surface;
FIG. 4(a) shows a super-junction IGBT of the invention, which comprises only a p-type top region with higher resistivity than p-pillar, wherein the p-type top region is isolated from the p-type base region by a first emitter-connected trench gate structure, and the upper surface of the p-type top region is p+A region, an emitter conductor overlying an upper surface of the p-type top region;
FIG. 4(b) shows a further semi-super junction IGBT of the invention comprising only a p-type top region having a higher resistivity than the p-pillar, the p-type top region being isolated from the p-type base region by a first emitter-connected trench gate structure, the upper surface of the p-type top region being partially p+A region, an emitter conductor overlying an upper surface of the p-type top region;
FIG. 5(a) shows a super-junction IGBT of the invention, which comprises only a p-type top region with higher resistivity than p-pillar, wherein the p-type top region is isolated from the p-type base region by a first emitter-connected trench gate structure, and the upper surface of the p-type top region is p+Region, emitter conductor covering p+A region upper surface;
FIG. 5(b) shows a further semi-super junction IGBT of the invention having only a p-type top region with a higher resistivity than the p-pillar, the p-type top region being isolated from the p-type base region by a first emitter-connected trench gate structure, the upper surface of the p-type top region being partially p+Region, emitter conductor covering p+A region upper surface;
FIG. 6(a) shows a super-junction IGBT of the invention, which comprises only a p-type top region with higher resistivity than p-type columns, wherein the p-type top region is isolated from the p-type base region by a trench-type gate structure of a control switch, and the upper surface of the p-type top region is p+Region, emitter conductor covering p+A region upper surface;
FIG. 6(b) shows another semi-super junction IGBT of the invention, which only contains a p-type top region with higher resistivity than p column, the p-type top region is isolated from the p-type base region by the trench gate structure of the control switch, and the upper surface of the p-type top region is p+Region, emitter conductor covering p+A region upper surface;
FIG. 7(a) yet another super junction IGBT of the invention contains only a p-type top region with higher resistivity than the p-column by controlling the trench gate of the switchThe structure and the first groove-shaped grid structure connected with the emitter are mutually isolated from the p-type base region, and the upper surface of the p-type top region is p+Region, emitter conductor covering p+A region upper surface;
FIG. 7(b) shows a further semi-super-junction IGBT of the invention comprising only a p-type top region having a higher resistivity than the p-pillar, the p-type top region being isolated from the p-type base region by the trenched gate structure controlling the switches and the first emitter-connected trenched gate structure, the upper surface of the p-type top region being p+Region, emitter conductor covering p+A region upper surface;
fig. 8(a) shows a super junction IGBT according to fig. 2, in which a second emitter-connected trench gate structure is formed over a p-pillar;
FIG. 8(b) shows a further semi-superjunction IGBT according to the invention, according to FIG. 3, with a second emitter-connected trench gate structure over the p-pillar;
fig. 9(a) shows a super junction IGBT according to the invention with a second emitter-connected trench gate structure over the p-pillar according to fig. 5 (a);
FIG. 9(b) shows a further semi-super junction IGBT according to the invention with a second emitter-connected trench gate structure over the p-pillar according to FIG. 5 (b);
fig. 10(a) shows a further super junction IGBT according to the invention with a second emitter-connected trench gate structure over both the p-and n-pillars according to fig. 6 (a);
FIG. 10(b) shows a further semi-super junction IGBT according to the invention, with a second emitter-connected trench gate structure over both the p-and n-pillars, according to FIG. 6 (b);
FIG. 11 is a schematic diagram of a three-dimensional structure of a semi-super junction IGBT according to the invention, shown in FIG. 3, wherein n is+The emitter region is a connected emitter region, and the upper surface of the p-type top region is a connected p+A zone;
FIG. 12 is a schematic diagram of the three-dimensional structure of still another semi-super junction IGBT according to the invention, shown in FIG. 3, wherein n is+The emitting region is multiple emitting regions not communicated with each other, and the upper surface of the p-type top region is a communicated p+A zone;
FIG. 13 according to FIG. 3, the inventionThe three-dimensional structure schematic diagram of the semi-super-junction IGBT is shown, wherein n is+The emitting region is a connected emitting region, and the upper surface of the p-type top region is provided with a plurality of p-type p-type p+A zone;
FIG. 14 is a schematic diagram of a three-dimensional structure of a semi-super junction IGBT according to the invention, shown in FIG. 3, with n+The emitter region is a plurality of emitter regions which are not communicated with each other, and the upper surface of the p-type top region is a plurality of p which are not communicated with each other+A zone;
FIG. 15 is a schematic diagram showing a three-dimensional structure of a semi-super junction IGBT according to FIG. 3, wherein the upper surface of the p-type top region is a plurality of p-type top regions which are not communicated with each other+Region, the emitter conductor covering the top region only covers p+A zone;
FIG. 16 shows a further semi-super junction IGBT according to the invention, with the doping concentration of the n-type carrier storage layer and the n-column being the same, according to FIG. 3;
FIG. 17 shows a further semi-superjunction IGBT according to FIG. 3, with the n-type auxiliary layer and the n-column doped at the same concentration;
FIG. 18 shows a semi-super junction IGBT according to the invention, wherein the doping concentrations of the n-type auxiliary layer, the n-column and the n-type carrier storage layer are the same according to FIG. 3;
FIG. 19 shows a further semi-superjunction IGBT according to FIG. 3, with the n-type buffer region and the n-type auxiliary layer doped at the same concentration;
FIG. 20 shows a semi-super junction IGBT according to the invention, wherein the doping concentrations of the n-type buffer region, the n-type auxiliary layer and the n-column are the same according to FIG. 3;
FIG. 21 shows a semi-super junction IGBT according to the invention, wherein the doping concentrations of the n-type buffer region, the n-type auxiliary layer, the n-column and the n-type carrier storage layer are the same according to FIG. 3;
FIG. 22 shows another semi-super junction IGBT according to the invention, which has a trench-type gate structure with a bottom p+A zone enclosure;
fig. 23 forward conduction of the half super junction IGBT of fig. 3 and the half super junction IGBT of fig. 1(b)I-VCurve line.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1(a) is a schematic diagram of a common super junction IGBT structure, and fig. 1(b) is a schematic diagram of a common semi-super junction IGBT structure. Compared with the super-junction IGBT, the semi-super-junction IGBT has one more n-type auxiliary layer (n-assist layer 30) for bearing partial applied voltage between the n column (n-pillar region 31) and the p column (p-pillar region 32) and the n-type buffer region (n-buffer region 20), wherein the doping concentration of the n-type auxiliary layer (n-assist layer 30) can be lower than or equal to that of the n region (n-pillar region 31). When a voltage exceeding the threshold voltage is applied to the grid electrode (G), an electron channel is formed near the interface of the base region (p-base region 41) and the insulating layer (49); if a positive voltage exceeding 0.7V is applied to the collector (C), electrons pass from the emitter (E) through the emitter region (n) under the influence of the electric field+Region 44) and electron channels into the n-pillar (n-pillar region 31), n-type assist layer (n-assist layer 30), n-type buffer region (n-buffer region 20), and then injected into the collector region (p-collector region 10); then, holes enter the collector region (p-collector region 10) from the collector (C), and are injected into the n-type buffer region (n-buffer region 20), the n-type assist layer (n-assist layer 30), and the n-column (n-pilar region 31), so that the device is turned on. Since the pn junction formed by the p-pillar (p-pillar region 32), the n-pillar (n-pillar region 31) and the n-type auxiliary layer (n-assist layer 30) is reverse biased, holes are easily collected by the p-pillar (p-pillar region 32) and enter the base region (formed by the p-base region 41 and the p-base region 30)+Region 43) and thus the carrier storage effect (conductance modulation effect) in the body is weak and the on-voltage will be high.
The main purpose of the present invention is to improve the disadvantage of high conduction voltage drop of the ordinary super junction IGBT and the ordinary half super junction IGBT shown in fig. 1.
Fig. 2 is a schematic diagram of a super junction IGBT cell structure according to the present invention, which is mainly different from the conventional super junction IGBT shown in fig. 1(a) in that the resistance of the hole path for the holes flowing from the p-pillar (p-pilar region 32) to the emitter E is larger and an n-type carrier storage layer (n-cs layer 33) is added.
In FIG. 2, above the p-pillar (p-pillar region 32) is a p-type top region (consisting of p-top region 42 and p-pillar region+Region 45) in which the top region is p-type in the vertical direction (From p-top region 42 and p+Region 45) is higher than the p-pillar (p-pilar region 32) and the p-type top region (composed of p-top region 42 and p-pillar region 32)+Region 45) is connected to the base region (formed by p-base regions 41 and p) by a first emitter-connected trench gate structure (formed by 46 and 48)+Region 43) is formed. In the forward conduction state, holes enter the p-pillar (p-pilar region 32) and pass up the p-type top region (formed by p-top region 42 and p-pillar region)+Region 45) toward emitter E. Due to the p-type top region (formed by p-top region 42 and p)+Region 45) is higher than the p-pillar (p-pilar region 32), the p-type top region (composed of p-top region 42 and p-pillar region)+Region 45) causes a non-negligible voltage drop across the hole, and the potential of the p-pillar (p-pilar region 32) is thus raised. When the p-type top region (composed of p-top region 42 and p)+Region 45) is sufficiently high, the potential of the p-pillar (p-pilar region 32) can be raised to 0.7V, and then the p-pillar/n-pillar junction becomes a forward biased junction, the concentration of non-equilibrium carriers near the p-pillar/n-pillar junction is higher, the in-vivo conductivity modulation effect is enhanced, and the conduction voltage drop is reduced. To form a p-type top region (composed of p-top region 42 and p)+Region 45) has a higher resistivity than the p-pillar (p-pilar region 32), with the heavily doped region (p) removed in the p-type top region+Region 45) has a lower average doping concentration (p-top region 42) than the average doping concentration of the p-pillars (p-pilar region 32). Removing heavily doped region (p) in p-type top region+Region 45) (p-top region 42) may be a gaussian doping profile in the vertical direction and the doping concentration at the interface with the p-pillar (p-pilar region 32) is much lower than the average doping concentration of the p-pillar (p-pilar region 32).
Further, in fig. 2, an n-type carrier storage layer (n-cs layer 33) is employed. Albeit due to the p-type top region (formed by p-top region 42 and p)+Region 45) causes a difficulty in flowing holes to the p-pillar (p-pillar region 32), but if the n-type carrier storage layer (n-cs layer 33) is not provided, holes in the n-pillar (n-pillar region 31) can flow more smoothly to the base region (formed by the p-base region 41 and the p-pillar region 32)+Region 43) so that the n-pillar (n-pilar region 31) is toppedThe conductance modulation effect of the partial region is weak, which increases the conduction voltage drop to some extent. When an n-type carrier storage layer (n-cs layer 33) with the doping concentration higher than that of the n column (n-pilar region 31) is introduced, the n-type carrier storage layer (n-cs layer 33) can inhibit holes from entering the base region (formed by the p-base region 41 and the p column region 31)+Region 43) to enhance the conductivity modulation effect in the top region of the n-pillar (n-pilar region 31) to further reduce the turn-on voltage drop.
In addition, a p-type top region (defined by p-top region 42 and p)+Region 45) is a heavily doped region (p)+Zone 45). The heavily doped region (p)+Region 45) for connecting emitter conductor 2 to the p-type top region (formed by p-top region 42 and p)+Region 45) forms a good ohmic contact. Of course, overlying the p-type top region (formed by p-top region 42 and p)+Region 45) does not necessarily have to cover only the heavily doped region (p)+Region 45), or a portion thereof may be overlaid in the p-type top region to remove the heavily doped region (p)+Region 45) (p-top region 42).
In FIG. 3, the main difference from the structure of FIG. 2 is that there is an n-type auxiliary layer (n-assit layer 30) between the n-type buffer region (n-buffer region 20) and the voltage-withstanding layer (composed of n-pilar region 31 and p-pilar region 32). The doping concentration of the n-type auxiliary layer (n-assit layer 30) and the n-pillar (n-pillar region 31) may be the same or comparable, or even much lower than the doping concentration of the n-pillar (n-pillar region 31).
In FIG. 4(a), the main difference from the structure of FIG. 2 is that the p-type top region (formed by p-top region 42 and p-top region)+Region 45) is not all heavily doped (p)+Region 45) and overlies the p-type top region (defined by p-top region 42 and p)+Region 45) does not cover only the heavily doped region (p)+Zone 45).
In FIG. 4(b), the main difference from the structure of FIG. 4(a) is that there is an n-type auxiliary layer (n-assist layer 30) between the n-type buffer region (n-buffer region 20) and the voltage-withstanding layer (composed of n-pillar region 31 and p-pillar region 32).
In FIG. 5(a)The main difference from the structure of FIG. 3 is that it is overlaid on the p-type top region (formed by p-top region 42 and p-top region)+Region 45) is only overlaid on the heavily doped p-region (p)+Zone 45).
In FIG. 5(b), the main difference from the structure of FIG. 5(a) is that there is an n-type auxiliary layer (n-assist layer 30) between the n-type buffer region (n-buffer region 20) and the voltage-withstanding layer (composed of n-pillar region 31 and p-pillar region 32).
In FIG. 6(a), the main difference from the structure of FIG. 2 is that the p-type top region (formed by p-top region 42 and p-top region)+Region 45) with the base region (formed by p-base regions 41 and p) by controlling the trench gate structure (formed by 47 and 49) of the switch+Region 43) is formed.
In FIG. 6(b), the main difference from the structure of FIG. 6(a) is that there is an n-type auxiliary layer (n-assist layer 30) between the n-type buffer region (n-buffer region 20) and the voltage-withstanding layer (composed of n-pillar region 31 and p-pillar region 32).
In FIG. 7(a), the main difference from the structure of FIG. 6(a) is that the p-type top region (composed of p-top region 42 and p-top region)+Region 45) is connected to the base region (formed by p-base regions 41 and p) via the trenched gate structure (formed by 47 and 49) controlling the switches and the first emitter-connected trenched gate structure (formed by 46 and 48)+Region 43) is formed.
In FIG. 7(b), the main difference from the structure of FIG. 7(a) is that there is an n-type auxiliary layer (n-assist layer 30) between the n-type buffer region (n-buffer region 20) and the voltage-withstanding layer (composed of n-pillar region 31 and p-pillar region 32).
In fig. 8(a), the main difference from the structure of fig. 2 is that there is also a second emitter-connected trench gate structure (consisting of 46 and 48) over the p-pillars (p-pilar regions 32). When the density of the groove type grid structure is increased, the electric field concentration effect at the bottom of the groove type grid structure is favorably relieved.
In FIG. 8(b), the main difference from the structure of FIG. 8(a) is that there is an n-type auxiliary layer (n-assist layer 30) between the n-type buffer region (n-buffer region 20) and the voltage-withstanding layer (composed of n-pillar region 31 and p-pillar region 32).
In fig. 9(a), the main difference from the structure of fig. 5(a) is that there is also a second emitter-connected trench gate structure (consisting of 46 and 48) over the p-pillar (p-pilar region 32).
In FIG. 9(b), the main difference from the structure of FIG. 9(a) is that there is an n-type auxiliary layer (n-assist layer 30) between the n-type buffer region (n-buffer region 20) and the voltage-withstanding layer (composed of n-pillar region 31 and p-pillar region 32).
In fig. 10(a), the main difference from the structure of fig. 6(a) is that there is a second emitter-connected trench gate structure (consisting of 46 and 48) above both the p-pillar (p-pilar region 32) and the n-pillar (n-pilar region 31).
In FIG. 10(b), the main difference from the structure of FIG. 10(a) is that there is an n-type auxiliary layer (n-assist layer 30) between the n-type buffer region (n-buffer region 20) and the voltage-withstanding layer (composed of n-pillar region 31 and p-pillar region 32).
In fig. 11, n-type emitter regions (n) are heavily doped in the extending direction along the trench gate structure (composed of 46 and 48, and composed of 47 and 49)+Zone 44) are connected.
In fig. 12, n-type emitter regions (n) are heavily doped in the extending direction along the trench gate structure (composed of 46 and 48, and composed of 47 and 49)+Region 44) is a plurality of areas that are not interconnected.
The main difference between the structure of fig. 13 and that of fig. 11 is the heavily doped region (p) in the p-type top region in the direction of extension along the trench gate structure (consisting of 46 and 48, and consisting of 47 and 49)+Region 45) is a plurality of regions that are not interconnected.
The main difference between the structure of fig. 14 and fig. 12 is the heavily doped region (p) in the p-type top region in the extension direction along the trench gate structure (consisting of 46 and 48, and consisting of 47 and 49)+Region 45) is a plurality of regions that are not interconnected.
In fig. 15, in the extending direction along the trench type gate structure (composed of 46 and 48, and composed of 47 and 49), the heavily doped region (p) in the p-type top region+Region 45) are a plurality of disconnected regions, and the emitter conductor 2 covering the p-type top region only covers the heavily doped region (p-type top region)+Zone 45). Such a configuration is more advantageous in increasing the resistance of holes flowing from the p-pillar (p-pilar region 32) into the emitter E path, thereby helping to improve the conductance modulation effect.
The main difference between the structures of fig. 16 and fig. 3 is that the n-type carrier storage layer (n-cs layer 33) and the n-pillar (n-pilar region 31) have the same doping concentration, and the n-type carrier storage layer (n-cs layer 33) and the n-pillar (n-pilar region 31) become the same region.
The main difference between the structure of fig. 17 and that of fig. 3 is that the n-type assist layer (n-assist layer 30) and the n-pillar (n-pillar region 31) have the same doping concentration, and the n-type assist layer (n-assist layer 30) and the n-pillar (n-pillar region 31) become the same region.
The main difference between the structures of fig. 18 and 17 is that the doping concentrations of the n-type carrier storage layer (n-cs layer 33) and the n-column (n-pilar region 31) are the same. In this case, the n-type carrier storage layer (n-cs layer 33), the n-type assist layer (n-assist layer 30), and the n-pillar (n-pilar region 31) become the same region.
The main difference between the structure of fig. 19 and that of fig. 3 is that the doping concentrations of the n-type buffer region (n-buffer region 20) and the n-type auxiliary layer (n-assist layer 30) are the same, and the n-type buffer region (n-buffer region 20) and the n-type auxiliary layer (n-assist layer 30) become the same region.
The main difference between the structure of fig. 20 and that of fig. 19 is that the doping concentration of the n-pillar (n-pilar region 31) is also the same as the doping concentrations of the n-type buffer region (n-buffer region 20) and the n-type auxiliary layer (n-assist layer 30). In this case, the n-pillar (n-pillar region 31), the n-type buffer region (n-buffer region 20), and the n-type auxiliary layer (n-assist layer 30) become the same region.
The main difference between the structures of fig. 21 and fig. 19 is that the doping concentration of the n-type carrier storage layer (n-cs layer 33) is also the same as the doping concentrations of the n-pillar (n-pilar region 31), the n-type buffer region (n-buffer region 20), and the n-type auxiliary layer (n-assist layer 30). In this case, the n-type carrier storage layer (n-cs layer 33), the n column (n-pillar region 31), the n-type buffer region (n-buffer region 20), and the n-type auxiliary layer (n-assist layer 30) become the same region.
The main difference between the structure of fig. 22 and that of fig. 3 is that the bottom of the trench gate structure (consisting of 46 and 48, and consisting of 47 and 49) is heavily doped p-type region (p)+Region 35). Heavily doped p-type region (p) when the device is voltage-resistant+Region 35) absorbs electric field lines generated by ionizing donors in vivo, thereby protecting the trench-type gate structure (composed of 46 and 48, and composed of 47 and 49) and the n-type carrier storage layer (n-cs layer 33) from high electric fields.
In order to illustrate the superiority of the IGBT of the present invention, the half super junction IGBT structure of the present invention in fig. 3 is taken as an example and compared with the ordinary half super junction IGBT in fig. 1(b) by simulation calculation. The structures in FIG. 1(b) and FIG. 3 both adopt Si material, a symmetrical super junction structure is adopted, minority carrier lifetime of electrons and holes is 5 mus, width of half cells is 6 mu m, and SiO is adopted as insulating medium layers (48 and 49)2The thickness of the film is 0.1 μm, and the thickness and doping concentration of the n-pillar (n-pillar region 31) and the p-pillar (p-pillar region 32)N pillarRespectively 70 μm and 3X 1015 cm-3The thickness, the highest concentration and the lowest concentration of the region (p-top region 42) excluding the heavily doped region in the p-type top region were 3 μm and 3X 10, respectively15 cm-3And 1X 1014 cm-3The thickness and doping concentration of the n-type assist layer (n-assist layer 30) were 20 μm and 5 × 10, respectively13 cm-3The n-type buffer region (n-buffer region 20) has a thickness of 2 μm and a doping concentration of 5X 10 at the peak, respectively16 cm-3The peak values of the thickness and the doping concentration of the collector region (p-collector region 10) are 1 μm and 1 × 10, respectively18 cm-3The thickness of the n-type carrier storage layer (n-cs layer 33) was 1.5 μm, and the doping concentration of the n-type carrier storage layer (n-cs layer 33)N csAdopt 3X 1016 cm-3Is uniformly doped.
FIG. 23 shows the forward conduction of the structure of FIGS. 3 and 1(b)I-VCurve of the grid voltageV G= 15V. At lower current densities, due to the p-type top region (from p-t)op regions 42 and p+Region 45) and conduction of the fig. 3 structure of the present invention is lessI-VConduction of the curve to the structure of FIG. 1(b)I-VThe curves almost coincide. And as the current density increases to some extent (J CE ≥ 50 A/cm2) P-type top region (composed of p-top region 42 and p)+Region 45) to gradually increase the forward bias voltage of the pn junction formed by the p pillar (p-pillar region 32) and the n pillar (n-pillar region 31), so that the in vivo conductance modulation effect is enhanced, and the slope of the current along with the voltage increase of the structure of fig. 3 of the invention can be obviously higher than that of the structure of fig. 1 (b). At 200A/cm2The turn-on voltage of the structure of fig. 3 is only about 1.25V at the turn-on current density of (a), while the turn-on voltage of the structure of fig. 1(b) is much higher, reaching 2V.
In the above description of many embodiments of the present invention, the n-type semiconductor material can be regarded as a first conductive type semiconductor material, and the p-type semiconductor material can be regarded as a second conductive type semiconductor material. Obviously, according to the principle of the present invention, the n-type and the p-type in the embodiments can be interchanged without affecting the content of the present invention. It is obvious to a person skilled in the art that many other embodiments are possible within the inventive idea without going beyond the claims of the invention.
Claims (8)
1. A super junction insulated gate bipolar transistor device, the cellular structure of which comprises: the collector structure, be located voltage-withstanding layer on the collector structure, be located second conductivity type's base region and second conductivity type's top region on the voltage-withstanding layer, with the heavily doped first conductivity type's emitter region that the base region has at least partial contact, with the emitter region, the base region and the voltage-withstanding layer all contacts be used for control switch's groove type grid structure, its characterized in that:
the current collection structure is composed of at least one collector region of a second conduction type and at least one buffer region of a first conduction type, and the lower surface of the buffer region is in contact with the upper surface of the collector region; the lower surface of the collector region is covered with a collector conductor and is connected to a collector through a lead;
the voltage-resisting layer is composed of at least one first-conductivity-type semiconductor region and at least one second-conductivity-type semiconductor region, the first-conductivity-type semiconductor region of the voltage-resisting layer is mutually contacted with the second-conductivity-type semiconductor region of the voltage-resisting layer, and a contact surface formed by the first-conductivity-type semiconductor region and the second-conductivity-type semiconductor region is perpendicular to the upper surface of the current collecting structure and the lower surfaces of the base region and the top region; the voltage-proof layer is in direct contact with the buffer area or in indirect contact with the buffer area through an auxiliary layer of a first conduction type;
the lower surface of the base region is in contact with the first-conductivity-type semiconductor region of the voltage-resisting layer through a first-conductivity-type carrier storage layer; at least part of the upper surface of the base region is covered with an emitter conductor and is connected to the emitter through a lead; at least one heavily doped region in the base region is in direct contact with the emitter conductor so as to form ohmic contact;
the upper surface of the emitting region is covered with an emitter conductor and is connected to the emitter through a lead;
the lower surface of the top region is in direct contact with the second-conductivity-type semiconductor region of the voltage-resisting layer, and the resistivity of the top region in the vertical direction is higher than that of the second-conductivity-type semiconductor region of the voltage-resisting layer in the vertical direction; the upper surface of the top area is at least partially covered with an emitter conductor and is connected to the emitter through a lead; at least one heavily doped region in the top region in direct contact with the emitter conductor so as to form an ohmic contact;
the top region and the base region are mutually isolated through a first groove-shaped grid structure connected with an emitter and/or the groove-shaped grid structure used for controlling a switch;
the groove-shaped grid structure for controlling the switch comprises an insulating medium layer and a conductor region surrounded by the insulating medium layer; the insulating medium layer of the groove-shaped grid structure for controlling the switch is in direct contact with the first conductivity type semiconductor regions of the emitter region, the base region, the carrier storage layer and the voltage-proof layer, or in direct contact with the first conductivity type semiconductor regions of the emitter region, the base region, the top region, the carrier storage layer, the voltage-proof layer and the second conductivity type semiconductor regions of the voltage-proof layer; the upper surface of a conductor region of the groove-shaped grid structure for controlling the switch is covered with a grid conductor and is connected to the grid through a lead;
the first groove-shaped grid structure connected with the emitter comprises an insulating medium layer and a conductor region surrounded by the insulating medium layer; the insulating medium layer of the first type of groove-shaped grid structure connected with the emitter is in direct contact with the base region, the top region, the carrier storage layer, the first conductivity type semiconductor region of the voltage-resisting layer and the second conductivity type semiconductor region of the voltage-resisting layer; the upper surface of a conductor region of the first type of the groove-shaped grid structure connected with the emitter is covered with an emitter conductor and is connected to the emitter through a lead;
the conductor region in the groove-shaped gate structure is made of heavily doped polycrystalline semiconductor materials; when the first conduction type is n type, the second conduction type is p type; when the first conductivity type is p-type, the second conductivity type is n-type.
2. The super junction insulated gate bipolar transistor device of claim 1, wherein:
a groove-shaped grid structure connected with an emitter of the second type is arranged above the semiconductor region of the first conductivity type of the voltage-resisting layer and/or the semiconductor region of the second conductivity type of the voltage-resisting layer; the second type of groove-shaped grid structure connected with the emitter comprises an insulating medium layer and a conductor region, the insulating medium layer is in direct contact with the base region, the carrier storage layer and the first conduction type semiconductor region of the voltage-resisting layer or in direct contact with the top region and the second conduction type semiconductor region of the voltage-resisting layer, and an emitter conductor covers the upper surface of the conductor region and is connected to the emitter through a lead.
3. The super junction insulated gate bipolar transistor device of claim 1, wherein:
in the extending direction of the groove-shaped grid structure for controlling the switch, the emitting region is a connected emitting region or a plurality of emitting regions which are not connected with each other; in the extending direction of the first type of emitter-connected groove-shaped gate structure, the heavily doped region in the top region is a connected heavily doped region or a plurality of heavily doped regions which are not connected with each other.
4. The super junction insulated gate bipolar transistor device of claim 1, wherein:
in the extending direction of the first type of groove-shaped grid structure connected with the emitter, the heavily doped regions in the top region are a plurality of heavily doped regions which are not communicated with each other, and the emitter conductor covered on the top region only covers the heavily doped regions in the top region.
5. The super junction insulated gate bipolar transistor device of claim 1, wherein:
the doping concentration of the carrier storage layer is higher than that of the first-conductivity-type semiconductor region of the voltage-resisting layer or equal to that of the first-conductivity-type semiconductor region of the voltage-resisting layer.
6. The super junction insulated gate bipolar transistor device of claim 1, wherein:
the doping concentration of the auxiliary layer is lower than that of the first-conductivity-type semiconductor region of the voltage-proof layer, or equal to that of the first-conductivity-type semiconductor region of the voltage-proof layer and that of the carrier storage layer.
7. The super junction insulated gate bipolar transistor device of claim 1, wherein:
the doping concentration of the buffer region is higher than that of the auxiliary layer, or equal to that of the auxiliary layer and that of the first-conductivity-type semiconductor region of the voltage-withstanding layer, or equal to that of the auxiliary layer, that of the first-conductivity-type semiconductor region of the voltage-withstanding layer, and that of the carrier storage layer.
8. The super junction insulated gate bipolar transistor device of claim 1, wherein:
the bottom of the groove-shaped gate structure is surrounded by a heavily doped semiconductor region of the second conductivity type; the heavily doped semiconductor region of the second conductivity type is in direct contact with the voltage-resistant layer.
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| CN108198851A (en) * | 2017-12-27 | 2018-06-22 | 四川大学 | A kind of superjunction IGBT with enhancing carrier storage effect |
| CN108389901A (en) * | 2018-04-24 | 2018-08-10 | 四川大学 | A kind of enhanced superjunction IGBT of carrier storage |
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| CN111668216A (en) * | 2019-03-08 | 2020-09-15 | 英飞凌科技奥地利有限公司 | Method for operating super junction transistor device |
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| CN108198851A (en) * | 2017-12-27 | 2018-06-22 | 四川大学 | A kind of superjunction IGBT with enhancing carrier storage effect |
| CN108389901A (en) * | 2018-04-24 | 2018-08-10 | 四川大学 | A kind of enhanced superjunction IGBT of carrier storage |
| CN111668216A (en) * | 2019-03-08 | 2020-09-15 | 英飞凌科技奥地利有限公司 | Method for operating super junction transistor device |
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