CN110491937B - IGBT with self-biased separation gate structure - Google Patents
IGBT with self-biased separation gate structure Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 abstract description 8
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- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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Abstract
The invention belongs to the technical field of power semiconductor devices, and relates to a power semiconductor deviceA TIGBT with self-biased PMOS split gate and a manufacturing method thereof. According to the invention, the PMOS structure is introduced on the basis of the traditional TIGBT, so that the saturation current of the device in the forward conduction is effectively improved under the condition of not reducing the channel density, the short-circuit safety working capacity of the device is improved, and meanwhile, the extra current leakage path provided by the PMOS structure accelerates the speed of the device for extracting holes in a blocking state, so that the switching speed of the device is improved, and the switching loss of the device is reduced. Meanwhile, for TIGBT with an N-type charge storage layer, the P-type buried layer can shield the influence of the N-type charge storage layer on the breakdown characteristic of the device, so that the doping concentration of the N-type charge storage layer can be increased, the carrier distribution of the device in forward conduction can be further improved, the conductivity modulation capability of a drift region can be improved, and the forward conduction voltage drop V of the device can be further improvedce(on)And turn-off loss EoffA compromise relationship between them.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and relates to an IGBT with a self-biased separation gate structure.
Background
Insulated Gate Bipolar Transistors (IGBTs) are one of the fastest growing electronic power devices today. Compared with the traditional transistor and MOSFET, the transistor and MOSFET have the advantages of both the transistor and MOSFET, and have the advantages of high input impedance, small control power, simple driving circuit, high switching speed and small switching loss of the MOSFET; the bipolar power transistor has the advantages of large current density, low saturation voltage, strong current processing capability and good stability, and is widely applied to the fields of high voltage, large current and the like.
The state of the art fabrication of IGBT device structures has been continuously improved since the beginning of the 20 th century and 80 th generation when IGBTs are available, through thirty years of development, and has now progressed to the seventh generation with charge storage insulated gate bipolar transistors (CSTBT). The seventh generation CSTBT introduces a layer of N-type charge storage layer with higher doping concentration below the surface P-type base region, and introduces a hole potential barrier below the P-type base region, so that the hole concentration of one end, close to an emitter, of the device is greatly improved when the device is conducted in the forward direction, and the electron concentration of the part is greatly increased according to the neutral requirement, therefore, the carrier concentration distribution of the N-drift region is improved, the conductivity modulation effect of the N-drift region is enhanced, the IGBT obtains lower forward conduction voltage drop, and the compromise relationship between the forward voltage drop and turn-off loss is improved. With the increase of the doping concentration of the N-type charge storage layer, the CSTBT conductivity modulation effect is stronger, and the forward conduction characteristic of the device is better. However, with the increasing doping concentration of the N-type charge storage layer, the breakdown voltage of the CSTBT device is remarkably reduced. In order to effectively shield the adverse effect of the N-type charge storage layer on the breakdown voltage of the device and obtain high withstand voltage, the adverse effect of the N-type charge storage layer can be shielded by increasing the depth of the trench gate (shown in fig. 1). However, an increase in the trench gate depth increases the gate capacitance, particularly the miller capacitance, of the device, resulting in a slower switching speed of the device.
Disclosure of Invention
In order to improve the influence of an N-type charge storage layer on the breakdown voltage of a device and reduce the adverse effect of a deep trench gate on the increase of the miller capacitance of the device, the invention provides an IGBT with a self-biased separation gate structure as shown in FIG. 2. According to the invention, the diode is connected between the P-type floating gate and the separation gate, the capacitor is connected between the separation gate and the emitter, when the device is in a blocking state, the separation gate structure can shield the influence of the N-type charge storage layer on the breakdown voltage of the device, and meanwhile, the capacitor connected between the separation gate and the emitter is in a charging state. When the device is conducted in the forward direction, the capacitor connected between the separation grid and the emitter starts to discharge, and then when the device is conducted in the forward direction, the separation grid is provided with a self-biased voltage, so that the N-type semiconductors nearby the side wall of the separation grid are distributed to form an accumulation layer, the on-resistance of the surface of the device is reduced, the on-voltage drop of the device is reduced, and the forward conduction characteristic of the device is improved.
The technical scheme of the invention is as follows:
an IGBT with a self-biased split gate structure, a half-cell structure of which is shown in fig. 2, comprising: the collector structure comprises a back collector metal 1, a P-type collector region 2, an N-type field stop layer 3 and an N-drift region 4 which are sequentially stacked from bottom to top; a P-type floating space region 8 is arranged on one side of the upper layer of the N-drift region 4, and a second metal 142 is arranged on the P-type floating space region 8; an N-type charge storage layer 7 is arranged on the other side of the upper layer of the N-drift region; a P-type base region 9 is arranged above the N-type charge storage layer 7; the upper layer of the P-type base region 9 is provided with an N + emitter region 11 and a P + emitter region 10 which are mutually independent; the upper surfaces of the N + emitting region 11 and the P + emitting region 10 are provided with emitter metal 13; one side of the P-type floating empty region 8 above the N-drift region 4 is provided with a groove structure, and the groove structure comprises a separation gate dielectric layer 51, a separation gate 52, a groove gate dielectric layer 61 and a groove gate 62; the upper surface of the separation gate dielectric layer is provided with a second dielectric layer 122; the upper surface of the separation gate is provided with a first metal 141; the upper surface of the trench gate is provided with a first dielectric layer 121; a diode 15 is connected between the second metal 142 and the first metal 141, and a capacitor 16 is connected between the first metal 141 and the emitter metal 13.
Further, a half-cell structure of the IGBT with a self-biased split gate structure is as shown in fig. 3, a super junction structure in which super junction P columns 42 and super junction N columns 41 are alternately arranged is introduced above the N-type field stop layer and below the P-type floating gate region 8, and doping concentrations of the P columns 42 and the N columns 41 meet charge balance requirements.
Further, a half-cell structure diagram of the IGBT with the self-biased split gate structure is shown in fig. 4, and a P + region 151 and an N + region 152 that are independent and placed side by side are integrated on one side of the second metal 142 on the upper surface of the second dielectric layer 122; a metal layer 143 is formed on the upper surface of the second dielectric layer 122 on one side of the N + region 152.
Further, a half-cell structure of the IGBT with a self-biased split gate structure is shown in fig. 5, and a P + region 151 is provided on one side above the P-type floating gate region 8; an N + region 152 is arranged on one side above the P + region; a metal layer 143 is formed on the top surface of the N + region, and one end of the metal layer 143 is connected to the N + region and the other end is connected to the capacitor 16.
Further, in the IGBT with the self-biased split gate structure, the half cell structure is as shown in fig. 6, a polysilicon layer 161 is provided inside the first dielectric layer 121, and the polysilicon layer 161 is connected to the first metal 141. The polysilicon layer 161, the first dielectric layer 121 and the metal 13 form a capacitor.
Working principle of the invention
When the collector 1 is connected with positive bias voltage, the gate electrode 62, the separation gate electrode 52 and the emitter metal 13 are connected with low voltage, the device is in a blocking state, the separation gate structure can shield the influence of the N-type charge storage layer on the breakdown voltage of the device, and because one end of the capacitor 16 is connected with the floating P area and the other end is connected with the emitter, the potential of the floating P area is higher in the blocking state, and the capacitor 16 is in a charging state; when the collector 1 is connected with a positive bias voltage, the gate electrode 62 is connected with a positive bias voltage higher than the threshold voltage of the device, the separation gate electrode 52 and the emitter metal 13 are connected with a low voltage, the device is in a conducting state, the potential of the floating P region is lower at the moment, the capacitor 16 starts to charge the separation gate electrode connected with the capacitor, and a certain voltage drop is generated on the separation gate electrode, so that an electron accumulation layer is generated on the N-type semiconductor on the side wall of the separation gate electrode, the conducting resistance of the device is greatly reduced, and the conducting voltage drop of the device is reduced.
The beneficial effects of the invention are as follows:
according to the invention, the diode is connected between the P-type floating space region and the separation gate electrode of the separation gate IGBT, and the capacitor is connected between the separation gate electrode and the emitter. When the split gate structure is applied to the IGBT with the charge storage layer and the charge storage layer with higher doping concentration, the split gate structure can shield the influence of the charge storage layer on the breakdown voltage of the device, the gate capacitance of the device is reduced while the breakdown voltage of the device is ensured, the switching speed of the device is improved, the switching loss is reduced, and the compromise relation between the forward conduction voltage drop and the turn-off loss of the device is improved. When the separation gate structure is applied to an IGBT without a charge storage layer or with a low doping concentration of the charge storage layer, when a device is in a blocking state, a capacitor connected between the separation gate electrode and an emitter is in a charging state, and when the device is conducted, the capacitor connected between the separation gate electrode and the emitter is in a discharging state, so that a higher potential is arranged on the separation gate electrode, silicon distributed along the side wall of the separation gate forms an accumulation layer due to the potential, the forward conduction resistance of the device is reduced, and the forward conduction characteristic of the device is improved. The separated gate structure can also be applied to the IGBT without a charge storage layer or with a low doping concentration of the charge storage layer.
Drawings
FIG. 1 is a schematic diagram of a conventional CSTBT cell;
fig. 2 is a schematic diagram of a half-cell structure of an IGBT with a self-biased split gate structure provided in embodiment 1 of the present invention;
fig. 3 is a schematic diagram of a half-cell structure of an IGBT with a self-biased split gate structure according to embodiment 2 of the present invention;
fig. 4 is a schematic diagram of a half-cell structure of an IGBT with a self-biased split gate structure according to embodiment 3 of the present invention;
fig. 5 is a schematic diagram of a half-cell structure of an IGBT with a self-biased split gate structure provided in embodiment 4 of the present invention;
fig. 6 is a schematic diagram of a half-cell structure of an IGBT with a self-biased split gate structure according to embodiment 5 of the present invention;
in fig. 1 to 6, 1 is a collector metal, 2 is a P + type collector region, 3 is an N-type field stop layer, 4 is an N-drift region, 41 is a super junction P column, 42 is a super junction N column, 51 is a split gate dielectric layer, 52 is a split gate electrode, 61 is a trench gate dielectric layer, 62 is a trench gate electrode, 7 is an N-type charge storage layer, 8 is a P-type floating space region, 9 is a P-type base region, 10 is a P + type emitter region, 11 is an N + emitter region, 12 is a dielectric layer, 121 is a first dielectric layer, 122 is a second dielectric layer, 13 is an emitter metal, 141 is a first metal, 142 is a second metal, 143 is a metal layer, 15 is a diode, 151 is a diode P + region, 152 is a diode N + region, 16 is a capacitor, and 161 is a polysilicon layer.
Detailed Description
The principles and features of the present invention are further described below in conjunction with the following drawings.
Example 1:
a IGBT with a self-biased separation gate structure, the half cell structure of which is shown in figure 2, comprises a collector metal 1; the collector structure comprises a P-type collector region 2 positioned on the upper surface of a collector metal 1, an N-type field stop layer 3 positioned above the P-type collector region 2, and an N-drift region 4 positioned above the N-type field stop layer 3; the P-type floating space region 8 is positioned on one side above the N-drift region 4; a second metal 142 positioned on the upper surface of the P-type floating gate region 8; the N-type charge storage layer 7 is positioned on the other side above the N-drift region, and the doping concentration of the N-type charge storage layer is greater than or equal to that of the N-drift region 4; a P-type base region 9 located on the upper surface of the N-type charge storage layer; the N + emitter region 11 and the P + emitter region 10 are arranged on the upper surface of the P-type base region 9 side by side and are independent of each other; emitter metal 13 on the upper surfaces of the N + emitter region 11 and the P + emitter region 10; the groove structure positioned on one side of the P-type floating space area comprises a separation gate dielectric layer 51 and a separation gate electrode 52, wherein the depth of the separation gate electrode 52 is greater than that of the N-type charge storage layer 7, the depth of the groove gate dielectric layer 61 and the depth of the groove gate electrode 62 are greater than that of the P-type base region 9 and less than that of the N-type charge storage layer 7; a second dielectric layer 122 located on the upper surface of the separation gate dielectric layer 51; a first metal 141 on an upper surface of the split gate electrode; a first dielectric layer 121 on an upper surface of the trench gate electrode; a diode 15 connected between the second metal 142 and the first metal 141; the capacitance between the first metal 141 and the emitter metal 13 is switched in.
Example 2
A IGBT with a self-biased separation gate structure, a half cell structure of which is shown in figure 3, comprises a collector metal 1; the collector structure comprises a P-type collector region 2 positioned on the upper surface of a collector metal 1, an N-type field stop layer 3 positioned above the P-type collector region 2, and an N-drift region 4 positioned above the N-type field stop layer 3; the P-type floating space region 8 is positioned on one side above the N-drift region 4; a second metal 142 positioned on the upper surface of the P-type floating gate region 8; an N-type charge storage layer 7 located on the other side above the N-drift region; a P-type base region 9 located on the upper surface of the N-type charge storage layer; the N + emitter region 11 and the P + emitter region 10 are arranged on the upper surface of the P-type base region 9 side by side and are independent of each other; emitter metal 13 on the upper surfaces of the N + emitter region 11 and the P + emitter region 10; the groove structure positioned on one side of the P-type floating space area comprises a separation gate dielectric layer 51 and a separation gate electrode 52, wherein the depth of the separation gate electrode 52 is greater than that of the N-type charge storage layer 7, the depth of the groove gate dielectric layer 61 and the depth of the groove gate electrode 62 are greater than that of the P-type base region 9 and less than that of the N-type charge storage layer 7; a second dielectric layer 122 located on the upper surface of the separation gate dielectric layer 51; a first metal 141 on an upper surface of the split gate electrode; a first dielectric layer 121 on an upper surface of the trench gate electrode; a diode 15 connected between the second metal 142 and the first metal 141; a capacitor connected between the first metal 141 and the emitter metal 13 is introduced, a super junction structure in which super junction P columns 42 and super junction N columns 41 are alternately arranged is introduced above the N-type field stop layer 3 and below the P-type floating space region 8, the doping concentrations of the P columns 42 and the N columns 41 meet the charge balance requirement, and the concentration of the super junction N columns 41 is greater than or equal to that of the N-drift region 4.
Example 3
A half-cell structure of the IGBT with the self-bias separation gate structure is shown in FIG. 4, a diode 15 is integrated on the surface of the IGBT on the basis of embodiment 1, and a P + region 151 and an N + region 152 which are arranged side by side on the upper surface of a second dielectric layer 122 and are independent of each other, a second metal 142 connected with the P + region 151 and a metal layer 143 connected with the N + region 152 form the diode.
The integration of the diode 15 into the IGBT reduces the package area of the chip and improves the integration of the chip.
Example 4
In the IGBT having a self-biased split gate structure, as shown in fig. 5, a diode 15 is integrated into the IGBT according to embodiment 2, and a P + region 151 located on the upper side of a P-type floating gate region, an N + region located on the upper side of the P + region 151, and a metal layer 143 connected to an N + region 152 constitute the diode.
The integration of the diode 15 into the IGBT reduces the package area of the chip and improves the integration of the chip.
Example 5
A half-cell structure of the IGBT with the self-bias separation gate structure is shown in FIG. 6, a capacitor 16 is integrated in the IGBT on the basis of embodiment 1, a capacitor formed by a polysilicon layer 161 and a metal emitter metal 13 and positioned in a first dielectric layer 121 replaces the capacitor 16, wherein the polysilicon layer 161 is connected with a first metal 141, and the metal 143 is connected with the first metal 141.
Integrating the capacitor 16 inside the IGBT reduces the package area of the chip and improves the integration of the chip.
Claims (5)
1. An IGBT with a self-biased split-gate structure comprising: the collector metal (1), a P + type collector region (2) positioned on the upper surface of the collector metal (1), an N-type field stop layer (3) positioned on the upper surface of the P + type collector region (2), and an N-drift region (4) positioned on the upper surface of the N-type field stop layer (3); the P-type floating area (8), the trench gate structure and the N-type charge storage layer (7) are sequentially arranged on the upper layer of the N-drift region (4) from one end to the other end, and the doping concentration of the N-type charge storage layer (7) is greater than or equal to that of the N-drift region (4); the junction depth of the P-type floating space region (8) and the trench gate structure is greater than that of the N-type charge storage layer (7); the upper surface of the N-type charge storage layer (7) is provided with a P-type base region (9), the upper surface of the P-type base region (9) is provided with an N + emitter region (11) and a P + emitter region (10) which are mutually independent side by side, and the N + emitter region (11) is positioned on one side close to the trench gate structure; the trench gate structure is characterized by comprising a separation gate dielectric layer (51), a separation gate electrode (52), a trench gate dielectric layer (61) and a trench gate electrode (62), wherein the junction depth of the separation gate electrode (52) is greater than that of an N-type charge storage layer (7), and the junction depth of the trench gate electrode (62) is greater than that of a P-type base region (9) and less than that of the N-type charge storage layer (7); a split gate electrode (52) semi-surrounding the trench gate electrode (62); the bottom of the separation gate electrode (52) is isolated from the N-drift region (4) through a separation gate dielectric layer (51), and the side surface of the separation gate electrode (52) is isolated from the P-type floating region (8) and the N-type charge storage layer (7) through the separation gate dielectric layer (51); the trench gate electrode (62) is isolated from the N + emitter region (11), the P-type base region (9) and the N-type charge storage layer (7) through a gate dielectric layer (61); the separation gate electrode (52) is separated from the trench gate electrode (62) through a separation gate dielectric layer (51); the upper surface of the separation gate dielectric layer (51) is provided with a second dielectric layer (122), and the upper surface of the separation gate electrode (52) is provided with a first metal (141); the upper surface of the trench gate electrode (62) is provided with a first dielectric layer (121); the upper surface of the P-type floating space region (8) is provided with a second metal (142); the upper surfaces of the N + emitting region (11) and the P + emitting region (10) are provided with emitter metal (13); the first metal (141) is connected with the second metal (142) through a diode, and the cathode of the diode is connected with the first metal (141); the first metal (141) is connected to the emitter metal (13) via a capacitor.
2. The IGBT with the self-biased split-gate structure according to claim 1, characterized in that: a P + region (151) and an N + region (152) which are mutually contacted and arranged side by side are integrated on one side of a second metal (142) on the upper surface of the second dielectric layer (122); and a metal layer (143) is arranged on one side of the N + region (152) and on the upper surface of the second dielectric layer (122).
3. The IGBT with the self-biased split-gate structure according to claim 1, characterized in that: a polysilicon layer (161) is arranged in the first dielectric layer (121), and the polysilicon layer (161) is connected with the first metal (141); the polycrystalline silicon layer (161), the first dielectric layer (121) and the emitter metal (13) form a capacitor.
4. An IGBT with a self-biased split-gate structure, comprising, a collector metal (1); the P + type collector region (2) is positioned on the upper surface of the collector metal (1), the N type field stop layer (3) is positioned on the upper surface of the P + type collector region (2), and the N-drift region (4) is positioned on the upper surface of the N type field stop layer (3); the P-type floating area (8) is positioned on one side above the N-drift area (4); a second metal (142) positioned on the upper surface of the P-type floating space region (8); an N-type charge storage layer (7) located on the other side above the N-drift region; a P-type base region (9) positioned on the upper surface of the N-type charge storage layer; the N + emitter region (11) and the P + emitter region (10) are arranged on the upper surface of the P-type base region (9) side by side and are mutually independent; an emitter metal (13) positioned on the upper surfaces of the N + emitting region (11) and the P + emitting region (10); the groove structure positioned on one side of the P-type floating space area comprises a separation gate dielectric layer (51), a separation gate electrode (52), a groove gate dielectric layer (61), a groove gate electrode (62), a P-type base region (9) and a P-type charge storage layer (7), wherein the depth of the separation gate electrode (52) is larger than that of the N-type charge storage layer (7); a second dielectric layer (122) positioned on the upper surface of the separation gate dielectric layer (51); a first metal (141) on an upper surface of the split gate electrode; a first dielectric layer (121) on an upper surface of the trench gate electrode; a diode (15) connected between the second metal (142) and the first metal (141); and a capacitor connected between the first metal (141) and the emitter metal (13), introducing a super junction structure with super junction P columns (42) and super junction N columns (41) which are alternately arranged above the N-type field stop layer (3) and below the P-type floating region (8), wherein the doping concentrations of the P columns (42) and the N columns (41) meet the charge balance requirement, and the concentration of the super junction N columns (41) is greater than or equal to that of the N-drift region (4).
5. The IGBT with the self-biased split-gate structure according to claim 4, characterized in that: a P + area (151) is arranged on one side above the P-type floating empty area (8); an N + region (152) is arranged on one side above the P + region; and a metal layer (143) is arranged on the upper surface of the N + region, one end of the metal layer (143) is connected with the N + region, and the other end of the metal layer (143) is connected with the capacitor (16).
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| CN113838917B (en) * | 2021-09-23 | 2023-03-28 | 电子科技大学 | Three-dimensional separation gate groove charge storage type IGBT and manufacturing method thereof |
| CN113838915B (en) * | 2021-09-23 | 2023-03-28 | 电子科技大学 | Trench gate charge storage type IGBT and manufacturing method thereof |
| CN113838922B (en) * | 2021-09-23 | 2023-04-28 | 电子科技大学 | Separated gate super-junction IGBT device structure with carrier concentration enhancement and method |
| CN113990933B (en) * | 2021-10-28 | 2023-05-26 | 电子科技大学 | Semiconductor longitudinal device and preparation method thereof |
| CN114256330B (en) * | 2021-12-22 | 2023-05-26 | 电子科技大学 | Super-junction IGBT terminal structure |
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| JP4136778B2 (en) * | 2003-05-07 | 2008-08-20 | 富士電機デバイステクノロジー株式会社 | Insulated gate bipolar transistor |
| JP4840738B2 (en) * | 2005-03-15 | 2011-12-21 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
| US8378411B2 (en) * | 2009-05-18 | 2013-02-19 | Force Mos Technology., Ltd. | Power semiconductor devices integrated with clamp diodes having separated gate metal pads to avoid breakdown voltage degradation |
| JP5961865B2 (en) * | 2010-09-15 | 2016-08-02 | ローム株式会社 | Semiconductor element |
| CN107170815B (en) * | 2017-05-11 | 2019-09-27 | 电子科技大学 | A kind of landscape insulation bar double-pole-type transistor |
| CN107293579B (en) * | 2017-06-29 | 2019-10-01 | 四川大学 | A kind of superjunction IGBT with low conduction voltage drop |
| CN107731898B (en) * | 2017-10-20 | 2020-09-15 | 电子科技大学 | CSTBT device and manufacturing method thereof |
| CN107623027B (en) * | 2017-10-20 | 2020-03-31 | 电子科技大学 | Trench gate charge storage type insulated gate bipolar transistor and manufacturing method thereof |
| CN107799582B (en) * | 2017-10-20 | 2021-03-16 | 电子科技大学 | Trench gate charge storage type insulated gate bipolar transistor and manufacturing method thereof |
| CN108198851B (en) * | 2017-12-27 | 2020-10-02 | 四川大学 | Super-junction IGBT with carrier storage effect |
| CN109300975B (en) * | 2018-09-29 | 2021-03-30 | 电子科技大学 | Trench gate bipolar transistor with low electromagnetic interference noise characteristic |
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