CN109300975B - Trench gate bipolar transistor with low electromagnetic interference noise characteristic - Google Patents
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- 239000004065 semiconductor Substances 0.000 claims abstract description 58
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 230000001413 cellular effect Effects 0.000 claims abstract description 20
- 230000000694 effects Effects 0.000 claims abstract description 7
- 238000002161 passivation Methods 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 6
- 238000006073 displacement reaction Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract description 3
- 238000000605 extraction Methods 0.000 abstract description 2
- 238000009825 accumulation Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
Abstract
The invention belongs to the technical field of semiconductor devices, and particularly relates to a trench gate bipolar transistor with low electromagnetic interference noise characteristics. The main scheme of the invention is as follows: firstly, a structure that cellular areas and dummy cellular areas are alternately arranged in the horizontal direction is adopted, and the dummy cellular areas are connected with a metalized emitter and do not float; and secondly, a polysilicon diode structure is formed by vertically extending the device on the upper surface of the dummy cell, so that the P-type semiconductor strip and the metalized emitter are connected with the polysilicon diode structure through floating ohmic contact, and the effect of clamping the potential of the P-type semiconductor strip is achieved. When the device is started, the charging effect of the hole current on the gate capacitor is greatly weakened, so that the gate control capability of the device is greatly improved, and the electromagnetic interference noise of the device is reduced. When the device is conducted, the potential of the P-type semiconductor strip is clamped by the diode, the extraction effect of the P-type semiconductor strip on holes is inhibited, the conductance modulation effect of the device is enhanced, and the conduction voltage drop is reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a Trench-Gate Bipolar transistor (TIGBT for short) with low electromagnetic interference noise characteristics.
Background
The high-voltage power semiconductor device is an important component of power electronics, and has wide application in fields such as motor driving in a power system, frequency conversion in consumer electronics and the like. In application, the high-voltage power semiconductor is required to have the characteristics of low power loss, high short circuit resistance, low electromagnetic interference noise and the like. The traditional Insulated Gate Bipolar Transistor (IGBT for short) is widely applied due to the excellent performance of the traditional Insulated Gate Bipolar Transistor in the field of medium-high voltage power electronics, but the key parameters of the IGBT as a Bipolar device are in a compromise relationship between the turn-on voltage drop and the turn-off loss. The IGBT with the floating dummy cells improves the power consumption compromise relationship of the traditional IGBT and obtains a larger short-circuit safe working area. However, the IGBT (Floating-P IGBT) with Floating dummy cells has too much electromagnetic interference noise during the turn-on process, which affects the reliability of the device.
Disclosure of Invention
The invention aims to solve the problems and provides a potential self-modulation groove gate type IGBT structure (called SRP-IGBT), which greatly reduces electromagnetic interference noise in the opening process of the IGBT, further reduces the power loss of a device and increases the short-circuit safe working area of the device.
In order to achieve the purpose, the invention adopts the following technical scheme:
a trench gate bipolar transistor is shown in figure 1; the cell is formed by alternately arranging a dummy cell area 1 and a cell area 2 in the horizontal direction; the dummy cell region 1 comprises a collector structure, a drift region structure and a polysilicon diode structure; the collector structure comprises a metalized collector 3 and a P-collector positioned on the upper surface of the metalized collector 3; the drift region structure comprises an N-buffer layer 5 positioned on the upper surface of the P-collector and a P-type semiconductor strip 6 positioned on the upper surface of the N-buffer layer 5; the polycrystalline silicon diode structure comprises an oxide layer 11, P-type polycrystalline silicon 12, N-type polycrystalline silicon 13, a floating ohmic contact 14, a passivation isolation layer 15 and a metalized emitter 17; the oxide layer 11 extends into the P-type semiconductor strip 6 along the vertical direction of the symmetry axis of the P-type semiconductor strip 6 to form a groove, and the side surface of the oxide layer 11 is only contacted with the P-type semiconductor strip 6; the P-type polycrystalline silicon 12 is positioned in the groove; the N-type polycrystalline silicon 13 extends into the P-type polycrystalline silicon 12 along the vertical direction of the symmetry axis of the P-type polycrystalline silicon 12, and the junction depth of the N-type polycrystalline silicon 13 is shallower than that of the P-type polycrystalline silicon 12; the floating ohmic contact 14 is in contact with the upper surfaces of the P-type semiconductor strips 6, the oxide layer 11 and the P-type polycrystalline silicon 12, and the floating ohmic contact 14 is isolated from the metalized emitter 17 through a passivation isolation layer 15; the metallized emitter 17 is positioned on the upper surfaces of the N-type polycrystalline silicon 13 and the passivation isolating layer 15; the cellular region 2 comprises a collector structure, a drift region structure, an emitter structure and a groove structure; the collector structure comprises a metalized collector 3 and a P-collector positioned on the upper surface of the metalized collector 3; the drift region structure comprises an N-buffer layer 5 positioned on the upper surface of the P-collector and an N-type semiconductor strip 7 positioned on the upper surface of the N-buffer layer 5; the emitter structure comprises a P-type base region 8, a P + contact region 9, an N + emitter region 10 and a metalized emitter 17, and is positioned on the upper layer of the N-type semiconductor strip 7 and between two adjacent groove structures; the N + emission regions 10 are positioned at two ends of the upper surface of the cellular region 2; the P + contact region 9 is positioned between two adjacent N + emitting regions 10; the metallized emitter 17 is positioned on the upper surfaces of the P + contact region 9 and the N + emitter region 10; the groove structure comprises a gate oxide layer 18 and a polysilicon gate 16; the gate oxide layer 18 extends into the N-type semiconductor strip 7 along the vertical direction of the device to form a groove, and the side face of the gate oxide layer is contacted with the N + emitter region 10, the P-type base region 8, the N-type semiconductor strip 7 and the P-type semiconductor 6; the polysilicon gate 16 is located in the trench. The SRP-IGBT is characterized by comprising dummy cell areas 1 and cell areas 2 which are alternately arranged in the horizontal direction; the dummy cell area 1 and the cell area 2 are connected together through a metalized emitter 17; the P-type semiconductor strip 6 and the metalized emitter 17 are connected together through the floating ohmic contact 14 and the polysilicon diode structure, so that the potential of the P-type semiconductor strip is clamped.
The general technical scheme of the invention mainly has three points, firstly, the device adopts a structure that cellular areas and dummy cellular areas are alternately arranged in the horizontal direction; the dummy cell area is connected with the metallized emitter and does not float; and thirdly, the P-type semiconductor strip and the metalized emitter are connected with the polysilicon diode structure through floating ohmic contact.
The invention has the beneficial effects that through the new structure of the trench gate bipolar transistor (SRP-IGBT), on the premise of not changing the parameters of the device, the electromagnetic noise interference of the device during opening is greatly reduced, the power loss of the device is reduced, and the short-circuit safe working area of the device is enlarged.
Drawings
FIG. 1 is a schematic diagram of an SRP-IGBT structure of the present invention;
FIG. 2 is a schematic diagram of an IGBT structure with floating dummy cells;
FIG. 3 is a graph comparing threshold voltages of an IGBT with floating dummy cells and an SRP-IGBT provided by the present invention;
FIG. 4 is a graph comparing breakdown voltages of an IGBT with floating dummy cells and an SRP-IGBT provided by the present invention;
FIG. 5 is a graph comparing the trade-off relationship between the electromagnetic interference noise and the turn-on power consumption of the IGBT with floating dummy cells and the SRP-IGBT provided by the invention;
FIG. 6 is a graph comparing the power consumption trade-off relationship between the IGBT with floating dummy cells and the SRP-IGBT provided by the invention;
FIG. 7 is a graph comparing the short circuit characteristics of an IGBT with floating dummy cells and an SRP-IGBT according to the present invention;
Detailed Description
The technical scheme of the invention is described in detail in the following with the accompanying drawings:
the novel trench gate bipolar transistor disclosed by the invention has the advantages that the structural schematic diagram is shown in fig. 1, the starting electromagnetic noise interference of the IGBT is greatly reduced, the power loss of the IGBT is reduced, and the short-circuit safe working area of the IGBT is enlarged. The main scheme of the invention is that a cellular area and a dummy cellular area which are alternately arranged in the horizontal direction are adopted, and the cellular area and the dummy cellular area are connected through a metallized emitter, so that the dummy cellular area is not floated; and secondly, connecting the P-type semiconductor strip and the metalized emitter together through a floating ohmic contact and a polysilicon diode structure, and clamping the potential of the P-type semiconductor strip.
A trench gate bipolar transistor is shown in figure 1; the cell is formed by alternately arranging a dummy cell area 1 and a cell area 2 in the horizontal direction; the dummy cell region 1 comprises a collector structure, a drift region structure and a polysilicon diode structure; the collector structure comprises a metalized collector 3 and a P-collector positioned on the upper surface of the metalized collector 3; the drift region structure comprises an N-buffer layer 5 positioned on the upper surface of the P-collector and a P-type semiconductor strip 6 positioned on the upper surface of the N-buffer layer 5; the polycrystalline silicon diode structure comprises an oxide layer 11, P-type polycrystalline silicon 12, N-type polycrystalline silicon 13, a floating ohmic contact 14, a passivation isolation layer 15 and a metalized emitter 17; the oxide layer 11 extends into the P-type semiconductor strip 6 along the vertical direction of the symmetry axis of the P-type semiconductor strip 6 to form a groove, and the side surface of the oxide layer 11 is only contacted with the P-type semiconductor strip 6; the P-type polycrystalline silicon 12 is positioned in the groove; the N-type polycrystalline silicon 13 extends into the P-type polycrystalline silicon 12 along the vertical direction of the symmetry axis of the P-type polycrystalline silicon 12, and the junction depth of the N-type polycrystalline silicon 13 is shallower than that of the P-type polycrystalline silicon 12; the floating ohmic contact 14 is in contact with the upper surfaces of the P-type semiconductor strips 6, the oxide layer 11 and the P-type polycrystalline silicon 12, and the floating ohmic contact 14 is isolated from the metalized emitter through a passivation isolation layer 15; the metallized emitter 17 is positioned on the upper surfaces of the N-type polycrystalline silicon 13 and the passivation isolating layer 15; the cellular region 2 comprises a collector structure, a drift region structure, an emitter structure and a groove structure; the collector structure comprises a metalized collector 3 and a P-collector positioned on the upper surface of the metalized collector 3; the drift region structure comprises an N-buffer layer 5 positioned on the upper surface of the P-collector and an N-type semiconductor strip 7 positioned on the upper surface of the N-buffer layer 5; the emitter structure comprises a P-type base region 8, a P + contact region 9, an N + emitter region 10 and a metalized emitter 17, and is positioned on the upper layer of the N-type semiconductor strip 7 and between two adjacent groove structures; the N + emission regions 10 are positioned at two ends of the upper surface of the cellular region 2; the P + contact region 9 is positioned between two adjacent N + emitting regions 10; the metallized emitter 17 is positioned on the upper surfaces of the P + contact region 9 and the N + emitter region 10; the groove structure comprises a gate oxide layer 18 and a polysilicon gate 16; the gate oxide layer 18 extends into the N-type semiconductor strip 7 along the vertical direction of the device to form a groove, and the side face of the gate oxide layer is contacted with the N + emitter region 10, the P-type base region 8, the N-type semiconductor strip 7 and the P-type semiconductor strip 6; the polysilicon gate 16 is located in the trench. The SRP-IGBT is characterized by comprising dummy cell areas 1 and cell areas 2 which are alternately arranged in the horizontal direction; the dummy cell area 1 and the cell area 2 are connected together through a metalized emitter 17; the P-type semiconductor strip 6 and the metalized emitter 17 are connected together through the floating ohmic contact 14 and the polysilicon diode structure, so that the potential of the P-type semiconductor strip is clamped.
The working principle of the invention is as follows: and applying a positive voltage to a metalized collector 11 of the IGBT and applying zero voltage to a metalized emitter 8, so that the IGBT works in a blocking state. At this time, a voltage is applied to the gate of the IGBT, and the IGBT is gradually turned from the blocking state to the opening state. In the initial stage of starting the IGBT, the N-type semiconductor strips in the cellular region and the P-type semiconductor strips in the dummy cellular region are laterally depleted, so that the potential of the P-type semiconductor strips is lower than that of the N-type semiconductor strips. At this time, the hole displacement current from the collector side flows along the P-type semiconductor strips to the emitter side and then flows out of the device through the polysilicon diode, suppressing the accumulation of holes near the gate. Meanwhile, the presence of the polysilicon diode occupies most of the area on the emitter side of the dummy cell, and also suppresses the accumulation of holes in the vicinity of the gate. The gate capacitor is charged by displacement current generated by the accumulation of the holes, so that the gate control capability of the IGBT is weakened when the IGBT is started, and the electromagnetic interference noise is increased. And the SRP-IGBT reduces the charging effect of the displacement current on the gate capacitor, thereby enhancing the gate control capability of the device when the device is started and reducing the electromagnetic interference noise.
When the SRP-IGBT is in a conducting state, the potential of the P-type semiconductor strip is clamped by the diode, the extraction of holes by the P-type semiconductor strip is inhibited, the conductance modulation effect of the device is enhanced, and the conducting voltage drop is reduced. Meanwhile, when the SRP-IGBT is turned off, because the N-type semiconductor strips of the cellular region and the P-type semiconductor strips of the dummy cellular region are transversely depleted, the excess current carriers are quickly extracted out of the device, and the turn-off time is greatly reduced. Therefore, the SRP-IGBT has extremely low power loss.
When the SRP-IGBT is in a short circuit state, because the potential of the P-type semiconductor strip is clamped by the polysilicon diode, part of hole current from the collector side is led out of the device through the polysilicon diode, and therefore the hole current flowing through the P-base region is reduced. And when the hole current flowing through the P-base region is large enough, the opening of the IGBT parasitic thyristor can be triggered, so that the device fails. For the SRP-IGBT, fewer holes flowing through the P-base region can greatly inhibit the starting of a parasitic thyristor, so that the short-circuit safe working area of the SRP-IGBT is enlarged.
The SRP-IGBT and the Floating dummy cell IGBT (Floating-P IGBT) structure provided by the invention are subjected to simulation comparison, and the superiority of the structure is further verified. Fig. 3 and 4 show a comparison of threshold voltage and withstand voltage characteristics of the SRP-IGBT and the Floating-P IGBT. In order to ensure fair comparison, the consistent blocking capability and threshold voltage of the SRP-IGBT and the Floating-P IGBT must be ensured; FIG. 5 shows SRP-IGBT and Floating-P IGBT turn-on power consumption and electromagnetic interference noise (Maxmum dV)KADt). As can be seen from FIG. 5, at the same power-on consumption (E)on) Maxmum dV of SRP-IGBTKAThe/dt is reduced from 12.86 kV/mu s to 2.82 kV/mu s, the reduction of 78% is realized, and the electromagnetic interference noise generated when the IGBT is turned on is greatly inhibited.
FIG. 6 shows the turn-on voltage drop (V) of the SRP-IGBT and the Floating-P IGBTon) And turn-off loss (E)off) A compromise relationship curve. As can be seen, the SRP-IGBT has a more optimized compromise curve of on-voltage drop and off-loss. Under the same turn-off loss, the turn-on voltage drop of the SRP-IGBT is reduced by 35 percent compared with the turn-on voltage of the C-IGBT.
FIG. 7 shows short-circuit characteristic comparison curves for SRP-IGBT and Floating-P IGBT. As can be seen, the SRP-IGBT fails after a 10.4 μ s short circuit impact, and the Floating-P IGBT fails after a 7.6 μ s short circuit impact. The short-circuit duration of the SRP-IGBT is 37% longer than that of the Floating-P IGBT.
By aiming at key parameters of the IGBT: compared with the electromagnetic interference noise, the power loss and the short-circuit resistance, the performance advantage of the structure of the invention in the application of the medium-high voltage power semiconductor device is intuitively demonstrated.
Claims (5)
1. A trench gate bipolar transistor with low electromagnetic interference noise characteristic is characterized in that along the transverse direction, the device is formed by alternately arranging a dummy cell area (1) and a cell area (2);
the dummy cell region (1) comprises a first collector structure, a first drift region structure and a polysilicon diode structure; the first collector structure comprises a metalized collector (3) and a P-collector (4) positioned on the upper surface of the metalized collector (3); the first drift region structure comprises an N-buffer layer (5) positioned on the upper surface of a P-collector (4) and a P-type semiconductor strip (6) positioned on the upper surface of the N-buffer layer (5); the polycrystalline silicon diode structure comprises an oxide layer (11), P-type polycrystalline silicon (12), N-type polycrystalline silicon (13), floating ohmic contacts (14), a passivation isolating layer (15) and a metalized emitter (17); the oxide layer (11) extends into the P-type semiconductor strip (6) along the vertical direction of the symmetry axis of the P-type semiconductor strip (6) to form a groove, and the side surface of the oxide layer (11) is only contacted with the P-type semiconductor strip (6); the P-type polycrystalline silicon (12) is positioned in the groove; the N-type polycrystalline silicon (13) extends into the P-type polycrystalline silicon (12) along the vertical direction of the symmetry axis of the P-type polycrystalline silicon (12), and the junction depth of the N-type polycrystalline silicon (13) is shallower than that of the P-type polycrystalline silicon (12); the floating ohmic contact (14) is in contact with the upper surfaces of the P-type semiconductor strips (6), the oxidation layer (11) and the P-type polycrystalline silicon (12), the metalized emitter (17) is positioned on the upper surfaces of the N-type polycrystalline silicon (13) and the passivation isolation layer (15), and the floating ohmic contact (14) is isolated from the metalized emitter (17) through the passivation isolation layer (15);
the cellular region (2) comprises a second collector structure, a second drift region structure, an emitter structure and a groove structure; the second collector structure comprises a metalized collector (3) and a P-collector (4) positioned on the upper surface of the metalized collector (3); the second drift region structure comprises an N-buffer layer (5) positioned on the upper surface of the P-collector (4) and an N-type semiconductor strip (7) positioned on the upper surface of the N-buffer layer (5); the emitter structure comprises a P-type base region (8), a P + contact region (9), an N + emitter region (10) and a metalized emitter (17), and is positioned on the upper layer of the N-type semiconductor strip (7) and between two adjacent groove structures; the N + emission regions (10) are positioned at two ends of the upper surface of the cellular region (2); the P + contact region (9) is positioned between two adjacent N + emission regions (10); the metalized emitter (17) is positioned on the upper surfaces of the P + contact region (9) and the N + emitter region (10); the groove structure comprises a gate oxide layer (18) and a polysilicon gate (16); the gate oxide layer (18) extends into the N-type semiconductor strip (7) along the vertical direction of the device to form a groove, and the side face of the gate oxide layer is contacted with the N + emitter region (10), the P-type base region (8), the N-type semiconductor strip (7) and the P-type semiconductor strip (6); the polysilicon gate (16) is located in the trench.
2. The trench gate bipolar transistor with low emi noise characteristics as claimed in claim 1, wherein:
the dummy cell area (1) and the cell area (2) are connected together through a metalized emitter, so that the dummy cells are not floated.
3. The trench gate bipolar transistor with low emi noise characteristics as claimed in claim 1, wherein:
the polysilicon diode is a groove structure which is manufactured on the upper surface of a dummy cell area which is vertically inserted.
4. The trench gate bipolar transistor with low emi noise characteristics as claimed in claim 1, wherein:
the polysilicon diode eliminates the collection capability of the P-type semiconductor strip (6) to holes by being embedded into the top of the dummy cell area, thereby reducing the charging effect of hole displacement current to gate capacitance in the starting process of the device and reducing electromagnetic interference noise.
5. The trench gate bipolar transistor with low emi noise characteristics as claimed in claim 1, wherein:
the polysilicon diode clamps the potential of the P-type semiconductor strip, so that most hole current is conducted away by the polysilicon diode when the device works in an open state and a short-circuit state.
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| CN109920841B (en) * | 2019-03-26 | 2020-12-18 | 电子科技大学 | Trench gate bipolar transistor |
| CN110491937B (en) * | 2019-08-22 | 2021-04-13 | 电子科技大学 | IGBT with self-biased separation gate structure |
| CN114093934B (en) * | 2022-01-20 | 2022-05-20 | 深圳市威兆半导体有限公司 | IGBT device and manufacturing method thereof |
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