CN114093934B - IGBT device and manufacturing method thereof - Google Patents
IGBT device and manufacturing method thereof Download PDFInfo
- Publication number
- CN114093934B CN114093934B CN202210062869.3A CN202210062869A CN114093934B CN 114093934 B CN114093934 B CN 114093934B CN 202210062869 A CN202210062869 A CN 202210062869A CN 114093934 B CN114093934 B CN 114093934B
- Authority
- CN
- China
- Prior art keywords
- region
- electrode
- junction structure
- gate
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 52
- 238000000034 method Methods 0.000 claims abstract description 29
- 230000008569 process Effects 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 239000000969 carrier Substances 0.000 claims description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 239000002800 charge carrier Substances 0.000 claims 1
- 239000004973 liquid crystal related substance Substances 0.000 claims 1
- 238000006073 displacement reaction Methods 0.000 abstract description 12
- 239000003990 capacitor Substances 0.000 abstract description 8
- 238000009825 accumulation Methods 0.000 abstract description 7
- 230000002829 reductive effect Effects 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 230000001052 transient effect Effects 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
An IGBT device and a method of manufacturing the same, the IGBT device comprising at least one cell, the cell comprising a first electrode, a second electrode, and a semiconductor unit located between the first electrode and the second electrode, the semiconductor unit comprising: the semiconductor device comprises a base region, a source region, a drift region and a collector region, wherein a first PN junction is formed between the source region and the base region, the semiconductor device further comprises a trench gate structure and a PN junction structure, the PN junction structure is formed in a gate dielectric layer and is positioned on at least one side of a grid electrode, the side of the grid electrode is far away from a channel region, a first conductive type region in the PN junction structure is electrically connected with a first electrode, and a second conductive type region in the PN junction structure is floated in the gate dielectric layer. In the forward voltage withstanding process, the potential of the second conductivity type region is raised, the voltage of the second electrode is maintained unchanged, so that the charge on the depletion layer capacitor cannot be discharged, the second conductivity type region maintains a higher potential, and the potential of the bottom of the surrounding trench gate is raised, so that the accumulation of holes at the bottom of the gate dielectric layer is inhibited, and the generation of displacement current is inhibited.
Description
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to an IGBT device and a manufacturing method thereof.
Background
The IGBT device is a mainstream device of a novel power semiconductor device, and is a core of a power electronic device and a system. The IGBT has the advantages of both an MOS transistor and a BJT (bipolar Junction transistor) transistor, has the excellent characteristics of low conduction voltage drop, driving power, high input impedance, high breakdown voltage, high switching frequency and the like, has a wide application voltage range, and can greatly improve the power utilization efficiency and quality of equipment.
In the process of the IGBT development, an FP IGBT (Floating P-base) structure is presented. Due to the introduction of the floating P region, holes are accumulated when the IGBT is started, so that the hole current density flowing from the bottom of the grooved gate dielectric layer to the emitter is improved, the unbalanced hole concentration at the bottom of the grooved gate is increased, the conduction voltage drop of the device is reduced, and the compromise of saturated conduction voltage drop and turn-off loss is realized. However, the large area of the trench gate opposite to the collector can cause large miller capacitance, which causes the miller plateau to be long when the device is in the on state and the miller capacitanceUnder the action of the current, a displacement current for charging the grid electrode is generated, so that the grid electrode resistance R is enabledGdI in open stateCDt and dVCEThe controllability of/dt is deteriorated, causing large EONAnd EMI noise.
Disclosure of Invention
The invention mainly solves the technical problem that the current IGBT device generates displacement current for charging a grid electrode by collector electrode hole current in the opening transient state.
According to a first aspect, an embodiment provides an IGBT device comprising at least one cell, the cell comprising a first electrode, a second electrode, and a semiconductor unit located between the first electrode and the second electrode, the semiconductor unit comprising:
a base region having a first conductivity type;
the source region is provided with a second conductive type, the first conductive type and the second conductive type belong to different semiconductor conductive types, a first PN junction is formed between the source region and the base region, and the base region and the source region are respectively and electrically connected with the first electrode;
the drift region is positioned below the base region, has a second conduction type and is used as a depletion layer when the IGBT device is in a forward voltage withstanding process;
the collector region is positioned below the drift region, has a first conduction type, is electrically connected with the second electrode and is used for providing current carriers when the IGBT device is in an on state;
the trench gate structure comprises a gate and a gate dielectric layer wrapping the gate, wherein the gate dielectric layer penetrates through the base region and extends to the drift region;
the PN junction structure is formed in the gate dielectric layer and located on at least one side, far away from the channel region, of the grid electrode, the first conduction type region in the PN junction structure is electrically connected with the first electrode, and the second conduction type region in the PN junction structure is floating in the gate dielectric layer.
According to a second aspect, an embodiment provides a method for manufacturing an IGBT device, including:
providing a substrate, wherein the substrate comprises a collector region, a buffer layer, a drift region and a base region which are stacked from bottom to top, or the substrate comprises a collector region, a drift region and a base region which are stacked from bottom to top;
forming a source region on the base region; the base region and the collector region are of a first conductivity type; the source region, the drift region and the buffer layer are of a second conduction type, the first conduction type and the second conduction type belong to different semiconductor conduction types, and a first PN junction is formed between the source region and the base region; the drift region is used as a depletion layer in the forward voltage withstanding process of the IGBT device; the collector region is used for providing current carriers when the IGBT device is in an on state; the buffer layer is used as a field stop layer in the forward voltage withstanding process of the IGBT device, and the doping concentration of the buffer layer is greater than that of the drift region;
forming a first trench on the substrate, wherein the first trench penetrates through the base region and extends to the drift region;
forming a trench gate structure on the first trench, wherein the trench gate structure comprises a gate and a gate dielectric layer wrapping the gate;
forming a second groove on the gate dielectric layer, and forming a PN junction structure on the second groove; the PN junction structure is positioned on at least one side of the grid electrode, which is far away from the channel region, and the second conductive type region in the PN junction structure is floated in the grid dielectric layer;
and forming a first electrode and a second electrode, wherein the base region, the source region and the first conductive type region in the PN junction structure are respectively electrically connected with the first electrode, and the collector region is electrically connected with the second electrode.
According to the IGBT device and the method of manufacturing the same of the above embodiments, a PN junction structure is formed in the gate dielectric layer, where the first conductivity type region of the PN junction structure is connected to the first electrode, and the second conductivity type region of the PN junction structure is in a floating state. When the IGBT device is in a forward voltage-resistant state, the PN junction structures are mutually depleted, and a depletion layer capacitor is formed. In the forward voltage withstanding process, the potential of the second conductivity type region of the PN junction structure is raised, and since the voltage of the second electrode is maintained unchanged, the charge on the depletion layer capacitor cannot be discharged, and the second conductivity type region of the PN junction structure maintains a higher potential, so that the potential at the bottom of the surrounding trench gate is raised. Since the bottom potential of the trench gate is raised, the gate is inhibited from being damaged in the on stateThe holes at the bottom of the dielectric layer are accumulated to suppress the displacement current for charging the gate electrode, so that the gate electrode is aligned with dICControllability of/dt is enhanced and EMI noise is suppressed.
Drawings
Fig. 1 to fig. 3 are schematic structural diagrams of an IGBT device according to an embodiment;
fig. 4 is a flowchart of a method for manufacturing an IGBT device according to an embodiment;
fig. 5 to 15 are schematic process diagrams of a method for manufacturing an IGBT device according to an embodiment;
fig. 16 is a schematic structural diagram of a conventional IGBT device;
fig. 17 is a schematic structural diagram of an IGBT device according to an embodiment.
Reference numerals: 1-a first electrode; 2-a second electrode; 3-base region; a 4-source region; 5-a drift region; 51-a first trench; 6-a collector region; 7-trench gate structure; 71-a gate; 72-a gate dielectric layer; 721-a second trench; 722-a third trench; 8-PN junction structure; 81-a first conductivity type region; 82-second conductivity type region; 9-buffer layer.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous specific details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of clearly describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where a certain sequence must be followed.
The ordinal numbers used herein for the components, such as "first," "second," etc., are used merely to distinguish between the objects described, and do not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
As shown in fig. 16, in the conventional trench gate IGBT device, during the device turn-on process, a hole current can only flow to the base region 3 through the long and narrow drift region 5 between the trench gates by diffusion, and then enters the emitter electrode (corresponding to the first electrode 1), and a hole injected by the collector electrode (corresponding to the second electrode 2) is accumulated in the dielectric layer at the bottom of the trench gate structure 7, so that a floating potential is generated, and a displacement current for charging the gate electrode 71 is generated.
As shown in fig. 17, it was found in the research that by reducing the width of the gate and covering the side of the trench gate structure 7 away from the channel a with a thicker gate dielectric layer 72, the facing area of the gate 71 and the collector is reduced, the miller capacitance is reduced, and the E is loweredON. Because the gate dielectric layer replaces the trench gate structure at the corresponding position, V is in the opening transient stateGEOvershoot and large dVGEThe/dt is inhibited to some extent. However, in this structure, during the turn-on transient of the device, the hole current injected from the collector still flows through the bottom of the gate dielectric layer of the trench gate, causing hole accumulation therein, generating a displacement current for charging the gate electrode 71, causing EMI noise and large dICThe situation of/dt, and the thicker oxide layer, also leads to the reduction of the turn-on voltage drop and the breakdown voltage of the device itself. In the present application, the gate dielectric layer is exemplified as a silicon dioxide layer, and therefore, the gate dielectric layer may also be referred to as a gate oxide layer or simply an oxide layer. In the absence of special characteristicsIn other cases, when describing the trench gate structure, the oxide layers are all referred to as gate dielectric layers.
In the present application, the first conductivity type and the second conductivity type belong to different semiconductor conductivity types, and the first conductivity type and the second conductivity type are P-type and N-type, and when the first conductivity type is N-type, the second conductivity type is P-type, and vice versa.
In the present application, the source region 4 may also be referred to as an emitter region, and is of a different conductivity type from the base region 3.
In the embodiment of the present invention, a further improvement is made on the basis of the IGBT device shown in fig. 17, by providing a longitudinal PN junction structure 8 on the gate dielectric layer 72, where the PN junction structure 8 is electrically connected to the first electrode 1 (emitter) to affect the potential at the bottom of the trench gate structure 7, and in the turn-on transient state of the IGBT device, suppressing the displacement current charging the gate 71, so that the gate 71 pair dI is enabledCThe/dt controllability is enhanced and EMI noise is suppressed.
The first embodiment is as follows:
referring to fig. 1, the present embodiment provides an IGBT device including at least one cell, where the cell includes a first electrode 1, a second electrode 2, and a semiconductor unit located between the first electrode 1 and the second electrode 2, and the semiconductor unit may include a base region 3, a source region 4, a drift region 5, a collector region 6, a trench gate structure 7, and a PN junction structure 8. The IGBT device is described below as an example of an N-channel enhancement type.
In the embodiment shown in fig. 1, the first electrode 1 corresponds to an emitter electrode overlying a first surface (e.g., an upper surface) of the device, and the second electrode 2 corresponds to a collector electrode overlying a second surface (e.g., a lower surface) of the device.
The base region 3 has a first conductivity type, for example the base region 3 is a P-type base region. The source region 4 has a second conductivity type, e.g. the source region 4 is an N-type region. As shown in fig. 1-3, two source regions 4 are separately located in a base region 3, a first PN junction is formed between the source region 4 and the base region 3, the two N-type source regions 4 are electrically connected to a first electrode 1, the P-type base region 3 is also electrically connected to the first electrode 1, and the first electrode 1 may be formed on the source region 4 and the base region 3 by one or more methods of deposition, plating, or welding to achieve electrical connection therebetween.
The drift region 5 is located below the base region 3 and has a second conductivity type (e.g., N-type) for acting as a depletion layer during forward withstand voltage of the IGBT device. The drift region 5 mainly plays a role of a withstand voltage, wherein, when the IGBT device is a punch-through IGBT device, the semiconductor unit may further include a buffer layer 9, and in this case, the buffer layer 9 and the drift region 5 have the same conductivity type, but the doping concentration of the drift region 5 needs to be significantly lower than that of the buffer layer 9.
The collector region 6 is located below the drift region 5 and has a first conductivity type (e.g., P-type), and the collector region 6 is electrically connected to the second electrode 2 for providing carriers in an on-state of the IGBT device.
The trench gate structure 7 (referred to as trench gate for short) may include a gate electrode 71 and a gate dielectric layer 72 wrapping the gate electrode 71, the gate dielectric layer 72 penetrating the base region 3 and extending to the drift region 5. As shown in fig. 1-3, the cell is a symmetrical structure, and two trench gate structures 7 are symmetrically located on two sides of the P-type base region 3 and extend into the drift region 5 through the P-type base region 3. The gate 71 is asymmetrically located in the gate dielectric layer 72, that is, the gate dielectric layer 72 close to the P-type base region 3 has a smaller thickness, and the gate dielectric layer 72 far from the P-type base region 3 has a larger thickness. The material of the gate 71 may be polysilicon or other available gate materials, such as metal; the gate dielectric layer 72 may be silicon dioxide or other insulating dielectric such as a high dielectric constant material or an oxynitride gate dielectric structure, such as silicon oxynitride. A passivation layer, such as a silicon nitride layer, may be further disposed between the gate dielectric layer 72 and the first electrode 1, and the passivation layer completely isolates the first electrode 1 from the gate dielectric layer 72. The trench gate structure is in contact with the source region and the base region, a channel can be formed in the base region when the positive grid electrode drops, normal conduction of the device is guaranteed, meanwhile, the channel can be turned off by negative grid electrode drops, the device is in an off state, high voltage is borne, and electric leakage is reduced.
The PN junction structure 8 is formed in the gate dielectric layer 72 and located on at least one side of the gate electrode 71 away from the channel region, as shown in fig. 1-3, the PN junction structure 8 is formed on the side of the gate dielectric layer 72 away from the channel region where the thickness is larger, the PN junction structure 8 is formed by a first conductive type region and a second conductive type region which are distributed along the longitudinal direction and are in contact with each other, the first conductive type region 81 in the PN junction structure 8 is electrically connected with the first electrode 1, and the second conductive type region 82 in the PN junction structure 8 is floating in the gate dielectric layer 72. In this embodiment, the first conductive type region 81 is a P region, and the second conductive type region 82 is an N region. It is to be understood that in the embodiment shown in fig. 3, a portion of the second conductivity type region 82 is located at the bottom of the gate 71, but the PN junction structure 8 is located entirely on at least one side of the gate 71 away from the channel region.
In practical application, the grid region is punched, so that potential is led out to provide voltage for the grid. Current collector-emitter voltage UCE> 0, and a gate-emitter voltage UGE＞UthAnd forming a gate channel, forming a channel in a region of the P-type base region 3 close to the gate, and enabling the IGBT device to be in a conducting state. When the gate-emitter of the IGBT is added with 0 or negative voltage, the channel in the P-type base region 3 disappears, and the IGBT device is in a turn-off state. Current collector-emitter voltage UCE> 0, and a gate-emitter voltage UGE＜UthIn this case, the channel cannot be formed, and the IGBT device is in a forward blocking state. Current collector-emitter voltage UCEWhen the voltage is less than 0, the IGBT device is in a reverse blocking state.
Taking an N-type IGBT device as an example, the following will explain the principle of the present invention in detail with reference to the following embodiments:
and forming a PN junction structure 8 close to the grid electrode on the grid dielectric layer 72, wherein a first conductive type region 81 of the PN junction structure 8 is connected with the first electrode 1, a second conductive type region 82 of the PN junction structure 8 is in a floating state, and a PN junction is formed between the first conductive type region and the second conductive type region.
When the grid and the emitter of the IGBT device are respectively connected with zero potential, no channel is formed in the P-type base region 3, and the IGBT device is in a turn-off state.
When the device is in an off state, if the potential of the collector is continuously increased, the emitter is still connected with zero potential, so that a depletion layer is formed between a P region and an N region of the longitudinal PN junction, and a depletion layer capacitor is generated. In the process, the potential of the PN junction N area is lifted, and the PN junction depletion layer capacitorWill be charged. When the collector-emitter voltage UCE is greater than 0 and the gate-emitter voltage UGE＜UthAnd when the IGBT device is in a forward blocking state, the N-drift region bears main voltage resistance. As the PN junction N region and the N-drift region are mutually depleted, the auxiliary withstand voltage of a longitudinal electric field exists, so that the forward withstand voltage capability of the device is improved.
After the forward blocking state is reached, the voltage of the collector is kept at a high potential and the charges stored on the PN junction depletion layer capacitor cannot be discharged, so that the N region of the PN junction is maintained at a high potential, the high potential of the N region of the PN junction structure can influence the potential distribution at the bottom of the trench gate, and the potential at the bottom of the surrounding trench gate is also raised. When gate-emitter voltage UGE＞Uth When the gate channel is formed, the IGBT device is turned on, carriers (holes in this embodiment) in the collector region 6 flow to the channel region through the drift region, and since the potential at the bottom of the trench gate is raised, the accumulation of the hole carriers at the bottom of the gate dielectric layer 72 is suppressed, so that the displacement current for charging the gate 71 is suppressed, and the dI of the gate 71 is adjusted to the dICControllability of/dt is enhanced and EMI noise is suppressed.
According to the above analysis, since the first conductive type region of the PN junction structure is connected to the emitter, and the second conductive type region is suspended, when the IGBT device is in the forward voltage withstanding state, and the first conductive type region is clamped by the emitter, the PN junction structures 8 are mutually depleted, and a depletion layer capacitance is formed, so that in the forward voltage withstanding process, the potential of the second conductive type region 82 of the PN junction structure 8 is closer to the potential of the collector, and the potential change of the second conductive type region 82 affects the potential distribution at the bottom of the trench gate, so that the potential at the bottom of the surrounding trench gate is also closer to the potential of the collector. When the IGBT device is turned on, the bottom of the grooved gate can inhibit accumulation of carriers (holes or electrons) in the area due to potential distribution of the grooved gate, and therefore displacement current for charging the gate 71 is inhibited, and the gate 71 is enabled to have dICControllability of/dt is enhanced and EMI noise is suppressed.
The IGBT device can be an N-channel or P-channel IGBT device, and the PN junction structure 8 can be made of monocrystalline silicon, gallium nitride or silicon carbide; when the IGBT device is an N-channel enhancement type, the doping element of the first conductivity type region 81 of the PN junction structure 8 may be a boron element; and/or, the doping element of the second conductive type region 82 of the PN junction structure 8 may be phosphorus or arsenic. The semiconductor material involved in the above semiconductor unit may be single crystal silicon, gallium nitride, or silicon carbide, and the gate electrode 71 may be a polycrystalline silicon material.
For example, when the IGBT device is an N-channel enhancement type IGBT device, the device may include a P + collector region 6, an N-type buffer layer 9, an N-drift region 5, a second electrode 2, and a first electrode 1; a grid electrode 71 region, a P-type base region 3, an N + source region 4 and a first electrode 1 are arranged in a region above the N-drift region 5; the gate 71 region may include a PN junction structure 8, a gate electrode (gate 71 for short), and a gate dielectric layer 72. The PN junction structure 8 comprises a P area (a first conductive type area 81) of the PN junction structure 8 and an N area (a second conductive type area) of the PN junction structure 8, the P area of the PN junction structure 8 is located on the left side of the gate electrode and is in contact with the N area of the PN junction structure 8 to realize electric connection, and the P area of the PN junction structure 8 is located above the N area of the PN junction structure 8. The P region of the PN junction structure 8 and the N region of the PN junction structure 8 are isolated from the gate electrode by gate dielectric layers 72, respectively. The gate electrode is isolated from the N-drift region 5, the P-type base region 3, the N + source region 4 and the metal emitter through the gate dielectric layer 72. The N + source region 4 and the P-type base region 3 are positioned on the right side of the gate dielectric layer 72. The gate dielectric layer 72 enters the N-drift region 5 along the vertical direction of the device to form a trench, and the gate electrode is disposed in the trench. The first electrode 1 is located on the upper surface of the trench gate IGBT device, and the P area of the PN junction structure 8 is connected with the first electrode 1. One side of the gate dielectric layer 72 is in contact with the N-drift region 5, the P-type base region 3 and the N + source region 4. The P-type base region 3 and the N + source region 4 are in contact with the first electrode 1.
The doping concentration of the first conductivity type region 81 of the above-described PN junction structure 8 is greater than the doping concentration of the second conductivity type region 82 of the PN junction structure 8. The doping manner of the first conductive type region 81 of the PN junction structure 8 may be uniform doping or non-uniform doping, and the doping manner of the second conductive type region 82 of the PN junction structure 8 may be uniform doping or non-uniform doping. The doping concentrations of the first conductivity-type region 81 and the second conductivity-type region 82 of the PN junction structure 8 can be adjusted according to the requirements of practical applications. That is, the first conductive type region 81 and the second conductive type region 82 of the PN junction structure 8 may be doped by ion implantation or thermal diffusion.
For example, the doping concentration of the first conductive type region 81 of the PN junction structure 8 is greater than or equal to 1000 times the doping concentration of the second conductive type region 82 of the PN junction structure 8. The doping concentration range of the second conductive type region 82 is 1 × 1015cm-3-1×1017cm-3The doping concentration range of the corresponding first conductive type region 81 is 1 × 1018cm-3-1×1020cm-3. The doping concentration of the second conductivity type region 82 affects the potential rise at the bottom of the trench gate structure 7 during power-on, and different doping concentrations have different effects on the final EMI suppression effect. Specifically, the doping concentration of the second conductive type region 82 is increased, so that the potential at the bottom of the trench gate structure 7 is increased and decreased; the doping concentration of the second conductivity type region 82 is reduced, resulting in an elevated bottom potential of the trench gate structure 7.
The bottom of the PN junction structure 8 may be flush with the bottom of the gate 71. When the bottom of the PN junction structure 8 is higher than the bottom of the gate electrode 71, the bottom of the PN junction structure 8 has a relatively thick gate dielectric layer 72, which provides a smaller series capacitance, which is beneficial to raising the top potential of the trench gate during power-up, but also leads to the potential of the gate electrode 71 not being conducted into the drift region 5 below the gate dielectric layer. Therefore, it is preferable to adopt a design in which the bottom of the PN junction structure 8 and the bottom of the gate 71 are flush.
The PN junction structure 8 may have various structural forms, which are represented by a height relationship with the surface of the gate dielectric layer 72. For example, as shown in fig. 2, the top surface of the PN junction structure 8 is higher than the top surface of the gate dielectric layer 72, wherein the bottom surface of the first conductive type region 81 of the PN junction structure 8 may be higher or lower than the top surface of the gate dielectric layer 72; or the top surface of the PN junction structure 8 is lower than the top surface of the gate dielectric layer 72.
The first conductivity type region 81 with high doping concentration provides good potential conduction, and when the first conductivity type region 81 is longer, the groove where the PN junction is located can provide a certain proportion of displacement current shielding effect, so as to better inhibit crosstalk of high-side potential under the condition of larger gate resistance. The second conductive type region 82 with low doping concentration provides a depletion region after power-on, optimizes the potential at the bottom of the trench gate structure 7, inhibits the accumulation of holes in the opening transient state, and reduces the EMI noise.
In the present embodiment, as shown in fig. 1, the PN junction structure 8 has an I-shaped profile; as shown in fig. 3, the second conductive type region 82 may also be L-shaped, and specifically, the second conductive type region 82 is wider and located below the gate 71, and is isolated by the gate dielectric layer 72, so that the L-shaped PN junction structure 8 may further reduce the problem of potential aggregation at the bottom of the trench gate in the original structure.
In the embodiment shown in fig. 3, taking the N-trench IGBT device as an example, when the device is in an off state, since the potential of the second electrode 2 is continuously increased, the first electrode 1 is at zero potential, so that the P region (corresponding to the first conductivity type region 81) and the N region (corresponding to the second conductivity type region 82) of the vertical PN junction structure 8 are mutually depleted, and the N region of the PN junction structure generates a depletion layer and is continuously widened, thereby forming capacitances with the interfaces of the gate 71, the gate dielectric layer 72, and the N-drift region 5, respectively. Therefore, a plurality of capacitors are connected in series between the gate electrode 71 and the second electrode 2, and the miller capacitance is reduced. Compared with the traditional IGBT, the capacitance from the grid 71 to the bottom oxide layer (the grid dielectric layer 72) of the trench grid structure 7 is C due to the existence of the PN junction structure N regionoxIt becomes a series connection of a plurality of capacitors, so that the capacitance from the gate electrode 71 to the oxide layer at the bottom of the trench gate structure 7 is reduced and the potential at the bottom of the trench gate structure 7 is raised. When the forward blocking state is reached, because the potential of the second electrode 2 is kept unchanged, the charges stored on the depletion layer capacitor of the PN junction structure cannot be discharged, and the width of the depletion layer of the N region of the PN junction structure is kept unchanged, the potential at the bottom of the trench gate structure 7 is kept unchanged, and a higher level is maintained.
When the device is in an on-state transient state, compared with a traditional IGBT device, the potential at the bottom of the trench gate structure 7 of the IGBT device with low miller capacitance is raised, so that accumulation of holes at the position is inhibited, generation of displacement current for charging the gate 71 is reduced, and dI of the gate 71 in an on-state is enhancedCControl ability of/dt. Meanwhile, V is enabled to be in the opening transient state due to the reduction of Miller capacitanceCEHas reduced voltage tail and is used for gridThe load is reduced, the E is reducedON。
In summary, in the invention, as for the IGBT device with low miller capacitance, compared with the conventional IGBT device structure, the invention introduces the PN junction structure in the thick oxide layer beside the trench gate, so that the miller capacitance of the device is reduced, and the potential at the bottom of the trench gate structure 7 is raised in the forward blocking state; under the starting transient state, the accumulation of holes at the bottom of the trench gate structure 7 can be reduced, the generation of displacement current is reduced, the controllability of the grid 71 on the current of a collector is enhanced, and meanwhile, the starting loss E is reduced due to the reduction of Miller capacitanceON. According to the type of the IGBT device, when a punch-through type IGBT device is used, the semiconductor unit may further include a buffer layer 9 located between the collector region 6 and the drift region 5, the buffer layer 9 having the second conductivity type, the buffer layer 9 being used as a field stop layer during the forward withstand voltage of the IGBT device, and the doping concentration of the buffer layer 9 being greater than the doping concentration of the drift region 5. The buffer layer 9 acts as a field stop layer to prevent punch-through of the device during forward withstand voltage.
Example two:
next, an example in which the IGBT device is an N-channel IGBT device will be described. In an embodiment, the first conductivity type is P-type and the second conductivity type is N-type.
Referring to fig. 4, the present embodiment provides a method for manufacturing an IGBT device, including:
step 1: and providing a substrate, wherein the substrate comprises a collector region 6, a buffer layer 9, a drift region 5 and a base region 3 which are stacked from bottom to top, or the substrate comprises the collector region 6, the drift region 5 and the base region 3 which are stacked from bottom to top.
As shown in fig. 5, the collector region 6, the buffer layer 9, the drift region 5, and the base region 3 may be formed in any conventional manner. For example, a single crystal silicon substrate is provided, P-type heavy doping is performed on the substrate to obtain a P + collector region 6, a buffer layer 9 or a drift layer is epitaxially formed on the upper surface of the collector region 6, and then N-type light doping is performed until reaching an N-drift layer or an N-buffer layer 9. The base region 3 may be formed by epitaxially forming a single crystal silicon on the drift layer and then performing P-type light doping, or may be formed by directly performing P-type light doping on the upper surface of the drift layer to form the P-base region 3.
Step 2: as shown in fig. 6, a source region 4 is formed on a base region 3; wherein the base region 3 and the collector region 6 have a first conductivity type; the source region 4, the drift region 5 and the buffer layer 9 have a second conduction type, the first conduction type and the second conduction type belong to different semiconductor conduction types, and a first PN junction is formed between the source region 4 and the base region 3; the drift region 5 is used as a depletion layer in the forward voltage withstanding process of the IGBT device; the collector region 6 is used for providing current carriers when the IGBT device is in an on state; the buffer layer 9 is used as a field stop layer in the forward voltage withstanding process of the IGBT device, and the doping concentration of the buffer layer 9 is larger than that of the drift region 5.
For example, a photoresist layer covering the base region 3 is formed on the base region 3, patterning corresponding to the source region 4 is performed, and N-type heavy doping is performed under the masking of the photoresist, so as to obtain a corresponding N + source region 4. And removing the photoresist and cleaning after doping.
And step 3: a first trench 51 is formed in the substrate, the first trench 51 penetrating the base region 3 and extending to the drift region 5.
For example, as shown in fig. 7, a photoresist layer covering the base region 3 is formed on the base region 3, patterning corresponding to the first trench 51 is performed, and etching is performed under the masking of the photoresist, so as to obtain a corresponding first trench 51.
And 4, step 4: a trench gate structure 7 is formed on the first trench 51, and the trench gate structure 7 includes a gate electrode 71 and a gate dielectric layer 72 wrapping the gate electrode 71.
The present application does not limit the way of forming the trench gate specifically, and the following ways may be adopted:
the step 4 may include:
step 401: a gate dielectric layer 72 is deposited over the first trench 51. For example, as shown in fig. 8, the gate dielectric layer 72 may be silicon dioxide or other insulating dielectric, such as a high dielectric constant material or oxynitride; when monocrystalline silicon is mostly used as a semiconductor material, a silicon dioxide material with higher process compatibility is used. At this point, silicon dioxide may be deposited into the first trench 51 in any manner to form the gate dielectric layer 72.
Step 402: a third trench 722 is formed in the gate dielectric layer 72. For example, as shown in fig. 9, a photoresist layer is formed to cover the base region 3 (including the source region 4) and the gate dielectric layer 72, patterning corresponding to the third trench 722 is performed, and etching is performed under the masking of the photoresist to obtain the corresponding third trench 722. The etching manner is specifically determined according to the material used for the gate dielectric layer 72.
Step 403: a gate 71 is formed on the third trench 722. For example, as shown in fig. 10, a polysilicon layer with a certain depth is formed on the second trench 721 by chemical vapor deposition as the gate 71, or after depositing the polysilicon layer, the polysilicon layer is etched back to control the depth of the polysilicon layer in the second trench 721.
Step 404: a gate dielectric layer 72 is formed overlying gate 71. As shown in fig. 11, the second trench 721 is then filled with a gate dielectric layer 72, covering the gate 71.
To further illustrate, when it is desired to fabricate the IGBT device shown in fig. 3, step 403 should be performed after step 5, or after step 501. Alternatively, step 4 may comprise: a gate dielectric layer 72 is formed on the first trench 51, and step 5 or step 501 is performed to form a trench gate structure 7 on the first trench 51. The trench gate structure 7 formed on the first trench 51 at this time is: a trench gate structure 7 is formed on the gate dielectric layer 72 over the first trench 51.
And 5: as shown in fig. 12, a second trench 721 is formed on the gate dielectric layer 72, and as shown in fig. 14, a PN junction structure 8 is formed on the second trench 721; wherein the PN junction structure 8 is located on at least one side of the gate 71 away from the channel region, and the second conductive type region 82 in the PN junction structure 8 is floating in the gate dielectric layer 72. Specifically, the first conductivity type region 81 and the second conductivity type region 82 of the PN junction structure 8 may be formed by dividing into two semiconductor structures, or may be formed by one semiconductor structure. The second trench 721 may be formed by etching, which is specifically determined by the material used for the gate dielectric layer 72. The second trenches 721 and the third trenches may be formed simultaneously, or formed in steps.
For example, in the step 5, the forming of the PN junction structure 8 on the second trench 721 may include:
step 501: as shown in fig. 13, a first semiconductor structure is formed on the second trench 721, and the first semiconductor structure is doped with a second conductivity type, resulting in the second conductivity type region 82 of the PN junction structure 8. The thickness of the second conductive type region 82 may be controlled by a deposition process, or the second conductive type region 82 may be controlled by chemical mechanical polishing after the second trench 721 is completely filled, followed by etching back or wet etching. For example, when the IGBT device is an N-channel device, after the third semiconductor structure is formed on the second trench 721, the third semiconductor structure is removed by chemical mechanical polishing to keep the third semiconductor structure flush with the top surface of the base region 3. And then carrying out N-type doping to obtain an N region.
Step 502: as shown in fig. 14, a second semiconductor structure is formed on the first semiconductor structure, and the second semiconductor structure is doped with the first conductivity type, resulting in a first conductivity type region 81 of the PN junction structure 8. Similarly, a second semiconductor structure is formed on the second trench 721, followed by chemical mechanical polishing and doping, resulting in the first conductive type region 81.
For another example, in the step 5, the forming the PN junction structure 8 on the second trench 721 may further include:
step 511: as shown in fig. 15, a third semiconductor structure is formed on the second trench 721, and the second conductivity type doping is performed on the first semiconductor structure, resulting in the second conductivity type region 82 of the PN junction structure 8. For example, when the IGBT device is an N-channel device, after the third semiconductor structure is formed on the second trench 721, the third semiconductor structure is removed by chemical mechanical polishing to keep the third semiconductor structure flush with the top surface of the base region 3. And then carrying out N-type doping to obtain an N region.
Step 512: as shown in fig. 14, a portion of the third semiconductor structure is doped with the first conductivity type, resulting in a first conductivity type region 81 of the PN junction structure 8. For example, a portion of the third semiconductor structure, i.e., above the N region, is doped P-type to a partial depth, resulting in a P region.
Step 6: as shown in fig. 1, a first electrode 1 and a second electrode 2 are formed, and the base region 3, the source region 4, and the first conductivity type region 81 in the PN junction structure 8 are electrically connected to the first electrode 1, and the collector region 6 is electrically connected to the second electrode 2, respectively. The material and the forming process of the electrode can refer to the existing process of the IGBT device, for example, the electrode is formed by electroplating or deposition.
Thus, the IGBT device shown in fig. 1 can be obtained, which has the technical effects of the IGBT device described in the first embodiment, and the technical effects of the IGBT device provided in the present application will not be described repeatedly here.
The semiconductor structures are not limited to specific materials and forming processes, and all materials that can be used for the trench gate IGBT device can be applied to the method for manufacturing the IGBT device. For example, the forming process of the semiconductor structure may be physical vapor deposition or chemical vapor deposition, and the forming of the trench may be dry etching or wet etching.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. Numerous simple deductions, modifications or substitutions may also be made by those skilled in the art in light of the present teachings.
Claims (9)
1. An IGBT device comprising at least one cell, characterized in that the cell comprises a first electrode (1), a second electrode (2) and a semiconductor unit between the first electrode (1) and the second electrode (2), the semiconductor unit comprising:
a base region (3) having a first conductivity type;
a source region (4) having a second conductivity type, the first conductivity type and the second conductivity type being different semiconductor conductivity types, a first PN junction being formed between the source region (4) and the base region (3), the base region (3) and the source region (4) being electrically connected to the first electrode (1), respectively;
a drift region (5) which is positioned below the base region (3), has a second conduction type and is used as a depletion layer in the process that the IGBT device is in forward voltage withstanding;
a collector region (6) located below the drift region (5) and having a first conductivity type, the collector region (6) being electrically connected with the second electrode (2) for providing charge carriers in the on-state of the IGBT device;
the trench gate structure (7) comprises a gate electrode (71) and a gate dielectric layer (72) wrapping the gate electrode (71), and the gate dielectric layer (72) penetrates through the base region (3) and extends to the drift region (5); the grid electrode (71) is asymmetrically positioned in the grid dielectric layer (72), and the thickness of the grid dielectric layer (72) close to one side of the base region (3) is smaller than that of the grid dielectric layer (72) far away from one side of the base region (3);
the PN junction structure (8) is formed in the gate dielectric layer (72) and located on one side, far away from the channel region, of the grid electrode (71), a first conduction type region (81) in the PN junction structure (8) is electrically connected with the first electrode (1), and a second conduction type region (82) in the PN junction structure (8) is floated in the gate dielectric layer (72); the bottom of the PN junction structure (8) is flush with the bottom of the grid electrode (71), and the junction of the first conductive type region (81) and the second conductive type region (82) in the PN junction structure (8) is close to the top of the PN junction structure (8).
2. The IGBT device according to claim 1, wherein the IGBT device is an N-channel enhancement type, and a material of the PN junction structure (8) is single crystal silicon, gallium nitride, or silicon carbide; the doping element of the first conduction type region (81) of the PN junction structure (8) is boron element, and/or the doping element of the second conduction type region (82) of the PN junction structure (8) is phosphorus element or arsenic element.
3. The IGBT device according to claim 1 or 2, characterized in that the doping concentration of the first conductivity type region (81) of the PN junction structure (8) is greater than the doping concentration of the second conductivity type region (82) of the PN junction structure (8).
4. The IGBT device according to claim 3, characterized in that the doping concentration of the first conductivity type region (81) of the PN junction structure (8) is greater than or equal to 1000 times the doping concentration of the second conductivity type region (82) of the PN junction structure (8).
5. The IGBT device according to claim 1, wherein a top surface of the PN junction structure (8) is higher than a top surface of the gate dielectric layer (72); or the top surface of the PN junction structure (8) is lower than the top surface of the gate dielectric layer (72).
6. The IGBT device according to claim 1, wherein the semiconductor unit further comprises a buffer layer (9) between the collector region (6) and the drift region (5), the buffer layer (9) having the second conductivity type, the buffer layer (9) being used as a field stop layer during forward withstand voltage of the IGBT device, the buffer layer (9) having a doping concentration greater than a doping concentration of the drift region (5).
7. A method for manufacturing an IGBT device is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a collector region (6), a buffer layer (9), a drift region (5) and a base region (3) which are stacked from bottom to top, or the substrate comprises the collector region (6), the drift region (5) and the base region (3) which are stacked from bottom to top;
forming a source region (4) on the base region (3); wherein the base region (3) and the collector region (6) have a first conductivity type; the source region (4), the drift region (5) and the buffer layer (9) are of a second conduction type, the first conduction type and the second conduction type belong to different semiconductor conduction types, and a first PN junction is formed between the source region (4) and the base region (3); the drift region (5) is used as a depletion layer in the process that the IGBT device is in forward voltage withstanding; the collector region (6) is used for providing current carriers when the IGBT device is in an on state; the buffer layer (9) is used as a field stop layer in the forward voltage withstanding process of the IGBT device, and the doping concentration of the buffer layer (9) is greater than that of the drift region (5);
forming a first trench (51) on the substrate, the first trench (51) penetrating the base region (3) and extending to the drift region (5);
forming a trench gate structure (7) on the first trench (51), wherein the trench gate structure (7) comprises a gate electrode (71) and a gate dielectric layer (72) wrapping the gate electrode (71); the grid electrode (71) is asymmetrically positioned in the grid dielectric layer (72), and the thickness of the grid dielectric layer (72) close to one side of the base region (3) is smaller than that of the grid dielectric layer (72) far away from one side of the base region (3);
forming a second groove (721) on the gate dielectric layer (72), and forming a PN junction structure (8) on the second groove (721); the PN junction structure (8) is positioned on at least one side of the grid electrode (71) far away from the channel region, and a second conduction type region (82) in the PN junction structure (8) is floated in the grid dielectric layer (72); the bottom of the PN junction structure (8) is flush with the bottom of the grid electrode (71), and the junction of the first conductive type region (81) and the second conductive type region (82) in the PN junction structure (8) is close to the top of the PN junction structure (8);
forming a first electrode (1) and a second electrode (2), wherein the base region (3), the source region (4) and a first conductive type region (81) in the PN junction structure (8) are respectively electrically connected with the first electrode (1), and the collector region (6) is electrically connected with the second electrode (2).
8. The method of manufacturing according to claim 7, wherein forming a trench-gate structure (7) over the first trench (51) comprises:
depositing a gate dielectric layer (72) on the first trench (51);
forming a third groove (722) on the gate dielectric layer (72);
forming a gate (71) over the third trench (722);
and forming a gate dielectric layer (72) covering the gate electrode (71).
9. The method of manufacturing according to claim 7 or 8, wherein said forming a PN junction structure (8) over said second trench (721) comprises:
forming a first semiconductor structure on the second trench (721), and doping the first semiconductor structure with a second conductivity type to obtain a second conductivity type region (82) of the PN junction structure (8);
forming a second semiconductor structure on the first semiconductor structure, and doping the second semiconductor structure with a first conductivity type to obtain a first conductivity type region (81) of the PN junction structure (8);
alternatively, the first and second liquid crystal display panels may be,
forming a third semiconductor structure on the second groove (721), and doping the first semiconductor structure with a second conductivity type to obtain a second conductivity type region (82) of the PN junction structure (8);
and doping a part of the third semiconductor structure with a first conductivity type to obtain a first conductivity type region (81) of the PN junction structure (8).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210062869.3A CN114093934B (en) | 2022-01-20 | 2022-01-20 | IGBT device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210062869.3A CN114093934B (en) | 2022-01-20 | 2022-01-20 | IGBT device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114093934A CN114093934A (en) | 2022-02-25 |
| CN114093934B true CN114093934B (en) | 2022-05-20 |
Family
ID=80308641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210062869.3A Active CN114093934B (en) | 2022-01-20 | 2022-01-20 | IGBT device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114093934B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114709258B (en) * | 2022-06-07 | 2022-08-30 | 深圳市威兆半导体股份有限公司 | Double-channel MOSFET device and manufacturing method thereof |
| CN117542877B (en) * | 2024-01-10 | 2024-03-19 | 上海林众电子科技有限公司 | Carrier storage type IGBT device and manufacturing method thereof |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9513420D0 (en) * | 1995-06-30 | 1995-09-06 | Philips Electronics Uk Ltd | Power semiconductor devices |
| GB0028031D0 (en) * | 2000-11-17 | 2001-01-03 | Koninkl Philips Electronics Nv | Trench-gate field-effect transistors and their manufacture |
| DE10203164B4 (en) * | 2002-01-28 | 2005-06-16 | Infineon Technologies Ag | Power semiconductor component and method for its production |
| US7989885B2 (en) * | 2009-02-26 | 2011-08-02 | Infineon Technologies Austria Ag | Semiconductor device having means for diverting short circuit current arranged in trench and method for producing same |
| US9184284B2 (en) * | 2012-12-31 | 2015-11-10 | Infineon Technologies Ag | Method for operating field-effect transistor, field-effect transistor and circuit configuration |
| JP5994938B2 (en) * | 2013-05-31 | 2016-09-21 | 富士電機株式会社 | Manufacturing method of semiconductor device |
| CN105027295B (en) * | 2013-08-06 | 2018-02-06 | 富士电机株式会社 | Trench grate MOS type semiconductor device and its manufacture method |
| TWI570917B (en) * | 2014-12-31 | 2017-02-11 | 帥群微電子股份有限公司 | Trench power mosfet and manufacturing method thereof |
| JP7057044B2 (en) * | 2018-02-22 | 2022-04-19 | ラピスセミコンダクタ株式会社 | Semiconductor devices and methods for manufacturing semiconductor devices |
| CN109300975B (en) * | 2018-09-29 | 2021-03-30 | 电子科技大学 | Trench gate bipolar transistor with low electromagnetic interference noise characteristic |
| CN110600537B (en) * | 2019-08-22 | 2020-12-29 | 电子科技大学 | Separation gate CSTBT with PMOS current clamping and manufacturing method thereof |
| CN113437141A (en) * | 2021-06-24 | 2021-09-24 | 电子科技大学 | Floating P-region CSTBT device with polysilicon diode grid structure |
| CN113451400A (en) * | 2021-06-28 | 2021-09-28 | 宁波达新半导体有限公司 | Trench gate reverse conducting type IGBT device |
| CN113838916B (en) * | 2021-09-23 | 2023-05-26 | 电子科技大学 | Separation gate CSTBT with PMOS current clamping function and manufacturing method thereof |
-
2022
- 2022-01-20 CN CN202210062869.3A patent/CN114093934B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN114093934A (en) | 2022-02-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114093934B (en) | IGBT device and manufacturing method thereof | |
| US20200020798A1 (en) | Power mosfet with an integrated pseudo-schottky diode in source contact trench | |
| US11888022B2 (en) | SOI lateral homogenization field high voltage power semiconductor device, manufacturing method and application thereof | |
| CN110491937B (en) | IGBT with self-biased separation gate structure | |
| CN109713037B (en) | Insulated gate bipolar transistor device and preparation method thereof | |
| CN110600537B (en) | Separation gate CSTBT with PMOS current clamping and manufacturing method thereof | |
| CN109075199A (en) | Semiconductor device | |
| US20230246096A1 (en) | Semiconductor cell structure, igbt cell structure, semiconductor structure, and method for manufacturing igbt cell structure | |
| US20230090883A1 (en) | Three-dimensional carrier stored trench igbt and manufacturing method thereof | |
| CN105489644B (en) | IGBT device and preparation method thereof | |
| WO2016101134A1 (en) | Bi-directional metal oxide semiconductor device and manufacturing method thereof | |
| CN114551577B (en) | IGBT device and manufacturing method thereof | |
| CN110504260B (en) | Transverse groove type IGBT with self-bias PMOS and preparation method thereof | |
| JP2008153389A (en) | Semiconductor device | |
| CN109166923B (en) | Shielding gate MOSFET | |
| CN114497201A (en) | Field effect transistor of integrated body relay diode, preparation method thereof and power device | |
| JP2014154739A (en) | Semiconductor device | |
| CN110504313B (en) | Transverse groove type insulated gate bipolar transistor and preparation method thereof | |
| CN104078494B (en) | Power semiconductor device and method of fabricating the same | |
| US20200219996A1 (en) | Igbt device | |
| CN108305893B (en) | Semiconductor device with a plurality of semiconductor chips | |
| CN116053325A (en) | High-resistance field plate shielding gate groove type field effect transistor device and manufacturing method | |
| CN107634094B (en) | Insulated gate bipolar transistor structure and manufacturing method thereof | |
| CN107464834B (en) | Power semiconductor device and method for manufacturing the same | |
| CN108461536B (en) | Bidirectional trench gate charge storage type IGBT and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 518000 1301, building 3, Chongwen Park, Nanshan Zhiyuan, No. 3370 Liuxian Avenue, Fuguang community, Taoyuan Street, Nanshan District, Shenzhen, Guangdong Patentee after: Shenzhen Weizhao Semiconductor Co.,Ltd. Address before: 518000 1301, building 3, Chongwen Park, Nanshan Zhiyuan, No. 3370 Liuxian Avenue, Fuguang community, Taoyuan Street, Nanshan District, Shenzhen, Guangdong Patentee before: VANGUARD SEMICONDUCTOR CO.,LTD. |