CN108461536B - Bidirectional trench gate charge storage type IGBT and manufacturing method thereof - Google Patents
Bidirectional trench gate charge storage type IGBT and manufacturing method thereof Download PDFInfo
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- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
Abstract
A bidirectional trench gate charge storage type IGBT belongs to the technical field of semiconductor power devices. According to the invention, the shielding groove structure with the same potential as the emitter metal is introduced on the basis of the traditional bidirectional CSTBT device structure, and the groove depth of the shielding groove structure is larger than that of the charge storage layer, so that the electric field of the charge storage layer is shielded, the introduction of the shielding groove structure plays an effective charge compensation role for the charge storage layer, the limitation of the doping concentration and thickness of the charge storage layer on the voltage resistance of the device is further improved, and the breakdown voltage of the device is improved; the compromise relation between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device is favorably improved, a wider short-circuit safe working area is obtained, the saturation current density of the device is favorably reduced, and the short-circuit safe working area of the device is further improved; in addition, the invention obviously reduces the grid capacitance of the device, especially the grid-collector capacitance, thereby improving the switching speed of the device, and reducing the switching loss of the device and the requirement on the capability of deleting the drive circuit.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a Bi-directional trench gate charge storage type insulated gate bipolar transistor (Bi-directional transistor).
Background
Insulated Gate Bipolar Transistors (IGBTs) are new power electronic devices developed based on the study of power MOSFETs and power Bipolar Junction Transistors (BJTs), and are equivalent to MOSFETs driven by Bipolar Junction Transistors (BJTs). IGBTs combine the advantages of power MOSFET structures and Bipolar Junction Transistor (BJT) structures: the power MOSFET has the advantages of easy driving, low input impedance and high switching speed, and also has the advantages of high on-state current density, low conduction voltage, low loss and good stability of a Bipolar Junction Transistor (BJT). Based on these excellent device characteristics, in recent years, IGBTs have become mainstream power devices widely used in medium and high voltage fields, such as electric vehicles, motor drives, grid-connected technologies, energy storage power stations, AC/DA conversion, variable frequency speed control, and the like.
Since the invention of the IGBT, efforts have been made to improve the performance of the IGBT. Through development of thirty years, seven generations of IGBT device structures are successively proposed to improve the performance of the device. From non-punch-through (NPT) type IGBT structures with symmetric blocking characteristics to FS IGBT structures employing a field stop layer to reduce the drift region thickness and improve the device turn-on characteristics. In addition, a JFET (junction field effect transistor) region of the original plane gate IGBT structure is eliminated by adopting a trench gate IGBT structure, so that the on-resistance of the device is reduced, higher MOS (metal oxide semiconductor) structure channel density is obtained, and the characteristics of the device are obviously improved. The seventh generation IGBT structure, namely a trench gate charge storage type insulated gate bipolar transistor (CSTBT), introduces an N-type charge storage layer with higher doping concentration and certain thickness below a P-type base region, so that a hole potential barrier is introduced below the P-type base region, the hole concentration of a device close to an emitter terminal is greatly improved, the electron concentration is greatly increased according to the electric neutral requirement, the carrier concentration distribution of the whole N-type drift region is improved, the conductivity modulation effect of the N-type drift region is enhanced, and the IGBT obtains lower forward conduction voltage drop and better compromise between the forward conduction voltage drop and turn-off loss. The higher the doping concentration of the N-type charge storage layer is, the greater the CSTBT conductivity modulation effect is improved, and the better the forward conduction characteristic of the device is.
As is well known, the conversion of electrical energy is a basic step in many power electronic applications, and is one of the basic functions of electrical devices, which can perform the conversion of alternating current to direct current (AC-DC), direct current to alternating current (DC-AC), direct current to direct current (DC-DC) and alternating current to alternating current (AC-AC) according to the requirements of loads. The conversion of AC-AC can adopt an indirect conversion mode, namely an AC-DC-AC mode, and also can adopt a direct conversion mode, namely an AC-AC mode. In a traditional AC-DC-AC indirect conversion system, a connection capacitor with a large capacitance value (voltage type conversion) or a connection inductor with a large inductance value (current type conversion) is needed to connect two relatively independent conversion systems, and the system is large in size and high in cost. In addition, the service life of the capacitor and the inductor is far shorter than that of a power device, which seriously influences the reliability and the service life of the system. AC-AC direct conversion systems avoid the use of connecting capacitors or inductors in conventional AC-DC-AC systems, but require bidirectional switching capability of the power switch. Therefore, the development of the bidirectional switch has been a research focus of the ac power converting apparatus. Early bi-directional switches employed thyristors equipped with external forced commutation circuitry. The most widely used semiconductor device for the bidirectional switch is the insulated gate bipolar transistor.
The traditional IGBT only has the functions of unidirectional conduction and unidirectional blocking, and the main forming mode of the IGBT bidirectional switch with the bidirectional conduction and bidirectional blocking functions is as follows: diode bridge, common collector, and common emitter. Later, reverse-blocking type IGBT (RB-IGBT) devices have larger capacity of bearing reverse voltage, so that the bidirectional switch can be simplified into a simple anti-parallel structure, and two fast recovery diodes are omitted. However, the above switch schemes all belong to combined switches, a large number of power chips are needed, the system cost is increased, in addition, a large number of wires are needed among the chips in the system, and a complex combination mode enhances the parasitic effect in the system, and the system reliability is influenced.
In the background described above, in order to solve the above problems and achieve integration of products, research and development of bidirectional IGBT chips are performed by using a bonding technique or a double-sided photolithography method. With the development of silicon-silicon bonding technology, in recent years, it has been proposed to bond two identical trench MOS structures back to back successfully in a single chip, i.e. a Bi-directional IGBT (Bi-directional IGBT) with bidirectional conduction and bidirectional blocking functions as shown in fig. 1, and the generation of the Bi-directional IGBT greatly reduces the cost of the device and reduces the stray parameters of the circuit. Compared with the traditional unidirectional IGBT, the bidirectional IGBT can realize the symmetrical turn-on and turn-off characteristics of the forward IGBT and the reverse IGBT by controlling the forward gate voltage and the back gate voltage. In addition, a front N-type layer 6 and a back N-type layer 26 which are higher than the doping concentration of the N-type drift region 9 are symmetrically adopted between the P-type base region 5 and the N-type drift region 9 and between the P-type base region 25 and the N-type drift region 9, so that on one hand, compared with an NPT-type bidirectional IGBT structure, the thickness of the N-type drift region is reduced, the resistance of the drift region is reduced, the forward conduction voltage drop is reduced, and the switching speed is improved; on the other hand, when the bidirectional IGBT works in any direction, the bidirectional IGBT is of an IGBT structure with a charge storage layer and an electric field stop layer, and the performance of the device is obviously improved. For the structure shown in fig. 1, when the forward or reverse IGBT works, the presence of the front N-type layer 6 and the back N-type layer 26 with higher doping concentration and a certain thickness as charge storage layers greatly improves the carrier concentration distribution of the IGBT device near the emitter terminal, improves the conductance modulation of the N-type drift region, improves the carrier concentration distribution of the entire N-type drift region, and makes the IGBT obtain a low forward conduction voltage drop and an improved compromise between forward conduction voltage drop and turn-off loss. However, with the bidirectional IGBT structure, during the operation of the forward or reverse IGBT, the device breakdown voltage is significantly reduced as the doping concentration and thickness of the front N-type charge storage layer 6 or the back N-type charge storage layer 26 are continuously increased, which limits the doping concentration and thickness of the N-type charge storage layer. In order to effectively shield the adverse effect of the N-type charge storage layer and obtain higher device withstand voltage, the prior art mainly adopts the following two ways:
(1) the depth of the trench gate is greater than the junction depth of the N-type charge storage layer under normal conditions;
(2) small cell width, i.e. making the MOS structure channel density large to obtain the smallest possible trench gate pitch.
However, the implementation of the above-mentioned means still has significant drawbacks: the implementation of the method (1) increases the gate-emitter capacitance and the gate-collector capacitance, and the switching process of the IGBT is essentially a process of charging/discharging the gate capacitance, so that the increase of the gate capacitance increases the charging/discharging time, and further decreases the switching speed. Therefore, the deep trench gate will reduce the switching speed of the device, increase the switching loss of the device, and affect the compromise characteristic of the conduction voltage drop and the switching loss of the device. On one hand, the implementation of the mode (2) can increase the grid capacitance of the device, so that the switching speed of the device is reduced, the switching loss is increased, and the compromise characteristic of the conduction voltage drop and the switching loss of the device is influenced; on the other hand, too high channel density will also result in increased saturation current density of the device, thus degrading the short-circuit safe operating area (SCSOA) of the device. In addition, the gate oxide layer used in the trench gate structure is usually formed in the trench by a thermal oxidation, which requires a smaller thickness of the entire gate oxide layer in order to ensure a certain threshold voltage. However, the size of the MOS capacitor in the device is inversely proportional to the thickness of the gate oxide layer, which results in a significant increase in the gate capacitance of the conventional CSTBT device, and in addition, the electric field concentration effect at the bottom of the trench also reduces the breakdown voltage of the device, resulting in poor reliability of the device.
Disclosure of Invention
In view of the above, the present invention aims to: aiming at the defects in the prior art, the bidirectional trench gate charge storage type IGBT and the manufacturing method thereof are provided, and the shielding trench structure for shielding the electric field of the charge storage layer is introduced, so that the limit of the doping concentration and thickness of the charge storage layer on the voltage resistance of a device is avoided, and the aims of improving the breakdown voltage of the device, improving the compromise relationship between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device, improving the switching performance of the device and improving the short-circuit safe working area of the device are fulfilled; in addition, the preparation method provided by the invention is compatible with the traditional manufacturing method of the bidirectional trench gate charge storage type IGBT.
In order to achieve the purpose, the invention adopts the following technical scheme:
in one aspect, the invention provides a bidirectional trench gate charge storage type IGBT, the quarter cell of which includes MOS structures symmetrically disposed on the front and back of a first conductivity type semiconductor drift region 9; the method is characterized in that: the front MOS structure comprises a front emitter metal 1, a front isolation dielectric layer 2, a front groove gate structure, a front shielding groove structure, a front first conductive type semiconductor emitting region 3, a front second conductive type semiconductor emitting region 4, a front second conductive type semiconductor base region 5 and a front first conductive type semiconductor charge storage layer 6; the back MOS structure comprises a back emitter metal 21, a back isolation dielectric layer 22, a back groove gate structure, a back shielding groove structure, a back first conductive type semiconductor emitting region 23, a back second conductive type semiconductor emitting region 24, a back second conductive type semiconductor base region 25 and a back first conductive type semiconductor charge storage layer 26;
in the front-side MOS structure, a front-side first conduction type semiconductor charge storage layer 6 is positioned on the top layer of the front-side first conduction type semiconductor drift region 9; the front second conductive type semiconductor base region 5 is positioned on the top layer of the front first conductive type semiconductor charge storage layer 6; the front second conduction type semiconductor emitter region 4 and the front first conduction type semiconductor emitter region 3 are mutually independent and are arranged on the top layer of the front second conduction type semiconductor base region 5 in parallel;
the top layer of the front first conduction type semiconductor drift region 9 is provided with a front groove gate structure and a front shielding groove structure, and the front groove gate structure and the front shielding groove structure are not consistent along the extending direction of the top layer of the device; the front-surface trench gate structure comprises a front-surface gate electrode 81 and a front-surface gate dielectric layer 82, wherein the front-surface gate electrode 81 downwards penetrates through the front-surface first conduction type semiconductor emitter region 3 and the front-surface second conduction type semiconductor base region 5 to enter the front-surface first conduction type semiconductor charge storage layer 6, namely the depth of the front-surface gate electrode 81 is smaller than the junction depth of the front-surface first conduction type semiconductor charge storage layer 6, the front-surface gate electrode 81 is connected with the front-surface first conduction type semiconductor emitter region 3, the front-surface second conduction type semiconductor base region 5 and the front-surface first conduction type semiconductor charge storage layer 6 through the front-surface gate dielectric layer 82, and the upper surface of the front-surface gate electrode 81 is connected with the front-; the front shielding trench structure comprises a front shielding electrode 71 and a front shielding trench dielectric layer 72, wherein the front shielding electrode 71 downwards penetrates through the front first conductive type semiconductor emitter region 3, the front second conductive type semiconductor emitter region 4, the front second conductive type semiconductor base region 5 and the front first conductive type semiconductor charge storage layer 6 to enter the front first conductive type semiconductor drift region 9, namely the depth of the front shielding electrode 71 is greater than the junction depth of the front first conductive type semiconductor charge storage layer 6, the front shielding electrode 71 is isolated from the front gate electrode 81 through the front gate dielectric layer 82 or the shielding trench dielectric layer 72, and the front shielding electrode 71 is communicated with the front first conductive type semiconductor emitter region 3, the front second conductive type semiconductor emitter region 4, the front second conductive type semiconductor base region 5, the front first conductive type semiconductor charge storage layer 6 and the front first conductive type semiconductor drift region 9 The front shielding groove dielectric layer 72 is connected, and the front shielding electrode 71 is equipotential to the front emitter metal 1; the back side MOS structure is the same as the front side MOS structure.
Further, the front side MOS structure and the back side MOS structure may be mirror-symmetric along the lateral centerline of the first conductivity type semiconductor drift region 9, or may be cross-symmetric along the lateral centerline of the first conductivity type semiconductor drift region 9, that is, the front side MOS structure and the back side MOS structure are centrosymmetric about the device center point.
Furthermore, a three-dimensional coordinate system is established by taking any inflection point of the quarter-cell as an origin, two sides of the bottom surface of the quarter-cell, which intersect at the inflection point, are respectively taken as an x axis and a z axis, and a straight line passing through the inflection point and perpendicular to the bottom surface is taken as a y axis, so that the gate electrode 81, 281 extends from one end of the device to the other end along the x axis or the z axis, the shielding electrode 71, 271 extends from one end of the device to the gate dielectric layer 82, 281 on the side surface of the gate electrode 81, 281 along the z axis or the x axis, and the extending directions of the gate electrode 81, 281 and the shielding electrode 71, 271 are.
Furthermore, a three-dimensional coordinate system is established by taking any inflection point of a quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively used as an x axis and a z axis, and a straight line passing through the inflection point and perpendicular to the bottom surface is used as a y axis, so that the shielding electrodes 71 and 271 extend from one end of the device to the other end along the x axis or the z axis, the gate electrodes 81 and 281 extend from one end of the device to the shielding trench dielectric layers 72 and 272 on the side surfaces of the shielding electrodes 71 and 271 along the z axis or the x axis, and the extending directions of the shielding electrodes 71 and 271 and the gate electrodes 81 and 281 are not consistent.
A depletion layer is formed when the PN junction formed by the first conductivity type semiconductor charge storage layer 6 and the second conductivity type semiconductor base region 5 is reverse biased, and fixed charges different from the free carrier conductivity type are respectively formed in the semiconductor layer: for an N-type semiconductor, positively charged ionization donors exist in a depletion layer, and for a P-type semiconductor, negatively charged ionization acceptors exist in the depletion layer; because the electrode in the shielding groove structure has the same electric potential as the emitter metal 1, the shielding groove structure can provide charges with the conductivity type opposite to that of the charge storage layer equivalently, namely the fixed charges in the second conductivity type semiconductor charge storage layer 6 are opposite to that of the charges provided by the shielding groove structure, so that charge compensation is formed, a transverse electric field is formed between the second conductivity type semiconductor charge storage layer 6 and the shielding groove structure to reduce the longitudinal electric field of the device, and the breakdown voltage of the device can be improved.
Furthermore, the front shielding trench structure has a front second conductive type semiconductor layer one 10 at the bottom and a back second conductive type semiconductor layer one 210 at the top.
Preferably, the second conductivity type semiconductor layers one 10, 210 both extend laterally to both sides into the first conductivity type semiconductor drift region 9 below the front first conductivity type semiconductor charge storage layer 6 or above the back first conductivity type semiconductor charge storage layer 26.
Further, the front-side trench gate structure has a second conductivity type semiconductor layer 11 at the bottom thereof, and the back-side trench gate structure has a second conductivity type semiconductor layer 211 at the top thereof.
Further, the front trench gate structure is a front split trench gate structure, and further includes: split-electrode 83 and split-electrode dielectric layer 84, and accordingly, the back-side trench-gate structure is a back-side split-trench-gate structure, and further includes: a split electrode 283 and a split electrode dielectric layer 284.
Further, when the trench gate structure is a split trench gate structure, the split electrodes 83, 283 are equipotential with the emitter metals 1, 21.
Further, when the trench-gate structure is a split trench-gate structure, the thickness of the split electrode dielectric layer 84, 284 is greater than the thickness of the gate dielectric layer 82, 282.
Furthermore, when the trench gate structure is a split trench gate structure, the second conductivity type semiconductor layer two 11 is further provided below the front-side split trench gate structure, and the second conductivity type semiconductor layer two 211 is further provided above the back-side split trench gate structure.
Preferably, the second conductivity type semiconductor layer two 11, 211 laterally extends to both sides into the first conductivity type semiconductor drift region 9 below the front first conductivity type semiconductor charge storage layer 6 or above the back first conductivity type semiconductor charge storage layer 26.
Since the above-mentioned charge compensation effect and the magnitude of the lateral electric field are related to the distance, in order to enhance the electric field shielding effect of the shielding trench structure on the second conductivity type semiconductor charge storage layer, a three-dimensional coordinate system is established with any inflection point of the quarter cell as an origin, two sides of the bottom surface of the quarter cell intersecting the inflection point are respectively used as an x axis and a z axis, and a straight line passing through the inflection point and perpendicular to the bottom surface is used as a y axis.
Further, in order to enhance the electric field shielding effect of the shielding trench structure on the second conductivity type semiconductor charge storage layer, reduce the extraction area of the emitter on the excess minority carrier in the drift region during forward conduction, reduce the gate capacitance, and improve the carrier concentration distribution in the drift region, preferably, the width of the shielding trench structure is greater than the width of the trench gate structure.
Preferably, the thickness of the shield trench dielectric layer 72, 272 is greater than the thickness of the gate dielectric layer 82, 282.
Specifically, the first conductivity type semiconductor is a P-type semiconductor, and the first conductivity type semiconductor is an N-type semiconductor; or the first conductive type semiconductor is an N-type semiconductor and the first conductive type semiconductor is a P-type semiconductor.
Further, the semiconductor material used by the device is any one or more of Si, SiC, GaAs and GaN, and the structures can adopt the same semiconductor material or different semiconductor materials.
Further, the gate electrode in the trench is any one or more of polysilicon, SiC, GaAs and GaN, and each portion can be made of the same material or different materials.
On the other hand, the invention provides a manufacturing method of a bidirectional trench gate charge storage type IGBT, which is characterized by comprising the following steps:
the method comprises the following steps: manufacturing two identical first conduction type semiconductor drift regions 9;
step two: respectively manufacturing first conductive type semiconductor charge storage layers 6 and 26 and second conductive type semiconductor base regions 5 and 25 on the top layers of the second conductive type semiconductor charge storage layers 6 and 26 on the front surfaces of the two first conductive type semiconductor drift regions 9 by adopting the same pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes;
step three: respectively etching two first conductive type semiconductor drift regions 9 to form first grooves by adopting the same photoetching, etching, thermal oxidation and deposition processes, wherein the depth of each first groove is greater than the junction depth of the first conductive type semiconductor charge storage layers 6 and 26 and extends along the transverse direction of the top layer of the device; forming shielding groove dielectric layers 72 and 272 on the inner walls of the first grooves, then depositing electrode materials in the first grooves to form shielding electrodes 71 and 271, and forming shielding groove structures by the shielding electrodes 71 and 271 and the shielding groove dielectric layers 72 and 272 on the peripheral sides of the shielding electrodes 71 and 271;
step four: respectively etching two first conduction type semiconductor charge storage layers 6 and 26 to form second grooves by adopting the same photoetching, etching, thermal oxidation and deposition processes, wherein the depth of each second groove is smaller than the junction depth of the first conduction type semiconductor charge storage layers 6 and 26 and extends along the longitudinal direction of the top layer of the device, and the second grooves are not communicated with the first grooves; forming gate dielectric layers 82 and 282 on the inner wall of the first trench, then depositing a gate electrode material in the trench to form gate electrodes 81 and 281, wherein the gate electrodes 81 and 281 and the gate dielectric layers 82 and 282 on the peripheral sides of the gate electrodes form a trench gate structure;
step five: respectively manufacturing second conductive type semiconductor emitter regions 4 and 24 and first conductive type semiconductor emitter regions 3 and 23 which are independent and arranged in parallel on the top layers of the two second conductive type semiconductor base regions 5 and 25 by adopting the same photoetching, etching, ion implantation and high-temperature annealing processes; one side of the first conductivity type semiconductor emission region 3, 23 is connected with the gate electrode 81, 281 along the longitudinal direction of the device top layer through the gate dielectric layer 82, 282, the other side thereof is connected with the shielding electrode 71, 271 along the transverse direction of the device top layer through the shielding trench dielectric layer 72, 272, and one side of the second conductivity type semiconductor emission region 4, 24 is connected with the shielding electrode 71, 271 along the transverse direction of the device top layer through the shielding trench dielectric layer 72, 272;
step six: forming isolation dielectric layers 2 and 22 on the upper surfaces of the two gate electrodes 81 and 281 and the upper surfaces of the gate dielectric layers 82 and 282 by the same photoetching, etching and deposition processes;
step seven: depositing metal on the surface, and respectively forming emitter metal 1 and emitter metal 21 on the isolation dielectric layers 2 and 22, the first conductive type semiconductor emitting regions 3 and 23, the second conductive type semiconductor emitting regions 4 and 24, the shielding electrodes 71 and 271 and the shielding groove dielectric layers 72 and 272 by adopting the same photoetching and etching processes;
step eight: and turning over the semiconductor wafers, respectively reducing the thickness of the two semiconductor wafers by adopting the same process, and then forming the bidirectional trench gate charge storage type IGBT device by back-to-back bonding the two completely same semiconductor wafers by adopting a bonding process, thereby completing the preparation of the device.
Further, the order of forming the trench gate structure and the shield trench structure may be interchanged.
Further, the order of forming the trench gate structure and forming the first conductivity type semiconductor charge storage layers 6, 26 and the first conductivity type semiconductor base regions 5, 25 may be interchanged.
Further, by changing the trenching manner, the trench gate structure extends from one end of the device to the other end of the device along the top layer of the device and blocks the extension of the shielding trench structure along the top layer of the device or the shielding trench structure extends from one end of the device to the other end of the device along the top layer of the device and blocks the extension of the trench gate structure along the top layer of the device.
Specifically, the first conductivity type semiconductor is a P-type semiconductor, and the first conductivity type semiconductor is an N-type semiconductor; or the first conductive type semiconductor is an N-type semiconductor and the first conductive type semiconductor is a P-type semiconductor.
Further, the semiconductor material used by the device is any one or more of Si, SiC, GaAs and GaN, and the structures can adopt the same semiconductor material or different semiconductor materials.
Further, the gate electrode in the trench is any one or more of polysilicon, SiC, GaAs and GaN, and each portion can be made of the same material or different materials.
The working principle of the invention is detailed as follows:
in order to solve the contradiction between the conduction characteristic and the breakdown voltage of the device caused by the improvement of the thickness and the doping concentration of the charge storage layer, a shielding groove structure with the same potential as the metal of an emitter is introduced on the basis of the traditional CSTBT structure, the extension directions of the shielding groove structure and the groove gate structure on the surface of the device are not consistent, the groove depth of the shielding groove structure is greater than that of the charge storage layer, a depletion layer is formed when a PN junction formed by the charge storage layer and the base region is reversely biased, and fixed charges different from the free carrier conduction type are respectively formed in a semiconductor layer; the electrode in the shielding groove structure has the same potential as the emitter metal and is equivalent to the shielding groove structure which can provide charges with the conductivity type opposite to that of the charge storage layer, so that charge compensation is formed, and a transverse electric field can be formed between the charge storage layer and the shielding groove structure to reduce the longitudinal electric field of the device. In addition, the dielectric layer of the inner wall of the groove of the shielding groove structure can be thickened, so that the electric field concentration effect can be relieved, and the breakdown voltage of the device can be further improved. Just because the doping concentration and thickness of the charge storage layer of the charge compensation effect of the shielding groove structure limit the voltage resistance of the device, the carrier concentration distribution of the drift region of the device can be improved by improving the doping concentration and thickness of the charge storage layer by adopting the device structure provided by the invention, so that the compromise relationship between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device is improved, and a wider short circuit safe working region (SCSOA) is obtained; meanwhile, the device structure provided by the invention can avoid large MOS structure channel density, is beneficial to reducing the saturation current density of the device, and can further improve the Short Circuit Safe Operating Area (SCSOA) of the device. In addition, the existence of the shielding groove structure reduces the effective contact area between the groove gate structure and the collector region and between the groove gate structure and the emitter region, and the large grid-emitter capacitance formed by the groove gate structure and the shielding groove rubbing structure is connected in parallel to reduce the grid-emitter capacitance, so that the switching loss of the device and the requirement on the capacity of a grid driving circuit are reduced, and the compromise between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device is further improved. Furthermore, the invention reduces the groove depth of the groove gate structure to be smaller than the junction depth of the charge storage layer, thereby further reducing the capacitance of a grid electrode and a collector electrode, improving the switching speed of the device, and reducing the conduction loss Eon of the device and the requirement on the capacity of a gate drive circuit. The existence of the further shielding groove structure reduces the extraction area of the emitter to the excessive minority carriers in the drift region when the emitter is conducted in the forward direction, reduces the capacitance of the grid electrode, improves the carrier concentration distribution of the drift region, and further improves the compromise relation between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device. In addition, the manufacturing method provided by the invention does not need to add extra process steps and is compatible with the traditional bidirectional CSTBT manufacturing method.
Compared with the prior art, the invention has the beneficial effects that:
the invention realizes the symmetrical forward and reverse conduction and turn-off characteristics of the device, avoids the limitation of the doping concentration and thickness of the charge storage layer on the voltage resistance of the device, not only improves the breakdown voltage of the device and the reliability of the device, but also obviously improves the carrier concentration distribution of the device, further improves the compromise relationship between the forward conduction voltage drop Vceon and the turn-off loss Eoff, and obtains a wider short-circuit safe working area; the invention avoids overlarge channel density of the MOS structure of the device, thereby reducing the saturation current density of the device and further improving the Short Circuit Safe Operating Area (SCSOA) of the device; the invention obviously reduces the grid capacitance of the device, particularly the grid-collector capacitance, thereby improving the switching speed of the device, reducing the switching loss of the device and the requirement on the capability of deleting a driving circuit, and further improving the compromise relationship between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device. In addition, the manufacturing method provided by the invention does not need to add extra process steps and is compatible with the manufacturing process of the traditional bidirectional CSTBT device.
Drawings
Fig. 1 is a schematic diagram of a quarter cell structure of a conventional bidirectional trench gate charge storage type IGBT device;
FIG. 2 is a schematic structural diagram of a conventional bidirectional trench gate charge storage type IGBT device before an isolation dielectric layer and an emitter metal layer are formed;
FIG. 3 is a schematic cross-sectional view of a quarter-cell structure of a conventional bi-directional trench gate charge storage type IGBT device along line AB;
fig. 4 is a schematic diagram of a quarter cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 1 of the present invention;
fig. 5 is a schematic structural diagram of a bidirectional trench gate charge storage type IGBT device provided in embodiment 1 of the present invention before forming an isolation dielectric layer and an emitter metal layer;
fig. 6 is a schematic cross-sectional view of a quarter cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 1 of the present invention along line AB;
fig. 7 is a schematic cross-sectional view of a quarter cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 1 of the present invention, taken along the line a 'B';
fig. 8 is a schematic diagram of a quarter cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 2 of the present invention;
fig. 9 is a schematic structural diagram of a bidirectional trench gate charge storage type IGBT device according to embodiment 2 of the present invention before forming an isolation dielectric layer and an emitter metal layer;
fig. 10 is a schematic cross-sectional view of a quarter-cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 2 of the present invention along line AB;
fig. 11 is a schematic cross-sectional view of a quarter cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 2 of the present invention, taken along the line a 'B';
fig. 12 is a schematic diagram of a quarter cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 3 of the present invention;
fig. 13 is a schematic structural diagram of a bidirectional trench gate charge storage type IGBT device according to embodiment 3 of the present invention before forming an isolation dielectric layer and an emitter metal layer;
fig. 14 is a schematic cross-sectional view of a quarter cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 3 of the present invention along line AB;
fig. 15 is a schematic cross-sectional view of a quarter cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 3 of the present invention, taken along the line a 'B';
fig. 16 is a schematic diagram of a quarter cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 4 of the present invention;
fig. 17 is a schematic structural diagram of a bidirectional trench gate charge storage type IGBT device according to embodiment 4 before forming an isolation dielectric layer and an emitter metal;
fig. 18 is a schematic cross-sectional view of a quarter cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 4 of the present invention along line AB;
fig. 19 is a schematic cross-sectional view of a quarter cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 4 of the present invention, taken along the line a 'B';
fig. 20 is a schematic diagram of a quarter cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 5 of the present invention;
fig. 21 is a schematic structural diagram of a bidirectional trench gate charge storage type IGBT device according to embodiment 5 of the present invention before forming an isolation dielectric layer and an emitter metal;
fig. 22 is a schematic cross-sectional view of a quarter-cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 5 of the present invention along line AB;
fig. 23 is a schematic cross-sectional view of a quarter cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 5 of the present invention, taken along the line a 'B';
fig. 24 is a schematic diagram of a quarter cell structure of a bidirectional trench gate charge storage IGBT device according to embodiment 6 of the present invention;
fig. 25 is a schematic structural diagram of a bidirectional trench gate charge storage type IGBT device according to embodiment 6 of the present invention before forming an isolation dielectric layer and an emitter metal;
fig. 26 is a schematic cross-sectional view of a quarter cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 6 of the present invention along line AB;
fig. 27 is a schematic cross-sectional view of a quarter cell structure of a bidirectional trench gate charge storage type IGBT device according to embodiment 6 of the present invention, taken along the line a 'B';
fig. 28 is a schematic diagram of a quarter-cell structure after forming a trench of a shield trench structure in the manufacturing method according to embodiment 1 of the present invention;
fig. 29 is a schematic diagram of a quarter cell structure after a shielding electrode dielectric layer is formed in the manufacturing method of embodiment 1 of the invention;
FIG. 30 is a diagram illustrating a quarter cell structure after forming a shielding electrode in the manufacturing method of embodiment 1 of the present invention;
fig. 31 is a schematic diagram of a quarter cell structure after forming a trench of a trench gate structure in the manufacturing method of embodiment 1 of the present invention;
fig. 32 is a schematic diagram of a quarter cell structure after a gate dielectric layer is formed in the manufacturing method of embodiment 1 of the invention;
fig. 33 is a schematic view of a quarter cell structure after a gate electrode is formed in the manufacturing method of embodiment 1 of the invention;
fig. 34 is a schematic diagram of a quarter cell structure after forming an N + emitter region and a P + emitter region in the manufacturing method of embodiment 1 of the invention;
FIG. 35 is a schematic diagram of a quarter-cell structure after forming an isolation dielectric layer in the method of embodiment 1 of the present invention;
fig. 36 is a schematic diagram of a quarter cell structure after emitter metal is formed in the manufacturing method of embodiment 1 of the invention;
FIG. 37 is a diagram showing a quarter cell structure after all the steps are completed in the manufacturing method of example 1 of the present invention;
fig. 38 is a schematic diagram of a quarter cell structure after forming a trench of a trench gate structure in the manufacturing method according to embodiment 3 of the present invention;
fig. 39 is a schematic diagram of a quarter cell structure after a gate dielectric layer is formed in the manufacturing method of embodiment 3 of the invention;
fig. 40 is a schematic diagram of a quarter cell structure after a gate electrode is formed in the manufacturing method of embodiment 3 of the invention;
fig. 41 is a schematic diagram of a quarter-cell structure after forming a trench of a shield trench structure in a manufacturing method according to embodiment 3 of the invention;
fig. 42 is a schematic diagram of a quarter-cell structure after a P-type layer is formed in the manufacturing method of embodiment 3 of the invention;
fig. 43 is a schematic diagram of a quarter cell structure after a gate dielectric layer is formed in the manufacturing method of embodiment 3 of the invention;
fig. 44 is a schematic diagram of a quarter cell structure after forming a gate electrode, an N + emitter region, and a P + emitter region in the manufacturing method of embodiment 3 of the invention;
fig. 45 is a schematic diagram of a quarter cell structure after forming an N + emitter region and a P + emitter region in the manufacturing method of embodiment 3 of the invention;
FIG. 46 is a schematic diagram of a quarter-cell structure after forming an isolation dielectric layer in the method of embodiment 3 of the present invention;
fig. 47 is a schematic diagram of a quarter cell structure after forming emitter metal in the manufacturing method of embodiment 3 of the invention;
FIG. 48 is a diagram illustrating a quarter cell structure after all the steps in the manufacturing method according to embodiment 3 of the present invention are completed;
in the figure: 1 is a front emitter metal, 2 is a front isolation dielectric layer, 3 is a front N + emitter region, 4 is a front P + emitter region, 5 is a front P-type base region, 6 is a front N-type charge storage layer, 71 is a front shield electrode, 72 is a front shield trench dielectric layer, 81 is a front gate electrode, 82 is a front gate dielectric layer, 83 is a front split electrode, 84 is a front split electrode dielectric layer, 9 is an N-type drift region, 10 is a front first P-type layer, 11 is a front second P-type layer, 21 is a back emitter metal, 22 is a back isolation dielectric layer, 23 is a back N + emitter region, 24 is a back P + emitter region, 25 is a back P-type base region, 26 is a back N-type charge storage layer, 271 is a back shield electrode, 272 is a back shield trench dielectric layer, 281 is a back gate electrode, 283 is a back gate dielectric layer, and is a back split electrode, 284 is a back split electrode dielectric layer, 210 is a back P-type layer, and 211 is a back second P-type layer.
Detailed Description
The principles and features of the present invention are explained in detail below in conjunction with the drawings and the detailed description of the invention:
in the drawings, the same reference numerals denote the same or similar components or elements. The bidirectional trench gate charge storage type IGBT device provided by the invention can be an N-channel device and also can be a P-channel device, the N-channel device is taken as an example for explanation, and the structure and the working principle of the P-channel device can be clear to the skilled person on the basis of disclosing the N-channel device.
Example 1:
the invention provides a bidirectional trench gate charge storage type IGBT, wherein a quarter cell of the IGBT is shown in figure 4, a section along an AB line and an A 'B' line is shown in figures 6 and 7, a three-dimensional coordinate system is established by taking any inflection point of the quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively taken as an x axis and a z axis, a straight line passing through the inflection point and perpendicular to the bottom surface is taken as a y axis, and the directions of the x axis, the y axis and the z axis are shown in figure 4;
the quarter-cell comprises MOS structures which are symmetrically arranged on the front surface and the back surface of the N-type drift region 9; the method is characterized in that: the front MOS structure comprises a front emitter metal 1, a front isolation dielectric layer 2, a front groove gate structure, a front shielding groove structure, a front N + emitter region 3, a front P + emitter region 4, a front P-type base region 5 and a front N-type charge storage layer 6; the back MOS structure comprises a back emitter metal 21, a back isolation dielectric layer 22, a back trench gate structure, a back shielding trench structure, a back N-type emitter region 23, a back P-type emitter region 24, a back P-type base region 25 and a back N-type charge storage layer 26;
in the front-side MOS structure, a front-side N-type charge storage layer 6 is positioned on the top layer of the front-side N-type drift region 9; the front P-type base region 5 is positioned on the top layer of the front N-type charge storage layer 6; the front surface P + emitter region 4 and the front surface N + emitter region 3 are mutually independent and are arranged on the top layer of the front surface P type base region 5 in parallel;
the top layer of the front N-type drift region 9 is provided with a front groove gate structure and a front shielding groove structure, and the front groove gate structure and the front shielding groove structure are not consistent along the extending direction of the top layer of the device; the front-side trench gate structure comprises a front-side gate electrode 81 and a front-side gate dielectric layer 82, wherein the front-side gate electrode 81 penetrates through the front-side N + emitter region 3 and the front-side P-type base region 5 downwards and enters the front-side N-type charge storage layer 6, namely the depth of the front-side gate electrode 81 is smaller than the junction depth of the front-side N-type charge storage layer 6, the front-side gate electrode 81 is connected with the front-side P-type base region 5 and the front-side N-type charge storage layer 6 through the front-side gate dielectric layer 82, the front-side gate electrode 81 extends from one end of the device to the other end of the device along the; the front side shield trench structure comprises a front side shield electrode 71 and a front side shield trench dielectric layer 72, the front shielding electrode 71 passes through the front P + emitter region 4, the front P-type base region 5 and the front N-type charge storage layer 6 downwards to enter the front N-type drift region 9, the depth of the front shielding electrode 71 is greater than the junction depth of the front N-type charge storage layer 6, the front shielding electrode 71 extends from one end of the device to the front gate dielectric layer 82 on the side surface of the front gate electrode 81 along the x axis, the front shielding electrode 71 is isolated from the front gate electrode 81 through the front gate dielectric layer 82 or the shielding trench dielectric layer 72, the front shielding electrode 71 is connected with the front N + emitter region 3, the front P + emitter region 4, the front P-type base region 5, the front N-type charge storage layer 6 and the front N-type drift region 9 through the front shielding trench dielectric layer 72, and the front shielding electrode 71 is equal in potential to the front emitter metal 1; the back side MOS structure is the same as the front side N-channel MOS structure, and the front side MOS structure and the back side MOS structure are in mirror symmetry along the transverse central line of the N-type drift region 9.
In this embodiment, the front P + emitter 4 and the back P + emitter 24 have a dimension along the z-axis of 0.2-0.5 um, and a dimension along the y-axis, i.e., a junction depth of 0.1-0.3 um; the front-side P-type base region 5 and the back-side P-type base region 25 are 2-10 um in size along the x-axis direction, and 0.3-1 um in size along the y-axis; the size of the front N-type charge storage layer 6 and the back N-type charge storage layer 26 along the y axis is 0.5-1 um; the groove depth of the front groove gate structure and the back groove gate structure is 0.6-2 um; the groove depth of the front shielding groove structure and the back shielding groove structure is 4-8 um.
The position relationship of the shielding trench structure and the trench gate structure in the three-dimensional space provided by the embodiment is different from that of the existing structure in which the two structures extend in parallel, the equipotential of the electrode in the shielding trench structure and the emitter metal can equivalently provide negative charges, when a PN junction formed by the second conductive type semiconductor charge storage layer and the first conductive type semiconductor base region is reversely biased, the positively charged ionization donor in the second conductive type semiconductor charge storage layer and the negative charges in the shielding trench form charge compensation, and the positively charged ionization donor generates a transverse electric field pointing to the negative charges so as to reduce a longitudinal electric field of the device, and meanwhile, both the front-side gate electrode 81 and the back-side gate electrode 281 are exposed on the xoy surface of the device, which is beneficial for leading out the electrode in subsequent chip packaging.
Example 2:
the invention provides a bidirectional trench gate charge storage type IGBT, wherein a quarter cell of the IGBT is shown in figure 8, a section along an AB line and an A 'B' line is shown in figures 10 and 11, a three-dimensional coordinate system is established by taking any inflection point of the quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively taken as an x axis and a z axis, a straight line passing through the inflection point and perpendicular to the bottom surface is taken as a y axis, and the directions of the x axis, the y axis and the z axis are shown in figure 8;
the present implementation differs from example 1 in that: the first P-type layer 10 is introduced into the bottom of the front shielding trench structure, the first P-type layer 10 is connected with the gate electrode 81 through the gate dielectric layer 82, the back shielding trench structure is the same as the front shielding trench structure and is mirror-symmetrical along the transverse center line of the N-type drift region 9, except that the other structures are the same as those in embodiment 1, and in this embodiment, the junction depth of the first P-type layer 10 is 0.5 to 1 μm.
As a preferred embodiment, the front first P-type layer 10 extends laterally into the N-type drift region 9 under the front N-type charge storage layer 6 towards both sides, and the back shielding trench structure is the same as the front shielding trench structure and is mirror symmetric along the lateral centerline of the N-type drift region 9. Based on the method, the influence of negative charges in the N-type charge storage layer 6 and the back N-type charge storage layer 26 can be shielded, the grid capacitance is further reduced, the electric field concentration effect at the bottom of the groove is improved, and the breakdown voltage and the reliability of the device are improved.
Example 3:
the invention provides a bidirectional trench gate charge storage type IGBT, wherein a quarter cell of the IGBT is shown in figure 12, a section along an AB line and an A 'B' line is shown in figures 14 and 15, a three-dimensional coordinate system is established by taking any inflection point of the quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively taken as an x axis and a z axis, a straight line passing through the inflection point and perpendicular to the bottom surface is taken as a y axis, and the directions of the x axis, the y axis and the z axis are shown in figure 12;
the present implementation differs from example 2 in that: in the front side MOS structure, the front side shielding electrode 71 extends from one end of the device to the other end along the x axis, the front side gate electrode 81 extends from one end of the device to the front side shielding trench dielectric layer 72 on the side surface of the front side shielding electrode 71 along the z axis, the front side shielding electrode 71 and the front side gate electrode 81 are connected by the front side shielding trench dielectric layer 72, the back side shielding trench structure is the same as the front side shielding trench structure and is mirror-symmetrical along the transverse centerline of the N-type drift region 9, and other structures are the same as those in embodiment 2 except that.
According to the embodiment, the depth of the groove gate structure extending along the z-axis direction is reduced, so that the channel density of the MOS structure is reduced, the saturation current density of the device is reduced, and the SCSOA (short-circuit safe operating area) characteristic of the device is improved.
Example 4:
the invention provides a trench gate charge storage type IGBT, wherein a quarter cell of the IGBT is shown in figure 16, a section along an AB line and an A 'B' line is shown in figures 18 and 19, a three-dimensional coordinate system is established by taking any inflection point of the quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively taken as an x axis and a z axis, a straight line passing through the inflection point and perpendicular to the bottom surface is taken as a y axis, and the directions of the x axis, the y axis and the z axis are shown in figure 16;
the present implementation differs from example 3 in that: the other structures of the embodiment are the same as those of embodiment 3 except that a front second P-type layer 11 is introduced at the bottom of the front trench gate structure, a back second P-type layer 211 is introduced at the bottom of the back trench gate structure, the front second P-type layer 11 is connected with the front gate electrode 81 through a front gate dielectric layer 82, and the back second P-type layer 211 is connected with the back gate electrode 281 through a back gate dielectric layer 282, wherein the junction depths of the second P- type layers 11 and 211 in the embodiment are 0.5 to 1 μm.
As a preferred embodiment, the second conductivity type semiconductor layer two 11, 211 laterally extends to both sides into the first conductivity type semiconductor drift region 9 below the front first conductivity type semiconductor charge storage layer 6 or above the back first conductivity type semiconductor charge storage layer 26, so as to shield the influence of negative charges in the N-type charge storage layer 6, 26, further reduce the gate capacitance, and simultaneously contribute to improving the electric field concentration at the bottom of the trench, and improve the breakdown voltage and reliability of the device.
Example 5:
the invention provides a trench gate charge storage type IGBT, wherein a quarter cell of the IGBT is shown in figure 20, a section along an AB line and an A 'B' line is shown in figures 22 and 23, a three-dimensional coordinate system is established by taking any inflection point of the quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively taken as an x axis and a z axis, a straight line passing through the inflection point and perpendicular to the bottom surface is taken as a y axis, and the directions of the x axis, the y axis and the z axis are shown in figure 20;
the present implementation differs from example 3 in that: the front split electrode 83 and the thick front split electrode dielectric layer 84 are introduced into the front trench gate structure, the back split electrode 283 and the thick back split electrode dielectric layer 284 are introduced into the back trench gate structure, the split electrodes 83 and 283 have the same electric potential as the emitter metals 1 and 21, and the thicknesses of the split electrode dielectric layers 84 and 284 are larger than those of the gate dielectric layers 82 and 282. This embodiment reduces the gate capacitance of the device by introducing the split electrode 83, 283, thereby increasing the switching speed and reducing the switching losses of the device, while the thick split electrode dielectric layer 84, 284 increases the device breakdown voltage, improving the reliability of the device.
Example 6:
the invention provides a trench gate charge storage type IGBT, wherein a quarter cell of the IGBT is shown in figure 24, a section along an AB line and an A 'B' line is shown in figures 26 and 27, a three-dimensional coordinate system is established by taking any inflection point of the quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively taken as an x axis and a z axis, a straight line passing through the inflection point and perpendicular to the bottom surface is taken as a y axis, and the directions of the x axis, the y axis and the z axis are shown in figure 24;
the present implementation differs from example 5 in that: and introducing a front second P-type layer 11 at the bottom of the front split trench gate structure, introducing a back second P-type layer 211 at the bottom of the back split trench gate structure, wherein the second P- type layers 11 and 211 are connected with split electrodes 83 and 283 through split electrode dielectric layers 84 and 284, and the junction depth of the second P- type layers 11 and 211 is 0.5-1 mu m. This example combines the features and superior characteristics of examples 4 and 5.
Example 7:
the present implementation differs from example 3 in that: the back-side shield trench structure is the same as the front-side shield trench structure and is symmetrical across the lateral centerline of the nth semiconductor drift region 9, and the rest of the structure is the same as that of embodiment 3. The device performance was also the same as that shown in example 3.
Example 8:
in this embodiment, a trench gate charge storage IGBT with a voltage level of 1200V is taken as an example for explanation, and devices with different performance parameters can be prepared according to actual requirements based on common knowledge in the art.
A manufacturing method of a bidirectional trench gate charge storage type IGBT is characterized by comprising the following steps:
step 1: two same N-type lightly doped monocrystalline silicon wafers are used as an N-type drift region 9 of the device, the thickness of the selected silicon wafers is 300-600 mu m, and the doping concentration is 1013～1014Per cm3；
Step 2: respectively growing a layer of field oxide layer on the surfaces of two silicon wafers by the same process, photoetching to obtain an active region, growing a layer of pre-oxide layer, and implanting N-type impurities by ions to obtain an N-type charge storage layer 6, wherein the energy of ion implantation is 200-500 keV, and the implantation dosage is 1013～1014Per cm2(ii) a And then, injecting P-type impurities above the N-type charge storage layer 6 by ions, and annealing to obtain a P-type base region 5, wherein the energy of the ion injection is 60-120 keV, and the injection dosage is 1013～1014Per cm2Annealing at 1100-1150 deg.c for 10-30 min;
and step 3: respectively depositing TEOS protective layers with the thickness of 700-1000 nm on the surfaces of two silicon wafers by adopting the same process, photoetching a window to perform groove silicon etching, and further etching an N-type drift region 9 to form a first groove, wherein as shown in figure 16, the first groove extends from the right end of a device to the left end of the device, and the depth of the first groove is greater than the junction depth of an N-type charge storage layer 6;
and 4, step 4: o at 1050-1150 deg.C2Under the atmosphere, respectively forming dielectric layers on the inner walls of the first trenches by the same process to serve as shielding electrode dielectric layers 72, as shown in fig. 17; then depositing a shielding electrode material in the first groove at 750-950 ℃ to form a shielding electrode 71In the embodiment, a polysilicon material is used as a shielding electrode material, the shielding electrode 71 in the first trench and the shielding electrode dielectric layer 72 on the peripheral side thereof form a shielding trench structure which plays a role in shielding an electric field of the N-type charge storage layer 6, and the shielding trench structure is as shown in fig. 18;
and 5: respectively depositing TEOS protective layers with the thickness of 700-1000 nm on the surfaces of two silicon wafers by adopting the same process, photoetching a window to perform groove silicon etching, and further etching and forming a second groove on the N-type drift region 9, wherein the second groove extends from the front end to the rear end of the device, the second groove and the first groove are mutually vertical in space and are not communicated with each other, and the second groove and the first groove are isolated by a gate dielectric layer 82; the depth of the second groove is smaller than the junction depth of the N-type charge storage layer 6;
step 6: o at 1050-1150 deg.C2Under the atmosphere, respectively forming dielectric layers on the inner walls of the second trenches by using the same process as shown in fig. 20 as gate dielectric layers 82; then, at 750-950 ℃, depositing a gate electrode material in the second trench as a gate electrode 81, wherein a polysilicon material is used as the gate electrode material in this embodiment, the gate electrode 81 in the second trench and the gate dielectric layer 82 around the gate electrode form a trench gate structure, and the trench gate structure is as shown in fig. 21;
and 7: respectively implanting N-type impurities and P-type impurities into the top layer of the P-type base region 5 between the first groove and the second groove on the two silicon chips by adopting the same photoetching and ion implantation processes, wherein the energy of the ion implantation of the N-type impurities is 30-60 keV, and the implantation dosage is 10 keV15～1016Per cm2The energy of ion implantation of P-type impurity is 60-80 keV, and the implantation dosage is 1015～1016Per cm2Annealing at 900 ℃ for 20-30 minutes to obtain an N + emission region 3 and a P + emission region 4 which are in mutual contact and arranged in parallel; as shown in fig. 22, the left side of the N + emitter region 3 is connected to the gate dielectric layer 82 along the longitudinal direction of the top layer of the device, and the back side is connected to the shielding trench dielectric layer 72 along the transverse direction of the top layer of the device; the back side of the P + emitting region 4 is connected with a shielding groove dielectric layer 72 along the transverse direction of the device;
and 8: as shown in fig. 23, dielectric layers are deposited on the surfaces of two devices by the same process, and isolation dielectric layers 2 are formed on the upper surfaces of a gate electrode 81 and a gate dielectric layer 82 by photolithography and etching processes;
and step 9: as shown in fig. 24, the same process is adopted to deposit metal on the surfaces of the two devices, and photolithography and etching processes are adopted to form an emitter metal 1 on the isolation dielectric layer 2, the N + emitter region 3, the P + emitter region 4, the shield electrode 71 and the shield trench dielectric layer 72;
step 10: turning over the two silicon wafers, respectively reducing the thicknesses of the two silicon wafers by adopting the same process, and then bonding the two silicon wafers back to back by adopting a bonding process to form a bidirectional CSTBT device, as shown in figure 25, so as to complete the preparation of the bidirectional trench gate charge storage type IGBT.
It should be noted that, in the manufacturing method provided in this embodiment, the lateral position of the device surface corresponds to the x-axis direction of the coordinate system shown in the drawings of the specification, and the longitudinal position of the device surface corresponds to the z-axis direction of the coordinate system shown in the drawings of the specification, which is not described in detail below.
Further, the order of forming the trench gate structure and the shield trench structure in the present invention may be switched.
Further, in the process of manufacturing the single-sided MOS structure, the order of forming the trench structure and forming the N-type charge storage layers 6 and 26 and the P- type base regions 5 and 25 in the present invention may be interchanged.
Further, in the process of manufacturing the single-sided MOS structure, the invention changes the trenching manner, so that the shield electrode 71, 271 in the shield trench structure extends from one end to the other end along the lateral direction of the device top layer, such as the x-axis direction in fig. 11, while the gate electrode 81, 281 in the trench gate structure extends from one end to the shield trench dielectric layer 72, 272 along the longitudinal direction of the device top layer, such as the z-axis direction in fig. 9, and the gate electrode 81, 281 and the shield electrode 71, 271 are isolated by the shield trench dielectric layer 72, 272.
Further, as shown in fig. 26 to 36, in the process of preparing the single-sided MOS structure, in step 4 of the present invention, an ion implantation step may be added to form the P- type layers 10 and 210 at the bottom of the shielding trench structure, so as to obtain the device structure illustrated in embodiment 2.
Furthermore, in the present invention, the materials of the isolation dielectric layers 2 and 22, the shield trench dielectric layers 72 and 272, and the gate dielectric layers 82 and 282 may be the same material or different materials.
The device structure and the preparation method are described by taking an N-channel IGBT device as an example, but the invention is also applicable to the preparation of a P-channel IGBT device, and details are not repeated herein.
The above is a preferred embodiment of the present invention, and various changes and modifications can be made by those skilled in the art without departing from the technical spirit of the present invention from the above description. Therefore, the technical scope of the present invention is not limited to the content of the specification, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.
Claims (10)
1. A kind of two-way ditch groove grid charge storage type IGBT, its quarter cell includes the MOS structure that is set up in the front and back of the semiconductor drift region (9) of the first conductivity type symmetrically; the method is characterized in that: the front MOS structure comprises a front emitter metal (1), a front isolation dielectric layer (2), a front groove gate structure, a front shielding groove structure, a front first conductive type semiconductor emitting region (3), a front second conductive type semiconductor emitting region (4), a front second conductive type semiconductor base region (5) and a front first conductive type semiconductor charge storage layer (6); the back MOS structure comprises a back emitter metal (21), a back isolation dielectric layer (22), a back groove gate structure, a back shielding groove structure, a back first conductive type semiconductor emitting region (23), a back second conductive type semiconductor emitting region (24), a back second conductive type semiconductor base region (25) and a back first conductive type semiconductor charge storage layer (26);
in the front-side MOS structure, a front-side first conduction type semiconductor charge storage layer (6) is positioned at the top layer of the front-side first conduction type semiconductor drift region (9); the front second conductive type semiconductor base region (5) is positioned on the top layer of the front first conductive type semiconductor charge storage layer (6); the front-surface second-conductivity-type semiconductor emitter region (4) and the front-surface first-conductivity-type semiconductor emitter region (3) are mutually independent and are arranged on the top layer of the front-surface second-conductivity-type semiconductor base region (5) in parallel;
the top layer of the front first conduction type semiconductor drift region (9) is provided with a front groove gate structure and a front shielding groove structure, and the front groove gate structure and the front shielding groove structure are different along the extending direction of the top layer of the device; the front-surface trench gate structure comprises a front-surface gate electrode (81) and a front-surface gate dielectric layer (82), wherein the front-surface gate electrode (81) downwards penetrates through a front-surface first conduction type semiconductor emitter region (3) and a front-surface second conduction type semiconductor base region (5) to enter a front-surface first conduction type semiconductor charge storage layer (6), the front-surface gate electrode (81) is connected with the front-surface first conduction type semiconductor emitter region (3), the front-surface second conduction type semiconductor base region (5) and the front-surface first conduction type semiconductor charge storage layer (6) through the front-surface gate dielectric layer (82), and the upper surface of the front-surface gate electrode (81) is connected with a front-surface emitter metal (1) through a front-surface isolation dielectric layer (2); the front shielding groove structure comprises a front shielding electrode (71) and a front shielding groove dielectric layer (72), the front shielding electrode (71) downwards penetrates through the front second conduction type semiconductor emitter region (4), the front second conduction type semiconductor base region (5) and the front first conduction type semiconductor charge storage layer (6) to enter the front first conduction type semiconductor drift region (9), the front shielding electrode (71) is isolated from the front gate electrode (81) through the front gate dielectric layer (82) or the shielding groove dielectric layer (72), the front shielding electrode (71) is connected with the front first conduction type semiconductor emitter region (3), the front second conduction type semiconductor emitter region (4), the front second conduction type semiconductor base region (5), the front first conduction type semiconductor charge storage layer (6) and the front first conduction type semiconductor drift region (9) through the front shielding groove dielectric layer (72), the front shielding electrode (71) and the front emitter metal (1) are equipotential; the back side MOS structure is the same as the front side MOS structure.
2. The bi-directional trench gate charge storage IGBT of claim 1 wherein: the first conductive type semiconductor is a P-type semiconductor, and the second conductive type semiconductor is an N-type semiconductor; or the first conductive type semiconductor is an N-type semiconductor and the second conductive type semiconductor is a P-type semiconductor.
3. The bi-directional trench gate charge storage IGBT of claim 2 wherein: a three-dimensional coordinate system is established by taking any inflection point of a quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively used as an x axis and a z axis, a straight line which passes through the inflection point and is perpendicular to the bottom surface is used as a y axis, a gate electrode (81, 281) extends from one end of a device to the other end along the x axis or the z axis, a shielding electrode (71, 271) extends from one end of the device to a gate dielectric layer (82, 281) on the side surface of the gate electrode (81, 281) along the z axis or the x axis, and the extending directions of the gate electrode (81, 281) and the shielding electrode (71, 271) are not.
4. The bi-directional trench gate charge storage IGBT of claim 2 wherein: a three-dimensional coordinate system is established by taking any inflection point of a quarter cell as an origin, two sides of the bottom surface of the quarter cell, which intersect at the inflection point, are respectively used as an x axis and a z axis, a straight line which passes through the inflection point and is perpendicular to the bottom surface is used as a y axis, a shielding electrode (71, 271) extends from one end of a device to the other end along the x axis or the z axis, a gate electrode (81, 281) extends from one end of the device to a shielding groove dielectric layer (72, 272) on the side surface of the shielding electrode (71, 271) along the z axis or the x axis, and the extending directions of the shielding electrode (71, 271) and the gate electrode (81, 281) are inconsistent.
5. The bi-directional trench gate charge storage IGBT of claim 1 wherein: the front groove gate structure is a front split groove gate structure.
6. The bi-directional trench gate charge storage IGBT of claim 1 wherein: the front shielding groove structure is also provided with a front second conduction type semiconductor layer (10) at the bottom, and the back shielding groove structure is also provided with a back second conduction type semiconductor layer (210) at the top, and the second conduction type semiconductor layers (10 and 210) laterally extend into a first conduction type semiconductor drift region (9) below the front first conduction type semiconductor charge storage layer (6) or above the back first conduction type semiconductor charge storage layer (26).
7. The bidirectional trench gate charge storage IGBT of any one of claims 2 to 6, wherein: the front MOS structure and the back MOS structure can be in mirror symmetry along the transverse center line of the first conduction type semiconductor drift region (9) or in crossed symmetry along the transverse center line of the first conduction type semiconductor drift region (9).
8. A manufacturing method of a bidirectional trench gate charge storage type IGBT is characterized by comprising the following steps:
the method comprises the following steps: manufacturing two identical first-conductivity-type semiconductor drift regions (9);
step two: respectively manufacturing a first conductive type semiconductor charge storage layer (6, 26) and a first conductive type semiconductor base region (5, 25) positioned at the top layer of a second conductive type semiconductor charge storage layer (6, 26) on the front surfaces of two first conductive type semiconductor drift regions (9) by adopting the same pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes;
step three: respectively etching two first conduction type semiconductor drift regions (9) to form first grooves by adopting the same photoetching, etching, thermal oxidation and deposition processes, wherein the depth of each first groove is greater than the junction depth of the first conduction type semiconductor charge storage layers (6 and 26) and extends along the transverse direction of the top layer of the device; forming a shielding groove dielectric layer (72, 272) on the inner wall of the first groove, then depositing an electrode material in the first groove to form a shielding electrode (71, 271), wherein the shielding electrode (71, 271) and the shielding groove dielectric layer (72, 272) on the peripheral side form a shielding groove structure;
step four: respectively etching two first conduction type semiconductor charge storage layers (6, 26) to form second grooves by adopting the same photoetching, etching, thermal oxidation and deposition processes, wherein the depth of each second groove is less than the junction depth of the first conduction type semiconductor charge storage layers (6, 26) and extends along the longitudinal direction of the top layer of the device, and the second grooves are not communicated with the first grooves; forming gate dielectric layers (82, 282) on the inner walls of the first trenches, then depositing a gate electrode material in the trenches to form gate electrodes (81, 281), wherein the gate electrodes (81, 281) and the gate dielectric layers (82, 282) on the peripheral sides of the gate electrodes form trench gate structures; step five: respectively manufacturing second conductive type semiconductor emitter regions (4, 24) and first conductive type semiconductor emitter regions (3, 23) which are independent and arranged in parallel on the top layers of the two second conductive type semiconductor base regions (5, 25) by adopting the same photoetching, etching, ion implantation and high-temperature annealing processes; one side of the first conduction type semiconductor emitting region (3, 23) is connected with the gate electrode (81, 281) through a gate dielectric layer (82, 282) along the longitudinal direction of the top layer of the device, the other side of the first conduction type semiconductor emitting region is connected with the shielding electrode (71, 271) through a shielding groove dielectric layer (72, 272) along the transverse direction of the top layer of the device, and one side of the second conduction type semiconductor emitting region (4, 24) is connected with the shielding electrode (71, 271) through the shielding groove dielectric layer (72, 272) along the transverse direction of the top layer of the device;
step six: respectively forming isolation dielectric layers (2, 22) on the upper surfaces of the two gate electrodes (81, 281) and the gate dielectric layers (82, 282) by adopting the same photoetching, etching and deposition processes;
step seven: depositing metal on the surface, and respectively forming emitter metal (1, 21) on the isolation dielectric layers (2, 22), the first conductive type semiconductor emitting regions (3, 23), the second conductive type semiconductor emitting regions (4, 24), the shielding electrodes (71, 271) and the shielding groove dielectric layers (72, 272) by adopting the same photoetching and etching processes;
step eight: and turning over the semiconductor wafers, respectively reducing the thickness of the two semiconductor wafers by adopting the same process, and then forming the bidirectional trench gate charge storage type IGBT device by back-to-back bonding the two completely same semiconductor wafers by adopting a bonding process, thereby completing the preparation of the device.
9. The method according to claim 8, wherein the method comprises the following steps: the first conductive type semiconductor is a P-type semiconductor, and the second conductive type semiconductor is an N-type semiconductor; or the first conductive type semiconductor is an N-type semiconductor and the second conductive type semiconductor is a P-type semiconductor.
10. The method according to claim 9, wherein the method comprises the following steps: in the third step and the fourth step, the trench gate structure extends from one end of the device to the other end of the device along the top layer of the device and blocks the extension of the shielding trench structure along the top layer of the device or the shielding trench structure extends from one end of the device to the other end of the device along the top layer of the device and blocks the extension of the trench gate structure along the top layer of the device by changing the trench digging mode.
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