CN112687743B - Groove type silicon carbide reverse resistance MOSFET device and preparation method thereof - Google Patents
Groove type silicon carbide reverse resistance MOSFET device and preparation method thereof Download PDFInfo
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Abstract
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a groove type silicon carbide reverse resistance MOSFET device and a preparation method thereof. Compared with the traditional groove type silicon carbide MOSFET, the groove type silicon carbide MOSFET is provided with the N type silicon carbide substrate removed, the first N type silicon carbide buffer layer is introduced to one side of the source region of the device, the second N type silicon carbide buffer layer is introduced to one side of the drain region of the device, and the junction type Schottky barrier diode structure is introduced to one side of the drain region of the device. The device structure can enable the groove type silicon carbide MOSFET to obtain large forward and reverse symmetrical voltage resistance and simultaneously have small forward conduction voltage drop. In addition, in order to further solve the problems of reliability of the gate oxide layer of the device and large gate leakage capacitance, a plurality of corresponding derivative structures are provided.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a groove type silicon carbide reverse resistance MOSFET device and a preparation method thereof.
Background
The inverter is a device for converting direct current into alternating current, and has a wide application range, such as a photovoltaic inverter, an uninterruptible power supply, a rail transit and trolley bus, a frequency converter and the like. The multi-level inverter has the excellent characteristics of low loss, low noise, output waveform close to a sine wave and the like, so that the application scene of the multi-level inverter is wider. The matrix inverter is a novel power converter, and can directly realize alternating current-alternating current conversion. Compared with the traditional alternating current-direct current-alternating current frequency conversion mode, the matrix inverter does not need a direct current capacitor for intermediate energy storage, the reliability of the whole system is improved, and the cost is reduced.
Bidirectional switches with forward and reverse conduction capability and blocking capability are core devices of multilevel inverters and matrix inverters. A reverse-blocking type insulated gate bipolar transistor (RB-IGBT) is a novel IGBT with bidirectional blocking capability, and two RB-IGBTs are reversely connected in parallel to form a bidirectional switch. Compared with the conventional bidirectional switch which is generally composed of two ordinary IGBTs and two fast recovery diodes, the bidirectional switch composed of RB-IGBTs has fewer elements and lower conduction loss. The conventional RB-IGBT generally adopts a non-punch-through (NPT) structure, which has a long IGBT drift region, and thus has a severe current tail and a large turn-off loss. How to reduce the power loss of the bidirectional switch is one of the current research hotspots.
Silicon carbide, which is one of typical representatives of the third-generation semiconductor materials, has excellent characteristics such as a large forbidden band width, a high electron saturation drift velocity, and a high thermal conductivity. Compared with the IGBT with the same voltage-resistant grade, the silicon carbide MOSFET has lower on-voltage drop and turn-off loss. Therefore, if the silicon carbide MOSFET can realize bidirectional blocking, its performance is much superior to that of the RB-IGBT. Fig. 1 shows a conventional trench-type silicon carbide MOSFET, which has a large forward blocking capability and a low on-state voltage drop. However, this structure does not have reverse blocking capability.
Disclosure of Invention
The invention aims to solve the problems of how to enable a trench type silicon carbide MOSFET to have large forward and reverse symmetrical voltage resistance and how to reduce the conduction voltage drop of the MOSFET. Conventional trench silicon carbide MOSFETs, as shown in fig. 1, do not have reverse blocking capability. The invention provides two technical schemes. Technical solution 1 as shown in fig. 2, in the present technical solution, a silicon carbide substrate in a conventional trench-type silicon carbide MOSFET structure is removed, a first N-type silicon carbide buffer layer is introduced at a source region side, a second N-type silicon carbide buffer layer is introduced at a drain region side, and a junction barrier schottky diode structure (JBS) is introduced at a drain region side. The device structure enables the groove type silicon carbide MOSFET to have reverse blocking capability and obtain lower forward conduction voltage drop. Technical solution 2 as shown in fig. 3, in the technical solution 2, a silicon carbide substrate in a conventional trench-type silicon carbide MOSFET structure is also removed, a first N-type silicon carbide buffer layer is introduced on one side of a source region, and a second N-type silicon carbide buffer layer is introduced on one side of a drain region, and a device back structure is different from that of the technical solution 1. The technical scheme also enables the groove type silicon carbide MOSFET to have reverse blocking capability and obtain lower forward conduction voltage drop. In addition, the invention also provides a preparation method of the device in the two technical schemes, and the preparation method is simple and controllable in manufacturing process and strong in compatibility with the existing process.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a scheme I
A trench-type silicon carbide reverse-resistance MOSFET, the half cell of which comprises:
the method comprises the following steps: a back drain metal 1, a second N-type silicon carbide buffer layer 21 and an N-type silicon carbide epitaxial layer 3 which are sequentially stacked from bottom to top,
a grid 4 and a first N-type silicon carbide buffer layer 10 are arranged above the N-type silicon carbide epitaxial layer 3, the first N-type silicon carbide buffer layer 10 is positioned on the right side of the grid 4, a P-type silicon carbide base region 9 is arranged above the first N-type silicon carbide buffer layer 10, and an N-type silicon carbide source region 6 and a P-type silicon carbide source region 7 are arranged above the P-type silicon carbide base region 9; the N-type silicon carbide source region 6 is connected with the P-type silicon carbide source region 7 left and right; a source metal 8 is arranged above the P-type silicon carbide source region 7, and the source metal 8 is respectively connected with the P-type silicon carbide source region 7 and part of the N-type silicon carbide source region 6 up and down; a gate dielectric layer 5 is arranged between the gate 4 and the N-type silicon carbide epitaxial layer 3, between the gate 4 and the first N-type silicon carbide buffer layer 10, between the gate 4 and the P-type silicon carbide base region 9 and between the gate 4 and the N-type silicon carbide source region 6;
the second N-type silicon carbide buffer layer 21 is provided with a disconnected P-type region 11, and an ohmic contact 13 is formed between the lower part of the P-type region 11 and the drain metal 1; the second N-type silicon carbide buffer layer 21 forms a schottky contact 12 with the drain metal 1.
Preferably, a P-type buried layer 14 is arranged at the bottom of the gate dielectric layer 5.
Preferably, the transistor further comprises a shielding gate 15 arranged below the gate dielectric layer 5, the shielding gate 15 is in short circuit with the source metal 8, and shielding gate dielectric layers 16 are arranged below and on the right side of the shielding gate 15.
Preferably, the N-type silicon carbide epitaxial layer 3 is replaced by a P column 31 and an N column 32.
Preferably, all silicon carbide materials are replaced by gallium nitride, gallium oxide, boron nitride, silicon materials.
Preferably, the trench type silicon carbide reverse-resistance MOSFET device front half-cell structure comprises a back drain metal 1, a second N type silicon carbide buffer layer 21 and an N type silicon carbide epitaxial layer 3 which are sequentially stacked from bottom to top,
a first N-type silicon carbide buffer layer 10 is arranged above the N-type silicon carbide epitaxial layer 3, a gate dielectric layer 5 is arranged above the first N-type silicon carbide buffer layer 10, a gate 4 is arranged inside the gate dielectric layer 5, a first P-type silicon carbide base region 9 is arranged on the right side of the gate dielectric layer 5, the left side of the first P-type silicon carbide base region 9 is in contact with the gate dielectric layer 5, the left upper surface of the first P-type silicon carbide base region is in contact with a first N-type silicon carbide source region 6, the right upper surface of the first P-type silicon carbide base region is in contact with a first P-type silicon carbide source region 7, the lower part of the first P-type silicon carbide base region is in contact with the first N-type silicon carbide buffer layer 10, and source metal 8 is arranged above the first P-type silicon carbide source region 7; the source metal 8 covers the upper and right surfaces of the first N-type source region 6,
preferably, the cell structure on the front surface of the trench type silicon carbide reverse-resistance MOSFET device comprises a back drain metal 1, a second N-type silicon carbide buffer layer 21 and an N-type silicon carbide epitaxial layer 3 which are sequentially stacked from bottom to top,
a first N-type silicon carbide buffer layer 10 is arranged above the N-type silicon carbide epitaxial layer 3, a grid 4 is arranged in the middle of the upper portion of the first N-type silicon carbide buffer layer 10, a second P-type source region 71 is arranged on the left portion of the upper portion of the first N-type silicon carbide buffer layer 10, a second N-type source region 61 and a second P-type base region 91 are arranged on the right side of the second P-type source region 71, the second N-type source region 61 and the second P-type base region 91 are connected in an up-and-down mode, a third P-type source region 72 is arranged on the right side of the grid 4, the third P-type source region 72 extends to the middle of the grid 4 leftwards, a third N-type source region 62 and a third P-type base region 92 are arranged on the right side of the third P-type source region 72, the third N-type source region 62 and the third P-type base region 92 are connected in an up-and-down mode, the grid 4 and the second N-type source region 61, the grid 4 and the second P-type base region 91, the grid 4 and the first N-type silicon carbide buffer layer 10 are isolated by a grid 5;
the invention also provides a preparation method of the groove type silicon carbide reverse resistance MOSFET device, which comprises the following preparation steps:
step 1: preparing a second N-type silicon carbide buffer layer 21 on the surface of the N-type silicon carbide substrate 2 by adopting an epitaxial process;
step 2: preparing an N-type silicon carbide epitaxial layer 3 on the surface of the second N-type silicon carbide buffer layer 21 by adopting an epitaxial process;
and step 3: etching a groove above the N-type silicon carbide epitaxial layer 3 by adopting photoetching and etching processes;
and 4, step 4: growing a gate dielectric layer 5 on the surface of the trench by adopting a thermal oxidation process;
and 5: depositing a gate 4 in the gate dielectric layer 5 by adopting a deposition process;
step 6: sequentially forming a first N-type silicon carbide buffer layer 10, a P-type silicon carbide base region 9, an N-type silicon carbide source region 6 and a P-type silicon carbide source region 7 in the N-type silicon carbide epitaxial layer 3 by adopting photoetching and ion implantation processes;
and 7: turning over the silicon wafer, and removing the N-type silicon carbide substrate 2 by adopting a grinding process;
and 8: manufacturing nonadjacent P-type regions 11 in the second N-type silicon carbide buffer layer 21 by adopting photoetching and ion implantation processes;
and step 9: preparing a source metal 8 by adopting an evaporation or sputtering process and an etching process;
step 10: and preparing the back drain metal 1 by adopting an evaporation or sputtering process and an etching process, forming Schottky contact between the back drain metal 1 and the second N-type silicon carbide buffer layer 21, and forming ohmic contact between the back drain metal 1 and the P-type region 11.
Second, scheme two
A trench-type silicon carbide reverse-resistance MOSFET, the half cell of which comprises:
a back drain metal 1, a second N-type silicon carbide buffer layer 21 and an N-type silicon carbide epitaxial layer 3 which are sequentially stacked from bottom to top,
a grid 4 and a first N-type silicon carbide buffer layer 10 are arranged above the N-type silicon carbide epitaxial layer 3, the first N-type silicon carbide buffer layer 10 is positioned on the right side of the grid 4, a P-type silicon carbide base region 9 is arranged above the first N-type silicon carbide buffer layer 10, and an N-type silicon carbide source region 6 and a P-type silicon carbide source region 7 are arranged above the P-type silicon carbide base region 9; the N-type silicon carbide source region 6 is connected with the P-type silicon carbide source region 7 left and right; a source metal 8 is arranged above the P-type silicon carbide source region 7, and the source metal 8 is respectively connected with the P-type silicon carbide source region 7 and part of the N-type silicon carbide source region 6 up and down; a gate dielectric layer 5 is arranged between the gate 4 and the N-type silicon carbide epitaxial layer 3, between the gate 4 and the first N-type silicon carbide buffer layer 10, between the gate 4 and the P-type silicon carbide base region 9, and between the gate 4 and the N-type silicon carbide source region 6;
the second N-type silicon carbide buffer layer 21 is provided with unconnected P-type floating areas 17; the lower part of the P-type floating space region 17 is not contacted with the back drain metal 1, namely the P-type floating space region 17 is completely floated in the second N-type silicon carbide buffer layer 21; a schottky contact is formed between the second N-type silicon carbide buffer layer 21 and the back drain metal 1.
Preferably, a P-type buried layer 14 is arranged at the bottom of the gate dielectric layer 5.
Preferably, the transistor further comprises a shielding gate 15 arranged below the gate dielectric layer 5, the shielding gate 15 is in short circuit with the source metal 8, and shielding gate dielectric layers 16 are arranged below and on the right side of the shielding gate 15.
Preferably, the N-type silicon carbide epitaxial layer 3 is replaced by a P column 31 and an N column 32.
Preferably, all silicon carbide materials are replaced by gallium nitride, gallium oxide, boron nitride, silicon materials.
Preferably, the trench type silicon carbide reverse-resistance MOSFET device front half-cell structure comprises a back drain metal 1, a second N type silicon carbide buffer layer 21 and an N type silicon carbide epitaxial layer 3 which are sequentially stacked from bottom to top,
a first N-type silicon carbide buffer layer 10 is arranged above the N-type silicon carbide epitaxial layer 3, a gate dielectric layer 5 is arranged above the first N-type silicon carbide buffer layer 10, a gate 4 is arranged inside the gate dielectric layer 5, a first P-type silicon carbide base region 9 is arranged on the right side of the gate dielectric layer 5, the left side of the first P-type silicon carbide base region 9 is in contact with the gate dielectric layer 5, the left upper surface of the first P-type silicon carbide base region is in contact with a first N-type silicon carbide source region 6, the right upper surface of the first P-type silicon carbide base region is in contact with a first P-type silicon carbide source region 7, the lower part of the first P-type silicon carbide base region is in contact with the first N-type silicon carbide buffer layer 10, and source metal 8 is arranged above the first P-type silicon carbide source region 7; the source metal 8 covers the upper and right surfaces of the first N-type source region 6,
preferably, the cell structure on the front surface of the trench type silicon carbide reverse resistance MOSFET device comprises a back drain metal 1, a second N-type silicon carbide buffer layer 21 and an N-type silicon carbide epitaxial layer 3 which are sequentially stacked from bottom to top,
a first N-type silicon carbide buffer layer 10 is arranged above the N-type silicon carbide epitaxial layer 3, a grid 4 is arranged in the middle of the upper portion of the first N-type silicon carbide buffer layer 10, a second P-type source region 71 is arranged on the left portion of the upper portion of the first N-type silicon carbide buffer layer 10, a second N-type source region 61 and a second P-type base region 91 are arranged on the right side of the second P-type source region 71, the second N-type source region 61 and the second P-type base region 91 are connected in an up-and-down mode, a third P-type source region 72 is arranged on the right side of the grid 4, the third P-type source region 72 extends to the middle of the grid 4 leftwards, a third N-type source region 62 and a third P-type base region 92 are arranged on the right side of the third P-type source region 72, the third N-type source region 62 and the third P-type base region 92 are connected in an up-and-down mode, the grid 4 and the second N-type source region 61, the grid 4 and the second P-type base region 91, the grid 4 and the first N-type silicon carbide buffer layer 10 are isolated by a grid 5;
the invention also provides a preparation method of the groove type silicon carbide reverse resistance MOSFET device, which comprises the following preparation steps:
step 1: preparing a second N-type silicon carbide buffer layer 21 on the surface of the N-type silicon carbide substrate 2 by adopting an epitaxial process;
step 2: preparing an N-type silicon carbide epitaxial layer 3 on the surface of the second N-type silicon carbide buffer layer 21 by adopting an epitaxial process;
and step 3: etching a groove above the N-type silicon carbide epitaxial layer 3 by adopting photoetching and etching processes;
and 4, step 4: growing a thin gate dielectric layer 5 on the surface of the trench by adopting a thermal oxidation process;
and 5: depositing a gate 4 in the gate dielectric layer 5 by adopting a deposition process;
step 6: forming a first N-type silicon carbide buffer layer 10, a P-type silicon carbide base region 9, an N-type silicon carbide source region 6 and a P-type silicon carbide source region 7 in the N-type epitaxial layer in sequence by adopting photoetching and ion implantation processes;
and 7: turning over the silicon wafer, and removing the N-type silicon carbide substrate 2 by adopting a grinding process;
and 8: preparing P-type floating empty regions 17 distributed at intervals in a second N-type silicon carbide buffer layer 21 by adopting photoetching and ion implantation processes;
and step 9: preparing a source metal 8 by adopting an evaporation or sputtering process and an etching process; step 10: the back drain metal 1 is prepared by an evaporation or sputtering process and an etching process, and a schottky contact is formed between the back drain metal 1 and the second N-type silicon carbide buffer layer 21.
Further, for simplicity of description, the device structure and the manufacturing method are described by taking an N-channel silicon carbide MOSFET as an example, but the present invention is also applicable to the manufacturing of a P-channel silicon carbide MOSFET device.
Further, for both technical solutions of the present invention, the front structure of the device structure mentioned above may be changed to the front structure shown in fig. 10 and fig. 11.
The working principle of the invention is as follows:
a conventional trench-type silicon carbide MOSFET is shown in fig. 1. During forward operation, a positive voltage is applied to the drain electrode, a negative voltage is applied to the source electrode, the device is started by applying a proper forward bias voltage to the grid electrode, when the device needs to be turned off, the forward bias voltage of the grid electrode is removed, a reverse PN junction formed by the P-type base region and the N-type drift region bears a withstand voltage, the depletion region expands towards the direction of the substrate, and the N-type substrate has high doping concentration, so that the further expansion of the depletion region is prevented, the punch-through of the device is prevented, and the forward withstand voltage is ensured. However, when the MOSFET is turned off in the reverse direction, the conventional trench silicon carbide MOSFET cannot form a voltage-withstanding region, and thus does not have a reverse voltage-withstanding capability.
The invention has two technical schemes of a first scheme and a second scheme, and the basic principles of the two technical schemes are similar, so that only the working principle of the first technical scheme is explained. In the first scheme, the silicon carbide substrate in the traditional groove type silicon carbide MOSFET structure is removed,a first N-type silicon carbide buffer layer is introduced at one side of a source region, a second N-type silicon carbide buffer layer is introduced at one side of a drain region, and a junction barrier Schottky diode structure (JBS) is introduced at one side of the drain region, so that a voltage-resistant region can be generated when the silicon carbide MOSFET is turned off in a reverse direction, the silicon carbide MOSFET has reverse blocking capability, and a lower forward conduction voltage drop can be obtained. It is noted that in the present invention, the first N-type silicon carbide buffer layer and the second N-type silicon carbide buffer layer are introduced in a concentration higher than the drift region concentration, but lower than the substrate concentration of the conventional trench-type silicon carbide MOSFET, in a concentration range of 1015cm-3To 1016cm-3And the order of magnitude ensures that the device can obtain larger symmetrical voltage resistance.
When the MOSFET device structure is normally conducted, because the Schottky barrier is lower than the PN junction barrier, current can flow through a conducting channel of the Schottky barrier at first, and the device is conductive for a plurality of sub-devices, when the device works in the forward direction, the JBS structure is equivalent to the SBD structure, because the Schottky barrier is lower than the barrier of ohmic contact, compared with the traditional groove type silicon carbide MOSFET, the device structure can obtain lower MOSFET drain contact resistance, and simultaneously, because the concentrations of the introduced first N type silicon carbide buffer layer and the second N type silicon carbide buffer layer are higher than the concentration of a drift region, the conduction voltage drop of the device can be further reduced. When a device passes a large surge current, because a large voltage drop is generated in the N-type silicon carbide by a large transverse current above a P-type silicon carbide/N-type silicon carbide PN junction, the P-type silicon carbide/N-type silicon carbide PN junction on the back is conducted, and a large number of holes are injected into the N-type silicon carbide by the P-type silicon carbide on the back to form local conductance modulation, so that the conduction resistance in the N-type silicon carbide is reduced, the loss of the device is obviously reduced, and the through-current capability of the device is improved, so that the surge current resistance of the device is improved, and the device has high surge current bearing capability.
When forward voltage resistance is achieved, firstly, the PN junction formed by the P-type base region and the first N-type silicon carbide buffer layer carries out voltage resistance, the concentration of the introduced first N-type silicon carbide buffer layer is not very high, so that the depletion region can penetrate through the first N-type silicon carbide buffer layer and continuously extends towards the lower part of the drift region, and when the depletion region reaches the second N-type silicon carbide buffer layer, the concentration of the second N-type silicon carbide buffer layer is higher than that of the drift region, so that the extension of the depletion region can be prevented, and larger forward voltage resistance is guaranteed. When the device reaches the first N-type silicon carbide buffer layer, because the concentration of the first N-type silicon carbide buffer layer is higher than that of the drift region, the expansion of the depletion region is stopped, the punch-through of the device is prevented, and the device is ensured to have larger reverse withstand voltage. Therefore, the device structure has larger forward and reverse symmetrical voltage resistance and smaller forward conduction voltage drop.
The beneficial effects of the invention are as follows:
bidirectional switches are the core devices of multilevel inverters and matrix inverters. Two RB-IGBTs are reversely connected in parallel to form a bidirectional switch, a non-punch-through (NPT) structure is usually adopted for the conventional silicon-based RB-IGBT, and the IGBT drift region of the structure is long, so that the current tailing is serious, and the turn-off loss is large. Compared with a silicon-based IGBT with the same voltage-resistant grade, the silicon carbide MOSFET has lower on-voltage drop and turn-off loss. The invention relates to a groove type silicon carbide reverse resistance MOSFET device, which has a structure with larger forward and reverse symmetrical voltage resistance and smaller forward conduction voltage drop.
Drawings
FIG. 1 is a schematic diagram of a conventional trench-type silicon carbide MOSFET half-cell structure;
FIG. 2 is a schematic diagram of a half-cell structure according to embodiment 1 of the present invention;
FIG. 3 is a schematic diagram of a half-cell structure according to embodiment 2 of the present invention;
FIG. 4 is a schematic view of a half-cell according to example 3 of the present invention;
FIG. 5 is a schematic view of a half-cell according to example 4 of the present invention;
FIG. 6 is a schematic view of a half-cell according to example 5 of the present invention;
FIG. 7 is a schematic view of a half-cell according to example 6 of the present invention;
FIG. 8 is a schematic view of a half-cell according to example 7 of the present invention;
FIG. 9 is a schematic view of a half-cell according to example 8 of the present invention;
fig. 10 is a schematic diagram of a half cell of a front structure of embodiment 9 of the present invention, the front structure being applicable to all devices of the present invention;
fig. 11 is a schematic diagram of a cell of a front structure of embodiment 10 of the present invention, which is applicable to all devices of the present invention;
fig. 12 is a schematic structural view after a second N-type silicon carbide buffer layer 21 is epitaxially formed on the N-type silicon carbide substrate 2 by an epitaxial process in the production process of embodiment 1 of the present invention;
fig. 13 is a schematic structural view after an N-type silicon carbide epitaxial layer 3 is epitaxially formed on the second N-type silicon carbide buffer layer 21 by an epitaxial process in the production process of embodiment 1 of the present invention;
fig. 14 is a schematic structural diagram after a trench is etched above the N-type silicon carbide epitaxial layer 3 by a photolithography and etching process in the preparation process of embodiment 1 of the present invention;
fig. 15 is a schematic structural diagram of a gate dielectric layer 5 grown on the surface of the trench by a thermal oxidation process in the preparation process of embodiment 1 of the present invention;
fig. 16 is a schematic structural diagram after a gate electrode 4 is formed in the gate dielectric layer 5 by deposition in the manufacturing process of embodiment 1 of the present invention;
fig. 17 is a schematic structural diagram after a first N-type silicon carbide buffer layer 10, a P-type silicon carbide base region 9, an N-type silicon carbide source region 6, and a P-type silicon carbide source region 7 are sequentially formed in an N-type epitaxial layer by photolithography and ion implantation in the manufacturing process of embodiment 1 of the present invention;
fig. 18 is a schematic structural view of the N-type silicon carbide substrate 2 removed by a grinding process after turning over the silicon wafer in the manufacturing process of embodiment 1 of the present invention;
fig. 19 is a schematic structural view after the P-type region 11 is formed in the second N-type silicon carbide buffer layer 21 by photolithography and ion implantation in the manufacturing process of embodiment 1 of the present invention;
fig. 20 is a schematic structural diagram of the manufacturing process of embodiment 1 of the present invention after the source metal 8 is formed on the surfaces of the N-type silicon carbide source region 6 and the P-type silicon carbide source region 7 by an evaporation or sputtering process and an etching process;
fig. 21 is a schematic structural diagram after a back drain metal 1 is formed through an evaporation or sputtering process and an etching process in the manufacturing process of embodiment 1 of the present invention, a schottky contact is formed between the drain metal 1 and the second N-type silicon carbide buffer layer 21, and an ohmic contact is formed between the drain metal and the P-type region 12.
In fig. 1 to 11, 1 is a back drain metal, 2 is an N-type silicon carbide substrate, 21 is a second N-type silicon carbide buffer layer, 3 is an N-type silicon carbide epitaxial layer, 31 is a P-type column, 32 is an N-type column, 4 is a gate electrode, 5 is a gate dielectric layer, 6 is an N-type silicon carbide source region, 61 is a first N-type source region, 62 is a second N-type source region, 7 is a P-type silicon carbide source region, 71 is a first P-type source region, 72 is a second P-type source region, 8 is a source metal, 9 is a P-type silicon carbide base region, 91 is a first P-type base region, 92 is a second P-type base region, 10 is a first N-type silicon carbide buffer layer, 11 is a P-type region, 12 is a schottky contact, 13 is an ohmic contact, 14 is a P-type buried layer, 15 is a shield gate dielectric layer, 16 is a shield gate dielectric layer, and 17 is a P-type floating void region.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1:
a trench-type SiC reverse-resistance MOSFET with a half-cell structure as shown in FIG. 2 comprises: a back drain metal 1, a second N-type silicon carbide buffer layer 21 and an N-type silicon carbide epitaxial layer 3 which are sequentially stacked from bottom to top,
a grid 4 and a first N-type silicon carbide buffer layer 10 are arranged above the N-type silicon carbide epitaxial layer 3, the first N-type silicon carbide buffer layer 10 is positioned on the right side of the grid 4, a P-type silicon carbide base region 9 is arranged above the first N-type silicon carbide buffer layer 10, and an N-type silicon carbide source region 6 and a P-type silicon carbide source region 7 are arranged above the P-type silicon carbide base region 9; the N-type silicon carbide source region 6 is connected with the P-type silicon carbide source region 7 left and right; a source metal 8 is arranged above the P-type silicon carbide source region 7, and the source metal 8 is respectively connected with the P-type silicon carbide source region 7 and part of the N-type silicon carbide source region 6 up and down; a gate dielectric layer 5 is arranged between the gate 4 and the N-type silicon carbide epitaxial layer 3, between the gate 4 and the first N-type silicon carbide buffer layer 10, between the gate 4 and the P-type silicon carbide base region 9, and between the gate 4 and the N-type silicon carbide source region 6;
the second N-type silicon carbide buffer layer 21 is provided with a disconnected P-type region 11, and an ohmic contact 13 is formed between the lower part of the P-type region 11 and the drain metal 1; the second N-type silicon carbide buffer layer 21 forms a schottky contact 12 with the drain metal 1.
Preferably, all silicon carbide materials are replaced by gallium nitride, gallium oxide, boron nitride, silicon materials.
The embodiment also provides a preparation method of the trench type silicon carbide reverse resistance MOSFET device, which comprises the following preparation steps:
step 1: as shown in fig. 12, a second N-type silicon carbide buffer layer 21 is formed on the surface of the N-type silicon carbide substrate 2 by an epitaxial process;
step 2: as shown in fig. 13, an epitaxial process is used to form an N-type silicon carbide epitaxial layer 3 on the surface of the second N-type silicon carbide buffer layer 21;
and step 3: as shown in fig. 14, a trench is etched above the N-type silicon carbide epitaxial layer 3 by using a photolithography and etching process;
and 4, step 4: as shown in fig. 15, a gate dielectric layer 5 is grown on the surface of the trench by a thermal oxidation process;
and 5: as shown in fig. 16, a gate 4 is deposited and formed in the gate dielectric layer 5 by a deposition process;
step 6: as shown in fig. 17, a first N-type silicon carbide buffer layer 10, a first P-type silicon carbide base region 9, a first N-type silicon carbide source region 6, and a first P-type silicon carbide source region 7 are sequentially formed in the N-type silicon carbide epitaxial layer 3 by using photolithography and ion implantation processes;
and 7: turning over the silicon wafer, and removing the N-type silicon carbide substrate 2 by a grinding process as shown in FIG. 18;
and 8: as shown in fig. 19, non-adjacent P-type regions 11 are formed in the second N-type silicon carbide buffer layer 21 by photolithography and ion implantation;
and step 9: as shown in fig. 20, the source metal 8 is prepared by an evaporation or sputtering process and an etching process;
step 10: as shown in fig. 21, an evaporation or sputtering process and an etching process are used to form the back drain metal 1, and a schottky contact is formed between the back drain metal 1 and the second N-type silicon carbide buffer layer 21, and an ohmic contact is formed between the back drain metal 1 and the P-type region 11.
Example 2:
a trench type sic reverse-resistance MOSFET, whose half-cell structure is shown in fig. 3, the difference between this embodiment and embodiment 1 is that: the second N-type silicon carbide buffer layer 21 is provided with non-adjacent P-type floating empty regions 17; the lower part of the P-type floating space region 17 is not contacted with the back drain metal 1, namely the P-type floating space region 17 is completely floated in the second N-type silicon carbide buffer layer 21; a schottky contact is formed between the second N-type silicon carbide buffer layer 21 and the back drain metal 1.
Preferably, all silicon carbide materials are replaced by gallium nitride, gallium oxide, boron nitride, silicon materials.
The embodiment also provides a preparation method of the trench type silicon carbide reverse resistance MOSFET device, which comprises the following preparation steps:
step 1: preparing a second N-type silicon carbide buffer layer 21 on the surface of the N-type silicon carbide substrate 2 by adopting an epitaxial process;
step 2: preparing an N-type silicon carbide epitaxial layer 3 on the surface of the second N-type silicon carbide buffer layer 21 by adopting an epitaxial process;
and step 3: etching a groove above the N-type silicon carbide epitaxial layer 3 by adopting photoetching and etching processes;
and 4, step 4: growing a gate dielectric layer 5 on the surface of the trench by adopting a thermal oxidation process;
and 5: depositing a gate 4 in the gate dielectric layer 5 by adopting a deposition process;
step 6: sequentially forming a first N-type silicon carbide buffer layer 10, a first P-type silicon carbide base region 9, a first N-type silicon carbide source region 6 and a first P-type silicon carbide source region 7 in the N-type silicon carbide epitaxial layer 3 by adopting photoetching and ion implantation processes;
and 7: turning over the silicon wafer, and removing the N-type silicon carbide substrate 2 through a grinding process;
and 8: preparing P-type floating empty regions 17 distributed at intervals in a second N-type silicon carbide buffer layer 21 by adopting photoetching and ion implantation processes;
and step 9: preparing a source metal 8 by adopting an evaporation or sputtering process and an etching process; step 10: the back drain metal 1 is prepared by an evaporation or sputtering process and an etching process, and a schottky contact is formed between the back drain metal 1 and the second N-type silicon carbide buffer layer 21.
Example 3:
the half-cell structure of a derivative structure of example 1 is shown in fig. 4, and this example is different from example 1 in that: and a P-type buried layer 14 is arranged at the bottom of the gate dielectric layer 5. The specific principle is as follows: because the silicon carbide has a higher critical breakdown electric field compared with silicon, the higher critical breakdown electric field causes that the electric field in the gate dielectric layer is far larger than the electric field in the gate dielectric layer of the silicon-based MOSFET when the silicon carbide MOSFET device breaks down, thereby reducing the reliability of the gate dielectric layer. The P-type buried layer 14 introduced in this embodiment can effectively reduce the electric field in the gate dielectric layer at the corner of the bottom of the trench, and improve the forward voltage withstanding capability.
Example 4:
a derivative structure of example 1, the half-cell structure of which is shown in fig. 5, the difference between this example and example 3 is: the transistor also comprises a shielding grid 15 arranged below the grid dielectric layer 5, the shielding grid 15 is in short circuit with the source metal 8, shielding grid dielectric layers 16 are arranged below and on the right side of the shielding grid 15, and a P-type buried layer 14 is arranged below the shielding grid dielectric layer 16.
The specific principle is as follows: the trench gate MOSFET can significantly increase the current density, but also brings about an increase in gate-drain capacitance, increasing the power loss at turn-off. The magnitude of the gate-drain capacitance is directly related to the effective overlap area between the gate region and the drain region. The shielding gate 15 introduced in the present embodiment effectively reduces the effective overlapping area between the gate region and the drain region, thereby reducing the gate-drain capacitance. In addition, the thickness of the shielding gate dielectric layer 16 is larger than that of the gate oxide layer, so that the forward voltage resistance of the device is improved.
Example 5:
a derivative structure of example 1, a half-cell structure of which is shown in fig. 6, is modified from example 4 by removing the P-type buried layer 14 and replacing the N-type silicon carbide epitaxial layer 3 with a P column 31 and an N column 32, and the rest of the structure is the same as example 4.
In the embodiment, a super junction MOSFET structure is formed by introducing the P column 31 and the N column 32, when the charges of the two are balanced, the whole drift region is approximately neutral in external non-conductivity, and the concentration of the drift region and the withstand voltage are relatively independent. The embodiment can ensure that the conduction voltage drop of the device can be effectively reduced under the same voltage withstanding grade, and the performance of the device is improved.
Example 6:
fig. 7 shows a half-cell structure of a derivative structure of embodiment 2, in this embodiment, a P-type buried layer 14 is disposed at the bottom of the gate dielectric layer 5 of embodiment 2.
The specific principle is as follows: because the silicon carbide has a higher critical breakdown electric field compared with silicon, the higher critical breakdown electric field causes that the electric field in the gate dielectric layer is far larger than the electric field in the gate dielectric layer of the silicon-based MOSFET when the silicon carbide MOSFET device breaks down, thereby reducing the reliability of the gate dielectric layer. The P-type buried layer 14 introduced in this embodiment can effectively reduce the electric field in the gate dielectric layer at the corner of the bottom of the trench, and improve the forward voltage withstanding capability.
Example 7:
a derived structure of embodiment 2 has a half-cell structure as shown in fig. 8, which is an improvement on the basis of embodiment 6, and further includes a shielding gate 15 disposed below the gate dielectric layer 5, the shielding gate 15 is shorted with the source metal 8, and shielding gate dielectric layers 16 are disposed below and on the right side of the shielding gate 15. And a P-type buried layer 14 is arranged below the shielding gate dielectric layer 16.
The specific principle is as follows: the trench gate MOSFET can significantly increase the current density, but also brings about an increase in gate-drain capacitance, increasing the power loss at turn-off. The magnitude of the gate-drain capacitance is directly related to the effective overlap area between the gate region and the drain region. The shielding gate 15 introduced in the present embodiment effectively reduces the effective overlapping area between the gate region and the drain region, thereby reducing the gate-drain capacitance. In addition, the thickness of the shielding gate dielectric layer 16 is larger than that of the gate oxide layer, so that the forward voltage resistance of the device is improved.
Example 8:
a derivative structure of embodiment 2, a half-cell structure of which is shown in fig. 9, is an improvement on embodiment 7, in which the P-type buried layer 14 is removed, and the N-type epitaxial layer 3 is replaced by a P column 31 and an N column 32.
In the embodiment, the super junction MOSFET structure is formed by introducing the P column 31 and the N column 32, when the two are in charge balance, the whole drift region exhibits no electricity to the outside and can be approximately neutral, so that the concentration of the drift region and the withstand voltage are relatively independent. The embodiment can ensure that the conduction voltage drop of the device can be effectively reduced under the same voltage withstanding grade, and the performance of the device is improved.
Example 9
Referring to fig. 10, the present embodiment provides a schematic structural diagram of a half-cell, which includes a back drain metal 1, a second N-type silicon carbide buffer layer 21, and an N-type silicon carbide epitaxial layer 3 stacked in sequence from bottom to top,
a first N-type silicon carbide buffer layer 10 is arranged above the N-type silicon carbide epitaxial layer 3, a gate dielectric layer 5 is arranged above the first N-type silicon carbide buffer layer 10, a gate 4 is arranged inside the gate dielectric layer 5, a first P-type silicon carbide base region 9 is arranged on the right side of the gate dielectric layer 5, the left side of the first P-type silicon carbide base region 9 is in contact with the gate dielectric layer 5, the left upper surface of the first P-type silicon carbide base region is in contact with a first N-type silicon carbide source region 6, the right upper surface of the first P-type silicon carbide base region is in contact with a first P-type silicon carbide source region 7, the lower part of the first P-type silicon carbide base region is in contact with the first N-type silicon carbide buffer layer 10, and source metal 8 is arranged above the first P-type silicon carbide source region 7; the source metal 8 covers the upper and right surfaces of the first N-type source region 6,
the second N-type silicon carbide buffer layer 21 is provided with unconnected P-type regions 11; ohmic contact is formed between the lower part of the P-type region 11 and the back drain metal 1; a schottky contact is formed between the second N-type silicon carbide buffer layer 21 and the back drain metal 1.
The front structure of the half cell is suitable for the device structure of any one of embodiments 1 to 8.
Example 10
As shown in fig. 11, the present embodiment provides a schematic structural diagram of a cell;
the cellular structure comprises a back drain metal 1, a second N-type silicon carbide buffer layer 21 and an N-type silicon carbide epitaxial layer 3 which are sequentially stacked from bottom to top,
a first N-type silicon carbide buffer layer 10 is arranged above the N-type silicon carbide epitaxial layer 3, a grid 4 is arranged in the middle of the upper portion of the first N-type silicon carbide buffer layer 10, a second P-type source region 71 is arranged on the left portion of the upper portion of the first N-type silicon carbide buffer layer 10, a second N-type source region 61 and a second P-type base region 91 are arranged on the right side of the second P-type source region 71, the second N-type source region 61 and the second P-type base region 91 are connected in an up-and-down mode, a third P-type source region 72 is arranged on the right side of the grid 4, the third P-type source region 72 extends to the middle of the grid 4 leftwards, a third N-type source region 62 and a third P-type base region 92 are arranged on the right side of the third P-type source region 72, the third N-type source region 62 and the third P-type base region 92 are connected in an up-and-down mode, the grid 4 and the second N-type source region 61, the grid 4 and the second P-type base region 91, the grid 4 and the first N-type silicon carbide buffer layer 10 are isolated by a grid 5;
the second N-type silicon carbide buffer layer 21 is provided with unconnected P-type regions 11; ohmic contact is formed between the lower part of the P-type region 11 and the back drain metal 1; a schottky contact is formed between the second N-type silicon carbide buffer layer 21 and the back drain metal 1.
The front structure of the cell is suitable for any one of the device structures of embodiments 1 to 8.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A trench-type silicon carbide reverse-resistance MOSFET, the half cell of which comprises:
the drain electrode structure comprises a back drain electrode metal (1), a second N-type silicon carbide buffer layer (21) and an N-type silicon carbide epitaxial layer (3), wherein the back drain electrode metal, the second N-type silicon carbide buffer layer (21) and the N-type silicon carbide epitaxial layer (3) are sequentially stacked from bottom to top, a grid electrode (4) and a first N-type silicon carbide buffer layer (10) are arranged above the N-type silicon carbide epitaxial layer (3), the first N-type silicon carbide buffer layer (10) is located on the right side of the grid electrode (4), a P-type silicon carbide base region (9) is arranged above the first N-type silicon carbide buffer layer (10), and an N-type silicon carbide source region (6) and a P-type silicon carbide source region (7) are arranged above the P-type silicon carbide base region (9); the N-type silicon carbide source region (6) is connected with the P-type silicon carbide source region (7) left and right; a source metal (8) is arranged above the P-type silicon carbide source region (7), and the source metal (8) is respectively connected with the P-type silicon carbide source region (7) and part of the N-type silicon carbide source region (6) up and down; a gate dielectric layer (5) is arranged between the gate (4) and the N-type silicon carbide epitaxial layer (3), between the gate (4) and the first N-type silicon carbide buffer layer (10), between the gate (4) and the P-type silicon carbide base region (9), and between the gate (4) and the N-type silicon carbide source region (6);
the method is characterized in that: the second N-type silicon carbide buffer layer (21) is provided with a disconnected P-type region (11), and an ohmic contact (13) is formed between the lower part of the P-type region (11) and the drain metal (1); a Schottky contact (12) is formed between the second N-type silicon carbide buffer layer (21) and the drain metal (1).
2. A trench-type silicon carbide reverse-resistance MOSFET, the half cell of which comprises:
a back drain metal (1), a second N-type silicon carbide buffer layer (21) and an N-type silicon carbide epitaxial layer (3) which are sequentially stacked from bottom to top,
a grid electrode (4) and a first N-type silicon carbide buffer layer (10) are arranged above the N-type silicon carbide epitaxial layer (3), the first N-type silicon carbide buffer layer (10) is positioned on the right side of the grid electrode (4), a P-type silicon carbide base region (9) is arranged above the first N-type silicon carbide buffer layer (10), and an N-type silicon carbide source region (6) and a P-type silicon carbide source region (7) are arranged above the P-type silicon carbide base region (9); the N-type silicon carbide source region (6) is connected with the P-type silicon carbide source region (7) left and right; a source metal (8) is arranged above the P-type silicon carbide source region (7), and the source metal (8) is respectively connected with the P-type silicon carbide source region (7) and part of the N-type silicon carbide source region (6) up and down; a gate dielectric layer 5 is arranged between the gate (4) and the N-type silicon carbide epitaxial layer (3), between the gate (4) and the first N-type silicon carbide buffer layer (10), between the gate (4) and the P-type silicon carbide base region (9), and between the gate (4) and the N-type silicon carbide source region (6);
the method is characterized in that: the second N-type silicon carbide buffer layer (21) is provided with unconnected P-type floating zones (17); the lower part of the P-type floating space region (17) is not contacted with the back drain metal (1), namely the P-type floating space region (17) is completely floated in the second N-type silicon carbide buffer layer (21); a Schottky contact is formed between the second N-type silicon carbide buffer layer (21) and the back drain metal (1).
3. The trench type silicon carbide reverse-blocking MOSFET device as set forth in any one of claims 1 or 2, wherein: and a P-type buried layer (14) is arranged at the bottom of the gate dielectric layer (5).
4. The trench type silicon carbide reverse-blocking MOSFET device as set forth in any one of claims 1 or 2, wherein: the grid-type semiconductor device is characterized by further comprising a shielding grid (15) arranged below the grid dielectric layer (5), wherein the shielding grid (15) is in short circuit with the source metal (8), and shielding grid dielectric layers (16) are arranged below and on the right side of the shielding grid (15).
5. The trench type silicon carbide reverse-blocking MOSFET device as claimed in claim 1 or 2, wherein: the N-type silicon carbide epitaxial layer (3) is replaced by a P column (31) and an N column (32).
6. The trench type silicon carbide reverse-blocking MOSFET device as set forth in any one of claims 1 or 2, wherein: all silicon carbide materials are replaced by gallium nitride, gallium oxide, boron nitride and silicon materials.
7. The trench type silicon carbide reverse-blocking MOSFET device as set forth in any one of claims 1 or 2, wherein:
the half-cell structure on the front side comprises a back drain metal (1), a second N-type silicon carbide buffer layer (21) and an N-type silicon carbide epitaxial layer (3) which are sequentially stacked from bottom to top,
a first N-type silicon carbide buffer layer (10) is arranged above the N-type silicon carbide epitaxial layer (3), a gate dielectric layer (5) is arranged above the first N-type silicon carbide buffer layer (10), a gate electrode (4) is arranged inside the gate dielectric layer (5), a first P-type silicon carbide base region (9) is arranged on the right side of the gate dielectric layer (5), the left side of the first P-type silicon carbide base region (9) is contacted with the gate dielectric layer (5), the upper left surface is contacted with a first N-type silicon carbide source region (6), the upper right surface is contacted with a first P-type silicon carbide source region (7), the lower part is contacted with the first N-type silicon carbide buffer layer (10), and source electrode metal (8) is arranged above the first P-type silicon carbide source region (7); the source metal (8) covers the upper surface and the right surface of the first N-type source region (6).
8. The trench type silicon carbide reverse-blocking MOSFET device as set forth in any one of claims 1 or 2, wherein:
the half-cell structure on the front side comprises a back drain metal (1), a second N-type silicon carbide buffer layer (21) and an N-type silicon carbide epitaxial layer (3) which are sequentially stacked from bottom to top,
a first N-type silicon carbide buffer layer (10) is arranged above the N-type silicon carbide epitaxial layer (3), a grid electrode (4) is arranged in the middle of the upper portion of the first N-type silicon carbide buffer layer (10), a second P-type source region (71) is arranged on the left portion of the upper portion of the first N-type silicon carbide buffer layer (10), a second N-type source region (61) and a second P-type base region (91) are arranged on the right side of the second P-type source region (71), the second N-type source region (61) and the second P-type base region (91) are connected up and down, a third P-type source region (72) is arranged on the right side of the grid electrode (4), the third P-type source region (72) extends to the middle of the grid electrode (4) leftwards, a third N-type source region (62) and a third P-type base region (92) are arranged on the right side of the third P-type source region (72), the third N-type source region (62) and the third P-type base region (92) are connected up and down, the grid electrode (4) and the second N-type base region (61) and the second P-type base region (91) are arranged on the right side, and between the grid electrode (4), The gate (4) and the first N-type silicon carbide buffer layer (10) are isolated from each other, and the gate (4) and the third P-type source region (72) are isolated from each other through the gate dielectric layer (5).
9. The method for preparing the trench type silicon carbide reverse resistance MOSFET device as claimed in claim 1, characterized by comprising the following steps:
step 1: preparing a second N-type silicon carbide buffer layer (21) on the surface of the N-type silicon carbide substrate (2) by adopting an epitaxial process;
step 2: preparing an N-type silicon carbide epitaxial layer (3) on the surface of the second N-type silicon carbide buffer layer (21) by adopting an epitaxial process;
and step 3: etching a groove above the N-type silicon carbide epitaxial layer (3) by adopting photoetching and etching processes;
and 4, step 4: growing a gate dielectric layer (5) on the surface of the trench by adopting a thermal oxidation process;
and 5: depositing a grid electrode (4) in the grid dielectric layer (5) by adopting a deposition process;
step 6: sequentially forming a first N-type silicon carbide buffer layer (10), a P-type silicon carbide base region (9), an N-type silicon carbide source region (6) and a P-type silicon carbide source region (7) in the N-type silicon carbide epitaxial layer (3) by adopting photoetching and ion implantation processes;
and 7: turning over the silicon wafer, and removing the N-type silicon carbide substrate (2) by adopting a grinding process;
and 8: manufacturing nonadjacent P-type regions (11) in the second N-type silicon carbide buffer layer (21) by adopting photoetching and ion implantation processes;
and step 9: preparing source metal (8) by adopting an evaporation or sputtering process and an etching process;
step 10: and preparing the back drain metal (1) by adopting an evaporation or sputtering process and an etching process, forming Schottky contact between the back drain metal (1) and the second N-type silicon carbide buffer layer (21), and forming ohmic contact between the back drain metal (1) and the P-type region (11).
10. The method for preparing the trench type silicon carbide reverse resistance MOSFET device as claimed in claim 2, characterized by comprising the following steps:
step 1: preparing a second N-type silicon carbide buffer layer (21) on the surface of the N-type silicon carbide substrate (2) by adopting an epitaxial process;
step 2: preparing an N-type silicon carbide epitaxial layer (3) on the surface of the second N-type silicon carbide buffer layer (21) by adopting an epitaxial process;
and step 3: etching a groove above the N-type silicon carbide epitaxial layer (3) by adopting photoetching and etching processes;
and 4, step 4: growing a thin gate dielectric layer (5) on the surface of the groove by adopting a thermal oxidation process;
and 5: depositing a grid electrode (4) in the grid dielectric layer (5) by adopting a deposition process;
step 6: sequentially forming a first N-type silicon carbide buffer layer (10), a P-type silicon carbide base region (9), an N-type silicon carbide source region (6) and a P-type silicon carbide source region (7) in the N-type epitaxial layer by adopting photoetching and ion implantation processes;
and 7: turning over the silicon wafer, and removing the N-type silicon carbide substrate (2) by adopting a grinding process;
and 8: preparing P-type floating empty regions (17) distributed at intervals in the second N-type silicon carbide buffer layer (21) by adopting photoetching and ion implantation processes;
and step 9: preparing source metal (8) by adopting an evaporation or sputtering process and an etching process;
step 10: and preparing the back drain metal (1) by adopting an evaporation or sputtering process and an etching process, and forming Schottky contact between the back drain metal (1) and the second N-type silicon carbide buffer layer (21).
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| CN102544100A (en) * | 2010-12-14 | 2012-07-04 | 万国半导体股份有限公司 | Self aligned trench MOSFET with integrated diode |
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| CN102544100A (en) * | 2010-12-14 | 2012-07-04 | 万国半导体股份有限公司 | Self aligned trench MOSFET with integrated diode |
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Application publication date: 20210420 Assignee: Zhuhai Gree Electronic Components Co.,Ltd. Assignor: University of Electronic Science and Technology of China Contract record no.: X2023980042422 Denomination of invention: Grooved silicon carbide reverse resistance MOSFET device and its preparation method Granted publication date: 20220517 License type: Common License Record date: 20230928 |