CN108807504B

CN108807504B - Silicon carbide MOSFET device and method of manufacturing the same

Info

Publication number: CN108807504B
Application number: CN201810990494.0A
Authority: CN
Inventors: 张金平; 邹华; 罗君轶; 赵阳; 李泽宏; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: Hangzhou Xinmai Semiconductor Technology Co ltd
Priority date: 2018-08-28
Filing date: 2018-08-28
Publication date: 2022-01-25
Anticipated expiration: 2038-08-28
Also published as: CN108807504A

Abstract

The invention provides a silicon carbide MOSFET device and a manufacturing method thereof.A silicon carbide deep P injection is carried out in a designated area, metal or polysilicon is etched and deposited through a groove above a silicon carbide deep P doping area, the deposited metal or polysilicon is directly contacted with silicon carbide N-epitaxy to form Schottky contact or Si/SiC heterojunction contact with rectification characteristic.

Description

Silicon carbide MOSFET device and method of manufacturing the same

Technical Field

The invention belongs to the power semiconductor technology, and particularly relates to a Metal Oxide Semiconductor Field Effect (MOSFET) device structure and a manufacturing method thereof.

Background

According to statistics, more than 90% of electricity consumption in the world is controlled by a power device. The power device and the module thereof provide an efficient way for realizing the conversion of various electric energy forms, and are widely applied to the fields of national defense construction, transportation, industrial production, medical treatment and health care and the like. Since the first power device application in the 50 s of the last century, energy sources were more efficiently converted and used with each generation of power devices. The history of the power semiconductor device, namely the power semiconductor device shows a new history.

The traditional power device and module are mainly based on silicon-based power devices, mainly comprising thyristors, power PIN devices, power bipolar junction devices, power MOSFETs, insulated gate field effect transistors and the like, and are widely applied in the full power range, and the leading market of the power semiconductor device is occupied by the long-standing history and mature design technology and process technology. However, as power semiconductor technology has matured, the characteristics of silicon-based power devices have gradually approached their theoretical limits. Researchers strive to find better parameters in a narrow optimization space of a silicon-based power device, and meanwhile, the researchers also pay attention to excellent material characteristics of third-generation wide-bandgap semiconductor materials such as SiC and GaN in the fields of high power, high frequency, high temperature resistance, radiation resistance and the like.

Silicon carbide MOSFET devices are the next generation of semiconductor devices fabricated with the wide bandgap semiconductor material silicon carbide. The silicon carbide material has many attractive properties, such as critical breakdown electric field strength 10 times that of the silicon material, high thermal conductivity, large forbidden band width, high electron saturation drift velocity and the like, so that the SiC material becomes a research hotspot of international power semiconductor devices, and the silicon carbide devices are highly expected in high-power application occasions, such as high-speed railways, hybrid electric vehicles, intelligent high-voltage direct-current transmission and the like. Meanwhile, the silicon carbide power device has a remarkable effect of reducing power loss, so that the silicon carbide power device is known as a green energy device driving 'new energy revolution'. However, the on-state current density of silicon carbide MOSFETs is greatly limited by the low MOS channel mobility due to non-idealities in the MOS channel. Thus, silicon carbide UMOSFETs having higher channel densities, and thus greater on-state current densities, have received extensive attention and research. Although the silicon carbide UMOSFET has lower on-state resistance and more compact cell layout, the problem of too high electric field of the bottom gate oxide layer brings reliability problem to the long-term use of the silicon carbide UMOSFET, and the robustness of the device is poor. A conventional silicon carbide UMOSFET structure is shown in fig. 1.

Silicon carbide MOSFET devices are often required to be used in applications in anti-parallel with a diode. There are two ways to achieve this. One is to directly makePbase and N are used in the device^-A parasitic diode formed by the region. The parasitic silicon carbide diode has large conduction voltage drop (the conduction voltage drop of a silicon carbide PN junction is about 3.1V), and high power loss is caused by poor reverse recovery characteristics (a large amount of excess carriers are injected by drift region conductance modulation during forward conduction), which is contrary to the application concept of emphasizing green environmental protection at present; meanwhile, the low working efficiency caused by low working speed is very unfavorable for the application of silicon carbide MOSFET devices in inverter circuits, chopper circuits and the like; the other is by using the device in anti-parallel with an external diode. However, this method causes an increase in production cost and a decrease in reliability after metal wiring, so that the popularization of the silicon carbide MOSFET device in practical application is greatly hindered.

Disclosure of Invention

Aiming at the problems, the invention provides a silicon carbide MOSFET device and a manufacturing method thereof, which can solve the problems of poor robustness, high power loss, low working efficiency, high production cost and the like of the silicon carbide MOSFET device in the application of an inverter circuit, a chopper circuit and the like due to overhigh gate dielectric electric field. Specifically, the invention is based on the traditional silicon carbide UMOSFET structure, silicon carbide deep P injection is carried out in a designated area, and metal or polysilicon is etched and deposited above a silicon carbide deep P doped area through a groove. The deposited metal or polysilicon is in direct contact with the silicon carbide N-epitaxy to form Schottky contact with rectification characteristic or Si/SiC heterojunction contact, and the Schottky barrier height can be regulated and controlled by changing the metal material, process control and the concentration of the silicon carbide N-epitaxy so as to form Schottky contact with lower on-state voltage drop (Von). Generally, the contact Von is in the range of 0.8V to 2V. Thereby realizing the in-vivo integration of the Schottky diode with the forward working performance superior to that of the parasitic diode. Because the diode is a multi-sub device, the diode has faster reverse recovery time, lower reverse recovery loss and better reverse recovery reliability due to the fact that minority carriers do not exist in the reverse recovery process, and has higher reverse recovery performance compared with a parasitic diode. Compared with a mode of anti-parallel connection of a diode in vitro, the improvement obviously reduces the volume of a power electronic system and reduces the packaging cost. Meanwhile, because the metal lead wire between the diode and the diode is not arranged, the parasitic effect caused by the metal lead wire is avoided, and the application reliability of the system is improved. Meanwhile, compared with a mode of monolithically integrating diodes in a plurality of bodies, the structure has a more compact cellular area. Meanwhile, the double deep silicon carbide P-type doped region designed by the invention is beneficial to improving the voltage withstanding level of the device and reducing the electric field of the gate dielectric layer of the device, thereby greatly improving the basic performance and long-term application reliability of the traditional UMOSFET device. Meanwhile, due to the fact that the voltage resistance of the device is improved by the double-deep silicon carbide P-type doped region, doping of the JFET region can be effectively improved, and therefore the device has low specific conductance Ron.sp. In addition, the integrated multi-sub rectifying device has the characteristic of low leakage. Therefore, the structure of the invention has good performance advantages.

In order to achieve the purpose, the technical scheme of the invention is as follows:

1. a silicon carbide MOSFET device comprises a metal drain electrode 1 and silicon carbide N arranged from bottom to top in sequence⁺Substrate 2 and silicon carbide N^-An epitaxial layer 3; the silicon carbide N^-A first source groove is formed in the upper left of the epitaxial layer 3, and a silicon carbide P + doped region 5 and a silicon carbide P-type doped region 4 are formed below the first source groove from top to bottom; the silicon carbide N^-A second source groove is formed in the right upper portion of the epitaxial layer 3, and a silicon carbide P + doped region 5 and a silicon carbide P-type doped region 4 are formed below the second source groove from top to bottom; the first source groove and the second source groove are both filled with Schottky contact metal 14; a gate groove is arranged above the silicon carbide N-epitaxial layer 3, the depth of the gate groove is shallower than that of the two source grooves, a gate structure is arranged inside and on the surface of the gate groove, the gate structure comprises a gate dielectric layer 10, a polysilicon gate 11 and a gate 12 from bottom to top, the polysilicon gate 11 is isolated from the silicon carbide body by the gate dielectric layer 10, and the upper part of the polysilicon gate 11 is led out through the gate 12; the polysilicon gate 11 is arranged in the gate groove, and the gate 12 is arranged on the surface of the gate groove; a first mesa structure and a second mesa structure are respectively arranged between the source trench and the gate trench, and each of the first mesa structure and the second mesa structure is composed of a silicon carbide Pbase region 7, a silicon carbide P + contact region 8 and a silicon carbide N + source region 9, wherein the silicon carbide P + contact region 8 and the silicon carbide N + source region 89 is positioned above the silicon carbide Pbase area 7, a silicon carbide P + contact area 8 is contacted with the source groove, a silicon carbide N + source area 9 is contacted with the gate groove, and the silicon carbide Pbase area 7 is simultaneously contacted with the source groove and the gate groove, and the depth of the silicon carbide Pbase area is shallower than that of the source groove and the gate groove; the source groove metal is directly contacted with the silicon carbide N-epitaxial layer 3 at the bottom of the side wall of the source groove to form Schottky contact with rectification characteristics; the device surface is covered by a layer of source metal 6, and the source metal 6 and the gate 12 are isolated from each other by borophosphosilicate glass BPSG 13.

Preferably, the silicon carbide material is replaced by a semiconductor material of Si, Ge, GaAs, GaN, diamond, silicon germanium, gallium oxide.

Preferably, the schottky contact metal 14 area is replaced with polysilicon 15.

Preferably, a split-gate polysilicon 16 is provided beneath the gate structure.

Preferably, the bottom of the schottky contact metal 14 or the polysilicon 15 extends to the middle of the silicon carbide P-type doped region 4 and the silicon carbide P + doped region 5, and contacts the silicon carbide N-epitaxial layer 3. As shown in fig. 10.

Preferably, a dielectric layer 17 is disposed below the schottky contact metal 14.

Preferably, the source trench is provided with discontinuous trenches below in the Z direction, the depth of the trenches is less than or equal to the depth of the silicon carbide P-type doped region 4, wherein the trenches are internally deposited with Schottky contact metal 14 or polysilicon 15, and the bottom of the trenches is provided with a silicon carbide N-epitaxial layer 3.

Further, as shown in fig. 4, the split-gate structure comprises split-gate polysilicon 16 and a dielectric layer 17 surrounding the split-gate polysilicon 16;

further, the silicon carbide P-type doped region 4 may be subjected to one-time diffusion to form a wider silicon carbide P-type doped region 4;

further, the silicon carbide P-type doped region 4 and the silicon carbide P + doped region 5 may be dielectric layers 17;

further, the silicon carbide MOSFET device is not limited to silicon carbide and silicon materials, and other wide and narrow bandgap materials can be used.

2. In order to achieve the above object, the present invention further provides a method for manufacturing the silicon carbide MOSFET device, including the steps of:

step 1: selecting a silicon carbide wafer as a silicon carbide N + substrate 2 and a silicon carbide N-epitaxial layer region 3;

step 2: performing aluminum ion implantation through a high-energy ion implantation process to form a silicon carbide Pbase area 7, or forming the silicon carbide Pbase area 7 in an epitaxial mode, and then forming a device behind the silicon carbide Pbase area 7;

and 3, step 3: performing aluminum ion implantation by using a PSD mask through photoetching and ion implantation processes to form a silicon carbide P + contact region 8;

and 4, step 4: performing phosphorus ion implantation by using an NSD mask through the processes of photoetching, ion implantation and the like to form a silicon carbide N + source region 9;

and 5, step 5: etching a source groove with a specified size by using a Trench mask through a groove etching process;

and 6, step 6: carrying out aluminum ion implantation through photoetching and ion implantation processes to form a silicon carbide P-type doped region 4; in the step 5, a deeper source groove is formed through etching, and then a silicon carbide P-type doped region 4 is formed through epitaxy and etching processes;

and 7, step 7: carrying out aluminum ion implantation through the processes of photoetching and ion implantation to form a silicon carbide P + doped region 5;

and 8, step 8: depositing a layer of metal at the bottom of the source trench by deposition and etching processes to form Schottky contact metal 14, and removing redundant metal by etching;

step 9: etching a gate groove with a specified size by using a Trench mask through a groove etching process;

step 10: forming a gate dielectric layer 10 by a dry oxygen oxidation process;

and 11, step 11: depositing a layer of polycrystalline silicon in the gate trench by deposition and etching processes to form a polycrystalline silicon gate 11, and removing redundant polycrystalline silicon by etching;

step 12: forming a gate electrode 12 by deposition, photolithography and etching processes;

step 13: forming boron phosphorus silicon glass BPSG13 through deposition, photoetching and etching processes;

step 14: and forming a source metal 6 and a metal drain 1 by deposition, photoetching and etching processes respectively, and thus finishing the manufacturing of the device.

Furthermore, the gate trench can also be formed first, and after the gate structure is completed, the source trench is formed;

further, in step 9, a deeper gate trench may be formed, and the bottom and sidewalls of the trench may be oxidized. Depositing split-gate polysilicon 16 at the bottom of the trench, and forming a split-gate structure by depositing a dielectric layer 17, etching the dielectric layer 17 and depositing a polysilicon gate 11, as shown in FIG. 4;

further, in step 8, the deposited source trench schottky contact metal 14 may also be replaced with polysilicon 15 material;

further, after the silicon carbide P-type doped region 4 is formed in the step 6, a wider silicon carbide P-type doped region 4 can be formed through a high-temperature diffusion process;

further, when the source trench is formed in the 5 th step, the etching strength can be increased to form deeper trench etching. And replacing the

steps

6 and 7 as the following descriptions: and depositing and etching to form an oxide layer with a certain thickness at the bottom of the source trench. And forming a gate dielectric layer 10 with the surface height lower than that of the silicon carbide Pbase region 7 by an etching process.

Furthermore, after the source trench is formed in the 5 th step, etching may be added again to form a discontinuous trench at the bottom of the source trench. The depth of the groove for the second etching is equal to the depth of the silicon carbide P-type doped region 4 formed in the later period;

furthermore, after the source trench is formed in the 5 th step, etching may be added again to form a discontinuous trench at the bottom of the source trench. The depth of the groove for the second etching is smaller than the depth of the silicon carbide P-type doped region 4 formed in the later period;

further, after the source trench is formed in the 5 th step, a second etching process may be added to form a continuous trench at the bottom of the source trench, and the depth of the second etching process is equal to the depth of the silicon carbide P-type doped region 4 formed in the later stage.

3. The following inventive solution can also solve the problems mentioned in the "background art": specifically, the present invention is based on the conventional silicon carbide UMOSFET structure (as shown in fig. 1), and also by performing a silicon carbide deep P implant in a designated region, and etching and depositing metal or polysilicon over and between two silicon carbide deep P doped regions. The deposited metal or polysilicon is in direct contact with the silicon carbide N-epitaxy to form a schottky contact or a Si/SiC heterojunction contact with rectifying properties. Typically, the contact Von is in the range of 0.6V to 1.8V. Thereby realizing the Schottky diode body integration with the forward working performance superior to that of a parasitic diode. The schottky diode is a multi-sub device, and has faster reverse recovery time, lower reverse recovery loss and higher reverse recovery reliability due to the absence of minority carrier storage in the reverse recovery process, so that the schottky diode has higher reverse recovery performance compared with a parasitic diode. Compared with a mode of anti-parallel connection of a diode in vitro, the improvement obviously reduces the volume of a power electronic system and reduces the packaging cost. Meanwhile, because the metal lead wire between the diode and the diode is not arranged, the parasitic effect caused by the metal lead wire is avoided, and the application reliability of the system is improved. Meanwhile, compared with a mode of integrating diodes in a plurality of in-vivo single blocks, the structure of the invention has more compact cellular area. Similarly, the structure of the invention has great optimization effect on the basic performance of the device, including the improvement of voltage blocking capability, the reduction of device specific conductance, the reduction of multi-sub device electric leakage and the improvement of long-term application reliability of the device. Therefore, the structure of the invention has good electrical performance advantages.

To achieve the above object, the present invention further provides a second silicon carbide MOSFET device, which has the following structure:

comprises a metal drain electrode 1 and silicon carbide N which are arranged from bottom to top in sequence⁺Substrate 2 and silicon carbide N^-An epitaxial layer 3; the silicon carbide N^-The upper left of the epitaxial layer 3 is provided with a first grid structure, and the silicon carbide N^-The second grid structure is arranged at the upper right part of the epitaxial layer 3, and the first and second grid structuresEach including a gate 12, a polysilicon gate 11 and a gate dielectric layer 10, wherein the polysilicon gate 11 is surrounded by the gate dielectric layer 10, the upper part of the polysilicon gate is led out by the gate 12, and the silicon carbide N is^-A source groove is formed above the epitaxial layer 3, the source groove is deposited and filled with Schottky contact metal 14, the Schottky contact metal 14 is in direct contact with the silicon carbide N-epitaxial layer 3 to form Schottky contact, a first mesa structure and a second mesa structure are respectively arranged between the source groove and the gate structure, the first mesa structure and the second mesa structure are respectively formed by a silicon carbide Pbase region 7, a silicon carbide P + contact region 8 and a silicon carbide N + source region 9, wherein the silicon carbide P + contact region 8 and the silicon carbide N + source region 9 are positioned above the silicon carbide Pbase region 7, the silicon carbide P + contact region 8 is in contact with the source groove, the silicon carbide N + source region 9 is in contact with the gate structure, and the silicon carbide Pbase region 7 is in contact with the source groove and the gate structure at the same time and is shallower than the source groove and the gate structure; p-type doped regions are arranged on two sides below the Schottky contact metal 14 and below part of the silicon carbide Pbase region 7, the deeper part of the P-type doped region is a silicon carbide P-type doped region 4, and the shallower part of the P-type doped region is a silicon carbide P + doped region 5 with narrower width; the silicon carbide P + doped region 5 forms an ohmic contact with the schottky contact metal 14 and the device surface is covered by a layer of source metal 6, the source metal 6 being separated from the gate 12 by borophosphosilicate glass BPSG 13.

Preferably, the original schottky contact metal 14 is replaced with polysilicon 15.

Preferably, split-gate polysilicon 16 is provided under both gate structures.

Preferably, the bottom of the schottky contact metal 14 or the polysilicon 15 extends to the middle of the silicon carbide P-type doped region 4 and the silicon carbide P + doped region 5, and contacts the silicon carbide N-epitaxial layer 3.

Preferably, the schottky contact metal 14 is formed with the silicon carbide N under the silicon carbide Pbase region 7^-The epitaxial layer 3 is in direct contact, so that the epitaxial layer not only forms a rectifying contact with the silicon carbide N-epitaxial layer 3 at the bottom of the metal, but also forms a rectifying contact with the side wall of the bottom of the source trenchThe silicon carbide N-epi 3 contacts, forming rectifying contacts.

Preferably, the silicon carbide P-type doped region 4 and the silicon carbide P + doped region 5 are replaced by a dielectric layer 17.

Preferably, a polysilicon 15 region is arranged below a partial region of the bottom of the schottky contact metal 14, which is in contact with the silicon carbide N-epitaxial layer 3, and the region is in contact with the silicon carbide N-epitaxial layer 3 to form a Si/SiC heterojunction.

Preferably, the two sides below the source trench are provided with discontinuous trenches in the Z direction, the depth of the trenches is equal to or less than the depth of the silicon carbide P-type doped region 4, and the interiors of the trenches are also filled with the deposition of the Schottky contact metal 14. The bottom of the trench is a silicon carbide N-epitaxial layer 3.

Further, the bottom region of the gate structure has a split-gate structure, as shown in fig. 27. The split-gate structure comprises split-gate polycrystalline silicon 16 and a dielectric layer 17 surrounding the split-gate polycrystalline silicon 16;

further, the structure has a larger schottky contact metal 14 depth and width, so that it not only forms a rectifying contact with the silicon carbide N-epi 3 at the metal bottom, but also forms a rectifying contact with the silicon carbide N-epi 3 at the source trench bottom sidewall;

4. To achieve the above object, the present invention further provides a method for manufacturing a silicon carbide MOSFET device, comprising the steps of:

step 1: selecting a silicon carbide wafer as a silicon carbide N + substrate 2 and a silicon carbide N-epitaxial layer 3;

step 2: performing aluminum ion implantation through a high-energy ion implantation process to form a silicon carbide Pbase area 7, and forming the silicon carbide Pbase area 7 in the step or in an epitaxial mode;

and 4, step 4: performing phosphorus ion implantation by using an NSD mask through photoetching and ion implantation processes to form a silicon carbide N + source region 9;

and 6, step 6: performing aluminum ion implantation at a certain angle through the processes of photoetching, ion implantation and the like to form a silicon carbide P-type doped region 4;

and 7, step 7: performing aluminum ion implantation through the processes of photoetching, ion implantation and the like to form a silicon carbide P + doped region 5;

step 10: forming a gate dielectric layer 10 by a dry oxygen oxidation process;

step 14: forming a source metal 6 and a metal drain 1 by deposition, photoetching and etching processes respectively; thus, the device is completed.

further, in step 9, a deeper gate trench may be formed, and the bottom and sidewalls of the trench may be oxidized. Depositing split-gate polysilicon 16 at the bottom of the trench, and forming a split-gate structure by depositing a gate dielectric layer 10, etching the gate dielectric layer 10 and depositing a polysilicon gate 11, as shown in fig. 27;

furthermore, when the source trench is etched in the step 5, the etching depth and width can be increased, and simultaneously, when aluminum ions are injected in the

steps

6 and 7, the aluminum ions are injected in a vertical mode, so that Schottky contact is realized at the bottom of the source trench, and meanwhile, Schottky contact is formed on two side walls of the source trench.

steps

Further, after the source trench is formed in the 5 th step, the bottom of the source trench is etched for the second time, and before the 6 th step, the second trench is filled with the deposited polysilicon to form the polysilicon 15 region.

further, the gate trench may also be formed first, and after the gate structure is completed, the source trench is formed.

The following illustrates the principles of the invention:

silicon carbide MOSFET devices are often required to be used in applications in anti-parallel with a diode. If monolithic integration in vivo is not considered, there are two ways to achieve this. One is a parasitic silicon carbide PiN diode formed by directly using a silicon carbide Pbase region, a silicon carbide N-region and a silicon carbide N + substrate of a silicon carbide MOSFET device. The forward conduction voltage drop Von of the parasitic silicon carbide Pin is about 3.1V, and the application of the high forward conduction voltage drop under low-voltage power is extremely unfavorable, so that the on-state loss of the device is remarkably increased. Meanwhile, since the device belongs to a bipolar device, minority carriers are accumulated in an on state due to the conductance modulation effect. Although minority carrier accumulation can reduce the on-state voltage drop in the on state, for switching transients, especially off transients, the parasitic diode has very poor reverse recovery characteristics due to problems of increased off time, increased off loss, increased reverse peak current, and reduced off reliability caused by minority carrier storage. Therefore, for the anti-parallel diode, the basic requirements of low conduction voltage drop Von and fast recovery are required; the other is by using the device in anti-parallel with a diode external to the device. Although the method meets the basic requirements of low conduction voltage drop Von and quick recovery, the method causes the increase of production cost and the reduction of reliability after the increase of metal connecting wires due to the increase of the number of devices, the increase of a power system, the improvement of heat dissipation requirements and other factors, so that the selection of the external parallel diode is not optimal. This also encourages the formation of other approaches to implementing anti-parallel diodes. According to the invention, silicon carbide deep P injection is carried out in a designated area, and metal or polysilicon is etched and deposited above a silicon carbide deep P doped area through a groove. The deposited metal or polysilicon is in direct contact with the silicon carbide N-epi to form a schottky contact or a Si/SiC heterojunction contact with rectifying properties as shown in fig. 2. When the structure is in the blocking work of the MOSFET, the voltage-resistant part of the device is provided by the silicon carbide P-type doped region 4 and the silicon carbide N-epitaxial layer 3, so that the improvement of the device has an optimization effect on the improvement of the voltage-resistant capability of the traditional structure; due to the shielding effect of the silicon carbide P-type doped region 4, the electric leakage of Schottky contact or heterojunction contact is greatly reduced, and the electric field of a gate oxide layer of the device is reduced, so that the long-term application reliability of the device is improved. When the device works in the forward direction of the MOSFET, the doping of the JFET area of the device can be made higher due to the improvement of the avalanche breakdown voltage resistance of the device and the protection of the gate dielectric layer by the silicon carbide P-type doped area, so that the specific conductance value of the MOSFET is reduced, and the conduction performance of the device is optimized; the structure of the invention has great optimization effect on the third quadrant operation of the device. The barrier height mentioned above can be adjusted by adjusting the metal species, process conditions, and silicon carbide N-epitaxy to form schottky contacts with a Von of about 0.6V to 2V; meanwhile, due to the protection function of the silicon carbide P-type doped region, the Schottky contact interface has small electric leakage. Silicon carbide PiN diodes are generally considered to have a Von of around 3.1V. The embedding of the Schottky barrier diode greatly reduces the on-state loss of the device under the third quadrant operation, and meanwhile, because the Schottky barrier diode belongs to a multi-sub device, the Schottky barrier diode has shorter reverse recovery time, lower turn-off loss, lower reverse recovery peak current and better reliability of the device in the reverse recovery process because of the absence of minority carrier storage effect; in addition, because the Schottky barrier diode integrated in the body does not increase the area of the device, the device has compact cellular arrangement, thereby having larger on-state current. Since the gate-drain capacitance has a great influence on the switching speed of the device, in order to further increase the switching speed of the device, the invention also provides a structure, as shown in fig. 4 and 26. The structure reduces the dead area between the device gate structure and the silicon carbide N-epitaxy, namely reduces the gate leakage charge, thereby reducing the gate leakage capacitance of the device and having great effect on improving the switching speed of the device;

the schottky contact metal 14 may also be replaced with polysilicon 15. And the polycrystalline silicon 15 and the silicon carbide N-epitaxy 3 contact with the side wall of the bottom of the source trench to form a Si/SiC heterojunction. The heterojunction is reported to have rectifying characteristics in relevant documents. Its forward conduction voltage drop Von is about 1.1V. Also with respect to the parasitic diode, has a greatly improved effect on the third quadrant operation of the device. Meanwhile, the diode is also a multi-sub device, and has excellent reverse recovery performance similar to a Schottky diode; in order to improve the withstand voltage of the device, the invention also increases the transverse size of the silicon carbide P-type doped region 4 in the device structure. The increase of the part is beneficial to the improvement of the withstand voltage of the device and the improvement of the reliability of the gate dielectric layer 10; in order to further improve the electrical characteristics of the device in the diode operating mode, the invention also provides another new structure, as shown in fig. 8 and fig. 9. The second etching is carried out at the bottom of the source groove, and the deposition of polysilicon is carried out in the groove. While the source trenches are still deposited with schottky contact metal. The improvement increases the rectifying contact area by about 50% from the increase of the rectifying contact area, thereby increasing the conducting junction area in the diode application. The leakage performance of the Si/SiC heterojunction is far better than that of a Schottky contact, and meanwhile, the P-type silicon has a good shielding effect on the Schottky junction surface, so that the leakage of the Schottky junction surface is further reduced. In order to further improve the working performance of the third quadrant of the device, the invention also provides another optimized structure. Namely, a discontinuous groove structure is formed inside the silicon carbide P-type doped region 4 by continuously etching the bottom of the source groove. The trench structure is also filled with a schottky contact metal 14 or polysilicon 15 deposition. The depth of the secondary groove etching is equal to or less than the depth of the silicon carbide P-type doped region 4 so as to increase the contact area of the Schottky/heterojunction and further optimize the working performance of the third quadrant of the device. The basic principle of the other optimization scheme proposed for the problems introduced in the background introduction is basically the same as that of the first invention scheme, and therefore, the description is omitted here.

In conclusion, the beneficial effects of the invention are as follows:

firstly, the structure of the invention realizes a multi-sub rectifying device, which comprises a Schottky barrier diode and a Si/SiC heterojunction embedded in a body, so that the device has better on-state performance and reverse recovery performance in a third quadrant working region compared with a parasitic diode in the device, and comprises shorter reverse recovery time, lower turn-off loss, lower reverse recovery peak current and better reliability of the device in a reverse recovery process. Meanwhile, the integrated multi-sub rectifier device has the characteristic of low electric leakage;

compared with the traditional silicon carbide UMOSFET, the structure of the invention has higher withstand voltage and lower specific conductance Ron.sp, and meanwhile, the highest electric field of the gate dielectric layer is reduced, so that the long-term application reliability of the device is greatly improved, and the device has good robustness;

compared with the mode of in-vitro anti-parallel connection of diodes, the structure of the invention reduces the interconnection number of metal leads, reduces parasitic inductance and improves the reliability of the device; the number of system components is reduced, the system volume is reduced, and the volume of a heat dissipation system is reduced; the packaging cost is reduced, so that the production cost is reduced;

fourthly, the structure of the invention has compact cellular arrangement, and the area of the invention is hardly increased compared with the traditional silicon carbide UMOSFET (SiC UMOSFET), so that the production cost of the device is further reduced;

fifthly, the invention optimizes the dynamic performance of the device and provides a split-gate structure. The structure obviously reduces the positive area of the gate-silicon carbide N-epitaxy, reduces the gate charge required in the starting process of the device, reduces the gate leakage capacitance of the device and improves the switching speed of the device;

sixth, the structure of the invention is compatible with the production process of the traditional silicon carbide UMOSFET device. The method has the advantages of simple process and easy realization.

Seventhly, the basic performance of the traditional silicon carbide UMOSFET is optimized, meanwhile, the working performance of the third quadrant of the device is optimized, and the better application performance of the diode is obtained.

Drawings

FIG. 1 is a schematic diagram of a conventional silicon carbide UMOSFET device cell structure;

fig. 2 is a schematic diagram of a basic cell structure of a silicon carbide double-trench MOSFET device provided in embodiment 1;

FIG. 3 is a schematic diagram of a basic cell structure of a SiC double-trench MOSFET device provided in embodiment 2;

fig. 4 is a schematic diagram of a basic cell structure of a silicon carbide double-trench MOSFET device provided in embodiment 3;

FIG. 5 is a schematic diagram of a basic cell structure of a SiC double trench MOSFET device provided in example 4;

FIG. 6 is a schematic diagram of a basic cell structure of a SiC double trench MOSFET device provided in example 5;

FIG. 7 is a Z-direction schematic view of the Region "Region A" of the structure of example 1;

FIG. 8 is a schematic diagram of a basic cell structure of a silicon carbide double trench MOSFET device provided in embodiment 6;

fig. 9 is a schematic diagram of a basic cell structure of a silicon carbide double-trench MOSFET device provided in embodiment 7;

FIG. 10 is a schematic diagram showing a basic cell structure of a silicon carbide double trench MOSFET device provided in example 8;

FIG. 11 is a schematic view of a silicon carbide substrate provided in example 9 of the present invention;

fig. 12 is a schematic view of a Pbase region 7 formed by an ion implantation process according to example 9 of the present invention;

fig. 13 is a schematic view of a silicon carbide P + contact region 8 formed by photolithography, ion implantation, or the like as provided in example 9 of the present invention;

fig. 14 is a schematic view of forming a silicon carbide N + source region 9 by performing a phosphorous ion implantation using an NSD mask through a photolithography process, an ion implantation process, and the like, according to embodiment 9 of the present invention;

fig. 15 is a schematic diagram of a source Trench etched to a specified size by using a Trench mask through a Trench etching process according to embodiment 9 of the present invention;

fig. 16 is a schematic view of forming a P-type doped region 4 of silicon carbide by performing aluminum ion implantation through photolithography, ion implantation, and the like according to embodiment 9 of the present invention;

fig. 17 is a schematic view of forming a P + doped silicon carbide region 5 by performing aluminum ion implantation through photolithography, ion implantation, or the like, according to embodiment 9 of the present invention;

fig. 18 is a schematic view of schottky contact metal 14 formed by depositing a layer of metal on the bottom of the source trench by a deposition and etching process according to embodiment 9 of the present invention;

fig. 19 is a schematic diagram of a Trench gate etched to a specified size by using a Trench mask through a Trench etching process according to embodiment 9 of the present invention;

fig. 20 is a schematic diagram of a gate dielectric layer 10 formed by a dry oxygen oxidation process according to embodiment 9 of the present invention;

fig. 21 is a schematic diagram of a polysilicon gate 11 formed by deposition, photolithography and etching processes according to embodiment 9 of the present invention;

fig. 22 is a schematic diagram of the gate electrode 12 formed by deposition, photolithography and etching processes according to embodiment 9 of the present invention;

FIG. 23 is a schematic illustration of deposition, photolithography and etching processes for forming BPSG13 according to example 9 of the present invention;

fig. 24 is a schematic diagram of forming the source electrode 6 and the metal drain electrode 1 by deposition, photolithography and etching processes according to embodiment 9 of the present invention.

Fig. 25 is a schematic diagram of a basic cell structure of a silicon carbide double trench MOSFET device provided in embodiment 10;

fig. 26 is a schematic view of a basic cell structure of a silicon carbide double trench MOSFET device provided in embodiment 11;

fig. 27 is a schematic diagram of a basic cell structure of a silicon carbide double trench MOSFET device provided in embodiment 12;

fig. 28 is a schematic diagram showing a basic cell structure of a silicon carbide double trench MOSFET device provided in embodiment 13;

fig. 29 is a schematic view of a basic cell structure of a silicon carbide double trench MOSFET device provided in example 14;

fig. 30 is a schematic diagram illustrating a basic cell structure of a silicon carbide double trench MOSFET device according to embodiment 15;

FIG. 31 is a Z-direction view of the Region "Region A" in the structure of example 10;

fig. 32 is a schematic diagram illustrating a basic cell structure of a silicon carbide double trench MOSFET device provided in embodiment 16;

fig. 33 is a schematic view of a basic cell structure of a silicon carbide double trench MOSFET device as provided in example 17;

FIG. 34 is a schematic view of a silicon carbide substrate provided in example 18 of the present invention;

fig. 35 is a schematic view of a Pbase region 7 formed by an ion implantation process according to example 18 of the present invention;

fig. 36 is a schematic view of forming a silicon carbide P + contact region 8 by performing aluminum ion implantation using a PSD mask through photolithography, ion implantation, or the like according to embodiment 18 of the present invention;

fig. 37 is a schematic view of silicon carbide N + source regions 9 formed by performing a process of photolithography, ion implantation, or the like, and performing phosphorous ion implantation using an NSD mask according to embodiment 18 of the present invention;

fig. 38 is a schematic view of a source Trench etched to a specified size by using a Trench mask through a Trench etching process according to embodiment 18 of the present invention;

fig. 39 is a schematic view of forming a P-type doped region 4 of silicon carbide by performing aluminum ion implantation at a certain incident angle through photolithography, ion implantation, and the like in accordance with embodiment 18 of the present invention;

fig. 40 is a schematic view of forming a P + doped silicon carbide region 5 by performing aluminum ion implantation through photolithography, ion implantation, and the like as provided in embodiment 18 of the present invention;

fig. 41 is a schematic view of schottky contact metal 14 formed by depositing a layer of metal on the bottom of the source trench by a deposition and etching process according to embodiment 18 of the present invention;

fig. 42 is a schematic diagram of a Trench gate etched to a specified size by using a Trench mask through a Trench etching process according to embodiment 18 of the present invention;

fig. 43 is a schematic diagram of a gate dielectric layer 10 formed by a dry oxygen oxidation process as provided in example 18 of the present invention;

fig. 44 is a schematic diagram of the formation of polysilicon 11 by deposition, photolithography and etching processes according to embodiment 18 of the present invention;

fig. 45 is a schematic diagram of the gate 12 formed by deposition, photolithography and etching processes according to embodiment 18 of the present invention;

FIG. 46 is a schematic illustration of deposition, photolithography and etching processes for forming BPSG13 in accordance with example 18 of the present invention;

fig. 47 is a schematic diagram of forming the source electrode 6 and the drain electrode 1 by deposition, photolithography and etching processes according to embodiment 18 of the present invention.

1 is a metal drain electrode; 2 is a silicon carbide N + substrate; 3 is a silicon carbide N-epitaxial layer; 4 is a silicon carbide P-type doped region; 5 is a silicon carbide P + doped region; 6 is source metal; 7 is a silicon carbide Pbase area; 8 is a silicon carbide P + contact region; 9 is a silicon carbide N + source region; 10 is a gate dielectric layer; 11 is a polysilicon gate; 12 is a grid; 13 is BPSG; 14 is Schottky contact metal; 15 is polysilicon; 16 is split-gate polysilicon and 17 is a dielectric layer.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Example 1:

a silicon carbide MOSFET device has a basic structure with a cell structure shown in FIG. 2, and comprises a metal drain 1 and silicon carbide N arranged from bottom to top⁺Substrate 2 and silicon carbide N^-An epitaxial layer 3; the silicon carbide N^-A first source groove is formed in the upper left of the epitaxial layer 3, and a silicon carbide P + doped region 5 and a silicon carbide P-type doped region 4 are formed below the first source groove from top to bottom; the silicon carbide N^-A second source groove is formed in the right upper portion of the epitaxial layer 3, and a silicon carbide P + doped region 5 and a silicon carbide P-type doped region 4 are formed below the second source groove from top to bottom; the first source groove and the second source groove are both filled with Schottky contact metal 14; a gate groove is arranged above the silicon carbide N-epitaxial layer 3, the depth of the gate groove is shallower than that of the two source grooves, a gate structure is arranged inside and on the surface of the gate groove, the gate structure comprises a gate dielectric layer 10, a polysilicon gate 11 and a gate 12 from bottom to top, the polysilicon gate 11 is isolated from the silicon carbide body by the gate dielectric layer 10, and the upper part of the polysilicon gate 11 is led out through the gate 12; the polysilicon gate 11 is arranged in the gate groove, and the gate 12 is arranged on the surface of the gate groove; a first mesa structure and a second mesa structure are respectively arranged between the source trench and the gate trench, and the first mesa structure and the second mesa structure are respectively composed of a silicon carbide Pbase region 7, a silicon carbide P + contact region 8 and a silicon carbide N + source region 9, wherein the silicon carbide P + contact region 8 and the silicon carbide N + source region 9 are positioned above the silicon carbide Pbase region 7, the silicon carbide P + contact region 8 is contacted with the source trench, the silicon carbide N + source region 9 is contacted with the gate trench, the silicon carbide Pbase region 7 is simultaneously contacted with the source trench and the gate trench, and the depth of the silicon carbide Pbase region is shallower than that of the source trench and the gate trench; the source groove metal is directly contacted with the silicon carbide N-epitaxial layer 3 at the bottom of the side wall of the source groove to form Schottky contact with rectification characteristics; the device surface is covered by a layer of source metal 6, and the source metal 6 and the gate 12 are isolated from each other by borophosphosilicate glass BPSG 13.

Wherein, the thickness of the metal drain electrode 1 is 0.5-2 μm, the width is 2-2.5 μm, the thickness of the metal of the grid electrode 12 is 0.5-2 μm, the width is 0.2-0.4 μm, the thickness of the metal of the source electrode is 4-6 μm, and the width is 2-2.5 μm; the thickness of the silicon carbide N + substrate 2 is 1-3 mu m, and the concentration is 1e 18-1 e19 cm-3; the thickness of the silicon carbide N-epitaxy 3 is 6-9 mu m, and the concentration is 1e 15-1 e16 cm-3; the thickness of the silicon carbide P-type doped region 4 is 1-2 mu m, the width is 0.5-2 mu m, and the concentration is 1e 17-6 e17 cm-3; the thickness of the silicon carbide P + doped region 5 is 1-2 mu m, the width is 0.2-1 mu m, and the concentration is 1e 18-6 e18 cm-3; the thickness of the silicon carbide Pbase area 7 is 0.3-0.8 μm, the width is 0.5-1.1 μm, and the concentration is 6e 16-4 e17 cm-3; the thickness of the silicon carbide P + contact zone 8 is 0.2-0.4 μm, the width is 0.2-0.4 μm, and the concentration is 8e 17-1 e19 cm-3; the thickness of the silicon carbide N + source region 9 is 0.2-0.4 μm, the width is 0.2-0.3 μm, and the concentration is 2e 18-1 e19 cm-3; the thickness of the gate dielectric layer 10 is 50 nm; the polysilicon gate 11 has a thickness of 0.4 to 1 μm and a width of 0.4 to 1 μm. The thickness of the Schottky contact metal 14 is 1-2 μm, and the width is 0.4-1.5 μm. According to the silicon carbide MOSFET provided by the invention, the Schottky barrier diode is integrated in the body, so that the basic performance of the device is optimized, the working performance of the third quadrant of the device is optimized, and the cost of a power system is reduced.

Example 2:

the structure of the present embodiment is substantially the same as that of embodiment 1, except that: the schottky contact metal 14 used is replaced by polysilicon 15 as shown in fig. 3. A Si/SiC heterojunction structure with rectifying contact is also formed on the sidewall of the bottom of the source trench and the silicon carbide N-epitaxy 3. The forward conduction voltage drop Von of the heterojunction structure is about 1.1V, and the forward conduction voltage drop Von also has a larger lifting effect on the third quadrant operation of the device. Meanwhile, the heterojunction belongs to a multi-sub device, so that the diode has good reverse recovery performance.

Example 3:

this embodiment is different from embodiment 1 in that the bottom region of the gate structure has a split-gate structure, as shown in fig. 4. The split-gate structure comprises split-gate polysilicon 16 and a gate dielectric layer 10 surrounding the split-gate polysilicon 16. The split-gate polysilicon 16 is led out from the back by a metal lead wire, and can be grounded or shorted with a source electrode. The mode obviously reduces the grid leakage charge of the device, thereby reducing the Miller capacitance and having great optimization effect on the improvement of the switching speed of the device.

Example 4:

the present embodiment is different from embodiment 1 in that: the silicon carbide P-type doped region 4 has a larger lateral dimension as shown in fig. 5. The larger lateral size of the silicon carbide P-type doped region 4 enables the silicon carbide P-type doped region 4 to have a better protective effect on the surface structure of the device, including a gate structure, a schottky contact structure and a Si/SiC heterojunction contact structure.

Example 5:

the present embodiment is different from embodiment 1 in that: the silicon carbide P-type doped region 4 and the silicon carbide P + doped region 5 are replaced by a dielectric layer 17, as shown in fig. 6. The introduction of the dielectric layer 17 has good protection effect on the surface structure of the device, including a grid structure, a Schottky contact structure and a Si/SiC heterojunction contact structure.

Example 6:

this embodiment is different from embodiment 1 in that the source trenches have a discontinuous trench profile in the Z direction below the source trenches, and the trenches are filled simultaneously with the deposition of the schottky contact metal 14 or the polysilicon 15. The bottom of the trench is a silicon carbide N-epitaxial layer 3. Meanwhile, the depth of the groove is consistent with that of the silicon carbide P-type doped region 4 or the gate dielectric layer 10, as shown in fig. 8. Example 1 the source trench under structure is shown in fig. 7. This example optimizes the on-state current density for the third quadrant operation of the device relative to example 1.

Example 7:

the structure of this embodiment is substantially the same as that of embodiment 6, except that the depth of the trench is smaller than that of the P-type doped region 4 of silicon carbide, as shown in fig. 9. Compared with embodiment 6, this embodiment has lower leakage in the off state, so that the embedded diode has better reliability.

Example 8:

the structure of this embodiment is substantially the same as that of embodiment 1, except that the schottky contact metal 14 or the polysilicon 15 extends from the bottom to the middle of the P-type doped silicon carbide region 4 and the P + doped silicon carbide region 5, and contacts the N-epitaxial silicon carbide layer 3. As shown in fig. 10. The improvement increases the rectifying area of the unipolar device, thereby optimizing the third quadrant operating performance of the device.

Example 9:

in this embodiment, a method for manufacturing a 1200V silicon carbide MOSFET device is also taken as an example to describe the specific implementation manner of the embodiments 1 to 8, and devices with different performance parameters can be manufactured according to actual requirements according to common knowledge in the art.

Step 1: a silicon carbide wafer with appropriate resistivity and thickness is selected as the following silicon carbide N + substrate 2 and silicon carbide N-region 3, as shown in fig. 11. Wherein the thickness of the silicon carbide N + substrate 2 is 1-3 μm, and the concentration is 1e 18-1 e19 cm-3; the thickness of the silicon carbide N-epitaxy 3 is 6-9 mu m, and the concentration is 1e 15-1 e16 cm-3;

step 2: and (3) performing aluminum ion implantation by a high-energy ion implantation process with the implantation energy of about 1500-2000 keV to form a silicon carbide Pbase region 7. The step can also form the Pbase region 7 of silicon carbide with a thickness of 0.3-0.8 μm, a width of 0.5-1.1 μm and a concentration of 6e 16-4 e17cm-3 by an epitaxial method. The device after formation of the silicon carbide Pbase region 7 is shown in fig. 12;

and 3, step 3: performing aluminum ion implantation at 450-550 ℃ by using a PSD mask through the processes of photoetching, ion implantation and the like, wherein the implantation energy is about 1300-1700 keV, and a silicon carbide P + contact region 8 with the thickness of 0.2-0.4 mu m, the width of 0.2-0.4 mu m and the concentration of 8e 17-1 e19cm-3 is formed, as shown in FIG. 13;

and 4, step 4: through the processes of photoetching, ion implantation and the like, phosphorus ion implantation is carried out by using an NSD mask, and the implantation energy is about 1300-1700 keV. A silicon carbide N + source region 9 having a thickness of 0.2 to 0.4 μm, a width of 0.2 to 0.3 μm, and a concentration of 2e18 to 1e19cm-3, as shown in FIG. 14;

and 5, step 5: etching a source groove with the thickness of 1-2 mu m and the width of 0.4-1.5 mu m by using a Trench mask through a groove etching process, as shown in FIG. 15;

and 6, step 6: performing aluminum ion implantation at 480-580 ℃ by the processes of photoetching, ion implantation and the like, wherein the implantation energy is about 1400-1700 keV, and forming a silicon carbide P-type doped region 4 as shown in FIG. 16; in the step 5, a deeper source groove can be formed by etching, and then silicon carbide P-type doping 4 with the thickness of 1-2 mu m, the width of 0.5-2 mu m and the concentration of 1e 17-6 e17cm-3 is formed by the epitaxial and etching processes;

and 7, step 7: performing aluminum ion implantation at 430-580 ℃ by photolithography, ion implantation, and the like, wherein the implantation energy is about 1200-1700 keV, and a silicon carbide P + doped region 5 with a thickness of 1-2 μm, a width of 0.2-1 μm, and a concentration of 1e 18-6 e18cm-3 is formed, as shown in FIG. 17;

and 8, step 8: a layer of metal is deposited at the bottom of the source groove through deposition and etching processes to form Schottky contact metal 14 with the thickness of 1-2 mu m and the width of 0.4-1.5 mu m, and redundant metal is removed through etching. As shown in fig. 18;

step 9: etching a gate groove with the thickness of 0.4-1 mu m and the width of 0.4-1 mu m by using a Trench mask through a groove etching process, as shown in figure 19;

step 10: forming a gate dielectric layer 10 with a thickness of 50nm by a dry oxygen oxidation process at a temperature of about 1000-1400 ℃, as shown in fig. 20;

and 11, step 11: through deposition and etching processes, a layer of polycrystalline silicon is deposited in the gate trench to form a polycrystalline silicon gate 11 with the thickness of 0.4-1 mu m and the width of 0.4-1 mu m, and redundant polycrystalline silicon is removed through etching. As shown in fig. 21;

step 12: the gate electrode 12 having a thickness of 0.5 to 2 μm and a width of 0.2 to 0.4 μm is formed by deposition, photolithography and etching processes, as shown in fig. 22.

Step 13: the borophosphosilicate glass BPSG13 is formed by deposition, photolithography, and etching processes as shown in fig. 23.

Step 14: respectively forming a source electrode 6 with the thickness of 4-6 mu m and the width of 2-2.5 mu m, and a drain electrode 1 with the thickness of 0.5-2 mu m and the width of 2-2.5 mu m by deposition, photoetching and etching processes. At this point, the device fabrication is complete, as shown in fig. 24.

Furthermore, the polysilicon 11 deposited in the 11 th step may be either N-type polysilicon or P-type polysilicon;

further, in step 8, the deposited source trench schottky contact metal 14 may also be replaced with polysilicon 15 material; the polysilicon can be N-type polysilicon or P-type polysilicon;

further, after the 9 th step of forming a deeper gate trench is completed, the bottom and sidewalls of the trench are oxidized. Depositing split-gate polysilicon 16 at the bottom of the trench, and forming a split-gate structure by depositing a dielectric layer 5, etching the dielectric layer 5 and depositing a polysilicon gate 11, as shown in FIG. 4;

further, after the silicon carbide P-type doped region 4 is formed in the step 6, the silicon carbide P-type doped region 4 with the thickness of 1-2 microns and the width of 0.6-2.3 microns can be formed through a high-temperature diffusion process;

further, when the source trench is formed in the 5 th step, the etching strength can be increased to form deeper trench etching. And the

steps

6 and 7 are replaced by the following processes: and depositing and etching the bottom of the source trench to form an oxide layer with the thickness of 1-2 mu m. And forming a dielectric layer 10 with the surface height lower than that of the silicon carbide Pbase region 7 through an etching process.

Furthermore, after the source trench is formed in the 5 th step, etching may be added again to form a discontinuous trench at the bottom of the source trench. The depth of the groove for the secondary etching is equal to the depth of the silicon carbide P-type doped region 4 formed in the later period, namely the thickness is 1-2 mu m;

furthermore, after the source trench is formed in the 5 th step, etching may be added again to form a discontinuous trench at the bottom of the source trench. The depth of the groove of the secondary etching is smaller than the depth of the silicon carbide P-type doped region 4 formed in the later stage, namely the thickness is smaller than 1um at minimum and smaller than 2um at maximum;

further, after the source trench is formed in the step 5, a second etching can be added to form a continuous trench at the bottom of the source trench, and the depth of the second etching trench is equal to the depth of the silicon carbide P-type doped region 4 formed in the later stage;

Example 10:

a silicon carbide MOSFET device whose basic structure has a cell structure as shown in fig. 25. Comprises a metal drain electrode 1 and silicon carbide N which are arranged from bottom to top in sequence⁺Substrate 2 and silicon carbide N^-An epitaxial layer 3; the silicon carbide N^-The upper left of the epitaxial layer 3 is provided with a first grid structure, and the silicon carbide N^-A second grid structure is arranged at the right upper part of the epitaxial layer 3, the first grid structure and the second grid structure respectively comprise a grid 12, a polysilicon grid 11 and a grid dielectric layer 10, wherein the polysilicon grid 11 is surrounded by the grid dielectric layer 10, the grid 12 is led out from the upper part of the polysilicon grid 11, and the silicon carbide N is arranged^-A source groove is formed above the epitaxial layer 3, the source groove is deposited and filled with Schottky contact metal 14, the Schottky contact metal 14 is in direct contact with the silicon carbide N-epitaxial layer 3 to form Schottky contact, a first mesa structure and a second mesa structure are respectively arranged between the source groove and the gate structure, the first mesa structure and the second mesa structure are respectively formed by a silicon carbide Pbase region 7, a silicon carbide P + contact region 8 and a silicon carbide N + source region 9, wherein the silicon carbide P + contact region 8 and the silicon carbide N + source region 9 are positioned above the silicon carbide Pbase region 7, the silicon carbide P + contact region 8 is in contact with the source groove, the silicon carbide N + source region 9 is in contact with the gate structure, and the silicon carbide Pbase region 7 is in contact with the source groove and the gate structure at the same time and is shallower than the source groove and the gate structure; p-type doped regions are arranged on two sides below the Schottky contact metal 14 and below part of the silicon carbide Pbase region 7, the deeper part of the P-type doped region is a silicon carbide P-type doped region 4, and the shallower part of the P-type doped region is a silicon carbide P + doped region 5 with narrower width; the silicon carbide P + doped region 5 forms an ohmic contact with the schottky contact metal 14 and the device surface is covered by a layer of source metal 6, the source metal 6 being separated from the gate 12 by borophosphosilicate glass BPSG 13. Wherein, the thickness of the drain electrode metal 1 is 0.5-1.6 μm, the width is 4-6 μm, the thickness of the grid electrode metal 12 is 0.5-1.6 μm, the width is 0.2-0.5 μm, the thickness of the source electrode metal is 4-6 μm, and the width is 4-6 μm; the thickness of the silicon carbide N + substrate 2 is 1-3 mu m, and the concentration is 1e 18-1 e19 cm-3; the thickness of the silicon carbide N-epitaxy 3 is 6-10 mu m, and the concentration is 1e 15-1 e16 cm-3; the thickness of the silicon carbide P-type doped region 4 is 1-2 mu m, the width is 0.5-3 mu m, and the concentration is 1e 17-6 e17 cm-3; silicon carbideThe thickness of the P + doped region 5 is 1-2 μm, the width is 0.2-1.5 μm, and the concentration is 1e 18-6 e18 cm-3; the thickness of the silicon carbide Pbase area 7 is 0.3-0.8 μm, the width is 0.5-1.1 μm, and the concentration is 6e 16-5 e17 cm-3; the thickness of the silicon carbide P + contact zone 8 is 0.2-0.5 μm, the width is 0.2-0.5 μm, and the concentration is 8e 17-1 e19 cm-3; the thickness of the silicon carbide N + source region 9 is 0.2-0.5 μm, the width is 0.2-0.5 μm, and the concentration is 2e 18-1 e19 cm-3; the thickness of the gate dielectric layer 10 is 20-70 nm; the polysilicon gate 11 has a thickness of 0.4 to 1 μm and a width of 0.4 to 1 μm. The thickness of the Schottky contact metal 14 is 1-2 μm, and the width is 0.4-3 μm. According to the silicon carbide MOSFET provided by the invention, the Schottky barrier diode is integrated in the body, so that the basic performance of the device is optimized, the working performance of the third quadrant of the device is optimized, and the application cost of a power conversion system is reduced.

Example 11:

this embodiment is modified to a certain extent with respect to embodiment 10, and the structure thereof is described by taking embodiment 10 as an example. The difference from embodiment 9 is that the schottky contact metal 14 used is replaced with polysilicon 15, as shown in fig. 26. A Si/SiC heterojunction structure with rectifying contact is also formed with the silicon carbide N-epi 3 at the bottom of the source trench. The forward conduction voltage drop Von of the heterojunction structure is about 1.1V, and the forward conduction voltage drop Von also has a larger lifting effect on the third quadrant operation of the device. Meanwhile, the heterojunction belongs to a multi-sub device, so that the diode has good reverse recovery performance.

Example 12:

the structure of this embodiment will be described by taking embodiment 10 as an example, as shown in fig. 27. The difference from embodiment 10 is that the bottom region of the gate structure has a split-gate structure. The split-gate structure comprises split-gate polysilicon 16 and a gate dielectric layer 10 surrounding the split-gate polysilicon 16. The split-gate polysilicon 16 is led out from the back by a metal lead wire, and can be grounded or shorted with a source electrode. The mode obviously reduces the grid leakage charge of the device, thereby reducing the Miller capacitance and having great optimization effect on the improvement of the switching speed of the device;

example 13:

this embodiment differs from embodiment 10 in that the structure has a larger schottky contact metal 14 depth and width, so that it not only forms a rectifying contact with the sic N-epi layer 3 at the bottom of the metal, but also forms a rectifying contact with the sic N-epi layer 3 at the sidewall of the bottom of the source trench, as shown in fig. 28;

example 14:

this embodiment is different from embodiment 10 in that the silicon carbide P-type doped region 4 and the silicon carbide P + doped region 5 are replaced by a dielectric layer 17, as shown in fig. 29. The introduction of the dielectric layer 10 has a good protection effect on the surface structures of the device, including a grid structure, a Schottky contact structure and a Si/SiC heterojunction contact structure.

Example 15:

this embodiment is different from embodiment 10 in that a polysilicon 15 region is provided under a portion of the region where the bottom of the schottky contact metal 14 contacts the silicon carbide N-epi 3, as shown in fig. 30. This region is in contact with the silicon carbide N-epi 3 forming a Si/SiC heterojunction. The improvement increases the rectifying contact area by about 50% from the increase of the rectifying contact area, thereby increasing the conducting junction area in the diode application. The leakage performance of the Si/SiC heterojunction is far better than that of a Schottky contact, and meanwhile, the P-type silicon has a good shielding effect on the Schottky junction surface, so that the leakage of the Schottky junction surface is further reduced.

Example 16:

this embodiment is different from embodiment 10 in that there is a discontinuous trench profile below the source trenches, and the trenches are simultaneously filled when the schottky contact metal 14 or the polysilicon 15 is deposited. And the depth of the groove is consistent with that of the silicon carbide P-type doped region 4 or the dielectric layer 10, as shown in fig. 32. Example 10 the source trench under structure is shown in fig. 31. This example optimizes the on-state current density for the third quadrant operation of the device relative to example 10.

Example 17:

the present embodiment is different from embodiment 16 in that the etching depth of the secondary source trench is shallower than that of embodiment 16, as shown in fig. 33. Compared with embodiment 16, this embodiment has lower leakage in the off state, so that the embedded diode has better reliability.

Example 18:

in this embodiment, a method for manufacturing a 1200V silicon carbide MOSFET device is also taken as an example to describe the specific implementation manner of the above 10 to 17 embodiments, and devices with different performance parameters can be manufactured according to actual requirements according to common knowledge in the art.

Step 1: a silicon carbide wafer of appropriate resistivity and thickness is selected as the following silicon carbide N + substrate 2 and silicon carbide N-region 3, as shown in fig. 34. Wherein the thickness of the silicon carbide N + substrate 2 is 1-3 μm, and the concentration is 1e 18-1 e19 cm-3; the thickness of the silicon carbide N-epitaxy 3 is 6-10 mu m, and the concentration is 1e 15-1 e16 cm-3;

step 2: and (3) performing aluminum ion implantation by a high-energy ion implantation process with the implantation energy of about 1500-2000 keV to form a silicon carbide Pbase region 7. The step can also form the Pbase region 7 of silicon carbide with a thickness of 0.3-0.8 μm, a width of 0.5-1.1 μm and a concentration of 6e 16-5 e17cm-3 by an epitaxial method. The device after formation of the silicon carbide Pbase region 7 is shown in fig. 35;

and 3, step 3: performing aluminum ion implantation at 450-550 ℃ by using a PSD mask through the processes of photoetching, ion implantation and the like, wherein the implantation energy is about 1300-1700 keV, and a silicon carbide P + contact region 8 with the thickness of 0.2-0.5 mu m, the width of 0.2-0.5 mu m and the concentration of 8e 17-1 e19cm-3 is formed, as shown in FIG. 36;

and 4, step 4: through the processes of photoetching, ion implantation and the like, phosphorus ion implantation is carried out by using an NSD mask, and the implantation energy is about 1300-1700 keV. A thickness of 0.2 to 0.5 μm, a width of 0.2 to 0.5 μm, and a concentration of 2e18 to 1e19cm^-3As shown in fig. 37, to form a silicon carbide N + source region 9;

and 5, step 5: etching a source groove with the thickness of 1-2 mu m and the width of 0.4-3 mu m by using a Trench mask through a groove etching process, as shown in figure 38;

and 6, step 6: performing aluminum ion implantation at a certain angle at 480-580 ℃ by photolithography, ion implantation and other processes, wherein the implantation energy is about 1400-1700 keV, and silicon carbide P-type doping 4 with the thickness of 1-2 μm, the width of 0.5-3 μm and the concentration of 1e 17-6 e17cm-3 is formed, as shown in FIG. 39;

and 7, step 7: performing aluminum ion implantation at 430-580 ℃ by photolithography, ion implantation, and the like, wherein the implantation energy is about 1200-1700 keV, and a silicon carbide P + doped region 5 with a thickness of 1-2 μm, a width of 0.2-1.5 μm, and a concentration of 1e 18-6 e18cm-3 is formed, as shown in FIG. 40;

and 8, step 8: a layer of metal is deposited at the bottom of the source groove through deposition and etching processes to form Schottky contact metal 14 with the thickness of 1-2 mu m and the width of 0.4-3 mu m, and redundant metal is removed through etching. As shown in fig. 41;

step 9: etching a gate Trench with the thickness of 0.4-1 μm and the width of 0.4-1 μm by using a Trench etching process and a Trench mask, as shown in FIG. 42;

step 10: forming a gate dielectric layer 10 with a thickness of 20-70 nm by a dry oxygen oxidation process at a temperature of about 1000-1400 ℃, as shown in fig. 43;

and 11, step 11: through deposition and etching processes, a layer of polycrystalline silicon is deposited in the gate trench to form a polycrystalline silicon gate 11 with the thickness of 0.4-1 mu m and the width of 0.4-1 mu m, and redundant polycrystalline silicon is removed through etching. As shown in fig. 44;

step 12: the gate electrode 12 having a thickness of 0.5 to 1.6 μm and a width of 0.2 to 0.5 μm is formed by deposition, photolithography and etching processes, as shown in fig. 45.

Step 13: the borophosphosilicate glass BPSG13 is formed by deposition, photolithography, and etching processes, as shown in fig. 46.

Step 14: the source electrode 6 with the thickness of 4-6 mu m and the width of 4-6 mu m, and the drain electrode 1 with the thickness of 0.5-1.6 mu m and the width of 4-6 mu m are respectively formed through deposition, photoetching and etching processes. At this point, the device fabrication is complete, as shown in fig. 47.

furthermore, a gate structure can be made first, and then a source trench is completed;

further, after the 9 th step of forming a deeper gate trench is completed, the bottom and sidewalls of the trench are oxidized. Depositing split-gate polysilicon 16 at the bottom of the trench, and forming a split-gate structure by depositing a gate dielectric layer 10, etching the gate dielectric layer 10 and depositing a polysilicon gate 11, as shown in fig. 27;

steps

Further, after the source trench is formed in the step 5, a second etching is performed on the bottom of the source trench, and before the step 6, the second trench is filled with a polysilicon deposition to form a polysilicon region 15. The polysilicon region 15 has a thickness of 0.5-0.9 um and a width of 0.3-0.7 um.

further, in the 5 th step of trench etching process, the surface of the device may be etched for the second time, the etching depth is equal to the depth of the later-stage silicon carbide P-type doped region 4, and when the schottky contact metal 14 or the polysilicon 15 is deposited in the 8 th step, the trench is also deposited for the second time at the same time to form a rectifying contact in the horizontal direction, and similar effects are shown in fig. 12;

it should also be claimed that: as known to those skilled in the art based on the basic knowledge in the art, in the structure of the silicon carbide power MOSFET of the present invention, the P-type polysilicon may also be implemented by N-type polysilicon, P-type single crystal silicon, or N-type single crystal silicon; the dielectric material used can be silicon dioxide (SiO)₂) This can also be achieved by using silicon nitride (Si)₃N₄) Hafnium oxide (HfO)₂) Aluminum oxide (Al)₂O₃) The realization of medium materials with equal height K; the silicon carbide material can also be replaced by wide bandgap materials such as gallium nitride, diamond and the like. Meanwhile, the specific implementation mode of the manufacturing process can be adjusted according to actual needs.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A silicon carbide MOSFET device, characterized by: comprises a metal drain electrode (1) and silicon carbide N which are arranged from bottom to top in sequence⁺Substrate (2) and silicon carbide N^-An epitaxial layer (3); the silicon carbide N^-A first source groove is formed in the upper left of the epitaxial layer (3), and a silicon carbide P + doped region (5) and a silicon carbide P-type doped region (4) are formed below the first source groove from top to bottom; the silicon carbide N^-A second source groove is formed in the right upper portion of the epitaxial layer (3), and a silicon carbide P + doped region (5) and a silicon carbide P-type doped region (4) are formed below the second source groove from top to bottom; the first and second source trenchesFilling and forming Schottky contact metal (14); a grid groove is arranged above the silicon carbide N-epitaxial layer (3), the depth of the grid groove is shallower than that of the two source grooves, grid structures are arranged inside and on the surface of the grid groove, each grid structure comprises a grid dielectric layer (10), a polysilicon grid (11) and a grid (12) from bottom to top, the polysilicon grid (11) is isolated from a silicon carbide body region by the grid dielectric layer (10), and the upper part of the polysilicon grid (11) is led out through the grid (12); the polysilicon gate (11) is arranged inside the gate groove, and the gate (12) is arranged on the surface of the gate groove; a first mesa structure and a second mesa structure are respectively arranged between the source trench and the gate trench, and the first mesa structure and the second mesa structure are respectively composed of a silicon carbide Pbase region (7), a silicon carbide P + contact region (8) and a silicon carbide N + source region (9), wherein the silicon carbide P + contact region (8) and the silicon carbide N + source region (9) are positioned above the silicon carbide Pbase region (7), the silicon carbide P + contact region (8) is contacted with the source trench, the silicon carbide N + source region (9) is contacted with the gate trench, and the silicon carbide Pbase region (7) is simultaneously contacted with the source trench and the gate trench and is shallower than the source trench and the gate trench; the source groove metal is directly contacted with the silicon carbide N-epitaxial layer (3) at the bottom of the side wall of the source groove to form Schottky contact with rectification characteristics; the surface of the device is covered by a layer of source metal (6), and the source metal (6) and the grid (12) are mutually isolated by boron-phosphorus-silicon-glass (BPSG) (13);

the lower part of the source trench is provided with a discontinuous trench distribution in the Z direction, and the trench is simultaneously filled when Schottky contact metal (14) or polysilicon (15) is deposited; the bottom of the groove is provided with a silicon carbide N-epitaxial layer (3); the deepest part of the bottom of the groove is in contact with the silicon carbide N-epitaxial layer (3), the shallowest part of the bottom of the groove is in contact with the silicon carbide P + doped region (5), and the side wall of the groove is in contact with the silicon carbide P-type doped region (4) and the silicon carbide P + doped region (5).

2. A silicon carbide MOSFET device, characterized by: comprises a metal drain electrode (1) and silicon carbide N which are arranged from bottom to top in sequence⁺Substrate (2) and silicon carbide N^-An epitaxial layer (3); the silicon carbide N^-The upper left part of the epitaxial layer (3) is provided with a first grid structure, and the silicon carbide N^-A second grid structure is arranged at the right upper part of the epitaxial layer (3), and the first and second grid structures comprise a grid (12) and a polysilicon grid(11) And a gate dielectric layer (10), wherein the polysilicon gate (11) is surrounded by the gate dielectric layer (10), the upper part of the polysilicon gate is led out by a gate electrode (12), and the silicon carbide N^-A source groove is arranged above the epitaxial layer (3), the source groove is deposited and filled by Schottky contact metal (14), the Schottky contact metal (14) is directly contacted with the silicon carbide N-epitaxial layer (3) to form Schottky contact, a first mesa structure and a second mesa structure are respectively arranged between the source groove and the grid structure, the first mesa structure and the second mesa structure are respectively formed by a silicon carbide Pbase region (7), a silicon carbide P + contact region (8) and a silicon carbide N + source region (9), wherein the silicon carbide P + contact region (8) and the silicon carbide N + source region (9) are positioned above the silicon carbide Pbase region (7), the silicon carbide P + contact region (8) is contacted with the source groove, the silicon carbide N + source region (9) is contacted with the grid structure, the silicon carbide Pbase area (7) is simultaneously contacted with the source trench and the grid structure, and the depth of the silicon carbide Pbase area is shallower than that of the source trench and the grid structure; p-type doped regions are arranged on two sides below the Schottky contact metal (14) and below part of the silicon carbide Pbase region (7), the deeper part of the P-type doped region is a silicon carbide P-type doped region (4), and the shallower part of the P-type doped region is a silicon carbide P + doped region (5) with narrower width; the silicon carbide P + doped region (5) and Schottky contact metal (14) form ohmic contact, the surface of the device is covered by a layer of source metal (6), and the source metal (6) and the grid (12) are separated by boron-phosphorus-silicon glass (BPSG) (13);

3. A silicon carbide MOSFET device as claimed in claim 1 or claim 2 in which: the silicon carbide material is replaced by one of semiconductor materials of Si, Ge, GaAs, GaN, diamond, silicon germanium and gallium oxide; the Schottky contact metal (14) region is polysilicon (15).

4. A silicon carbide MOSFET device as claimed in claim 1 or claim 2 in which: the gate structure has split-gate polysilicon (16) thereunder.

5. A silicon carbide MOSFET device as claimed in claim 1 or claim 2 in which: the bottom of the Schottky contact metal (14) or the polycrystalline silicon (15) extends to the middle parts of the silicon carbide P-type doped region (4) and the silicon carbide P + doped region (5) and is in contact with the silicon carbide N-epitaxial layer (3).

6. A silicon carbide MOSFET device as claimed in claim 2, wherein: a Schottky contact metal (14) and silicon carbide N under the silicon carbide Pbase region (7)^-The epitaxial layer (3) is in direct contact, so that the metal bottom and the silicon carbide N-epitaxial layer (3) form rectifying contact, and the side wall of the bottom of the source groove is in contact with the silicon carbide N-epitaxial layer (3) to form rectifying contact.

7. A silicon carbide MOSFET device as claimed in claim 2, wherein: the bottom of the Schottky contact metal (14) is in contact with the silicon carbide N-epitaxial layer (3) and is provided with a polycrystalline silicon (15) region below a partial region, and the region is in Si/SiC heterojunction contact with the silicon carbide N-epitaxial layer (3).

8. The method of fabricating a silicon carbide MOSFET device as claimed in claim 1, comprising the steps of:

step 1: selecting a silicon carbide wafer as a silicon carbide N + substrate (2) and a silicon carbide N-epitaxial layer region (3) at the back;

step 2: performing aluminum ion implantation through a high-energy ion implantation process to form a silicon carbide Pbase area (7), or forming the silicon carbide Pbase area (7) in an epitaxial mode, and then forming a device behind the silicon carbide Pbase area (7);

and 3, step 3: performing aluminum ion implantation by using a PSD mask through photoetching and ion implantation processes to form a silicon carbide P + contact region (8);

and 4, step 4: performing phosphorus ion implantation by using an NSD mask through photoetching and ion implantation processes to form a silicon carbide N + source region (9);

and 6, step 6: carrying out aluminum ion implantation through photoetching and ion implantation processes to form a silicon carbide P-type doped region (4); in the step 5, a deeper source groove is formed through etching, and then a silicon carbide P-type doped region (4) is formed through epitaxy and etching processes;

and 7, step 7: carrying out aluminum ion implantation through the processes of photoetching and ion implantation to form a silicon carbide P + doped region (5);

and 8, step 8: depositing a layer of metal at the bottom of the source groove by deposition and etching processes to form Schottky contact metal (14), and removing redundant metal by etching;

step 10: forming a gate dielectric layer (10) by a dry oxygen oxidation process;

and 11, step 11: depositing a layer of polysilicon in the gate trench by deposition and etching processes to form a polysilicon gate (11), and removing redundant polysilicon by etching;

step 12: forming a gate (12) by deposition, photolithography and etching processes;

step 13: forming BPSG (13) of borophosphosilicate glass by deposition, photoetching and etching processes;

step 14: and forming a source metal (6) and a metal drain (1) by deposition, photoetching and etching processes respectively, and thus finishing the manufacturing of the device.

9. The method of manufacturing a silicon carbide MOSFET device as claimed in claim 2, comprising the steps of:

step 1: selecting a silicon carbide wafer as a silicon carbide N + substrate (2) and a silicon carbide N-epitaxial layer (3) at the back;

step 2: performing aluminum ion implantation through a high-energy ion implantation process to form a silicon carbide Pbase region (7), and forming the silicon carbide Pbase region (7) in the step or in an epitaxial mode;

and 6, step 6: performing aluminum ion implantation at a certain angle through the processes of photoetching and ion implantation to form a silicon carbide P-type doped region (4);

and 7, step 7: carrying out aluminum ion implantation through the working procedures of photoetching and ion implantation to form a silicon carbide P + doped region (5);

step 14: forming a source metal (6) and a metal drain (1) by deposition, photoetching and etching processes respectively; thus, the device is completed.