CN105633168A - SiC grooved metal oxide semiconductor field effect transistor (MOSFET) with integration of Schottky diode and fabrication method of SiC grooved MOSFET - Google Patents
SiC grooved metal oxide semiconductor field effect transistor (MOSFET) with integration of Schottky diode and fabrication method of SiC grooved MOSFET Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 title claims abstract description 9
- 239000004065 semiconductor Substances 0.000 title abstract description 8
- 230000005669 field effect Effects 0.000 title abstract description 3
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 3
- 150000004706 metal oxides Chemical class 0.000 title abstract description 3
- 230000010354 integration Effects 0.000 title abstract 2
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000007789 sealing Methods 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 18
- 238000001459 lithography Methods 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 12
- 238000005468 ion implantation Methods 0.000 description 10
- 238000001020 plasma etching Methods 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 238000000926 separation method Methods 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The invention provides a SiC grooved metal oxide semiconductor field effect transistor (MOSFET) with integration of a Schottky diode and a fabrication method of the SiC grooved MOSFET. The transistor comprises: 1) a grooved MOSFET comprising an N+ substrate and an N- drift layer on the N+ substrate, wherein the N- drift layer comprises P wells, U-shaped channels outside the P wells, a gate, an isolation layer on parts of N+ source regions, a source on the front surface and a drain on the back surface, the P wells are provided with the N+ source regions and are isolated, oxide layers are arranged on the surface of the U-shaped channels, and the gate is arranged in the U-shaped channels; and 2) the Schottky diode, in which the N- drift layer among the P wells in the N- drift layer forms Schottky contact with source metal. By introducing the Schottky diode into the grooved SiC MOSFET, an effect of a fly-wheel diode is developed during device working, the working efficiency and reliability of a circuit are improved, and the fabrication cost of the circuit is reduced.
Description
Technical field
The present invention relates to a kind of semiconductor device, be specifically related to SiC trench MOSFET device and the manufacture method thereof of a kind of integrated schottky diode.
Background technology
Carborundum (SiC) is the third generation semi-conducting material grown up after first generation Semiconducting Silicon Materials, germanium and the second carrying semiconductor material GaAs, indium phosphide, the broad stopband of carbofrax material is 2��3 times of silicon and GaAs so that semiconductor device (more than 500 DEG C) can work and have the ability launching blue light at relatively high temperatures; Its high breakdown electric field is intended to a high order of magnitude than silicon and GaAs, determines the high pressure of semiconductor device, high-power performance; Its high saturated electron drift velocity and low-k determine the high frequency of device, high speed operation performance; The thermal conductivity of carborundum is 3.3 times of silicon, 10 times of GaAs, it is meant that its good heat conductivity, it is possible to be greatly improved the integrated level of circuit, reduces cooling heat radiation system, thus reducing the volume of complete machine. Therefore constantly perfect along with carbofrax material and device technology, part Si field is carbonized silicon and is substituted within sight. Carborundum has the features such as broad-band gap, high critical breakdown strength, high thermal conductivity, the high saturated elegant speed of electronics, is particularly suitable for high-power, high-voltage power electronic device, therefore becomes the study hotspot of current power electronic applications.
The theoretical maximum operating voltage scope of SiC base power device is more than 10kV, higher than the running voltage of silica-based insulated gate bipolar transistor (IGBT) device; As unipolar device, its switching speed is faster than ambipolar silica-based IGBT, and required epitaxial layer reduces owing to SiC decuples silica-based critical breakdown electric field especially, is accordingly regarded as the ideal chose substituting silica-based IGBT device.
Power electronic devices such as IGBT, metal oxide layer semiconductor field-effect transistor (MOSFET) etc. for gate-controlled switch type, it is when application, often with diode inverse parallel to play afterflow effect in circuit, power IGBT as shown in Figure 1 and the antiparallel circuit diagram of diode. Silica-based IGBT is usually and antiparallel diode is encapsulated into power model simultaneously, and silica-based MOSFET then naturally form anti-paralleled diode due to p-well and drift region, does not therefore need additionally increase diode encapsulation in parallel.
Although SiC base MOSFET also has the anti-paralleled diode of self-assembling formation, but owing to the energy gap of SiC is high, the cut-in voltage of its PN junction diode is high, reaches about 3V, when using the anti-paralleled diode within SiCMOSFET, can greatly increase the power consumption in circuit; Simultaneously as the basic vector face dislocation in SiC material can induce fault due to the work of PN junction, therefore, adopt its internal PN junction diode to make anti-paralleled diode and can affect the reliability of device. When using SiCMOSFET device, it is generally required in its outer counter parallel connection SiC Schottky diode, but so can increase the cost of manufacture of device.
Summary of the invention
It is an object of the invention to provide the carborundum trench MOSFET of a kind of integrated schottky device and manufacture method thereof, overcome the drawbacks described above that prior art exists, by introducing Schottky diode in groove-shaped SiCMOSFET, when device works, play the effect of fly-wheel diode, improve efficiency and the reliability of circuit work, reduce circuit production cost.
In order to achieve the above object, the present invention is by the following technical solutions:
A kind of SiC trench MOSFET device of integrated schottky diode, described device includes:
1) trench MOSFET:
N+ substrate and N-drift layer thereon, described N-drift layer comprises the p-well having N+ source region being isolated from each other;
U-shaped raceway groove outside described p-well, described U-shaped channel surface has oxide layer, has grid in it;
Described grid and the described N+ source region of part are sealing coat;
Front is source electrode and the back side is drain electrode;
2) Schottky diode: the Schottky contacts that the N-drift layer between described p-well in described N-drift layer is formed with described source metal.
First optimal technical scheme of described device, described Schottky diode is fly-wheel diode.
Second optimal technical scheme of described device, the resistivity of described N+ substrate is 0.015��0.02 ohmcm.
3rd optimal technical scheme of described device, the thickness of described N-drift layer is 10��500 ��m, and its doping content is 1 �� 1014��5 �� 1015cm-3��
4th optimal technical scheme of described device, the distance between described p-well is 1��3 ��m, and its well depth is 1��3 ��m.
5th optimal technical scheme of described device, width and the degree of depth in described N+ source region are respectively less than described p-well.
6th optimal technical scheme of described device, the degree of depth of described U-shaped raceway groove is 4��10 ��m.
7th optimal technical scheme of described device, the thickness of described oxide layer is 50��150 ��m; The thickness of described sealing coat is 15��50 ��m.
8th optimal technical scheme of described device, described grid is n-type or the polysilicon of p-type degeneracy doping.
The manufacture method of the SiC trench MOSFET device of a kind of described integrated schottky diode, described method comprises the steps:
1) making mask on N+ substrate epitaxial N-drift layer surface and graphical, implanted dopant forms p-well;
2) making mask on described p-well surface and graphical, doping forms N+ source region;
3) making mask on described N-drift layer and graphical, etching SiC forms U-shaped raceway groove;
4) in described raceway groove inner surface deposited oxide layer;
5) in the described raceway groove with oxide layer, fill polysilicon poly, form grid;
6) on the described N+ source region of described grid and part, sealing coat is deposited;
7) deposit metal in described drift layer front and described substrate back, form source electrode and drain electrode respectively.
With immediate prior art ratio, there is advantages that
1) source electrode of carborundum trench MOSFET of the present invention forms Schottky contacts with epitaxial layer between p-well, and the Schottky diode of formation, when device works, plays the effect of fly-wheel diode, improves efficiency and the reliability of circuit work;
2), when the integrated device of the present invention avoids the PN junction in SiCMOSFET as fly-wheel diode, SiCPN ties the problem that the circuit conversion efficiency that causes of cut-in voltage height is low;
3) SiC Schottky diode of the present invention is unipolar device, it is to avoid the BPD dislocation caused during PN junction work increases, the problem that device reliability reduces;
4) SiC Schottky diode of the present invention and the integrated preparation of SiCMOSFET, reduce the material and technology cost of element manufacturing.
Accompanying drawing explanation
Fig. 1: IGBT with the antiparallel circuit diagram of diode;
Fig. 2: N+ substrate is formed the profile of N-drift layer;
Fig. 3: N-drift layer ion implanting forms the profile of p-well;
Fig. 4: in p-well, ion implanting forms the profile in N+ source region;
Fig. 5: outside p-well, etching forms the profile of U-shaped raceway groove;
Fig. 6: trench bottom and sidewall form the profile of oxide-film;
Fig. 7: fill the profile of polysilicon poly in raceway groove;
The profile of layer deposited isolating on Fig. 8: N-drift layer;
Fig. 9: the profile after lithographic section sealing coat;
Figure 10: front deposition metal forms the profile of source electrode;
Figure 11: backside deposition metal forms the profile of drain electrode.
Detailed description of the invention
Below in conjunction with example, the present invention will be described in detail, the invention is not limited in this specific embodiment, and general replacement the known by those skilled in the art is also covered by protection scope of the present invention.
Embodiment 1
First on N+ substrate, extension generates N-drift layer, and the thickness of this drift layer is 12 ��m, and doping content is 2 �� 1015cm-3. The resistivity of N+ substrate is 0.015-0.02 ohmcm.
Then the mask plate on N-drift layer makes the figure needing doping by lithography, carries out the ion implantation technology of p-well, and the distance between each p-well is 1 ��m, and p-well is 1 ��m deeply. This part is used for forming Schottky contacts with metal.
Then, utilizing mask plate to make N+ source region figure by lithography, carry out the ion implantation technology in N+ source region, the degree of depth in N+ source region, less than p-well, is 0.5 ��m, and width is again smaller than p-well.
Then, utilize mask plate to make grid groove (U-shaped raceway groove) figure by lithography, adopt reactive ion etching (RIE) or sense coupling (ICP) to form groove, channel depth 5 ��m.
Then, forming oxide-film at channel bottom and sidewall, thickness is 100nm.
Then, in groove, polysilicon poly is filled.
Then, one layer of Si is grown by plasma reinforced chemical vapour deposition (PECVD)3N4As sealing coat, separation layer thickness is 20nm.
Then, by photoetching, other positions except grid and part N+ source region are exposed, as shown in Figure 9.
Then, deposit metal in front, form Schottky contacts, as source electrode.
Finally, deposit metal overleaf, form Ohmic contact, as drain electrode.
Embodiment 2
First on N+ substrate, extension generates N-drift layer, and the thickness of this drift layer is 15 ��m. and doping content is 1 �� 1015cm-3. The resistivity of N+ substrate is 0.015-0.02 ohmcm.
Then the mask plate on N-drift layer makes the figure needing doping by lithography, carries out the ion implantation technology of p-well, and the distance between each p-well is 1.5 ��m, and p-well is 1 ��m deeply. This part is used for forming Schottky contacts with metal.
Then, utilizing mask plate to make N+ source region figure by lithography, carry out the ion implantation technology in N+ source region, the degree of depth in N+ source region, less than p-well, is 0.5 ��m, and width is again smaller than p-well.
Then, utilize mask plate to make grid groove (U-shaped raceway groove) figure by lithography, adopt reactive ion etching (RIE) or sense coupling (ICP) to form groove, channel depth 7 ��m.
Then, forming oxide-film at channel bottom and sidewall, thickness is 100nm.
Then, in groove, polysilicon poly is filled.
Then, plasma reinforced chemical vapour deposition (PECVD) grows one layer of Si3N4As sealing coat, separation layer thickness is 30nm.
Then, by photoetching, other positions except grid and part N+ source region are exposed, as shown in Figure 9.
Then, deposit metal in front, form Schottky contacts, as source electrode.
Finally, deposit metal overleaf, form Ohmic contact, as drain electrode.
Embodiment 3
First on N+ substrate, extension generates N-drift layer, and the thickness of this drift layer is 50 ��m, and doping content is 8 �� 1014cm-3. The resistivity of N+ substrate is 0.015-0.02 ohmcm.
Then the mask plate on N-drift layer makes the figure needing doping by lithography, carries out the ion implantation technology of p-well, and the distance between each p-well is 1.5 ��m, and p-well is 1.5 ��m deeply. This part is used for forming Schottky contacts with metal.
Then, utilizing mask plate to make N+ source region figure by lithography, carry out the ion implantation technology in N+ source region, the degree of depth in N+ source region, less than p-well, is 0.5 ��m, and width is again smaller than p-well.
Then, utilize mask plate to make grid groove (U-shaped raceway groove) figure by lithography, adopt reactive ion etching (RIE) or sense coupling (ICP) to form groove, channel depth 10 ��m.
Then, forming oxide-film at channel bottom and sidewall, thickness is 100nm.
Then, in groove, polysilicon poly is filled.
Then, plasma reinforced chemical vapour deposition (PECVD) grows one layer of Si3N4As sealing coat, separation layer thickness is 20nm.
Then, by photoetching, other positions except grid and part N+ source region are exposed, as shown in Figure 9.
Then, deposit metal in front, form Schottky contacts, as source electrode.
Finally, deposit metal overleaf, form Ohmic contact, as drain electrode.
Embodiment 4
First on N+ substrate, extension generates N-drift layer, and the thickness of this drift layer is 100 ��m, and doping content is 5 �� 1014cm-3. The resistivity of N+ substrate is 0.015-0.02 ohmcm.
Then the mask plate on N-drift layer makes the figure needing doping by lithography, carries out the ion implantation technology of p-well, and the distance between each p-well is 2 ��m, and p-well is 2 ��m deeply. This part is used for forming Schottky contacts with metal.
Then, utilizing mask plate to make N+ source region figure by lithography, carry out the ion implantation technology in N+ source region, the degree of depth in N+ source region, less than p-well, is 0.5 ��m, and width is again smaller than p-well.
Then, utilize mask plate to make grid groove (U-shaped raceway groove) figure by lithography, adopt reactive ion etching (RIE) or sense coupling (ICP) to form groove, channel depth 10 ��m.
Then, forming oxide-film at channel bottom and sidewall, thickness is 100nm.
Then, in groove, polysilicon poly is filled.
Then, plasma reinforced chemical vapour deposition (PECVD) grows one layer of Si3N4As sealing coat, separation layer thickness is 20nm.
Then, by photoetching, other positions except grid and part N+ source region are exposed, as shown in Figure 9.
Then, deposit metal in front, form Schottky contacts, as source electrode.
Finally, deposit metal overleaf, form Ohmic contact, as drain electrode.
Embodiment 5
First on N+ substrate, extension generates N-drift layer, and the thickness of this drift layer is 112 ��m, and doping content is 7 �� 10-14cm-3. The resistivity of N+ substrate is 0.015-0.02 ohmcm.
Then the mask plate on N-drift layer makes the figure needing doping by lithography, carries out the ion implantation technology of p-well, and the distance between each p-well is 1.5 ��m, and p-well is 2 ��m deeply. This part is used for forming Schottky contacts with metal.
Then, utilizing mask plate to make N+ source region figure by lithography, carry out the ion implantation technology in N+ source region, the degree of depth in N+ source region, less than p-well, is 0.5 ��m, and width is again smaller than p-well.
Then, utilize mask plate to make grid groove (U-shaped raceway groove) figure by lithography, adopt reactive ion etching (RIE) or sense coupling (ICP) to form groove, channel depth 10 ��m.
Then, forming oxide-film at channel bottom and sidewall, thickness is 100nm.
Then, in groove, polysilicon poly is filled.
Then, plasma reinforced chemical vapour deposition (PECVD) grows one layer of Si3N4As sealing coat, separation layer thickness is 20nm.
Then, by photoetching, other positions except grid and part N+ source region are exposed, as shown in Figure 9.
Then, deposit metal in front, form Schottky contacts, as source electrode.
Finally, deposit metal overleaf, form Ohmic contact, as drain electrode.
Finally should be noted that: above example is only in order to illustrate that technical scheme is not intended to limit, although the present invention being described in detail with reference to above-described embodiment, those of ordinary skill in the field are it is understood that still can modify to the specific embodiment of the present invention or equivalent replacement, and without departing from any amendment of spirit and scope of the invention or equivalent replace, it all should be encompassed in the middle of scope of the presently claimed invention.
Claims (10)
1. the SiC trench MOSFET device of an integrated schottky diode, it is characterised in that described device includes:
1) trench MOSFET:
N+ substrate and N-drift layer thereon, described N-drift layer comprises the p-well having N+ source region being isolated from each other;
U-shaped raceway groove outside described p-well, described U-shaped channel surface has oxide layer, has grid in it;
Described grid and the described N+ source region of part are sealing coat;
Front is source electrode and the back side is drain electrode;
2) Schottky diode: the Schottky contacts that the N-drift layer between described p-well in described N-drift layer is formed with described source metal.
2. the device according to claims 1, it is characterised in that described Schottky diode is fly-wheel diode.
3. the device according to claims 1, it is characterised in that the resistivity of described N+ substrate is 0.015��0.02 ohmcm.
4. the device according to claims 1, it is characterised in that the thickness of described N-drift layer is 10��500 ��m, its doping content is 1 �� 1014��5 �� 1015cm-3��
5. the device according to claims 1, it is characterised in that the distance between described p-well is 1��3 ��m, its well depth is 1��3 ��m.
6. the device according to claims 1, it is characterised in that width and the degree of depth in described N+ source region are respectively less than described p-well.
7. the device according to claims 1, it is characterised in that the degree of depth of described U-shaped raceway groove is 4��10 ��m.
8. the device according to claims 1, it is characterised in that the thickness of described oxide layer is 50��150 ��m; The thickness of described sealing coat is 15��50 ��m.
9. the device according to claims 1, it is characterised in that described grid is n-type or the polysilicon of p-type degeneracy doping.
10. the manufacture method of the device described in a claim 1, it is characterised in that described method comprises the steps:
1) making mask on N+ substrate epitaxial N-drift layer surface and graphical, implanted dopant forms p-well;
2) making mask on described p-well surface and graphical, doping forms N+ source region;
3) making mask on described N-drift layer and graphical, etching SiC forms U-shaped raceway groove;
4) in described raceway groove inner surface deposited oxide layer;
5) in the described raceway groove with oxide layer, fill polysilicon poly, form grid;
6) on the described N+ source region of described grid and part, sealing coat is deposited;
7) deposit metal in described drift layer front and described substrate back, form source electrode and drain electrode respectively.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511032546.6A CN105633168A (en) | 2015-12-31 | 2015-12-31 | SiC grooved metal oxide semiconductor field effect transistor (MOSFET) with integration of Schottky diode and fabrication method of SiC grooved MOSFET |
| PCT/CN2016/108849 WO2017114113A1 (en) | 2015-12-31 | 2016-12-07 | Sic trench mosfet device for integrating schottky diode, and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511032546.6A CN105633168A (en) | 2015-12-31 | 2015-12-31 | SiC grooved metal oxide semiconductor field effect transistor (MOSFET) with integration of Schottky diode and fabrication method of SiC grooved MOSFET |
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| CN105633168A true CN105633168A (en) | 2016-06-01 |
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106783851A (en) * | 2017-01-19 | 2017-05-31 | 北京世纪金光半导体有限公司 | SiCJFET devices of integrated schottky diode and preparation method thereof |
| WO2017114113A1 (en) * | 2015-12-31 | 2017-07-06 | 全球能源互联网研究院 | Sic trench mosfet device for integrating schottky diode, and manufacturing method thereof |
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| CN116759424A (en) * | 2023-08-21 | 2023-09-15 | 深圳平创半导体有限公司 | Self-aligned trench type silicon carbide hybrid diode structure and preparation method thereof |
| CN117497580A (en) * | 2023-12-29 | 2024-02-02 | 深圳天狼芯半导体有限公司 | Heterojunction silicon carbide IGBT device, preparation method thereof and chip |
| CN117497580B (en) * | 2023-12-29 | 2024-04-19 | 深圳天狼芯半导体有限公司 | Heterojunction silicon carbide IGBT device, preparation method thereof and chip |
| CN118136672A (en) * | 2024-04-30 | 2024-06-04 | 河北博威集成电路有限公司 | Silicon carbide MOSFET device integrated with SBD and preparation method thereof |
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