WO2012034515A1 - High-voltage mos device and method for manufacturing the same - Google Patents

High-voltage mos device and method for manufacturing the same Download PDF

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Publication number
WO2012034515A1
WO2012034515A1 PCT/CN2011/079616 CN2011079616W WO2012034515A1 WO 2012034515 A1 WO2012034515 A1 WO 2012034515A1 CN 2011079616 W CN2011079616 W CN 2011079616W WO 2012034515 A1 WO2012034515 A1 WO 2012034515A1
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region
layer
source
trench
epitaxial layer
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PCT/CN2011/079616
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French (fr)
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Zhiyong Zhao
Le Wang
Linchun Gui
Kongwei Zhu
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Csmc Technologies Fab1 Co., Ltd.
Csmc Technologies Fab2 Co., Ltd.
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Publication of WO2012034515A1 publication Critical patent/WO2012034515A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Definitions

  • the present disclosure relates to a semiconductor device, and, particularly, to a high-voltage MOS device and a method for manufacturing a high-voltage MOS device.
  • a new type of high-voltage MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device has recently been developed which uses a "superj unction," that is, a combination of N " and P " type strips in parallel, as a drift region.
  • An example of a superjunction MOS device is a CoolMOSTM device commercially available from Infineon Technologies AG.
  • a superjunction MOS device can work under a high voltage, and at the same time provide an on-resistance (referred to as Rdson) one order of magnitude smaller than that of a conventional high voltage MOSFET.
  • a superjunction MOS device comprises an epitaxial layer formed on a growing substrate.
  • the epitaxial layer may be N-type doped or P-type doped. If the epitaxial layer is N-type doped, a P-type region extending from a top of the epitaxial layer to the growing substrate is formed in the epitaxial layer. On the other hand, if the epitaxial layer is P-type doped, an N-type region extending from the top of the epitaxial layer to the growing substrate is formed. Thus, a lateral P-N junction is formed in the epitaxial layer.
  • a source electrode is formed over the epitaxial layer and connected to the P-type (or N-type) region, and a drain electrode is formed below the growing substrate.
  • Figure 1 shows a structure of a conventional N-type superjunction MOS device.
  • the conventional N-type superjunction device includes a substrate 101.
  • the substrate 101 includes a body layer 102 and an epitaxial layer 103 formed on the body layer 102.
  • the body layer 102 has a drain region.
  • the body layer 102 and the epitaxial layer 103 are both N-type doped.
  • a first region 104 and a second region 105 are formed in the epitaxial layer 103.
  • the first region 104 and the second region 105 have the same doping state, and are doped with impurities having a conductivity type opposite to that for the epitaxial layer 103. That is, the first region 104 and second region 105 are P-type doped.
  • Doping state may include doping concentration and conductivity type of impurities.
  • the same doping state may refer to same conductivity type of impurities and substantially same doping concentration.
  • a first body region 106 and a second body region 107 are formed on the first region 104 and the second region 105, respectively.
  • the first body region 106 and the second body region 107 are both P-type doped and have the same doping state.
  • a first source region 108 and a second source region 109 are formed in the first body region 106 and the second body region 107, respectively.
  • the first source region 108 and the second source region 109 are both N-type doped and have the same doping state.
  • a first source electrode 110 is formed on an upper surface of the first source region 108, and a second source electrode 111 is formed on an upper surface of the second source region 109.
  • a gate oxide layer 112 is formed on an upper surface of the substrate 101 and between the first source electrode 110 and the second source electrode 111.
  • a gate electrode 113 is formed on an upper surface of the gate oxide layer 112.
  • a drain electrode 114 is formed on a lower surface of the body layer 102.
  • a length of a conducting channel is determined by lateral junction depths formed by diffusions during formation of the body regions 106 and 107 and the source regions 108 and 109. Therefore, the length of the conducting channel can be made very short.
  • the first region 104 and the second region 105 are formed by a conjunction injection process, and are doped with impurities having a conductivity type opposite to that in the epitaxial layer 103. Therefore, an increased amount of charges in a drift region caused by an improved doping concentration therein can be compensated, so as to keep the total doping concentration unchanged.
  • a thickness of the epitaxial layer 103 can ensure a high enough breakdown voltage, while a slightly higher doping concentration can reduce the on-resistance.
  • the critical dimension (CD) of the gate electrode 113 needs to be greater than the length of the conducting channel. Therefore, each device occupies a relatively large area on the substrate surface, resulting in a low utilization ratio of the substrate surface.
  • a high- voltage MOS device comprising a substrate, which includes a body layer and an epitaxial layer on the body layer.
  • the body layer includes a drain region, and the epitaxial layer is of a first conductivity type.
  • the device also includes a first region and a second region located in the epitaxial layer. The first region and the second region have a same doping state, and are of a second conductivity type opposite to the first conductivity type.
  • the device further includes a gate oxide layer formed on an inner surface of a trench located in the epitaxial layer and between the first region and the second region. A bottom of the trench extends into the body layer. A gate is formed on the gate oxide layer.
  • the device includes a first body region and a second body region located at sides of the trench.
  • the first body region and the second body region have a same doping state.
  • the device also includes a first source region and a second source region located in the first body region and the second body region, respectively.
  • the first source region and the second source region have a same doping state, and are of the first conductivity type.
  • a method for manufacturing a high-voltage MOS device comprises preparing a substrate, which comprises a body layer and an epitaxial layer located on the body layer.
  • the body layer includes a drain region and the epitaxial layer is of a first conductivity type.
  • the method also includes forming a first region and a second region in the epitaxial layer.
  • the first region and the second region have a same doping state, and are of a second conductivity type opposite to the first conductivity type.
  • the method further includes forming a trench in the epitaxial layer between the first region and the second region, forming a gate oxide layer on an inner surface of the trench, and forming a gate on the gate oxide layer.
  • the method further includes forming a first body region and a second body region at sides of the trench.
  • the first body region and the second body region have a same doping state.
  • the method includes forming a first source region and a second source region in the first body region and the second body region, respectively.
  • the first source region and the second source region have a same doping state.
  • Figure 1 is a schematic view showing a conventional superjunction MOS device.
  • Figure 2 is a schematic view showing a superjunction MOS device according to one embodiment consistent with the present disclosure.
  • Figure 3 is an electron microscopic picture showing the cross section of a trench in a superjunction MOS device according to one embodiment consistent with the present disclosure.
  • Figures 4-8 are schematic cross-sectional views showing a method for manufacturing the superjunction MOS device according to one embodiment consistent with the present disclosure.
  • Figure 2 shows a superj unction MOS device consistent with embodiments of the present disclosure.
  • the superjunction MOS device shown in Figure 2 includes a substrate 201, which includes a body layer 202 and an epitaxial layer 203 formed on the body layer 202.
  • the body layer 202 includes a drain region.
  • the superjunction MOS device consistent with embodiments of the present disclosure also includes a first region 204 and a second region 205 formed in the epitaxial layer 203, and extending vertically through the entire epitaxial layer 203.
  • the conductivity type of dopant in the first region 204 and the second region 205 may be opposite to that in the epitaxial layer 203.
  • Such doping scheme may compensate the increased amount of charges in a drift region caused by an increased doping concentration in the epitaxial layer 203. Thus, the total doping concentration may be kept substantially constant.
  • the first region 204 and the second region 205 may have the same doping state.
  • the superjunction MOS device consistent with embodiments of the present disclosure also includes a trench formed in the epitaxial layer 203 and located between the first region 204 and the second region 205, with its bottom extending into the body layer 202.
  • the trench is filled with a gate oxide layer 206 and a gate 207. Extending of the trench into the body layer 202 may prevent leakage current from occurring in the epitaxial layer 203, and thus improve the breakdown voltage and decrease the on-resistance of the device.
  • the superjunction MOS device consistent with embodiments of the present disclosure further includes a first body region 208 and a second body region 209 formed at the both sides of the trench.
  • the first body region 208 and the second body region 209 may have the same doping state.
  • first body region 208 may reside completely inside the first region 204, or may reside partially in the first region 204 and partially outside the first region 204 but still in the epitaxial layer 203.
  • second body region 209 may reside completely inside the second region 205, or may reside partially in the second region 205 and partially outside the second region 205 but still in the epitaxial layer 203.
  • the superj unction MOS device consistent with embodiments of the present disclosure also includes a first source region 210 located in the first body region 208 and a second source region 211 located in the second body region 209.
  • the first source region 210 and the second source region 211 may have the same doping state, and the conductivity type of doping impurities in the first source region 210 and the second source region 211 may be opposite to that in the first body region 208 and the second body region 209.
  • a drain electrode 215 is formed on a lower surface of the substrate 201.
  • a first source electrode 212 and a second source electrode 213 are formed on an upper surface of the device at positions above the first source region 210 and the second source region 211, respectively, and located on the both sides of the trench.
  • a gate electrode 214 is formed on the upper surface of the device and between the first source electrode 212 and the second source electrode 213.
  • An interlayer dielectric layer (i.e. an ILD layer) 216 is formed on an upper surface of the substrate 201, but below the first source electrode 212, second source electrode 213, and gate electrode 214.
  • a first through hole 217 is formed in the interlayer dielectric layer 216 and filled with a metal to connect the first source region 210 and the first source electrode 212.
  • a second through hole 218 is formed in the interlayer dielectric layer 216 and filled with a metal to fill the second source region 211 and the second source electrode 213.
  • a third through hole 219 is formed in the interlayer dielectric layer 216 and filled with a metal to connect the gate 207 and the gate electrode 214.
  • the superjunction MOS device consistent with embodiments of the present disclosure may be, for example, an N-type superjunction MOS device.
  • the first region 204 and the second region 205 may be of P-type doping
  • the epitaxial layer 203 may be of N-type doping
  • the body layer 202 may be of N-type doping
  • the first body region 208 and the second body region 209 may be of P-type doping
  • the first source region 210 and the second source region 211 may be of N-type doping.
  • the doping impurities for N-type doping may be phosphorus or other pentavalent elements, and the doping impurities may be boron or other trivalent elements.
  • the doping impurities in the first region 204 and the second region 205 may be phosphorus, with a doping dose of 2E cm "
  • the doping impurities in the first body region 208 and the second body region 209 may be boron, with a doping dose of 4E cm "
  • the doping impurities in the first source region 210 and the second source region 211 may be phosphorus, with a doping dose of 6E cm " .
  • the epitaxial layer 203 may be an N-type epitaxial layer. Doping dose in the epitaxial layer 203 may be controlled appropriately according to the specific requirements of the device.
  • the superjunction MOS device consistent with embodiments of the present disclosure may also be a P-type superjunction MOS device, in which the first region 204 and the second region 205 may be of N-type doping, the epitaxial layer 203 may be of P-type doping, the body layer 202 may be of P-type doping, the first body region 208 and the second body region 209 may be of N-type doping, and the first source region 210 and the second source region 211 may be of P-type doping.
  • the conducting channel in the superjunction MOS device may be made perpendicular to the device surface by utilizing a trench manufacturing process.
  • This method may also be applied in a process of manufacturing other surface-type devices with a lateral carrier flow to change the direction of the conducting channel, thus reducing the device area and improving utilization ratio of the substrate.
  • the bottom of the trench (which is filled with the gate oxide layer 206 and the gate 207) of the superjunction MOS device consistent with embodiments of the present disclosure extends into the body layer 202.
  • Such arrangement may improve the breakdown voltage.
  • the on-resistance may be decreased.
  • the resistance of the epitaxial layer 203 may be made equal to the resistance of the first region 204 and the second region 205. That is, the doping concentration of the first region 204 and the second region 205 may be made to compensate the increased doping concentration in the epitaxial layer 203 for reducing the on-resistance.
  • the resistance value of the epitaxial layer 203 as well as the resistance values of the first region 204 and the second region 205 can be measured.
  • the breakdown voltage may be improved, the on-resistance may be reduced, and thus the on-current may be improved.
  • the conducting channel may be made perpendicular to the device surface, thus reducing the device area and improving utilization ratio of the substrate surface.
  • the superjunction MOS device consistent with embodiments of the present disclosure needs smaller device area as compared to a conventional superjunction MOS device, when a same conducting channel length is required. For example, if a conducting channel length of 1 ⁇ is required, the conventional superjunction device requires that a critical dimension of the gate be larger than 1 ⁇ because its conducting channel is parallel to the device surface.
  • the channel length may be controlled by controlling junction depths formed by diffusions when forming the first and second body regions 208 and 209 and the first and second source regions 210 and 211.
  • the critical dimension of the trench i.e., the width of the trench, can be very small, even at the order of magnitude of nm, as long as the isolation function of the trench can be achieved. In this way, the device area is reduced, and the utilization ratio of the substrate is improved.
  • Figure 3 is a sectional view of a trench according to some embodiments of the present disclosure.
  • An angle between a bottom and a sidewall of the trench, which is denoted by reference numeral 31, is greater than 90° and smaller than 95°, so as to avoid the occurrence of leakage current.
  • An upper corner of the trench, i.e., the joint of the gate electrode and the source electrode, which is denoted by reference numeral 32, is of a smooth structure, so as to avoid point discharge.
  • Figures 4-8 are sectional views showing a method for manufacturing the superjunction MOS device consistent with embodiments of the present disclosure.
  • the method for forming an N-type superjunction MOS device is shown as an example.
  • a substrate 401 is prepared.
  • the substrate 401 includes a body layer 402 and an epitaxial layer 403 on the body layer 402.
  • the body layer 402 includes a drain region.
  • the body layer 402 and the epitaxial layer 403 are of N-type doping.
  • a material for the substrate 401 may include a semiconductor, such as silicon or silicon germanium (SiGe) with a monocrystal, a polycrystal or an amorphous structure.
  • the substrate 401 may include a compound semiconductor material, such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, an alloy semiconductor, or a combination thereof.
  • the substrate 401 may include a silicon-on-insulator (SOI).
  • SOI silicon-on-insulator
  • the substrate 401 may also include other materials, such as a multi-layer epitaxial layer or buried layer.
  • the body layer 402 may be silicon
  • the epitaxial layer 403 may be an N-type epitaxial layer grown on the body layer 402.
  • a thickness of the epitaxial layer 403 may be determined according to the specific application requirements of the device.
  • first region 404 and a second region 405 are formed in the epitaxial layer 403.
  • the first region 404 and the second region 405 may have the same doping state, and may be doped with impurities having a conductivity type opposite to that of the impurities in the epitaxial layer 403.
  • the first region 404 and the second region 405 may be of P-type doping.
  • the method for forming the first region 404 and the second region 405 may include the following steps: forming photoresist patterns for the first region 404 and the second region 405 on a surface of the epitaxial layer 403 by a photolithography process, and forming the first region 404 and the second region 405 by an ion implantation using the photoresist patterns (not shown) as a mask.
  • the method for forming the first region 404 and the second region 405 may include the following steps: growing a silicon dioxide film on the epitaxial layer 403, forming silicon dioxide patterns for the first region 404 and the second region 405 on the surface of the N-type epitaxial layer 403 by a photolithography process, forming trenches by etching the epitaxial layer 403 using the silicon dioxide patterns as a mask, the depth and width of the trenches being the same as the depth and width of the first region 404 and the second region 405 required for the superjunction device, and growing P-type epitaxial silicon by an epitaxial growth method to fill the trenches, so as to form the first region 404 and the second region 405.
  • the method may further include: removing the P-type epitaxial silicon grown on the surface of the silicon dioxide film by an etch back process using the silicon dioxide film formed on the surface of the epitaxial layer 403 as an etch stop layer, so that surfaces of the first region 404 and the second region 405 are flush with the surface of the epitaxial layer 403 to ensure a surface smoothness of the wafer, and removing the silicon dioxide film by wet etching or other methods.
  • a trench 406 is formed in the epitaxial layer 403 between the first region 404 and the second region 405. A bottom of the trench 406 extends into the body layer 402.
  • the trench 406 may be formed by: forming a photoresist pattern for the trench 406 on the surface of the epitaxial layer 403 by a photolithography process, and forming the trench 406 in the epitaxial layer by a plasma etching using the photoresist pattern (not shown) as a mask.
  • a gate oxide layer 407 is formed on an inner surface of the trench 406, and a gate 408 is formed on the gate oxide layer 407.
  • the gate oxide layer 407 and the gate 408 may be formed by a process described below.
  • an oxide layer may be formed on the surface of the substrate by a thermal oxidation process.
  • the oxide layer may cover the substrate surface including the inner surface of the trench 406.
  • the oxide layer may at least include silicon oxide.
  • a polysilicon layer (not shown) may be deposited on the oxide layer.
  • the oxide layer and the polysilicon layer outside the trench 406 may be removed by a chemical mechanical polishing process or an etching process.
  • the oxide layer the polysilicon layer left inside the trench may form the gate oxide layer 407 and the gate 408, respectively.
  • the gate 408 may include doped polysilicon or a laminated layer made up of polysilicon and metallic silicide on the polysilicon.
  • a first body region 409 and a second body region 410 are formed on both sides of the trench and located in the first region 404 and the second region 405, respectively.
  • the first body region 409 and the second body region 410 may have the same doping state.
  • a first source region 411 is formed in the first body region 409, and a second source region 412 is formed in the second body region 410.
  • the first source region 411 and the second source region 412 may have the same doping state.
  • the first body region 409 and the second body region 410 are of P-type doping
  • the first source region 411 and the second source region 412 are of N-type doping.
  • various doping processes may be employed during the manufacturing of the superj unction MOS device, such as doping in melt growth, gas phase doping, neutron transmutation doping, ion implantation, surface coating doping, and etc.
  • the first body region 409 and the second body region 410, as well as the first source region 411 and the second source region 412, may be formed by ion implantation.
  • the first source region 411 and the second source region 412 may be formed by: forming photoresist patterns for the first source region 411 and the second source region 412 at both sides of the trench by a photolithography process, and forming the first source region 411 and the second source region 412 in the first body region 409 and the second body region 410, respectively, by ion implantation using the photoresist patterns as a mask.
  • a drain electrode 413 is formed on the lower surface of the substrate 401.
  • a first source electrode 414 and a second source electrode 415 are formed on the upper surface of the device at locations corresponding to the first source region 411 and the second source region 412, respectively, and located at both sides of the trench.
  • a gate electrode 416 is formed on the upper surface of the device and between the first source electrode 414 and the second source electrode 415.
  • the drain electrode 413 may be formed by sputtering metal on the bottom surface of the substrate 401.
  • the first source electrode 414 and the second source electrode 415 may be formed as described below.
  • an isolation layer i.e., an interlayer dielectric layer 417
  • photoresist patterns for a first through hole 418 and a second through hole 419 are formed on a surface of the interlayer dielectric layer 417 by a photolithography process.
  • the first through hole 418 and the second through hole 419 are then formed in the interlayer dielectric layer 417 by an etching process using the photoresis patterns (not shown) as a mask.
  • a metal is deposited in the first through hole 418 and the second through hole 419 and on the surface of the interlayer dielectric layer 417 to form the first source electrode 414 and the second source electrode 415.
  • the first source electrode 414 and the second source electrode 415 are connected with the first source region 411 and the second source region 412 through the first through hole 418 and the second through hole 419, respectively.
  • the gate electrode 416 may be formed in a manner similar to that for forming the first source electrode 414 and the second source electrode 415. That is, a photoresist pattern for a third through hole 420 is formed on the surface of the interlayer dielectric layer 417 by a photolithography process. The third through hole 420 is formed in the interlayer dielectric layer 417 by an etching process using the photoresist pattern (not shown) as a mask. A metal is deposited in the third through hole 420 and on the surface of the interlayer dielectric layer 417 to form the gate electrode 416. The gate electrode 416 is connected with the gate 408 through the third through hole 420.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A high-voltage MOS device comprising a substrate, which includes a body layer and an epitaxial layer formed on the body layer and being of a first conductivity type. The device also includes a first and a second regions located in the epitaxial layer. The first and second regions have a same doping state, and are of a second conductivity type. The device further includes a gate oxide layer formed on an inner surface of a trench located in the epitaxial layer and between the first and second regions and a gate formed on the gate oxide layer. A bottom of the trench extends into the body layer. The device also includes a first and a second body regions located at sides of the trench, and having a same doping state. The device also includes a first and a second source regions located in the first and second body regions, respectively. The first and second source regions have a same doping state, and are of the first conductivity type.

Description

HIGH- VOLTAGE MOS DEVICE AND
METHOD FOR MANUFACTURING THE SAME
TECHNOLOGY FIELD [0001] The present disclosure relates to a semiconductor device, and, particularly, to a high-voltage MOS device and a method for manufacturing a high-voltage MOS device.
BACKGROUND
[0002] A new type of high-voltage MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device has recently been developed which uses a "superj unction," that is, a combination of N" and P" type strips in parallel, as a drift region. An example of a superjunction MOS device is a CoolMOS™ device commercially available from Infineon Technologies AG. A superjunction MOS device can work under a high voltage, and at the same time provide an on-resistance (referred to as Rdson) one order of magnitude smaller than that of a conventional high voltage MOSFET.
[0003] A superjunction MOS device comprises an epitaxial layer formed on a growing substrate. The epitaxial layer may be N-type doped or P-type doped. If the epitaxial layer is N-type doped, a P-type region extending from a top of the epitaxial layer to the growing substrate is formed in the epitaxial layer. On the other hand, if the epitaxial layer is P-type doped, an N-type region extending from the top of the epitaxial layer to the growing substrate is formed. Thus, a lateral P-N junction is formed in the epitaxial layer. A source electrode is formed over the epitaxial layer and connected to the P-type (or N-type) region, and a drain electrode is formed below the growing substrate. When working under a high voltage, both a vertical electric field from the drain electrode to the source electrode and a lateral electric field generated by the lateral P-N region exist in the superjunction MOS device. Therefore, the electric field can distribute uniformly in the lateral direction and the vertical direction, such that a high voltage MOS transistor can be fabricated on an epitaxial wafer with a low resistivity.
[0004] Figure 1 shows a structure of a conventional N-type superjunction MOS device. The conventional N-type superjunction device includes a substrate 101. The substrate 101 includes a body layer 102 and an epitaxial layer 103 formed on the body layer 102. The body layer 102 has a drain region. The body layer 102 and the epitaxial layer 103 are both N-type doped.
[0005] As shown in Figure 1, a first region 104 and a second region 105 are formed in the epitaxial layer 103. The first region 104 and the second region 105 have the same doping state, and are doped with impurities having a conductivity type opposite to that for the epitaxial layer 103. That is, the first region 104 and second region 105 are P-type doped. Doping state may include doping concentration and conductivity type of impurities. The same doping state may refer to same conductivity type of impurities and substantially same doping concentration.
[0006] A first body region 106 and a second body region 107 are formed on the first region 104 and the second region 105, respectively. The first body region 106 and the second body region 107 are both P-type doped and have the same doping state.
[0007] A first source region 108 and a second source region 109 are formed in the first body region 106 and the second body region 107, respectively. The first source region 108 and the second source region 109 are both N-type doped and have the same doping state.
[0008] As shown in Figure 1, a first source electrode 110 is formed on an upper surface of the first source region 108, and a second source electrode 111 is formed on an upper surface of the second source region 109. A gate oxide layer 112 is formed on an upper surface of the substrate 101 and between the first source electrode 110 and the second source electrode 111. A gate electrode 113 is formed on an upper surface of the gate oxide layer 112. A drain electrode 114 is formed on a lower surface of the body layer 102.
[0009] In the conventional superj unction MOS device described above, a length of a conducting channel is determined by lateral junction depths formed by diffusions during formation of the body regions 106 and 107 and the source regions 108 and 109. Therefore, the length of the conducting channel can be made very short. Moreover, the first region 104 and the second region 105 are formed by a conjunction injection process, and are doped with impurities having a conductivity type opposite to that in the epitaxial layer 103. Therefore, an increased amount of charges in a drift region caused by an improved doping concentration therein can be compensated, so as to keep the total doping concentration unchanged. A thickness of the epitaxial layer 103 can ensure a high enough breakdown voltage, while a slightly higher doping concentration can reduce the on-resistance. [0010] However, in the above-mentioned superj unction structure, since the conducting channel is parallel to the surface of the device, the critical dimension (CD) of the gate electrode 113 needs to be greater than the length of the conducting channel. Therefore, each device occupies a relatively large area on the substrate surface, resulting in a low utilization ratio of the substrate surface.
SUMMARY OF THE DISCLOSURE
[0011] In accordance with the present disclosure, there is provided a high- voltage MOS device. The device comprises a substrate, which includes a body layer and an epitaxial layer on the body layer. The body layer includes a drain region, and the epitaxial layer is of a first conductivity type. The device also includes a first region and a second region located in the epitaxial layer. The first region and the second region have a same doping state, and are of a second conductivity type opposite to the first conductivity type. The device further includes a gate oxide layer formed on an inner surface of a trench located in the epitaxial layer and between the first region and the second region. A bottom of the trench extends into the body layer. A gate is formed on the gate oxide layer. Furthermore, the device includes a first body region and a second body region located at sides of the trench. The first body region and the second body region have a same doping state. The device also includes a first source region and a second source region located in the first body region and the second body region, respectively. The first source region and the second source region have a same doping state, and are of the first conductivity type.
[0012] In accordance with the present disclosure, there is also provided a method for manufacturing a high-voltage MOS device. The method comprises preparing a substrate, which comprises a body layer and an epitaxial layer located on the body layer. The body layer includes a drain region and the epitaxial layer is of a first conductivity type. The method also includes forming a first region and a second region in the epitaxial layer. The first region and the second region have a same doping state, and are of a second conductivity type opposite to the first conductivity type. The method further includes forming a trench in the epitaxial layer between the first region and the second region, forming a gate oxide layer on an inner surface of the trench, and forming a gate on the gate oxide layer. A bottom of the trench extends into the body layer. The method further includes forming a first body region and a second body region at sides of the trench. The first body region and the second body region have a same doping state. Furthermore, the method includes forming a first source region and a second source region in the first body region and the second body region, respectively. The first source region and the second source region have a same doping state.
[0013] Features consistent with the present disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present disclosure. Such features will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The above-mentioned features of the present disclosure will be more obvious with reference to the drawings. In all drawings, the same reference numeral indicates similar parts. The drawings may not be drawn to scale, but merely to show the main idea of the present disclosure.
[0015] Figure 1 is a schematic view showing a conventional superjunction MOS device.
[0016] Figure 2 is a schematic view showing a superjunction MOS device according to one embodiment consistent with the present disclosure.
[0017] Figure 3 is an electron microscopic picture showing the cross section of a trench in a superjunction MOS device according to one embodiment consistent with the present disclosure; and
[0018] Figures 4-8 are schematic cross-sectional views showing a method for manufacturing the superjunction MOS device according to one embodiment consistent with the present disclosure.
DESCRIPTION OF EMBODIMENTS
[0019] Hereinafter, embodiments of the present disclosure will be described in detail in conjunction with the drawings. More specific details will be set forth in the following to facilitate understanding of the disclosure. However, the disclosure can also be implemented by other ways different from those described herein. Those skilled in the art can extend the applications of the present disclosure without departing from the spirit thereof, and thus the invention is not limited to particular embodiments disclosed hereinafter.
[0020] In addition, the disclosure is described in conjunction with schematic drawings. For ease of illustration, sectional views showing the structure of the device may be enlarged partially. The drawings are merely schematic, which should not be understood as limiting the scope of the present invention. Furthermore, in an actual manufacture process, the sizes in all three dimensions, i.e., length, width, and depth, should be considered.
[0021] Figure 2 shows a superj unction MOS device consistent with embodiments of the present disclosure. The superjunction MOS device shown in Figure 2 includes a substrate 201, which includes a body layer 202 and an epitaxial layer 203 formed on the body layer 202. The body layer 202 includes a drain region.
[0022] The superjunction MOS device consistent with embodiments of the present disclosure also includes a first region 204 and a second region 205 formed in the epitaxial layer 203, and extending vertically through the entire epitaxial layer 203. The conductivity type of dopant in the first region 204 and the second region 205 may be opposite to that in the epitaxial layer 203. Such doping scheme may compensate the increased amount of charges in a drift region caused by an increased doping concentration in the epitaxial layer 203. Thus, the total doping concentration may be kept substantially constant. In some embodiments, the first region 204 and the second region 205 may have the same doping state.
[0023] As shown in Figure 2, the superjunction MOS device consistent with embodiments of the present disclosure also includes a trench formed in the epitaxial layer 203 and located between the first region 204 and the second region 205, with its bottom extending into the body layer 202. The trench is filled with a gate oxide layer 206 and a gate 207. Extending of the trench into the body layer 202 may prevent leakage current from occurring in the epitaxial layer 203, and thus improve the breakdown voltage and decrease the on-resistance of the device.
[0024] The superjunction MOS device consistent with embodiments of the present disclosure further includes a first body region 208 and a second body region 209 formed at the both sides of the trench. The first body region 208 and the second body region 209 may have the same doping state.
[0025] It is noted that the first body region 208 may reside completely inside the first region 204, or may reside partially in the first region 204 and partially outside the first region 204 but still in the epitaxial layer 203. Similarly, the second body region 209 may reside completely inside the second region 205, or may reside partially in the second region 205 and partially outside the second region 205 but still in the epitaxial layer 203.
[0026] The superj unction MOS device consistent with embodiments of the present disclosure also includes a first source region 210 located in the first body region 208 and a second source region 211 located in the second body region 209. The first source region 210 and the second source region 211 may have the same doping state, and the conductivity type of doping impurities in the first source region 210 and the second source region 211 may be opposite to that in the first body region 208 and the second body region 209.
[0027] Furthermore, in the superjunction MOS device consistent with embodiments of the present disclosure, a drain electrode 215 is formed on a lower surface of the substrate 201. A first source electrode 212 and a second source electrode 213 are formed on an upper surface of the device at positions above the first source region 210 and the second source region 211, respectively, and located on the both sides of the trench. A gate electrode 214 is formed on the upper surface of the device and between the first source electrode 212 and the second source electrode 213. An interlayer dielectric layer (i.e. an ILD layer) 216 is formed on an upper surface of the substrate 201, but below the first source electrode 212, second source electrode 213, and gate electrode 214. A first through hole 217 is formed in the interlayer dielectric layer 216 and filled with a metal to connect the first source region 210 and the first source electrode 212. A second through hole 218 is formed in the interlayer dielectric layer 216 and filled with a metal to fill the second source region 211 and the second source electrode 213. A third through hole 219 is formed in the interlayer dielectric layer 216 and filled with a metal to connect the gate 207 and the gate electrode 214.
[0028] The superjunction MOS device consistent with embodiments of the present disclosure may be, for example, an N-type superjunction MOS device. The first region 204 and the second region 205 may be of P-type doping, the epitaxial layer 203 may be of N-type doping, the body layer 202 may be of N-type doping, the first body region 208 and the second body region 209 may be of P-type doping, and the first source region 210 and the second source region 211 may be of N-type doping.
[0029] In some embodiments, the doping impurities for N-type doping may be phosphorus or other pentavalent elements, and the doping impurities may be boron or other trivalent elements. In some embodiments, the doping impurities in the first region 204 and the second region 205 may be phosphorus, with a doping dose of 2E cm" , the doping impurities in the first body region 208 and the second body region 209 may be boron, with a doping dose of 4E cm" , and the doping impurities in the first source region 210 and the second source region 211 may be phosphorus, with a doping dose of 6E cm" . In some embodiments, the epitaxial layer 203 may be an N-type epitaxial layer. Doping dose in the epitaxial layer 203 may be controlled appropriately according to the specific requirements of the device.
[0030] The superjunction MOS device consistent with embodiments of the present disclosure may also be a P-type superjunction MOS device, in which the first region 204 and the second region 205 may be of N-type doping, the epitaxial layer 203 may be of P-type doping, the body layer 202 may be of P-type doping, the first body region 208 and the second body region 209 may be of N-type doping, and the first source region 210 and the second source region 211 may be of P-type doping.
[0031] Consistent with embodiments of the present disclosure, the conducting channel in the superjunction MOS device may be made perpendicular to the device surface by utilizing a trench manufacturing process. This method may also be applied in a process of manufacturing other surface-type devices with a lateral carrier flow to change the direction of the conducting channel, thus reducing the device area and improving utilization ratio of the substrate.
[0032] As shown in Figure 2, the bottom of the trench (which is filled with the gate oxide layer 206 and the gate 207) of the superjunction MOS device consistent with embodiments of the present disclosure extends into the body layer 202. Such arrangement may improve the breakdown voltage. In addition, by increasing the doping concentration in the epitaxial layer 203, the on-resistance may be decreased. In some embodiments, in order to maximize the breakdown voltage, the resistance of the epitaxial layer 203 may be made equal to the resistance of the first region 204 and the second region 205. That is, the doping concentration of the first region 204 and the second region 205 may be made to compensate the increased doping concentration in the epitaxial layer 203 for reducing the on-resistance. The resistance value of the epitaxial layer 203 as well as the resistance values of the first region 204 and the second region 205 can be measured. Thus, consistent with embodiments of the present disclosure, by controlling the depth of the trench and the doping concentration of the epitaxial layer 203, the breakdown voltage may be improved, the on-resistance may be reduced, and thus the on-current may be improved.
[0033] Consistent with embodiments of the present disclosure, by forming the trench in the epitaxial layer 203 between the first region 204 and the second region 205, and forming the gate oxide layer 206 and the gate region 207 in the trench, the conducting channel may be made perpendicular to the device surface, thus reducing the device area and improving utilization ratio of the substrate surface.
[0034] Specifically, the superjunction MOS device consistent with embodiments of the present disclosure needs smaller device area as compared to a conventional superjunction MOS device, when a same conducting channel length is required. For example, if a conducting channel length of 1 μιη is required, the conventional superjunction device requires that a critical dimension of the gate be larger than 1 μιη because its conducting channel is parallel to the device surface. On the other hand, in the superjunction MOS device consistent with embodiments of the present disclosure, the channel length may be controlled by controlling junction depths formed by diffusions when forming the first and second body regions 208 and 209 and the first and second source regions 210 and 211. The critical dimension of the trench, i.e., the width of the trench, can be very small, even at the order of magnitude of nm, as long as the isolation function of the trench can be achieved. In this way, the device area is reduced, and the utilization ratio of the substrate is improved.
[0035] Figure 3 is a sectional view of a trench according to some embodiments of the present disclosure. An angle between a bottom and a sidewall of the trench, which is denoted by reference numeral 31, is greater than 90° and smaller than 95°, so as to avoid the occurrence of leakage current. An upper corner of the trench, i.e., the joint of the gate electrode and the source electrode, which is denoted by reference numeral 32, is of a smooth structure, so as to avoid point discharge.
[0036] Figures 4-8 are sectional views showing a method for manufacturing the superjunction MOS device consistent with embodiments of the present disclosure. In Figures 4-8, the method for forming an N-type superjunction MOS device is shown as an example.
[0037] As show in Figure 4, first, a substrate 401 is prepared. The substrate 401 includes a body layer 402 and an epitaxial layer 403 on the body layer 402. The body layer 402 includes a drain region. The body layer 402 and the epitaxial layer 403 are of N-type doping.
[0038] In some embodiments, a material for the substrate 401 may include a semiconductor, such as silicon or silicon germanium (SiGe) with a monocrystal, a polycrystal or an amorphous structure. In some embodiments, the substrate 401 may include a compound semiconductor material, such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, an alloy semiconductor, or a combination thereof. In some embodiments, the substrate 401 may include a silicon-on-insulator (SOI). In addition, the substrate 401 may also include other materials, such as a multi-layer epitaxial layer or buried layer.
[0039] In some embodiments, the body layer 402 may be silicon, and the epitaxial layer 403 may be an N-type epitaxial layer grown on the body layer 402. A thickness of the epitaxial layer 403 may be determined according to the specific application requirements of the device.
[0040] Next, a first region 404 and a second region 405 are formed in the epitaxial layer 403. The first region 404 and the second region 405 may have the same doping state, and may be doped with impurities having a conductivity type opposite to that of the impurities in the epitaxial layer 403. In some embodiments, the first region 404 and the second region 405 may be of P-type doping.
[0041] In some embodiments, the method for forming the first region 404 and the second region 405 may include the following steps: forming photoresist patterns for the first region 404 and the second region 405 on a surface of the epitaxial layer 403 by a photolithography process, and forming the first region 404 and the second region 405 by an ion implantation using the photoresist patterns (not shown) as a mask.
[0042] In some embodiments, the method for forming the first region 404 and the second region 405 may include the following steps: growing a silicon dioxide film on the epitaxial layer 403, forming silicon dioxide patterns for the first region 404 and the second region 405 on the surface of the N-type epitaxial layer 403 by a photolithography process, forming trenches by etching the epitaxial layer 403 using the silicon dioxide patterns as a mask, the depth and width of the trenches being the same as the depth and width of the first region 404 and the second region 405 required for the superjunction device, and growing P-type epitaxial silicon by an epitaxial growth method to fill the trenches, so as to form the first region 404 and the second region 405.
[0043] In the embodiments described in the previous paragraph, after the first region 404 and the second region 405 are formed, the method may further include: removing the P-type epitaxial silicon grown on the surface of the silicon dioxide film by an etch back process using the silicon dioxide film formed on the surface of the epitaxial layer 403 as an etch stop layer, so that surfaces of the first region 404 and the second region 405 are flush with the surface of the epitaxial layer 403 to ensure a surface smoothness of the wafer, and removing the silicon dioxide film by wet etching or other methods.
[0044] As shown in Figure 5, a trench 406 is formed in the epitaxial layer 403 between the first region 404 and the second region 405. A bottom of the trench 406 extends into the body layer 402.
[0045] In some embodiments, the trench 406 may be formed by: forming a photoresist pattern for the trench 406 on the surface of the epitaxial layer 403 by a photolithography process, and forming the trench 406 in the epitaxial layer by a plasma etching using the photoresist pattern (not shown) as a mask.
[0046] As shown in Figure 6, a gate oxide layer 407 is formed on an inner surface of the trench 406, and a gate 408 is formed on the gate oxide layer 407.
[0047] In some embodiments, the gate oxide layer 407 and the gate 408 may be formed by a process described below. First, an oxide layer may be formed on the surface of the substrate by a thermal oxidation process. The oxide layer may cover the substrate surface including the inner surface of the trench 406. The oxide layer may at least include silicon oxide. Then, a polysilicon layer (not shown) may be deposited on the oxide layer. The oxide layer and the polysilicon layer outside the trench 406 may be removed by a chemical mechanical polishing process or an etching process. The oxide layer the polysilicon layer left inside the trench may form the gate oxide layer 407 and the gate 408, respectively. In some embodiments, the gate 408 may include doped polysilicon or a laminated layer made up of polysilicon and metallic silicide on the polysilicon.
[0048] As shown in Figure 7, a first body region 409 and a second body region 410 are formed on both sides of the trench and located in the first region 404 and the second region 405, respectively. The first body region 409 and the second body region 410 may have the same doping state.
[0049] A first source region 411 is formed in the first body region 409, and a second source region 412 is formed in the second body region 410. The first source region 411 and the second source region 412 may have the same doping state. In some embodiments, the first body region 409 and the second body region 410 are of P-type doping, and the first source region 411 and the second source region 412 are of N-type doping.
[0050] Consistent with embodiments of the present disclosure, various doping processes may be employed during the manufacturing of the superj unction MOS device, such as doping in melt growth, gas phase doping, neutron transmutation doping, ion implantation, surface coating doping, and etc. In some embodiments, the first body region 409 and the second body region 410, as well as the first source region 411 and the second source region 412, may be formed by ion implantation.
[0051] In some embodiments, the first source region 411 and the second source region 412 may be formed by: forming photoresist patterns for the first source region 411 and the second source region 412 at both sides of the trench by a photolithography process, and forming the first source region 411 and the second source region 412 in the first body region 409 and the second body region 410, respectively, by ion implantation using the photoresist patterns as a mask.
[0052] As shown in Figure 8, a drain electrode 413 is formed on the lower surface of the substrate 401. A first source electrode 414 and a second source electrode 415 are formed on the upper surface of the device at locations corresponding to the first source region 411 and the second source region 412, respectively, and located at both sides of the trench. A gate electrode 416 is formed on the upper surface of the device and between the first source electrode 414 and the second source electrode 415. [0053] In some embodiments, the drain electrode 413 may be formed by sputtering metal on the bottom surface of the substrate 401.
[0054] In some embodiments, the first source electrode 414 and the second source electrode 415 may be formed as described below. First, an isolation layer, i.e., an interlayer dielectric layer 417, is formed on the upper surface of the substrate 401. Then photoresist patterns for a first through hole 418 and a second through hole 419 are formed on a surface of the interlayer dielectric layer 417 by a photolithography process. The first through hole 418 and the second through hole 419 are then formed in the interlayer dielectric layer 417 by an etching process using the photoresis patterns (not shown) as a mask. A metal is deposited in the first through hole 418 and the second through hole 419 and on the surface of the interlayer dielectric layer 417 to form the first source electrode 414 and the second source electrode 415. The first source electrode 414 and the second source electrode 415 are connected with the first source region 411 and the second source region 412 through the first through hole 418 and the second through hole 419, respectively.
[0055] In some embodiments, the gate electrode 416 may be formed in a manner similar to that for forming the first source electrode 414 and the second source electrode 415. That is, a photoresist pattern for a third through hole 420 is formed on the surface of the interlayer dielectric layer 417 by a photolithography process. The third through hole 420 is formed in the interlayer dielectric layer 417 by an etching process using the photoresist pattern (not shown) as a mask. A metal is deposited in the third through hole 420 and on the surface of the interlayer dielectric layer 417 to form the gate electrode 416. The gate electrode 416 is connected with the gate 408 through the third through hole 420.
[0056] The above embodiments are merely for exemplification purpose, and are not intended to limit the invention in any form.
[0057] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Claims

1. A high-voltage MOS device, comprising: a substrate, the substrate comprising: a body layer; and an epitaxial layer on the body layer, the epitaxial layer being of a first conductivity type; a first region and a second region located in the epitaxial layer, the first region and the second region having a same doping state, and the first region and the second region being of a second conductivity type opposite to the first conductivity type; a gate oxide layer formed on an inner surface of a trench located in the
epitaxial layer and between the first region and the second region, a bottom of the trench extending into the body layer; a gate formed on the gate oxide layer; a first body region and a second body region located at sides of the trench, the first body region and the second body region having a same doping state; and a first source region and a second source region located in the first body region and the second body region, respectively, the first source region and the second source region having a same doping state, and the first source region and the second source region being of the first conductivity type.
2. The device according to claim 1, wherein an angle between the bottom of the trench and a sidewall of the trench is greater than 90° and smaller than 95°.
3. The device according to claim 1, wherein an upper corner angle of the trench is of a smooth structure.
4. The device according to claim 1, further comprising: a drain electrode arranged on a lower surface of the substrate; a first source electrode and a second source electrode arranged over an upper surface of the substrate at locations over the first source region and the second source region, respectively, and located at opposite sides of the trench; and a gate electrode arranged over the upper surface of the substrate and between the first source electrode and the second source electrode.
5. The device according to claim 1, wherein the first region and the second region run through the epitaxial layer.
6. The device according to claim 1, wherein the first region and the second region are of
P-type doping, and the epitaxial layer is of N-type doping.
7. The device according to claim 1, wherein the body layer is of N-type doping, the first body region and the second body region are of P-type doping, and the first source region and the second source region are of N-type doping.
8. The device according to any one of claims 1-7, wherein a resistance of the epitaxial layer is equal to a resistance of the first region and the second region.
9. A method for manufacturing a high- voltage MOS device, comprising: preparing a substrate, the substrate comprising: a body layer; and an epitaxial layer located on the body layer, the epitaxial layer being of a first conductivity type; forming a first region and a second region in the epitaxial layer, the first region and the second region having a same doping state, and the first region and the second region being of a second conductivity type opposite to the first conductivity type; forming a trench in the epitaxial layer between the first region and the second region, a bottom of the trench extending into the body layer; forming a gate oxide layer on an inner surface of the trench; forming a gate on the gate oxide layer; forming a first body region and a second body region at sides of the trench, the first body region and the second body region having a same doping state; and forming a first source region and a second source region in the first body
region and the second body region, respectively, the first source region and the second source region having a same doping state.
10. The method according to claim 9, further comprising: forming a drain electrode on a lower surface of the substrate; forming a first source electrode and a second electrode over an upper surface of the substrate at the locations over the first source region and the second source region, respectively, and located at opposite sides of the trench; and forming a gate electrode over the upper surface of the substrate between the first source electrode and the second source electrode.
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