CN103681779A - Field effect transistor structure and manufacturing method thereof - Google Patents
Field effect transistor structure and manufacturing method thereof Download PDFInfo
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- CN103681779A CN103681779A CN201210333874.XA CN201210333874A CN103681779A CN 103681779 A CN103681779 A CN 103681779A CN 201210333874 A CN201210333874 A CN 201210333874A CN 103681779 A CN103681779 A CN 103681779A
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- 230000005669 field effect Effects 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 31
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 238000000407 epitaxy Methods 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000001459 lithography Methods 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims description 2
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 description 13
- 238000009826 distribution Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention discloses an epitaxial structure of a field effect transistor. The epitaxial structure comprises an N+ substrate, an N- epitaxial layer formed on the substrate, an inclined trough which is formed in the N- epitaxial layer and is filled with a P- epitaxial layer, a P+ trap formed in the P- epitaxial layer, an N+ source region formed in the P+ trap, and a polycrystalline silicon gate formed on the N- epitaxial layer in an area beyond a P trough, wherein the doping concentration of the N- epitaxial layer slowly varies from the N+ substrate to a direction away from the substrate. The epitaxial structure of the field effect transistor is high in breakdown voltage and low in on resistance.
Description
Technical field
The present invention relates to semiconductor technology, the invention particularly relates to a kind of field-effect transistor structure and preparation method thereof.
Background technology
As everyone knows, the drift layer puncture voltage of power field effect transistor is to be limited by the doping content of drift layer and the thickness of drift layer.And under normal conditions, people wish that power field effect transistor has higher puncture voltage and lower drift layer conducting resistance.Higher puncture voltage requires the thickness of drift layer larger, but larger thickness makes the resistance of drift layer larger.
In order to solve this contradiction, make power field effect transistor there is higher puncture voltage, make again drift layer resistance lower as far as possible, people have carried out a large amount of research, development, try hard to develop a kind of higher puncture voltage that has, make again the lower power field effect transistor of conducting resistance of drift layer.
The present invention has disclosed a kind of epitaxial structure that meets the super junction power field effect transistor of trench fill type of this demand.
Adopt the epitaxial structure of the super junction power field effect transistor of trench fill type of the present invention, can be so that the field-effect transistor of making have higher puncture voltage, its conducting resistance is also lower simultaneously.
Summary of the invention
An object of the present invention is to provide a kind of puncture voltage compared with the super junction field effect transistor structure of trench fill high and that conducting resistance is simultaneously less.
Another object of the present invention is to provide a kind of puncture voltage compared with manufacture method high and the super junction field effect transistor of trench fill that conducting resistance is simultaneously less.
According to one aspect of the present invention, the invention provides a kind of epitaxial structure of field-effect transistor, other comprises: N
+substrate, as the drain electrode of field-effect transistor; Be formed on the N on substrate
-epitaxial loayer; Be formed on N
-groove in epitaxial loayer, and in groove, be filled with P
-epitaxial loayer; Be formed on P
-p in epitaxial loayer
+trap; Be formed on P
+n in trap
+source region; And be formed on P
-groove is with the N of exterior domain
-polysilicon gate on epitaxial loayer, wherein, N
-the doping content of epitaxial loayer is gradual from N+ substrate towards the direction away from substrate.
According to the epitaxial structure of the field-effect transistor in aspect first of the present invention, N
-the thickness of epitaxial loayer can be 30 μ m-60 μ m, and N
-the doping content of epitaxial loayer is in the thickness range of 30 μ m-60 μ m, from N
+substrate is towards the direction away from substrate, from 4.9e
15-9.5e
15linear gradual to initial concentration 1.15 times of initial concentration.
In the epitaxial structure of the field-effect transistor according to during the present invention is aspect first, be filled with P
-the edge of the groove of epitaxial loayer is with respect to there is an inclination angle perpendicular to substrate end face, and inclination angle presents groove to be positioned at N
+one side of substrate is compared with narrow and away from N
+the wider shape of one side of substrate.
In the epitaxial structure of the field-effect transistor according to during the present invention is aspect first, the inclination angle of groove is 85-89 degree.
In the epitaxial structure of the field-effect transistor according to during the present invention is aspect first, at N
-between epitaxial loayer and polysilicon gate, be also formed with one deck gate oxide, the thickness of gate oxide is 800-1200.
In the epitaxial structure of the field-effect transistor according to during the present invention is aspect first, the degree of depth of groove is 30 μ m-50 μ m.
According to second aspect of the present invention, the epitaxy technique of a kind of fabricating yard effect transistor structure is provided, it comprises following step: step a): at N
+grown one deck N
-epitaxial loayer; Step b): at N
-etching groove in epitaxial loayer; Step c): fill P in groove
-epitaxial loayer; Step d): the P that is filled with being formed by step c)
-the groove of epitaxial loayer is with the N of exterior domain
-in epi-layer surface, form one deck gate oxide; Step e): the heavily doped N of one deck grows on the gate oxide being formed by step c)
+polysilicon layer, or after the polysilicon of the non-doping of deposit one deck in the polysilicon of non-doping implanted dopant to form N
+polysilicon gate; Step f): the P forming
-in epitaxial loayer, carry out P
+the injection of trap and annealing; Step g): the P forming
+in trap, carry out N
+the injection in source region and annealing; And step h): at formed P
+trap top forms metal source, and at N
+the deposit of the enterprising row metal aluminium of substrate drains to form, wherein, and N
-doping content in epitaxial loayer is from N
+substrate is gradual towards the direction away from substrate.
In the epitaxy technique of the fabricating yard effect transistor structure aspect second of the present invention, N
-the thickness of epitaxial loayer is 30 μ m-60 μ m, and N
-the doping content of epitaxial loayer is in the thickness range of 30 μ m-60 μ m, from N
+substrate is towards the direction away from substrate, from 4.9e
15-9.5e
15linear gradual to this initial concentration 1.15 times of initial concentration.
In the epitaxy technique of the fabricating yard effect transistor structure aspect second of the present invention, in step b) to N
-before epitaxial loayer carries out etching groove, also comprise first at N
-the layer of oxide layer of growing on epitaxial loayer, and then take formed oxide layer as mask plate, carry out the etching of groove.
In the epitaxy technique of the fabricating yard effect transistor structure aspect second of the present invention, at completing steps c) groove has been carried out to P
-after the filling of epitaxial loayer and before carrying out step d) formation gate oxide, also comprise the steps:
Step c-1): adopting CMP is that chemical-mechanical planarization technology or silicon return lithography, to through P
-substrate surface after epitaxial loayer is filled carries out planarization; And
Step c-2): growth one deck sacrificial oxide layer, and then remove the sacrificial oxide layer of growing, to make device surface more clean.
In the epitaxy technique of the fabricating yard effect transistor structure aspect second of the present invention, the thickness of gate oxide is 800-1200.
In the epitaxy technique of the fabricating yard effect transistor structure aspect second of the present invention, be filled with P
-the edge of the groove of epitaxial loayer is with respect to there is an inclination angle perpendicular to substrate end face, and inclination angle presents groove to be positioned at N
+one side of substrate is compared with narrow and away from N
+the wider shape of one side of substrate.
In the epitaxy technique of the fabricating yard effect transistor structure aspect second of the present invention, the inclination angle of groove is 85-89 degree.
Accompanying drawing explanation
Fig. 1 is longitudinal double diffusion structure schematic diagram of high voltage planar power field-effect transistor;
Fig. 2 illustrates the schematic diagram of the super junction device structure of the what is called that is;
Shown in Fig. 3 a to 3e is by repeatedly extension and injection mode, to realize the technical process principle schematic of super junction device structure shown in Fig. 2;
Shown in Fig. 4 a to 4c is to recharge technique by etching groove, makes the principle schematic of the technical process of super junction device structure;
Fig. 5 a and 5b further improve the schematic diagram of puncture voltage in the gradual situation of explanation P district doping content;
Fig. 6 a to 6h is the specific embodiment schematic diagram that illustrates the super junction field effect transistor structure of formation varying doping trench fill of the embodiment of the present invention;
Shown in Fig. 7 a and 7b is in the situation that the constant and deep trench sidewall of N-type outer layer doping concentration is 90 degree right angle, longitudinal distribution map of electric field N-type outer layer doping concentration when puncturing;
Shown in Fig. 8 a and 8b is in the situation that the constant and deep trench sidewall of N-type outer layer doping concentration is 89 degree inclination angle, longitudinal distribution map of electric field N-type outer layer doping concentration when puncturing; And
Shown in Fig. 9 a and 9b is in the situation that the gradual and deep trench sidewall of N-type outer layer doping concentration is 89 degree inclination angle, longitudinal distribution map of electric field N-type outer layer doping concentration when puncturing.
Embodiment
To be designed to be a kind of longitudinal double diffusion structure to high voltage planar power field-effect transistor as shown in Figure 1.
So-called longitudinal double diffusion structure, utilizes the edge of polysilicon to realize double diffusion longitudinally as mask, to form p exactly
+district and n
+district.Puncture voltage is mainly reflected in p
+district and drift layer (are n
-epitaxial loayer) on formed PN junction.
As can be seen from Figure 1, puncture voltage is mainly determined by drift layer.In order to obtain higher puncture voltage, a kind of consideration is to make the doping content of drift layer lower, and increases the thickness of drift layer simultaneously.
But, in order to improve the object of puncture voltage, constantly reduce the doping content of drift layer and constantly increase thickness, can make to raise as the drift layer resistance of current path, thereby cause the increase of conducting resistance, and then on-state power consumption is increased.Therefore, the raising of puncture voltage and the reduction of conducting resistance are conflicts.
For desirable N channel power field-effect transistor, at conducting resistance R
oN only consider drift layer resistance R
dsituation under, conducting resistance R
oN and puncture voltage
between there is following relation:
From above formula 1, can see, conducting resistance is referred to as the limit of " silicon limit (silicon limit) " because being subject to the restriction of puncture voltage to have one.Thereby conducting resistance cannot continue to reduce.
In order to break through this limit, can adopt the super junction device structure shown in Fig. 2.
The super junction device structure of what is called shown in Fig. 2 is in its turn on process, to only have majority carrier (being electronics) and the process that do not have minority carrier to participate in.
The switching loss of this super-junction structure is identical with other MOS (metal-oxide-semiconductor) memory, and the doping content of the voltage support layer of this super-junction structure can improve an order of magnitude nearly for identical puncture voltage.
In addition,, owing to inserting LiaopXing district in vertical direction, can compensate excessive current lead-through electric charge.When applying reverse bias voltage to drift layer, will produce a transverse electric field, p-n junction is exhausted.When voltage is increased to certain value, drift layer will exhaust completely, play the effect of voltage support layer.
Because this super-junction structure can be so that doping content improves greatly, thereby under identical puncture voltage, can greatly reduce conducting resistance R
oN, make it to break through silicon limit value.
Meanwhile, at same breakdown voltage, identical conducting resistance R
oNsituation under, can make die area do littlely, thereby reduce grid electric charge, improve switching frequency.
In addition, because the device of super-junction structure is majority carrier device, device does not have the current tail phenomenon of bipolar transistor.Therefore, the device of super-junction structure has lower on-state power consumption and higher switching speed.
In the device of super-junction structure, due to the mutual balance of electric charge in N district and P district, make Electric Field Distribution different with the Electric Field Distribution in traditional MOS (metal-oxide-semiconductor) memory.In the device of super-junction structure, critical field strength is almost constant.This just makes puncture voltage only depend on the thickness of epitaxial loayer, and has nothing to do with doping content, thereby makes conducting resistance R
oNwith puncture voltage V
bbetween relation from traditional quadratic relationship, become linear relationship:
(formula 2)
In above formula, cp is the width of primitive unit cell, μ
nelectron mobility, E
cbe critical electric field, Q represents the quantity of electric charge, ε
siit is the electric medium constant of silicon Si.
Below with reference to Fig. 3 a to Fig. 3 e, the process that realizes super-junction structure by repeatedly extension and injection mode is described.
First, at N
+on substrate, epitaxial growth N for the first time
-layer;
At grown N
-in specific region on layer, smear photoresist, and carry out boron injection in the window staying;
Remove photoresist and anneal, after annealing, carrying out epitaxial growth N for the second time
-layer;
Then, at epitaxially grown N for the second time
-on layer, as last step, smear photoresist, and carry out boron for the second time and inject, carry out subsequently removal and the annealing of photoresist.
Repeat above-mentioned steps, until form required super-junction structure device.
Also can, by recharging technique as the etching groove shown in 4a and 4b, make super-junction structure device.
First, at N
+on substrate, epitaxial growth N
-layer;
Then, adopt as extension repeatedly, step that injection mode is identical, at N
-on layer, without doing, on the region of further etching, smear photoresist;
Then, in the location of not smearing photoresist, carry out deep plough groove etchedly, for the super-junction structure device of puncture voltage 600V, the degree of depth of deep trench is 30-50 μ m;
Then,, in groove, epitaxial growth is through boron doped P
-district;
Complete P
-after district growth, adopts back quarter or CMP(chemical-mechanical planarization) technique, to through P
-n after district's growth
-layer carries out polishing, and after subsequent technique, forms super-junction structure device.
At above-mentioned the second etching groove, recharge in technique, in deep trench, carry out P
-the boron doping concentration of outer layer growth is constant.When filling boron doping, if dealt with improperly, easily there is cavity to produce, thereby affect the electric leakage of device source, drain electrode, thereby and affect puncture voltage.Therefore, in order to reduce cavity, produce, require to carry out very harsh process conditions, to guarantee carrying out P in groove
-epitaxial loayer does not have cavity and produces while filling, thereby guarantees the quality of super-junction structure device.
During in order to ensure trench fill at super-junction structure device, do not have as much as possible cavity and produce, can consider that the cross section that groove is made as shown in Fig. 4 c is shape wide at the top and narrow at the bottom.Experiment showed, when trenched side-wall being made in a situation that has small inclination with respect to vertical direction P in groove
-the doping quality in district can improve greatly.
In order further to improve in valley gutter situation, the puncture voltage of super-junction structure device, we can further consider the N making outside groove
-district's doping content is soft phase.
Below in conjunction with Fig. 5 a and 5b, N is described
-in the gradual situation of district's doping content, further improve the principle of puncture voltage.
Shown in Fig. 5 a.The desirable puncture voltage of super-junction structure device obtains in charge balance situation.When departing from the situation of charge balance, puncture voltage can obviously reduce.
In the ideal case, suppose P
-the concentration of electric charges in district is steady state value N
p, and P
-the width in district is steady state value W
p.Meanwhile, suppose N
-the concentration of electric charges in district is steady state value N
n, and N
-the width in district is steady state value W
n.So, when reaching charge balance, should have
(formula 3)
This means, in upper and lower each cross section shown in Fig. 5 a, puncture voltage is only by P
-district and N
-the width in district and doping content separately determine, are constant.
Below, let us look at if at groove with inclination angle and N
-situation when district's concentration is constant.
As shown in Figure 5 b.As the groove and the N that adopt as shown in Figure 5 b with inclination angle
-when district's concentration is constant structure, if P
-the doping content in district is constant, the different position in cross section, and the balance of electric charge is different.
Suppose (ii) to locate to meet equation 3 in the position shown in Fig. 5 b, but (iii) locate in position, equation 3 just can not be satisfied.
For this reason, can adopt and make N
-from substrate one side direction, the direction away from substrate increases and makes linear gradual mode the doping content of district's epitaxial loayer gradually, makes all to meet equation 3 at each place, sectional position as shown in Figure 5 b.
Experiment shows, adopts this N of making
-district's outer layer doping concentration is linear gradual mode, the in the situation that of valley gutter, can meet equation 3, and prepared super-junction structure device has higher puncture voltage.
In order more clearly to describe the present invention, below with reference to Fig. 6 a to 6h, a kind of embodiment of the present invention is described for example.
As shown in Figure 6 a.First, at N
+the certain thickness N of Grown
-epitaxial loayer.The doping content of this epitaxial loayer is from N
+substrate starts towards away from N
+it is linear gradual that the direction of substrate is.For instance, the N of growth
-the thickness of epitaxial loayer is 30-60 μ m, and initial concentration is 4.9e
15to 9.5e
15, 1.15 times of left and right with this concentration linear increment to initial concentration.
Then, as shown in Figure 6 b, at grown N
-the certain thickness oxide layer of growing on the linear gradual epitaxial loayer of doping content, for example, thickness is the oxide layer of 1-2 μ m.
Take this oxide layer as mask plate carries out the etching of deep trench, for example, etch the groove of 30-50 μ m.Formed groove is shape wide at the top and narrow at the bottom.The inclination angle of formed shape wide at the top and narrow at the bottom and vertical elevation is 85 degree-89 degree.
Then, as shown in Fig. 6 c, in the formed groove of etching, carry out P
-the filling of type epitaxial loayer.
P in completing groove
-after the filling of type epitaxial loayer, adopting CMP(Chemical-Mechanical Planarization, chemical-mechanical planarization) technology or silicon returns lithography, to having carried out P
-substrate surface after type epitaxial loayer is filled carries out planarization.
So-called CMP technology is that a kind of chemical corrosion and mechanical force used carried out the technology of planarization to the surface of the semi-conducting material in the course of processing.
And silicon returns lithography, be after completing the etching of groove, due to P
-type epitaxial loayer not only can be grown in groove, also can be at groove outgrowth, now, a kind of technology that can adopt chemical method (for example reagent) or plasma gas that the silicon etching outside groove is fallen.
Due to CMP technology and silicon, returning lithography is that in semiconductor technology, people are known, so, repeat no more herein.
Return carving technology and make through P completing CMP technique or silicon
-after flattening surface after type epitaxial loayer is filled, then carry out SiO
2the growth of sacrificial oxide layer.After the growth that completes sacrificial oxide layer, then remove grown sacrificial oxide layer.The object of doing like this, is because returning after carving technology through CMP technique or silicon, may have damage or leave impurity on the surface of device.And after the sacrificial oxide layer of having grown, then remove grown sacrificial oxide layer, and then carrying out subsequent technique, can make the surface of device more clean.
Then, as shown in Fig. 6 d, removing on the device surface of sacrificial oxide layer, heat growth gate oxide, for example thickness is 800-1200.
In heat, grow on formed gate oxide surface, the more heavily doped N of one deck that then grows
+polysilicon layer.Or in deposit after the polysilicon of the non-doping of one deck, in the polysilicon of non-doping, implanted dopant is to form N
+polysilicon gate.
Then, formed heavily doped polysilicon gate layer and gate oxide are carried out to photoetching, form the device architecture as shown in Fig. 6 e.
Then, as shown in Figure 6 f, at the P of described filling
-in epitaxial loayer, carry out P
+the injection of trap and annealing.And as shown in Fig. 6 g, at formed P
+in trap, carry out N
+the injection in source region and annealing.
After completing above-mentioned technique, then carry out the photoetching of metal source and grid, and P
+the injection of trap contact, the deposit of the row metal aluminium of going forward side by side and photoetching are to form drain electrode.Finally obtain as the device architecture of Fig. 6 h.
Hereinafter, 7a to 9b with reference to the accompanying drawings, when being described in trench cross section and being 90 degree and 89 and spending, and doping content is in constant and gradual situation, the puncture voltage of the super junction power field effect pipe of groove-shaped filling and the situation of featured resistance.
Shown in Fig. 7 a and 7b is at N
-type outer layer doping concentration is constant and deep trench sidewall is in the situation at 90 degree right angles, and electric field is N when puncturing
-longitudinal distribution map of type outer layer doping concentration.
In Fig. 7 a, shown in abscissa is the fore-and-aft distance of device, and shown in ordinate is electric field strength.
In Fig. 7 b, shown in abscissa is the fore-and-aft distance of device, and shown in ordinate is the concentration of phosphorus doping.
Shown in Fig. 8 a and 8b is at N
-type outer layer doping concentration is constant and deep trench sidewall is in the situation at 89 degree inclination angles, and electric field is N when puncturing
-longitudinal distribution map of type outer layer doping concentration.
In Fig. 8 a, shown in abscissa is the fore-and-aft distance of device, and shown in ordinate is electric field strength.
In Fig. 8 b, shown in abscissa is the fore-and-aft distance of device, and shown in ordinate is the concentration of phosphorus doping.
Shown in Fig. 9 a and 9b is at N
-type outer layer doping concentration is gradual and deep trench sidewall is in the situation at 89 degree inclination angles, and electric field is N when puncturing
-longitudinal distribution map of type outer layer doping concentration.
In Fig. 9 a, shown in abscissa is the fore-and-aft distance of device, and shown in ordinate is electric field strength.
In Fig. 9 b, shown in abscissa is the fore-and-aft distance of device, and shown in ordinate is the concentration of phosphorus doping.
From 7a to 9b, can see, work as N
-when the doping content of type epitaxial loayer is constant, if trench wall is right angle, due to P
-type epitaxial loayer and N
-type epitaxial loayer can fully exhaust well in the horizontal direction as shown in Fig. 5 a and 5b, and therefore, puncture voltage is also higher.
But when sidewall has a small inclination, owing to fully exhausting well in the horizontal direction as shown in Fig. 5 a and 5b, therefore, puncture voltage is lower.
Yet, from Fig. 9 a and 9b, can see, at N
-type epitaxial loayer adopts in the gradual situation of doping content, even if the sidewall of groove is not right angle, in the horizontal direction, along with the increase of drain voltage, due to P
-type epitaxial loayer and N
-the doping content of type epitaxial loayer and width are different, also can in the horizontal direction as shown in Fig. 5 a and 5b, accomplish that well electric charge fully exhausts.Therefore, puncture voltage is also higher.
Simulated experiment shows, in the situation that having ditch groove tilt angle, if adopt N
-the gradual technology of type outer layer doping concentration, can be so that puncture voltage be higher, and conducting resistance is lower, as shown in table 1 below simultaneously.
Table 1
| Trenched side-wall inclination angle | N epitaxial layer concentration (cm -3） | Breakdown voltage value (V) | Conducting resistance (mOhmcm 2) |
| 90 o | Constant | 845 | 19.5 |
| 89 o | Constant | 73 | 23 |
| 89 o | Gradual | 802 | 19 |
From description above, can see, in the present invention, owing to having adopted the gradual and trenched side-wall of doping content to there is this technology in little inclination angle, make N
-type epitaxial loayer and P
-type epitaxial loayer can fully exhaust in the horizontal direction well, thereby when puncture voltage is improved, the conducting resistance of device is also less.
Above, describe specific embodiments of the invention with reference to the accompanying drawings.But those skilled in the art can understand, in the situation that not departing from principle of the present invention and spirit, can also make some modifications and changes to the above embodiment of the present invention.Above mentioned special angle value, specific epitaxy layer thickness and specific doping content etc. parameter just in order to describe convenience of the present invention for example, can not be understood as is limitation of the present invention.Those skilled in the art can understand, and these numerical value are actually and can set in addition according to concrete service condition.The description of embodiment is only used to make those skilled in the art can understand, implement the present invention, the present invention should not understood and only only limits to these embodiment.Protection scope of the present invention is limited by claims.
Claims (13)
1. an epitaxial structure for field-effect transistor, is characterized in that, it comprises:
N+ substrate, as the drain electrode of described field-effect transistor;
Be formed on the N on described substrate
-epitaxial loayer;
Be formed on described N
-groove in epitaxial loayer, and be filled with P in described groove
-epitaxial loayer;
Be formed on described P
-p in epitaxial loayer
+trap;
Be formed on described P
+n in trap
+source region; And
Be formed on described P
-groove is with the described N of exterior domain
-polysilicon gate on epitaxial loayer,
Wherein, described N
-the doping content of epitaxial loayer is gradual from described N+ substrate towards the direction away from described substrate.
2. the epitaxial structure of field-effect transistor as claimed in claim 1, is characterized in that, described N
-the thickness of epitaxial loayer is 30 μ m-60 μ m, and described N
-the doping content of epitaxial loayer in the thickness range of described 30 μ m-60 μ m, from described N+ substrate towards the direction away from described substrate, from 4.9e
15-9.5e
15linear gradual to described initial concentration 1.15 times of initial concentration.
3. the epitaxial structure of field-effect transistor as claimed in claim 1, is characterized in that, is filled with described P
-the edge of the groove of epitaxial loayer is with respect to having an inclination angle perpendicular to described substrate end face, and described inclination angle presents described groove to be positioned at described N
+one side of substrate is compared with narrow and away from described N
+the wider shape of one side of substrate.
4. the epitaxial structure of field-effect transistor as claimed in claim 2, is characterized in that, the inclination angle of described groove is 85-89 degree.
5. the epitaxial structure of field-effect transistor as claimed in claim 1, is characterized in that, at described N
-between epitaxial loayer and described polysilicon gate, be also formed with one deck gate oxide, the thickness of described gate oxide is 800-1200.
6. the epitaxial structure of the field-effect transistor as described in arbitrary claim in claim 1 to 5, is characterized in that, the degree of depth of described groove is 30 μ m-50 μ m.
7. make an epitaxy technique for field-effect transistor structure as claimed in claim 1, it is characterized in that, it comprises following step:
Step a): at N
+grown one deck N
-epitaxial loayer;
Step b): at described N
-etching groove in epitaxial loayer;
Step c): fill P in described groove
-epitaxial loayer;
Step d): the P that is filled with being formed by step c)
-the described groove of epitaxial loayer is with the N of exterior domain
-in epi-layer surface, form one deck gate oxide;
Step e): the heavily doped N of one deck grows on the described gate oxide being formed by step c)
+polysilicon layer, or after the polysilicon of the non-doping of deposit one deck in the polysilicon of non-doping implanted dopant to form N
+polysilicon gate;
Step f): the described P forming
-in epitaxial loayer, carry out P
+the injection of trap and annealing;
Step g): the described P forming
+in trap, carry out N
+the injection in source region and annealing; And
Step h): at formed P
+trap top forms metal source, and at described N
+the deposit of the enterprising row metal aluminium of substrate drains to form,
Wherein, described N
-doping content in epitaxial loayer is from described N
+substrate is gradual towards the direction away from described substrate.
8. epitaxy technique as claimed in claim 7, is characterized in that, described N
-the thickness of epitaxial loayer is 30 μ m-60 μ m, and described N
-the doping content of epitaxial loayer is in the thickness range of described 30 μ m-60 μ m, from described N
+substrate is towards the direction away from described substrate, from 4.9e
15-9.5e
15linear gradual to described initial concentration 1.15 times of initial concentration.
9. epitaxy technique as claimed in claim 7, is characterized in that, in step b) to described N
-before epitaxial loayer carries out etching groove, also comprise first at described N
-the layer of oxide layer of growing on epitaxial loayer, and then take formed oxide layer as mask plate, carry out the etching of described groove.
10. epitaxy technique as claimed in claim 7, is characterized in that, at completing steps c) described groove has been carried out to P
-after the filling of epitaxial loayer and carrying out, before step d) forms described gate oxide, also comprise the steps:
Step c-1): adopting CMP is that chemical-mechanical planarization technology or silicon return lithography, to described through P
-substrate surface after epitaxial loayer is filled carries out planarization; And
Step c-2): growth one deck sacrificial oxide layer, and then remove the sacrificial oxide layer of growing.
11. epitaxy techniques as claimed in claim 7, is characterized in that, the thickness of described gate oxide is 800-1200.
12. epitaxy techniques as described in arbitrary claim in claim 7 to 11, is characterized in that, are filled with described P
-the edge of the groove of epitaxial loayer is with respect to having an inclination angle perpendicular to described substrate end face, and described inclination angle presents described groove to be positioned at described N
+one side of substrate is compared with narrow and away from described N
+the wider shape of one side of substrate.
13. epitaxy techniques as claimed in claim 12, is characterized in that, the inclination angle of described groove is 85-89 degree.
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| CN201210333874.XA CN103681779A (en) | 2012-09-11 | 2012-09-11 | Field effect transistor structure and manufacturing method thereof |
| PCT/CN2013/082821 WO2014040507A1 (en) | 2012-09-11 | 2013-09-02 | Epitaxy structure and process of field effect transistor and method of manufacturing the same |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050045922A1 (en) * | 2003-08-28 | 2005-03-03 | Infineon Technologies Ag | Semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it |
| US20080048175A1 (en) * | 2006-08-25 | 2008-02-28 | De Fresart Edouard D | Semiconductor superjunction structure |
| CN102403354A (en) * | 2010-09-15 | 2012-04-04 | 无锡华润上华半导体有限公司 | CoolMOS device and manufacturing method for same |
| CN102456715A (en) * | 2010-10-25 | 2012-05-16 | 上海华虹Nec电子有限公司 | Semiconductor device structure and manufacturing method thereof |
-
2012
- 2012-09-11 CN CN201210333874.XA patent/CN103681779A/en active Pending
-
2013
- 2013-09-02 WO PCT/CN2013/082821 patent/WO2014040507A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050045922A1 (en) * | 2003-08-28 | 2005-03-03 | Infineon Technologies Ag | Semiconductor power device with charge compensation structure and monolithic integrated circuit, and method for fabricating it |
| US20080048175A1 (en) * | 2006-08-25 | 2008-02-28 | De Fresart Edouard D | Semiconductor superjunction structure |
| CN102403354A (en) * | 2010-09-15 | 2012-04-04 | 无锡华润上华半导体有限公司 | CoolMOS device and manufacturing method for same |
| CN102456715A (en) * | 2010-10-25 | 2012-05-16 | 上海华虹Nec电子有限公司 | Semiconductor device structure and manufacturing method thereof |
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| CN107134492B (en) * | 2016-02-26 | 2020-01-14 | 苏州东微半导体有限公司 | Super junction power device and manufacturing method thereof |
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| CN109346524A (en) * | 2018-09-30 | 2019-02-15 | 重庆大学 | A kind of hyperconjugation VDMOS device with ladder concentration polysilicon side wall structure |
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| WO2014040507A1 (en) | 2014-03-20 |
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