CN102263133B

CN102263133B - Low-gate charge low-on resistance deep trench power metal oxide semiconductor field effect transistor (MOSFET) device and manufacturing method

Info

Publication number: CN102263133B
Application number: CN2011102415250A
Authority: CN
Inventors: 朱袁正; 秦旭光; 丁磊; 叶鹏
Original assignee: NCE POWER SEMICONDUCTOR CO Ltd
Current assignee: Wuxi NCE Power Co Ltd
Priority date: 2011-08-22
Filing date: 2011-08-22
Publication date: 2012-11-07
Anticipated expiration: 2031-08-22
Also published as: CN102263133A

Abstract

The invention relates to a low-gate charge low-on resistance deep trench power metal oxide semiconductor field effect transistor (MOSFET) device and a manufacturing method. Shield grid conducting polycrystalline silicon bodies are arranged in cellular trenches of the device. The two sides of the shield grid conducting polycrystalline silicon body are provided with gate conducting polycrystalline silicon. An insulating gate oxide layer is arranged between the gate conducting polycrystalline silicon and the upper sidewall of the cellular trench. Second shield grid conducting polycrystalline silicon is arranged below the gate conducting polycrystalline silicon. A shield grid oxide layer covers the lower part of the shield grid conducting polycrystalline silicon. A trench opening of the cellular trench is covered by an insulating dielectric layer. The two sides of the cellular trench are provided with a contact hole respectively. Metal connecting wires are deposited on the insulating dielectric layer, are in ohmic contact with a first-conduction type source region and a second-conduction type well layer and realize gate conducting polycrystalline silicon electrical connection, shield grid conducting polycrystalline silicon body electrical connection and second shield grid conducting polycrystalline silicon electrical connection. The device is low in on resistance, gate-drain charge (Qgd), switching loss and cost and high in switching speed; and a process is simple.

Description

Low gate charge low on-resistance deep-groove power MOS FET device and manufacturing approach thereof

Technical field

The present invention relates to a kind of power MOSFET device and manufacturing approach thereof, especially a kind of low gate charge low on-resistance deep-groove power MOS FET device and manufacturing approach thereof belong to the technical field of semiconductor device.

Background technology

Power MOS (Metal Oxide Semiconductor) device with groove has integrated level height, conducting resistance is low, switching speed is fast, switching loss is little characteristics, is widely used in all kinds of power managements and switch transition.Along with industrial expansion; Global warming causes climatic environment more and more abominable; Various countries begin more and more to pay attention to carbon reduction and sustainable development; Therefore require increasingly highly for the power consumption of power MOS (Metal Oxide Semiconductor) device and conversion efficiency thereof, power consumption mainly is made up of conduction loss and switching loss, the conduction loss influence big or small with the characteristic conducting resistance of mainly being limited by; Wherein, the characteristic conducting resistance is more little, and conduction loss is more little; Switching loss mainly is limited by the gate charge size, and gate charge is more little, and switching loss is also more little.Therefore, reducing conducting resistance and gate charge is two effective ways that reduce the power MOS (Metal Oxide Semiconductor) device power consumption, thereby can use the energy more efficiently, reduces more electric energy that are consumed more, is the effectively approach of guaranteeing future source of energy safety.

Reducing the characteristic conducting resistance has two kinds of methods usually, and the first increases total effective width of unit cell through improving unit cell density, thereby reaches the purpose that reduces the characteristic conducting resistance.But after unit cell density improved, corresponding grid electric charge also can increase, and is difficult to reach and not only reduces conducting resistance but also reduce the grid electric charge simultaneously; It two is through improving the epitaxial wafer doping content, reduce epitaxy layer thickness and realize, but this method can reduce the source drain breakdown voltage, and therefore simple dependence reduced doping content/reduce epitaxy layer thickness, is limited by the size requirements of puncture voltage.Reduce gate charge several different methods is arranged; Like the NEC of Huahong electronics thick bottom gate oxygen technology (Thick bottom oxide) has been proposed in the patent application (publication number is CN1877856A) of China; Reduce gate leakage capacitance Cgd, thereby reach the purpose that reduces gate charge Qg, this technology reduces Qg about about 30%; But still can not satisfy increasingly high frequency applications, and can not obviously reduce the characteristic conducting resistance simultaneously.

Therefore, how to reduce characteristic conducting resistance and gate charge simultaneously, thereby reduce the research direction that power MOS (Metal Oxide Semiconductor) device conduction loss and switching loss become those skilled in the art of the present technique greatly.

Summary of the invention

The objective of the invention is to overcome the deficiency that exists in the prior art; A kind of low gate charge low on-resistance deep-groove power MOS FET device and manufacturing approach thereof are provided, and its conducting resistance is low, and gd is little for the grid leak charge Q; Switching speed is fast, switching loss is low, and technology simply reaches with low cost.

According to technical scheme provided by the invention; Said low gate charge low on-resistance deep-groove power MOS FET device; On the top plan view of said MOSFET device; Comprise the cellular region and the terminal protection district that are positioned at semiconductor substrate, said terminal protection district is positioned at the outer ring of cellular region, and the terminal protection district is around surrounding cellular region; Comprise the cellular of arranging several rules and being parallel to each other parallel connection being provided with in the cellular region; On the cross section of said MOSFET device; Semiconductor substrate has corresponding first interarea and second interarea; Comprise the first conduction type drain region between said first interarea and second interarea and be positioned at first conduction type, first epitaxial loayer and first conduction type, second epitaxial loayer of top, the said first conduction type drain region, first conduction type, first epitaxial loayer adjacency, the first conduction type drain region; Top in first conduction type, second epitaxial loayer is provided with the second conductive type of trap layer; The cellular of cellular region adopts groove structure, and the cellular groove is positioned at first conduction type, first epitaxial loayer top, and the degree of depth stretches into first conduction type, second epitaxial loayer or first conduction type, first epitaxial loayer of second conductive type of trap layer below; The sidewall top of adjacent cellular groove is provided with the first conduction type source area, and the first conduction type source area is positioned at the top of the second conductive type of trap layer; Its innovation is:

On the cross section of said MOSFET device; Be provided with shield grid conductive polycrystalline silicon body in the said cellular groove; Said shield grid conductive polycrystalline silicon body is positioned at the center of cellular groove; And the both sides of said shield grid conductive polycrystalline silicon body are provided with the grid conductive polycrystalline silicon, are provided with the insulated gate oxide layer between the upper portion side wall of grid conductive polycrystalline silicon and cellular groove, and said insulated gate oxide layer growth is in the upper portion side wall of cellular groove; The below of grid conductive polycrystalline silicon is provided with secondary shielding grid conductive polycrystalline silicon; The bottom growth of cellular groove has the shield grid oxide layer; The shield grid thickness of oxide layer is more than or equal to the insulated gate thickness of oxide layer; The shield grid oxide layer covers the sidewall and the lower surface of cellular groove bottom, and the shield grid oxide layer coats the bottom of shield grid conductive polycrystalline silicon body;

The grid conductive polycrystalline silicon is isolated with shield grid conductive polycrystalline silicon body and secondary shielding grid conductive polycrystalline silicon respectively through the conductive polycrystalline silicon insulating medium layer; Be provided with first isolating oxide layer between secondary shielding grid conductive polycrystalline silicon and shield grid oxide layer, secondary shielding grid conductive polycrystalline silicon is isolated through the sidewall and the shield grid conductive polycrystalline silicon body of first isolating oxide layer and cellular groove; The lower end of grid conductive polycrystalline silicon and shield grid conductive polycrystalline silicon body all extends the below of the second conductive type of trap layer, and the extension degree of depth of shield grid conductive polycrystalline silicon body is greater than the extension degree of depth of grid conductive polycrystalline silicon;

The notch of cellular groove is covered by insulating medium layer, and the both sides of cellular groove are provided with contact hole, is deposited with metal connecting line on the insulating medium layer, and said metal connecting line is covered on the insulating medium layer and is filled in the contact hole; The said metal connecting line and the first conduction type source area and the second conductive type of trap layer ohmic contact, and realization and grid conductive polycrystalline silicon, secondary shielding grid conductive polycrystalline silicon and the electric connection of shield grid conductive polycrystalline silicon body.

Said shield grid conductive polycrystalline silicon body comprises the first shield grid conductive polycrystalline silicon, and the said first shield grid conductive polycrystalline silicon is positioned at the center of cellular groove, and the first shield grid conductive polycrystalline silicon extends in the shield grid oxide layer from the top of cellular groove.

Said shield grid conductive polycrystalline silicon body comprises the 3rd shield grid conductive polycrystalline silicon and is positioned at the 4th shield grid conductive polycrystalline silicon of said the 3rd shield grid conductive polycrystalline silicon below; The 3rd shield grid conductive polycrystalline silicon is positioned at the center of cellular groove, and extends to the bottom land direction of cellular groove from the top of cellular groove; Isolated through second isolating oxide layer between said the 3rd shield grid conductive polycrystalline silicon and the 4th shield grid conductive polycrystalline silicon, the 4th shield grid conductive polycrystalline silicon extends in the shield grid oxide layer; Grid conductive polycrystalline silicon and secondary shielding grid conductive polycrystalline silicon all are positioned at the both sides of the 3rd shield grid conductive polycrystalline silicon.

The doping content of said first conduction type, second epitaxial loayer is more than or equal to the doping content of first conduction type, first epitaxial loayer.

A kind of manufacturing approach of low gate charge low on-resistance deep-groove power MOS FET device is characterized in that the manufacturing approach of said power MOSFET device comprises the steps:

A, the semiconductor substrate with two relative interareas is provided; Said semiconductor substrate comprises the first conduction type drain region and is positioned at first conduction type, first epitaxial loayer and first conduction type, second epitaxial loayer of top, the said first conduction type drain region; The surface of first conduction type, second epitaxial loayer forms first interarea of semiconductor substrate, and the surface of the first conduction type drain region forms second interarea of semiconductor substrate; B, on first interarea of semiconductor substrate the deposit hard mask layer, and optionally shelter and the said hard mask layer of etching, on first interarea of semiconductor substrate, form the hard mask window of etching groove; C, utilize above-mentioned hard mask window, on first interarea, through the dry etching semiconductor substrate, above first conduction type, first epitaxial loayer of semiconductor substrate, form groove, said groove comprises the cellular groove; D, on first interarea of above-mentioned semiconductor substrate the growth regulation dioxide layer, said second oxide layer is covered on first interarea, and is covered in the sidewall and the lower surface of cellular groove, and in the cellular groove, forms the first polysilicon depositing groove; E, on first interarea of above-mentioned semiconductor substrate deposition gate polysilicon body material layer, said shield grid polysilicon body material layer is filled in the first polysilicon depositing groove; F, remove the shield grid polysilicon body material layer on semiconductor substrate first interarea, obtain being positioned at the shield grid conductive polycrystalline silicon body of the first polysilicon depositing groove; G, on first interarea of semiconductor substrate, make photoresist, defining second oxide layer needs the zone of etching to carry out photoetching, removes second oxide layer of defined range then through etching, obtains being positioned at the shield grid oxide layer of cellular groove bottom; H, on first interarea of semiconductor substrate, the 3rd oxide layer is set, said the 3rd oxide layer is covered on first interarea, and coats the upper face of shield grid conductive polycrystalline silicon body, and forms the second polysilicon depositing groove in shield grid conductive polycrystalline silicon body both sides; I, in the second polysilicon body depositing groove deposit second conductive polycrystalline silicon floor, and pass through back to carve second conductive polycrystalline silicon floor and the 3rd oxide layer, obtain first isolating oxide layer and be positioned at the secondary shielding grid conductive polycrystalline silicon of second polysilicon depositing groove bottom; J, on first interarea of above-mentioned semiconductor substrate growth regulation four oxide layers, said the 4th oxide layer is covered in first interarea and the cellular groove, removes above-mentioned the 4th oxide layer through wet etching then; K, on first interarea of above-mentioned semiconductor substrate thermal oxide growth the 5th oxide layer; The 5th oxide layer is covered on first interarea and the cellular groove upper portion side wall; And be covered on secondary shielding grid conductive polycrystalline silicon and the shield grid conductive polycrystalline silicon body, and form the 3rd polysilicon depositing groove in shield grid conductive polycrystalline silicon body both sides; L, on first interarea of above-mentioned semiconductor substrate deposit the 3rd conductive polycrystalline silicon floor, through the 3rd conductive polycrystalline silicon floor on etching first interarea, obtain being positioned at the grid conductive polycrystalline silicon of cellular groove; M, on first interarea of above-mentioned semiconductor substrate, inject the second conductive type impurity ion; And through pushing away the second conductive type of trap layer that trap forms cellular region, the degree of depth of the second conductive type of trap layer in first conduction type, second epitaxial loayer in the said cellular region less than the grid conductive polycrystalline silicon in the cellular groove to the distance that extends below; N, on first interarea of above-mentioned semiconductor substrate, carry out the source area photoetching, and inject the first conductive type impurity ion, form the first conduction type source area of cellular region through knot; O, on first interarea of above-mentioned semiconductor substrate the deposit insulating medium layer, said insulating medium layer is covered in first interarea of semiconductor substrate; P, above-mentioned insulating medium layer is carried out contact hole photoetching and etching, all form contact hole in the both sides of cellular groove; Q, on above-mentioned insulating medium layer deposited metal, said metal level is covered on the insulating medium layer, and is filled in the contact hole, forms metal connecting line; The said metal connecting line and the first conduction type source area and the second conductive type of trap layer ohmic contact.

Also comprise the steps: r behind the said step q, on above-mentioned metal connecting line the deposit passivation layer, and on passivation layer, make photoresist and define the metal wire window, form said metal wire window through dry etching.

Said passivation layer comprises and is deposited on the silicon dioxide layer on the metal connecting line and is positioned at the silicon nitride layer on the said silicon dioxide layer.

Among said step e and the step f, when the shield grid conductive polycrystalline silicon body that obtains was the first shield grid conductive polycrystalline silicon, step e and step f were specially:

E, on first interarea of above-mentioned semiconductor substrate deposit first conductive polycrystalline silicon floor, said first conductive polycrystalline silicon floor is covered in first interarea of semiconductor substrate and is filled in the first polysilicon depositing groove; F, remove first conductive polycrystalline silicon floor on semiconductor substrate first interarea, obtain being positioned at the first shield grid conductive polycrystalline silicon of the first polysilicon depositing groove.

Among said step e and the step f, when the shield grid conductive polycrystalline silicon body that obtains was the 3rd shield grid conductive polycrystalline silicon and the 4th shield grid conductive polycrystalline silicon, step e and step f were specially:

E, on first interarea of above-mentioned semiconductor substrate deposit the 4th conductive polycrystalline silicon floor, said the 4th conductive polycrystalline silicon floor is covered in first interarea of semiconductor substrate and is filled in the first polysilicon depositing groove; Remove the 4th conductive polycrystalline silicon floor on above-mentioned semiconductor substrate first interarea, obtain being positioned at the 4th shield grid conductive polycrystalline silicon of the first polysilicon depositing groove; On the 4th shield grid conductive polycrystalline silicon, generate second isolating oxide layer, and on second isolating oxide layer deposit the 5th conductive polycrystalline silicon floor, said the 5th conductive polycrystalline silicon floor is covered in first interarea of semiconductor substrate; The 5th conductive polycrystalline silicon floor on f, removal semiconductor substrate first interarea obtains the 3rd shield grid conductive polycrystalline silicon.

Said insulating medium layer is silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).

Said " first conduction type " and " second conduction type " are among both, and for N type MOSFET device, first conduction type refers to the N type, and second conduction type is the P type; For P type MOSFET device, the type and the N type semiconductor device of first conduction type and the second conduction type indication are just in time opposite.

Advantage of the present invention:

1, the present invention adopts and increases shield grid conductive polycrystalline silicon structure and effectively reduce grid leak parasitic capacitance Cgd, and it is about 85% effectively to reduce Qgd, has improved switching speed and has reduced switching loss.

2, the present invention adopts the combining structure of shield grid conductive polycrystalline silicon body and shield grid oxide layer; Leak when receiving reverse biased in the source; Because of producing the transverse electric field mudulation effect; Can receive transverse electric field mudulation effect zone of action doping content through raising, reduce the characteristic conducting resistance, and keep the source drain breakdown voltage constant.Can know through simulation result, the existing structure of comparing, it is about 40% that structure proposed by the invention, its characteristic conducting resistance reduce, and greatly reduces conduction loss.

Description of drawings

Fig. 1 is the structural representation of the embodiment of the invention 1.

Fig. 2 ~ Figure 18 is the practical implementation technology cutaway view of the embodiment of the invention 1, wherein:

Fig. 2 is the cutaway view of semiconductor substrate of the present invention.

Fig. 3 is the cutaway view behind the hard mask window of formation.

Fig. 4 is the cutaway view after formation second oxide layer.

Fig. 5 is the cutaway view behind the deposit first conduction polycrystal layer.

Fig. 6 is the cutaway view behind the formation first shield grid conductive polycrystalline silicon.

Fig. 7 is the cutaway view after the formation shield grid oxide layer.

Fig. 8 is the cutaway view after formation the 3rd oxide layer.

Fig. 9 is the cutaway view behind the formation secondary shielding grid conductive polycrystalline silicon.

Figure 10 is the cutaway view behind formation first isolating oxide layer.

Figure 11 is the cutaway view after formation the 4th oxide layer.

Figure 12 is the cutaway view after formation the 5th oxide layer.

Figure 13 is the cutaway view behind the formation grid conductive polycrystalline silicon.

Figure 14 is the cutaway view behind the formation second conductive type of trap layer.

Figure 15 is for forming the cutaway view of the first conduction type source area.

Figure 16 is the cutaway view behind the formation insulating medium layer.

Figure 17 is the cutaway view behind the formation contact hole.

Figure 18 is the cutaway view behind the formation metal connecting line.

Figure 19 is the structural representation of the embodiment of the invention 2.

Figure 20 ~ Figure 36 is the practical implementation technology cutaway view of the embodiment of the invention 2, wherein,

Figure 20 is the cutaway view after formation second oxide layer.

Figure 21 is the cutaway view behind formation the 4th conductive polycrystalline silicon floor.

Figure 22 is the cutaway view behind formation the 4th shield grid conductive polycrystalline silicon.

Figure 23 is the cutaway view behind formation second isolating oxide layer.

Figure 24 is the cutaway view behind formation the 3rd shield grid conductive polycrystalline silicon.

Figure 25 is the cutaway view after the formation shield grid oxide layer.

Figure 26 is the cutaway view after formation the 3rd oxide layer.

Figure 27 is the cutaway view behind the formation secondary shielding grid conductive polycrystalline silicon.

Figure 28 is the cutaway view behind formation first isolating oxide layer.

Figure 29 is the cutaway view after formation the 4th oxide layer.

Figure 30 is the cutaway view after formation the 5th oxide layer.

Figure 31 is the cutaway view behind the formation grid conductive polycrystalline silicon.

Figure 32 is the cutaway view behind the formation second conductive type of trap layer.

Figure 33 is for forming the cutaway view of the first conduction type source area.

Figure 34 is the cutaway view behind the formation insulating medium layer.

Figure 35 is the cutaway view behind the formation contact hole.

Figure 36 is the cutaway view behind the formation metal connecting line.

Figure 37 is the gate charge emulation sketch map of existing power MOSFET device.

Figure 38 is the gate charge emulation sketch map of power MOSFET device of the present invention.

Embodiment

Below in conjunction with concrete accompanying drawing and embodiment the present invention is described further.

Embodiment 1

Like Fig. 1 ~ shown in Figure 180: with N type power MOSFET device is example, the present invention includes insulating medium layer 12 between N type drain region 1, N type first epitaxial loayer 2, N type second epitaxial loayer 3, P trap layer 4, cellular groove 5, insulated gate oxide layer 6, N+ source area 7, grid conductive polycrystalline silicon 8, the first shield grid conductive polycrystalline silicon 9, secondary shielding grid conductive polycrystalline silicon 10, shield grid oxide layer 11, conductive polycrystalline silicon, insulating medium layer 13, metal connecting line 14, first isolating oxide layer 15, contact hole 16, first interarea 17, second interarea 18, hard mask layer 19, hard mask window 20, second oxide layer 21, the first polysilicon depositing groove 22, first conductive polycrystalline silicon floor 23, the 3rd oxide layer 24, the second polysilicon depositing groove 25, the 4th oxide layer 26, the 5th oxide layer 27 and the 3rd polysilicon depositing groove 28.

Like Fig. 1 and shown in Figure 180: on the top plan view of said power MOSFET device; Comprise the cellular region that is positioned at the semiconductor substrate center and be positioned at the terminal protection district of said cellular region outer ring; Said terminal protection district surrounds around cellular region, comprises in the said cellular region that several rules is arranged and the cellular of connection parallel with one another.The cellular region structure of only having represented power MOSFET device among Fig. 1 and Figure 19, power MOSFET device can adopt existing conventional terminal protection plot structure.On the cross section of said power MOSFET device; Said semiconductor substrate comprises N type drain region 1 and is positioned at N type first epitaxial loayer 2 and N type second epitaxial loayer 3 of 1 top, said N type drain region; Said N type first epitaxial loayer 2 is in abutting connection with N type drain region 1, and the doping content of N type second epitaxial loayer 3 is more than or equal to the doping content of N type first epitaxial loayer 2.Semiconductor substrate has two corresponding interareas, and said two interareas are first interarea 17 and second interarea 18; The surface of N type second epitaxial loayer 3 forms first interarea 17, and the surface of N type drain region 1 forms second interarea, 18, the first interareas 17 and the 18 corresponding distributions of second interarea.Top in N type second epitaxial loayer 3 is provided with P trap layer 4.

On the cross section of said power MOSFET device; Cellular in the cellular region adopts groove structure; Said cellular groove 5 is positioned at first epitaxial loayer, 2 tops; And cellular groove 5 extends to the direction of second interarea 18 from first interarea 17 in P trap layer 4, and the bottom land of cellular groove 5 extends in N type second epitaxial loayer 3 of P trap layer 4 below or in first epitaxial loayer 2.Be provided with the first shield grid conductive polycrystalline silicon 9 in the cellular groove 5, promptly this moment, shield grid conductive polycrystalline silicon body was the first shield grid conductive polycrystalline silicon 9; The said first shield grid conductive polycrystalline silicon 9 is positioned at the center of cellular groove 5, and the first shield grid conductive polycrystalline silicon 9 extends to the bottom land direction from the notch of cellular groove 5.The both sides of the first shield grid conductive polycrystalline silicon 9 are provided with grid conductive polycrystalline silicon 8, and the below of said grid conductive polycrystalline silicon 8 is provided with secondary shielding grid conductive polycrystalline silicon 10.Grid conductive polycrystalline silicon 8 is corresponding with the first shield grid conductive polycrystalline silicon 9 in the longitudinal direction with secondary shielding grid conductive polycrystalline silicon 10, and promptly secondary shielding grid conductive polycrystalline silicon 10 is positioned at the top of the first shield grid conductive polycrystalline silicon, 9 bottoms; And the degree of depth that the grid conductive polycrystalline silicon 8 and the first shield grid conductive polycrystalline silicon 9 extend in cellular groove 5 is all below P trap layer 4.Grid conductive polycrystalline silicon 8 is positioned at the top of cellular groove 5, and is provided with insulated gate oxide layer 6 between grid conductive polycrystalline silicon 8 and cellular groove 5 sidewalls, and said insulated gate oxide layer 6 grows on the sidewall of corresponding cellular groove 5.Grid conductive polycrystalline silicon 8 is isolated through insulating medium layer 12 between conductive polycrystalline silicon and the first shield grid conductive polycrystalline silicon 9 and secondary shielding grid conductive polycrystalline silicon 10; Insulating medium layer 12 is an oxide layer between conductive polycrystalline silicon, and insulating medium layer 12 coats the upper face of the first shield grid conductive polycrystalline silicon 9 between conductive polycrystalline silicon.The bottom of the first shield grid conductive polycrystalline silicon 9 is provided with shield grid oxide layer 11, and said shield grid oxide layer 11 coats the bottom of the first shield grid conductive polycrystalline silicon 9, and the thickness of shield grid oxide layer 11 is more than or equal to the thickness of insulated gate oxide layer 6.11 of the secondary shielding grid conductive polycrystalline silicon 10 and the first shield grid conductive polycrystalline silicon 9 and shield grid oxide layers are isolated through first isolating oxide layer 15.The lateral wall on cellular groove 5 tops is provided with N+ source area 7, and said N+ source area 7 is positioned at the top of P trap layer 4.

On the cross section of said power MOSFET device; The notch of cellular groove 5 is covered by insulating medium layer 13; The both sides of said cellular groove 5 are provided with contact hole 16, and said contact hole 16 extends in the P trap layer 4 from the surface of insulating medium layer 13, and contact hole 16 passes corresponding N+source area 7.Be deposited with metal connecting line 14 on the insulating medium layer 13, said metal connecting line 14 is covered on the insulating medium layer 13, and is filled in the contact hole 16.Metal connecting line 14 and N+ source area 7 and P trap layer 4 ohmic contact, and the first shield grid conductive polycrystalline silicon 9 is connected with metal connecting line 14 equipotentials, and particularly, the first shield grid conductive polycrystalline silicon 9 is connected with metal connecting line 14 zero potentials.Being connected of the first shield grid conductive polycrystalline silicon 9 and 14 of metal connecting lines can also can connect through fairlead and the filling metal that is positioned at fairlead through grid exit mode.On metal connecting line 14, passivation layer can also be set, said passivation layer is the stack by silicon dioxide layer and silicon nitride layer.

The power MOSFET device of said structure, can realize through following processing step:

A, the semiconductor substrate with two relative interareas is provided; Said semiconductor substrate comprises N type drain region 1 and is positioned at N type first epitaxial loayer 2 and N type second epitaxial loayer 3 of 1 top, said N type drain region; The surface of N type second epitaxial loayer 3 forms first interarea 17 of semiconductor substrate, and the surface of N type drain region 1 forms second interarea 18 of semiconductor substrate;

As shown in Figure 2: the material of semiconductor substrate comprises silicon, and the doping content of N type second epitaxial loayer 3 is more than or equal to the concentration of N type first epitaxial loayer 2; Through on bigger N type second epitaxial loayer 3 of concentration, carrying out relative set, can reduce the conducting resistance of power MOSFET device;

B, on first interarea 17 of semiconductor substrate deposit hard mask layer 19, and optionally shelter and the said hard mask layer 19 of etching, on first interarea 17 of semiconductor substrate, form the hard mask window 20 of etching groove;

As shown in Figure 3: said hard mask layer 19 can adopt LPTEOS (low-pressure chemical vapor deposition tetraethyl orthosilicate), thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride, forms hard mask through photoetching and anisotropic etching thereafter; Can in the N of semiconductor substrate type second epitaxial loayer 3, etch groove structure through hard mask window 20;

C, utilize above-mentioned hard mask window 20, on first interarea 17, through the anisotropic dry etch semiconductor substrate, above the N of semiconductor substrate type first epitaxial loayer 2, form groove, said groove comprises cellular groove 5;

The degree of depth of said cellular groove 5 is generally 1 μ m between 30 μ m;

D, on first interarea 17 of above-mentioned semiconductor substrate growth regulation dioxide layer 21, said second oxide layer 21 is covered on first interarea 17, and is covered in the sidewall and the lower surface of cellular groove 5, and in cellular groove 5, forms the first polysilicon depositing groove 22;

As shown in Figure 4: therefore second oxide layer, 21 thickness of growth can form the first polysilicon depositing groove 22 less than the width of cellular groove 5 in cellular groove 5 in cellular groove 5; Second oxide layer 21 is consistent at the thickness of the thickness of cellular groove 5 bottoms and shield grid oxide layer 11; The thickness of second oxide layer 21 is generally 200 ~ 15000 à;

E, on first interarea 17 of above-mentioned semiconductor substrate deposit first conductive polycrystalline silicon floor 23, said first conductive polycrystalline silicon floor 23 is filled in the first polysilicon depositing groove 22;

As shown in Figure 5: said first conductive polycrystalline silicon floor 23 is covered on first interarea 17, and can fill in the first polysilicon depositing groove 22, and the aperture of the first polysilicon depositing groove 22 is consistent with the first shield grid conductive polycrystalline silicon 9 that need obtain;

F, remove first conductive polycrystalline silicon floor 23 on semiconductor substrate first interarea 17, obtain being positioned at the first shield grid conductive polycrystalline silicon 9 of the first polysilicon depositing groove 22;

As shown in Figure 6: as after removing first conductive polycrystalline silicon floor 23, can to remove first polycrystal layer 23 that surrounds the first shield grid conductive polycrystalline silicon, 9 tops, thereby can in cellular groove 5, form the first shield grid conductive polycrystalline silicon 9;

G, on first interarea 17 of semiconductor substrate, make photoresist, defining second oxide layer 21 needs the zone of etchings to carry out photoetching, removes second oxide layer 21 of defined range then through etching, obtains being positioned at the shield grid oxide layer 11 of cellular groove 5 bottoms;

As shown in Figure 7: as to remove second oxide layer 21 and second oxide layer 21 on cellular groove 5 upper portion side wall on first interarea through photoresist; After removing second oxide layer 21 of above-mentioned zone; Can keep cellular groove 5 bottoms second oxide layer 21; To form shield grid oxide layer 11, said shield grid oxide layer 11 is covered in the surface of cellular groove 5 bottoms and bottom;

H, on first interarea 17 of semiconductor substrate, the 3rd oxide layer 24 is set; Said the 3rd oxide layer 24 is covered on first interarea 17; And coat the upper face of the first shield grid conductive polycrystalline silicon 9, and form the second polysilicon depositing groove 25 in the first shield grid conductive polycrystalline silicon, 9 both sides;

As shown in Figure 8: in order to access secondary shielding grid conductive polycrystalline silicon 10; And the isolation that obtains 9 of secondary shielding grid conductive polycrystalline silicon 10 and shield grid oxide layer 11 and the first shield grid conductive polycrystalline silicons; The 3rd oxide layer 24 need be set, and said the 3rd oxide layer 24 can form through thermal oxidation or deposit; The second polysilicon depositing groove, 25 apertures are consistent with the secondary shielding grid conductive polycrystalline silicon 10 that need obtain;

I, in the second polysilicon body depositing groove 25 deposit second conductive polycrystalline silicon floor; And pass through back to carve second conductive polycrystalline silicon floor and the 3rd oxide layer 24, obtain first isolating oxide layer 15 and be positioned at the secondary shielding grid conductive polycrystalline silicon 10 of the second polysilicon depositing groove, 25 bottoms;

As shown in Figure 9: behind deposit second conductive polycrystalline silicon floor, second conductive polycrystalline silicon floor is covered on first interarea 17, and is filled in the second polysilicon depositing groove 25; Behind corresponding second conductive polycrystalline silicon floor of etching, can in the second polysilicon depositing groove 25, obtain secondary shielding grid conductive polycrystalline silicon 10; Simultaneously; Remove the 3rd oxide layer 24 and the 3rd oxide layer 24 on cellular groove 5 tops on first interarea 17; Obtain first isolating oxide layer 15; Said first isolating oxide layer 15 surrounds secondary shielding grid conductive polycrystalline silicons 10, and the thickness of first isolating oxide layer 15 and secondary shielding grid conductive polycrystalline silicon 10 are consistent;

J, on first interarea 17 of above-mentioned semiconductor substrate growth regulation four oxide layers 26, said the 4th oxide layer 26 is covered in first interarea 17 and the cellular groove 5, removes above-mentioned the 4th oxide layer 26 through wet etching then;

Shown in figure 11: said the 4th oxide layer 26 is a sacrificial oxide layer, can remove the impurity on cellular groove 5 sidewalls through sacrificial oxide layer 26; Remove the 4th oxide layer 26 of growth then through wet etching;

K, on first interarea 17 of above-mentioned semiconductor substrate thermal oxide growth the 5th oxide layer 27; The 5th oxide layer 27 is covered on first interarea 17 and cellular groove 5 upper portion side wall; And be covered on the secondary shielding grid conductive polycrystalline silicon 10 and the first shield grid conductive polycrystalline silicon 9, and form the 3rd polysilicon depositing groove 28 in the first shield grid conductive polycrystalline silicon, 9 both sides;

Shown in figure 12: the thickness of the thickness of said the 5th oxide layer 27 and insulated gate oxide layer 6 is consistent; Insulating medium layer 12 is same manufacturing layer with insulated gate oxide layer 6 between conductive polycrystalline silicon; Therefore when generating the 5th oxide layer 27, also express insulating medium layer 12 between conductive polycrystalline silicon in scheming; Can form the 3rd polysilicon depositing groove 28 through the 5th oxide layer 27, said the 3rd polysilicon depositing groove 28 apertures and grid conductive polycrystalline silicon 8 width are consistent; The 3rd polysilicon depositing groove 28 is positioned at the top of cellular groove 5; The thickness of the 5th oxide layer 27 is 100 ~ 2500 à;

L, on first interarea 17 of above-mentioned semiconductor substrate deposit the 3rd conductive polycrystalline silicon floor, through the 3rd conductive polycrystalline silicon floor on etching first interarea 17, obtain being positioned at the grid conductive polycrystalline silicon 8 of cellular groove 5;

Shown in figure 13: the 3rd conductive polycrystalline silicon floor that deposit obtains is covered on the 5th oxide layer 27 of first interarea 17; Behind corresponding the 3rd conductive polycrystalline silicon floor on removal first interarea 17; Can access the grid conductive polycrystalline silicon 8 that is positioned at cellular groove 5, said grid conductive polycrystalline silicon 8 is isolated through insulating medium layer 12 between conductive polycrystalline silicon and the first shield grid conductive polycrystalline silicon 9 and secondary shielding grid conductive polycrystalline silicon 10;

M, on first interarea 17 of above-mentioned semiconductor substrate, inject the p type impurity ion; And through pushing away the P trap layer 4 that trap forms cellular region, the degree of depth of P trap layer 4 in N type second epitaxial loayer 3 in the said cellular region less than grid conductive polycrystalline silicon 8 in cellular groove 5 to the distance that extends below;

Shown in figure 14: said p type impurity ion is generally the boron ion;

N, on first interarea 17 of above-mentioned semiconductor substrate, carry out the source region photoetching, and inject the N type foreign ion of high concentration, form the N+ source area 7 of cellular region through knot;

Shown in figure 15: said N type foreign ion is an arsenic ion, and said N+ source area 7 is positioned at the top of cellular groove 7 lateral walls, and N+ source area 7 is positioned at P trap layer 4;

O, on first interarea 17 of above-mentioned semiconductor substrate deposit insulating medium layer 13, said insulating medium layer 13 is covered in first interarea 17 of semiconductor substrate;

Shown in figure 16: said insulating medium layer 13 is silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG);

P, above-mentioned insulating medium layer 13 is carried out contact hole photoetching and etching, all form contact hole 16 in the both sides of cellular groove 5;

Shown in figure 17: said contact hole 16 extends downwardly in the P trap layer 4 from the surface of insulating medium layer 13, and contact hole 16 passes the 5th oxide layer 27 on the N+ source area 7 and first interarea 17;

Q, on above-mentioned insulating medium layer 13 deposited metal, said metal level is covered on the insulating medium layer 13, and is filled in the contact hole 16, forms metal connecting line 14; Said metal connecting line 14 and N type source area 7 and P trap layer 4 ohmic contact, shown in figure 18.

Shown in figure 18: said metal connecting line 14 connects into equipotential with N type source area 7 and P trap layer 4; And the first shield grid conductive polycrystalline silicon 9 electrically connects with metal connecting line 14.Particularly, metal connecting line 14 comprises source metal line and gate metal line, but continuous 14 the corresponding source metal lines of expression of the metal among the figure; The gate metal line is connected with grid conductive polycrystalline silicon 8 equipotentials, and the first shield grid conductive polycrystalline silicon 9 both can be connected with source metal line equipotential with secondary shielding grid conductive polycrystalline silicon 10, also can be connected with gate metal line equipotential; Thereby can obtain, when shield grid conductive polycrystalline silicon body adopted other structures, shield grid conductive polycrystalline silicon body also promptly can be connected with source metal line equipotential with secondary shielding grid conductive polycrystalline silicon 10, also can be connected with gate metal line equipotential.On the metal connecting line 14 passivation layer can also be set, and the making photoresist defines the metal wire window on passivation layer, forms said metal wire window through dry etching.Passivation layer comprises and is positioned at the silicon dioxide layer on the metal connecting line 14 and is positioned at the silicon nitride layer on the said silicon dioxide layer.

Embodiment 2

Like Figure 19 ~ shown in Figure 36: with N type power MOSFET device is example, the present invention includes insulating medium layer 12 between N type drain region 1, N type first epitaxial loayer 2, N type second epitaxial loayer 3, P trap layer 4, cellular groove 5, insulated gate oxide layer 6, N+ source area 7, grid conductive polycrystalline silicon 8, secondary shielding grid conductive polycrystalline silicon 10, shield grid oxide layer 11, conductive polycrystalline silicon, insulating medium layer 13, metal connecting line 14, first isolating oxide layer 15, contact hole 16, first interarea 17, second interarea 18, second oxide layer 21, the first polysilicon depositing groove 22, first conductive polycrystalline silicon floor 23, the 3rd oxide layer 24, the second polysilicon depositing groove 25, the 4th oxide layer 26, the 5th oxide layer 27, the 3rd polysilicon depositing groove 28, the 3rd shield grid conductive polycrystalline silicon 29, the 4th shield grid conductive polycrystalline silicon 30, second isolating oxide layer 31 and the 4th conductive polycrystalline silicon floor 32.

Like Figure 19 and shown in Figure 36: on the cross section of said MOSFET device, the cellular of cellular region adopts groove structure.Shield grid conductive polycrystalline silicon body in the said cellular groove 5 comprises the 3rd shield grid conductive polycrystalline silicon 29 and is positioned at the 4th shield grid conductive polycrystalline silicon 30 of said the 3rd shield grid conductive polycrystalline silicon 29 belows that said the 3rd shield grid conductive polycrystalline silicon 29 and the 4th shield grid are isolated through second isolating oxide layer 31 to 30 of conductive polycrystalline silicons; Be the 3rd shield grid conductive polycrystalline silicon 29 and the 4th shield grid conductive polycrystalline silicon 30 formation shield grid conductive polycrystalline silicon body structures in the present embodiment 2; In concrete the application; Shield grid conductive polycrystalline silicon body can also be divided into the structure of similar the 3rd shield grid conductive polycrystalline silicon 29 and the combination of the 4th shield grid conductive polycrystalline silicon 30, and the combination through corresponding construction can reach the object of the invention equally.When shield grid conductive polycrystalline silicon body adopts the structure of the 3rd shield grid conductive polycrystalline silicon 29 and 30 combinations of the 4th shield grid conductive polycrystalline silicon; All the other structures in the cellular groove 5 all with embodiment 1 in structure identical, its concrete multiple version no longer illustrates.When shield grid conductive polycrystalline silicon body adopted multiple combining structure, it was identical with the situation of explanation among the annexation of metal connecting line 14 and the embodiment 1.The bottom of cellular groove 5 is provided with shield grid oxide layer 11, and said shield grid oxide layer 11 coats the 4th shield grid conductive polycrystalline silicon 30, and the upper surface of shield grid oxide layer 11 upper surfaces and the 4th shield grid conductive polycrystalline silicon 30 is consistent.The both sides of the 3rd shield grid conductive polycrystalline silicon 29 are provided with grid conductive polycrystalline silicon 8, and the below of said grid conductive polycrystalline silicon 8 is provided with secondary shielding grid conductive polycrystalline silicon 10; The lower end part of secondary shielding grid conductive polycrystalline silicon 10 in the top of the 3rd shield grid conductive polycrystalline silicon 29 bottoms.Be provided with insulated gate oxide layer 6 between the sidewall on grid conductive polycrystalline silicon 8 and cellular groove 5 tops; Grid conductive polycrystalline silicon 8 is isolated with the 3rd shield grid conductive polycrystalline silicon 29 and secondary shielding grid conductive polycrystalline silicon 10 through insulating medium layer 12 between conductive polycrystalline silicon, and it is isolated that secondary shielding grid conductive polycrystalline silicon 10 passes through first isolating oxide layer 15 and second isolating oxide layer 16 and the 3rd shield grid conductive polycrystalline silicon 29 and the 4th shield grid conductive polycrystalline silicon 30.The thickness of shield grid oxide layer 11 is more than or equal to the thickness of insulated gate oxide layer 6; All the other structures of power MOSFET device be provided with all with embodiment 1 in structure be provided with identical, the description that concrete structure and function setting can reference implementation examples 1.

C, utilize above-mentioned hard mask window 20, on first interarea 17 through the anisotropic dry etch semiconductor substrate, formation groove the N of semiconductor substrate type second epitaxial loayer 3 in, said groove comprises cellular groove 5;

Shown in figure 20: therefore second oxide layer, 21 thickness of growth can form the first polysilicon depositing groove 22 less than the width of cellular groove 5 in cellular groove 5 in cellular groove 5; Second oxide layer 21 is consistent at the thickness of the thickness of cellular groove 5 bottoms and shield grid oxide layer 11;

E, on first interarea 17 of above-mentioned semiconductor substrate deposit the 4th conductive polycrystalline silicon floor 32, said the 4th conductive polycrystalline silicon floor 32 is covered in first interarea 17 of semiconductor substrate and is filled in the first polysilicon depositing groove 22; Remove the 4th conductive polycrystalline silicon floor 32 on above-mentioned semiconductor substrate first interarea 17, obtain being positioned at the 4th shield grid conductive polycrystalline silicon 30 of the first polysilicon depositing groove 22; Deposit second isolating oxide layer 31 on the 4th shield grid conductive polycrystalline silicon 30, and on second isolating oxide layer 31 deposit the 5th conductive polycrystalline silicon floor, said the 5th conductive polycrystalline silicon floor is covered in first interarea 17 of semiconductor substrate;

Like Figure 22, Figure 23 and shown in Figure 23: be positioned at through removal that the 4th conductive polycrystalline silicon floor 32 can access the 4th shield grid conductive polycrystalline silicon 30 that is positioned at the first polysilicon depositing groove 22 on semiconductor substrate first interarea 17; Second isolating oxide layer 31 of growing, and on second isolating oxide layer 31 deposit the 5th conductive polycrystalline silicon floor, can form the 3rd shield grid conductive polycrystalline silicon 29 through the 5th conduction polycrystal layer;

F, remove the 5th conductive polycrystalline silicon floor on semiconductor substrate first interarea 17, obtain being positioned at the 3rd shield grid conductive polycrystalline silicon 29 of the first polysilicon depositing groove 22;

Shown in figure 24: as after removing the 5th conductive polycrystalline silicon floor on first interarea 17, to access the 3rd shield grid conductive polycrystalline silicon 29

G, on first interarea 17 of semiconductor substrate, make photoresist; Defining second oxide layer 21 needs the zone of etching to carry out photoetching; Remove second oxide layer 21 of defined range then through etching, obtain being positioned at the shield grid oxide layer 11 of cellular groove 5 bottoms, shown in figure 25;

H, on first interarea 17 of semiconductor substrate, the 3rd oxide layer 24 is set; Said the 3rd oxide layer 24 is covered on first interarea 17; And coat the upper face of the first shield grid conductive polycrystalline silicon 9; And form the second polysilicon depositing groove 25 in the first shield grid conductive polycrystalline silicon, 9 both sides, shown in figure 26;

I, in the second polysilicon body depositing groove 25 deposit second conductive polycrystalline silicon floor; And pass through back to carve second conductive polycrystalline silicon floor and the 3rd oxide layer 24; Obtain first isolating oxide layer 15 and be positioned at the secondary shielding grid conductive polycrystalline silicon 10 of the second polysilicon depositing groove, 25 bottoms, like Figure 27 and shown in Figure 28;

J, on first interarea 17 of above-mentioned semiconductor substrate growth regulation four oxide layers 26, said the 4th oxide layer 26 is covered in first interarea 17 and the cellular groove 5, removes above-mentioned the 4th oxide layer 26 through wet etching then, and is shown in figure 29;

K, on first interarea 17 of above-mentioned semiconductor substrate thermal oxide growth the 5th oxide layer 27; The 5th oxide layer 27 is covered on first interarea 17 and cellular groove 5 upper portion side wall; And be covered on secondary shielding grid conductive polycrystalline silicon 10 and the 3rd shield grid conductive polycrystalline silicon 29; And form the 3rd polysilicon depositing groove 28 in the 3rd shield grid conductive polycrystalline silicon 29 both sides, shown in figure 30;

L, on first interarea 17 of above-mentioned semiconductor substrate deposit the 3rd conductive polycrystalline silicon floor, through the 3rd conductive polycrystalline silicon floor on etching first interarea 17, obtain being positioned at the grid conductive polycrystalline silicon 8 of cellular groove 5, shown in figure 31;

M, on first interarea 17 of above-mentioned semiconductor substrate, inject the p type impurity ion; And push away the P trap layer 4 that trap forms cellular region through high temperature; The degree of depth of P trap layer 4 in N type second epitaxial loayer 3 in the said cellular region less than grid conductive polycrystalline silicon 8 in cellular groove 5 to the distance that extends below, shown in figure 32;

N, on first interarea 17 of above-mentioned semiconductor substrate, carry out the source area photoetching, and inject the N type foreign ion of high concentration, form the N+ source area 7 of cellular region through knot, shown in figure 33;

O, on first interarea 17 of above-mentioned semiconductor substrate deposit insulating medium layer 13, said insulating medium layer 13 is covered in first interarea 17 of semiconductor substrate, and is shown in figure 34;

P, above-mentioned insulating medium layer 13 is carried out contact hole photoetching and etching, all form contact hole 16 in the both sides of cellular groove 5, shown in figure 35; Etching forms the injection process that contact hole 16 processes generally have the p type impurity ion, so that the hole that etching obtains can form ohmic contact;

Q, on above-mentioned insulating medium layer 13 deposited metal, said metal level is covered on the insulating medium layer 13, and is filled in the contact hole 16, forms metal connecting line 14; Said metal connecting line 14 and N type source area 7 and P trap layer 4 ohmic contact; Shown in figure 36.The concrete process conditions of present embodiment 2 are identical with the processing step condition of embodiment 1, and difference is for forming the process of the 3rd shield grid conductive polycrystalline silicon 29, the 4th shield grid conductive polycrystalline silicon 30 and second isolating oxide layer 31.

Operation principle of the present invention: P trap layer 4, the N+ source area 7 of grid conductive polycrystalline silicon 8, insulated gate oxide layer 6 and insulated gate oxide layer 6 sides in the cellular groove 5 have constituted groove-shaped MOS structure (Metal-oxide-semicondutor); Because the thickness of insulated gate oxide layer 6 and the gate oxide thickness basically identical of common groove type power MOS FET; Thickness all is about 200 à-1200 à; Therefore, the threshold voltage basically identical of the threshold voltage vt h of groove type power MOS FET of the present invention and common groove type power MOS FET.Through secondary shielding grid conductive polycrystalline silicon 10 and shield grid conductive polycrystalline silicon body are set in cellular groove 5; Said shield grid conductive polycrystalline silicon body can be the form of the first shield grid conductive polycrystalline silicon 9; Also can be the structure of the 3rd shield grid conductive polycrystalline silicon 29 with the 30 corresponding cooperations of the 4th shield grid conductive polycrystalline silicon, or other similar structures; Through increasing shield grid conductive polycrystalline silicon structure, effectively reduce the grid leak parasitic capacitance Cgd of this MOSFET device, thereby reduced gate charge Qgd, reduced switching loss significantly; N type below P trap layer 4 and between cellular groove 5 second epitaxial loayer 3 zones in addition; Because of its both sides are surrounded by the combining structure of shield grid conductive polycrystalline silicon body and shield grid oxide layer 11; Leak generation transverse electric field mudulation effect when receiving reverse biased in the source; This zone electric field is reduced significantly, improved the source drain breakdown voltage.Thereby can reduce the characteristic conducting resistance through improving this region doping concentration, and not reduce the source drain breakdown voltage.Figure 37 is the emulation sketch map of the gate charge of existing power MOSFET device when working, and Figure 38 is the gate charge emulation sketch map of power MOSFET device when working of structure of the present invention; Both l-G simulation test conditions are identical, the equal express time of abscissa, and ordinate is represented magnitude of voltage.Can find out that by Figure 37 and Figure 38 the shield grid conductive polycrystalline silicon that the present invention adopts and the structure of grid conductive polycrystalline silicon 8 can reduce gate charge.

Because the technique scheme utilization, the present invention compared with prior art has advantage and effect:

The foregoing description only is explanation technical conceive of the present invention and characteristics, and its purpose is to let the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.

Claims

1. low gate charge low on-resistance deep-groove power MOS FET device; On the top plan view of said MOSFET device; Comprise the cellular region and the terminal protection district that are positioned at semiconductor substrate, said terminal protection district is positioned at the outer ring of cellular region, and the terminal protection district is around surrounding cellular region; Comprise the cellular of arranging several rules and being parallel to each other parallel connection being provided with in the cellular region; On the cross section of said MOSFET device; Semiconductor substrate has corresponding first interarea and second interarea; Comprise the first conduction type drain region between said first interarea and second interarea and be positioned at first conduction type, first epitaxial loayer and first conduction type, second epitaxial loayer of top, the said first conduction type drain region, first conduction type, first epitaxial loayer adjacency, the first conduction type drain region; Top in first conduction type, second epitaxial loayer is provided with the second conductive type of trap layer; The cellular of cellular region adopts groove structure, and the cellular groove is positioned at first conduction type, first epitaxial loayer top, and the degree of depth stretches into first conduction type, second epitaxial loayer or first conduction type, first epitaxial loayer of second conductive type of trap layer below; The sidewall top of adjacent cellular groove is provided with the first conduction type source area, and the first conduction type source area is positioned at the top of the second conductive type of trap layer; It is characterized in that:

The notch of cellular groove is covered by insulating medium layer, and the both sides of cellular groove are provided with contact hole, is deposited with metal connecting line on the insulating medium layer, and said metal connecting line is covered on the insulating medium layer and is filled in the contact hole; The said metal connecting line and the first conduction type source area and the second conductive type of trap layer ohmic contact, and realization and grid conductive polycrystalline silicon, secondary shielding grid conductive polycrystalline silicon and the electric connection of shield grid conductive polycrystalline silicon body;

2. low gate charge low on-resistance deep-groove power MOS FET device according to claim 1; It is characterized in that: said shield grid conductive polycrystalline silicon body comprises the first shield grid conductive polycrystalline silicon; The said first shield grid conductive polycrystalline silicon is positioned at the center of cellular groove, and the first shield grid conductive polycrystalline silicon extends in the shield grid oxide layer from the top of cellular groove.

3. low gate charge low on-resistance deep-groove power MOS FET device according to claim 1; It is characterized in that: said shield grid conductive polycrystalline silicon body comprises the 3rd shield grid conductive polycrystalline silicon and is positioned at the 4th shield grid conductive polycrystalline silicon of said the 3rd shield grid conductive polycrystalline silicon below; The 3rd shield grid conductive polycrystalline silicon is positioned at the center of cellular groove, and extends to the bottom land direction of cellular groove from the top of cellular groove; Isolated through second isolating oxide layer between said the 3rd shield grid conductive polycrystalline silicon and the 4th shield grid conductive polycrystalline silicon, the 4th shield grid conductive polycrystalline silicon extends in the shield grid oxide layer; Grid conductive polycrystalline silicon and secondary shielding grid conductive polycrystalline silicon all are positioned at the both sides of the 3rd shield grid conductive polycrystalline silicon.

4. the manufacturing approach of a low gate charge low on-resistance deep-groove power MOS FET device is characterized in that the manufacturing approach of said power MOSFET device comprises the steps:

(a), the semiconductor substrate with two relative interareas is provided; Said semiconductor substrate comprises the first conduction type drain region and is positioned at first conduction type, first epitaxial loayer and first conduction type, second epitaxial loayer of top, the said first conduction type drain region; The surface of first conduction type, second epitaxial loayer forms first interarea of semiconductor substrate, and the surface of the first conduction type drain region forms second interarea of semiconductor substrate;

The doping content of said first conduction type, second epitaxial loayer is more than or equal to the doping content of first conduction type, first epitaxial loayer;

(b), on first interarea of semiconductor substrate the deposit hard mask layer, and optionally shelter and the said hard mask layer of etching, on first interarea of semiconductor substrate, form the hard mask window of etching groove;

(c), utilize above-mentioned hard mask window, on first interarea, through the dry etching semiconductor substrate, above first conduction type, first epitaxial loayer of semiconductor substrate, form groove, said groove comprises the cellular groove;

(d), on first interarea of above-mentioned semiconductor substrate the growth regulation dioxide layer, said second oxide layer is covered on first interarea, and is covered in the sidewall and the lower surface of cellular groove, and in the cellular groove, forms the first polysilicon depositing groove;

(e), on first interarea of above-mentioned semiconductor substrate deposition gate polysilicon body material layer, said shield grid polysilicon body material layer is filled in the first polysilicon depositing groove;

(f), remove the shield grid polysilicon body material layer on semiconductor substrate first interarea, obtain being positioned at the shield grid conductive polycrystalline silicon body of the first polysilicon depositing groove;

(g), on first interarea of semiconductor substrate, make photoresist, defining second oxide layer needs the zone of etching to carry out photoetching, removes second oxide layer of defined range then through etching, obtains being positioned at the shield grid oxide layer of cellular groove bottom;

(h), on first interarea of semiconductor substrate, the 3rd oxide layer is set; Said the 3rd oxide layer is covered on first interarea; And coat the upper face of shield grid conductive polycrystalline silicon body, and form the second polysilicon depositing groove in shield grid conductive polycrystalline silicon body both sides;

(i), in the second polysilicon body depositing groove deposit second conductive polycrystalline silicon floor, and pass through back to carve second conductive polycrystalline silicon floor and the 3rd oxide layer, obtain first isolating oxide layer and be positioned at the secondary shielding grid conductive polycrystalline silicon of second polysilicon depositing groove bottom;

(j), on first interarea of above-mentioned semiconductor substrate growth regulation four oxide layers, said the 4th oxide layer is covered in first interarea and the cellular groove, removes above-mentioned the 4th oxide layer through wet etching then;

(k), thermal oxide growth the 5th oxide layer on first interarea of above-mentioned semiconductor substrate; The 5th oxide layer is covered on first interarea and the cellular groove upper portion side wall; And be covered on secondary shielding grid conductive polycrystalline silicon and the shield grid conductive polycrystalline silicon body, and form the 3rd polysilicon depositing groove in shield grid conductive polycrystalline silicon body both sides;

(l), on first interarea of above-mentioned semiconductor substrate deposit the 3rd conductive polycrystalline silicon floor, through the 3rd conductive polycrystalline silicon floor on etching first interarea, obtain being positioned at the grid conductive polycrystalline silicon of cellular groove;

(m), on first interarea of above-mentioned semiconductor substrate, inject the second conductive type impurity ion, and through pushing away the second conductive type of trap layer that trap forms cellular region;

(n), on first interarea of above-mentioned semiconductor substrate, carry out the source area photoetching, and inject the first conductive type impurity ion, form the first conduction type source area of cellular region through knot;

(o), on first interarea of above-mentioned semiconductor substrate the deposit insulating medium layer, said insulating medium layer is covered in first interarea of semiconductor substrate;

(p), above-mentioned insulating medium layer is carried out contact hole photoetching and etching, all form contact hole in the both sides of cellular groove;

(q), on above-mentioned insulating medium layer deposited metal, said metal level is covered on the insulating medium layer, and is filled in the contact hole, forms metal connecting line; The said metal connecting line and the first conduction type source area and the second conductive type of trap layer ohmic contact.

5. the manufacturing approach of low gate charge low on-resistance deep-groove power MOS FET device according to claim 4 is characterized in that, also comprises the steps: after the said step (q)

(r), on above-mentioned metal connecting line the deposit passivation layer, and on passivation layer, make photoresist and define the metal wire window, form said metal wire window through dry etching.

6. the manufacturing approach of low gate charge low on-resistance deep-groove power MOS FET device according to claim 5 is characterized in that: said passivation layer comprises and is deposited on the silicon dioxide layer on the metal connecting line and is positioned at the silicon nitride layer on the said silicon dioxide layer.

7. the manufacturing approach of low gate charge low on-resistance deep-groove power MOS FET device according to claim 4; It is characterized in that; In said step (e) and the step (f); When the shield grid conductive polycrystalline silicon body that obtains was the first shield grid conductive polycrystalline silicon, step (e) and step (f) were specially:

(e), on first interarea of above-mentioned semiconductor substrate deposit first conductive polycrystalline silicon floor, said first conductive polycrystalline silicon floor is covered in first interarea of semiconductor substrate and is filled in the first polysilicon depositing groove;

(f), remove first conductive polycrystalline silicon floor on semiconductor substrate first interarea, obtain being positioned at the first shield grid conductive polycrystalline silicon of the first polysilicon depositing groove.

8. the manufacturing approach of low gate charge low on-resistance deep-groove power MOS FET device according to claim 4; It is characterized in that; In said step (e) and the step (f); When the shield grid conductive polycrystalline silicon body that obtains was the 3rd shield grid conductive polycrystalline silicon and the 4th shield grid conductive polycrystalline silicon, step (e) and step (f) were specially:

(e), on first interarea of above-mentioned semiconductor substrate deposit the 4th conductive polycrystalline silicon floor, said the 4th conductive polycrystalline silicon floor is covered in first interarea of semiconductor substrate and is filled in the first polysilicon depositing groove; Remove the 4th conductive polycrystalline silicon floor on above-mentioned semiconductor substrate first interarea, obtain being positioned at the 4th shield grid conductive polycrystalline silicon of the first polysilicon depositing groove; On the 4th shield grid conductive polycrystalline silicon, generate second isolating oxide layer, and on second isolating oxide layer deposit the 5th conductive polycrystalline silicon floor, said the 5th conductive polycrystalline silicon floor is covered in first interarea of semiconductor substrate;

(f), remove the 5th conductive polycrystalline silicon floor on semiconductor substrate first interarea, obtain the 3rd shield grid conductive polycrystalline silicon.

9. the manufacturing approach of low gate charge low on-resistance deep-groove power MOS FET device according to claim 4 is characterized in that: said insulating medium layer is silex glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).