CN115863413A - Method for manufacturing trench oxide layer and semiconductor device - Google Patents
Method for manufacturing trench oxide layer and semiconductor device Download PDFInfo
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- CN115863413A CN115863413A CN202310181101.2A CN202310181101A CN115863413A CN 115863413 A CN115863413 A CN 115863413A CN 202310181101 A CN202310181101 A CN 202310181101A CN 115863413 A CN115863413 A CN 115863413A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims description 51
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 42
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 33
- 230000003647 oxidation Effects 0.000 claims abstract description 32
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 32
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 31
- 238000000151 deposition Methods 0.000 claims abstract description 28
- 230000001590 oxidative effect Effects 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 43
- 229920005591 polysilicon Polymers 0.000 claims description 39
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 32
- 230000008569 process Effects 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- 235000012239 silicon dioxide Nutrition 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 2
- 230000008901 benefit Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 221
- 239000000463 material Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 230000008021 deposition Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
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- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000001657 homoepitaxy Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- 239000002344 surface layer Substances 0.000 description 1
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Abstract
The application provides a trench oxide layer manufacturing method and a semiconductor device, and relates to the technical field of semiconductors. Firstly, providing a silicon carbide epitaxial layer with a groove, oxidizing along the surface of the groove to form a first oxidation layer, and then depositing amorphous silicon along the surface of the first oxidation layer; and finally, oxidizing the amorphous silicon, and forming a second oxide layer on the surface of the first oxide layer. The manufacturing method of the trench oxide layer and the semiconductor device have the advantage of improving the uniformity of the trench oxide layer.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a method for manufacturing a trench oxide layer and a semiconductor device.
Background
Currently, when a part of a semiconductor device is manufactured, for example, when a Trench MOSFET is manufactured, a Trench needs to be etched on an epitaxial layer and a Trench oxide layer needs to be formed.
The conventional process is to directly oxidize the epitaxial layer after etching a groove on the epitaxial layer, but for a silicon carbide device, the thickness of the side wall of the groove is thicker due to the anisotropic characteristic of the crystal direction of the silicon carbide, the thickness uniformity of an oxide layer of the product is poorer, and the product performance is influenced.
In summary, the silicon carbide device in the prior art has the problem of poor uniformity of the trench oxide layer.
Disclosure of Invention
The present application provides a method for manufacturing a trench oxide layer and a semiconductor device, so as to solve the problem of poor uniformity of the trench oxide layer in the prior art.
In order to achieve the above object, the embodiments of the present application adopt the following technical solutions:
in a first aspect, an embodiment of the present application provides a method for manufacturing a trench oxide layer, where the method includes:
providing a silicon carbide epitaxial layer with a groove;
oxidizing along the surface of the groove to form a first oxidation layer;
depositing amorphous silicon along the surface of the first oxide layer; wherein the thickness of the amorphous silicon is greater than that of the first oxide layer;
and oxidizing the amorphous silicon, and forming a second oxide layer on the surface of the first oxide layer.
Optionally, after the step of oxidizing the amorphous silicon, the method further comprises:
depositing polysilicon based on the trench;
carrying out back etching on the polycrystalline silicon;
and oxidizing the polysilicon on the surface of the groove to form a silicon dioxide layer on the surface of the polysilicon.
Optionally, the step of depositing amorphous silicon along the surface of the first oxide layer includes:
and depositing amorphous silicon with the thickness of 2 to 3 times of the thickness of the first oxide layer.
Optionally, the step of forming a first oxide layer along the surface of the trench by oxidation includes:
oxidizing the surface of the groove to form a first oxide layer with the thickness of 100 to 150 angstroms;
the step of depositing amorphous silicon along the surface of the first oxide layer comprises:
and amorphous silicon with the thickness of 300 angstroms is deposited along the surface of the first oxide layer.
Optionally, the step of depositing amorphous silicon along the surface of the first oxide layer includes:
amorphous silicon is deposited using an LPCVD process.
Optionally, the step of providing a silicon carbide epitaxial layer with a trench comprises:
spin-coating a photoresist along the surface of the epitaxial layer;
patterning the photoresist;
and etching a groove on the epitaxial layer based on the photoresist.
On the other hand, an embodiment of the present application further provides a semiconductor device, which is manufactured by the above trench oxide layer manufacturing method, and the semiconductor device includes:
a silicon carbide epitaxial layer; the silicon carbide epitaxial layer is provided with a groove;
the first oxidation layer is positioned on the surface of the groove;
the second oxidation layer is positioned on the surface of the first oxidation layer; wherein the thickness of the second oxide layer is greater than the thickness of the first oxide layer.
Optionally, the semiconductor device further includes a polysilicon layer located in the trench and a silicon dioxide layer located on a surface of the polysilicon layer.
Optionally, the thickness of the second oxide layer is 2 to 3 times of the thickness of the first oxide layer.
Optionally, the thickness of the first oxide layer is 100 to 150 angstroms, and the thickness of the second oxide layer is 300 angstroms.
Compared with the prior art, the method has the following beneficial effects:
the application provides a method for manufacturing a groove oxidation layer and a semiconductor device, firstly, a silicon carbide epitaxial layer with a groove is provided, then, a first oxidation layer is formed along the surface of the groove through oxidation, and then, amorphous silicon is deposited along the surface of the first oxidation layer; and finally, oxidizing the amorphous silicon, and forming a second oxide layer on the surface of the first oxide layer. Because this application is when making the trench oxide layer, earlier at the trench surface grow the first oxide layer that the one deck is thin, and then can improve the interface state of carborundum, on this basis, continue through deposit amorphous silicon and the processing mode of oxidation, can make the second oxide layer of formation more even, and then make the homogeneity of whole trench oxide layer promote.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic cross-sectional view illustrating the formation of an oxide layer on the surface of a trench and on the mesa surface of an epitaxial layer according to the prior art.
Fig. 2 is a schematic cross-sectional view of the epitaxial layer mesa in fig. 1 after the oxide layer is removed.
Fig. 3 is an exemplary flowchart of a method for fabricating a trench oxide layer according to an embodiment of the present disclosure.
Fig. 4 is a schematic cross-sectional view corresponding to S1021 in the embodiment of the present application.
Fig. 5 is a schematic cross-sectional view corresponding to S1022 in the present embodiment.
Fig. 6 is a schematic cross-sectional view of S1023 according to an embodiment of the present disclosure.
Fig. 7 is a schematic cross-sectional view illustrating a process of removing the photoresist according to an embodiment of the present disclosure.
Fig. 8 is a schematic cross-sectional view corresponding to S104 provided in the embodiment of the present application.
Fig. 9 is a schematic cross-sectional view illustrating a second oxide layer formed after the second oxide layer is formed according to an embodiment of the disclosure.
Fig. 10 is a schematic cross-sectional view illustrating a first oxide layer and a second oxide layer removed according to an embodiment of the disclosure.
Fig. 11 is a schematic cross-sectional view of the polysilicon deposited on the substrate shown in fig. 9 according to the embodiment of the present application.
Fig. 12 is another exemplary flowchart of a method for forming a trench oxide layer according to an embodiment of the present disclosure.
Fig. 13 is a schematic cross-sectional view corresponding to S110 provided in the embodiment of the present application.
Fig. 14 is a schematic cross-sectional view of S112 according to an embodiment of the present application.
Fig. 15 is a schematic cross-sectional view corresponding to S114 provided in the embodiment of the present application.
Fig. 16 is a schematic cross-sectional view illustrating a polysilicon layer deposited according to an embodiment of the present disclosure.
Fig. 17 is a schematic cross-sectional view of polysilicon etched back according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not construed as indicating or implying relative importance.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.
In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
As described in the background art, in the prior art, when a trench oxide layer is formed, a method of directly oxidizing a trench etched on an epitaxial layer is commonly used.
Referring to fig. 1 and 2, which are cross-sectional views illustrating the fabrication of a trench oxide layer in the prior art, first, a trench is fabricated on an epitaxial layer, and then a thermal oxidation process is performed to fabricate an oxide layer on the surface of the trench, at this time, as shown in fig. 1, oxide layers are formed on the surface of the trench and on the mesa surface of the epitaxial layer, wherein the surface of the trench includes sidewalls of the trench and a bottom wall of the trench. Then, as shown in fig. 2, the oxide layer on the epitaxial layer mesa is removed, for example, by using a grinding process to remove the oxide layer on the epitaxial layer mesa, and only the oxide layer on the surface of the trench remains, thereby completing the fabrication of the trench oxide layer.
However, the thicknesses of the respective hierarchical structures and the thicknesses of the oxide layers in fig. 2 are only examples, and in practical applications, when the epitaxial layer is a SiC epitaxial layer, the thicknesses of the oxide layers on the sidewalls are thicker due to the anisotropic characteristic of the crystal orientation of silicon carbide, the thickness uniformity of the oxide layers of the product is poor, and the product performance may be affected.
Specifically, the side wall of the trench is an a surface (11-20 surfaces) of the silicon carbide material, and the bottom of the trench is a Si surface (0001 surface) of the silicon carbide material, so that during thermal oxidation, due to the particularity of the crystal orientation of the silicon carbide, the oxidation rate of the side wall of the trench is much greater than that of the bottom of the trench, and therefore the thickness of the oxide layer of the side wall of the trench is much greater than that of the oxide layer of the bottom of the trench, generally, the thickness of the oxide layer of the side wall of the trench is 3 to 5 times that of the oxide layer of the bottom of the trench, so that the uniformity of the oxide layer of the trench is poor, and the performance of the manufactured semiconductor device is affected.
In view of the above, in order to solve the above problems, the present application provides a method for manufacturing a trench oxide layer, in which a thin first oxide layer is formed by oxidation, and then a second oxide layer is formed by depositing amorphous silicon and then oxidizing, so as to achieve the purpose of improving uniformity of the trench oxide layer.
The following is an exemplary description of the trench oxide layer manufacturing method provided in the present application:
as an alternative implementation, referring to fig. 3, the method for fabricating the trench oxide layer includes:
and S102, providing a silicon carbide epitaxial layer with a groove.
And S104, oxidizing along the surface of the groove to form a first oxidation layer.
S106, depositing amorphous silicon along the surface of the first oxide layer; wherein the thickness of the amorphous silicon is larger than that of the first oxide layer.
S108, the amorphous silicon is oxidized, and a second oxide layer is formed on the surface of the first oxide layer.
The interface state of the silicon carbide epitaxial layer can be improved by forming the thin first oxide layer on the surface of the groove, and meanwhile, in the subsequent process of depositing and oxidizing amorphous silicon, the deposition process can enable the formed second oxide layer to be more uniform, so that the uniformity of the whole groove oxide layer is improved.
Wherein, S102 includes:
and S1021, coating photoresist along the surface of the epitaxial layer in a spinning mode.
And S1022, patterning the photoresist.
And S1023, etching a groove on the epitaxial layer based on the photoresist.
Referring to fig. 4, first, an epitaxial layer is grown on a substrate, the epitaxial layer is a silicon carbide epitaxial layer, and the material of the substrate is not limited in the present application, for example, the epitaxial layer may be a homoepitaxy, and at this time, the materials of the epitaxial layer and the substrate are the same and are both silicon carbide materials; of course, the epitaxial layer may be heteroepitaxial, in which case the epitaxial layer is not of the same material as the substrate, e.g., the substrate may be a sapphire substrate, a silicon substrate, etc.
To form trenches in the epitaxial layer, the epitaxial layer may be etched using photoresist. Continuing with fig. 4, a photoresist may be spun onto the surface of the epitaxial layer and used as a masking layer. Then, referring to fig. 5, the photoresist may be patterned, for example, the photoresist may be patterned by using a mask plate and ultraviolet light, so as to form a masking layer with a plurality of through holes. Then, the epitaxial layer is etched through an etching process, and due to the masking of the photoresist, the region coated with the photoresist is not etched, and the region not coated with the photoresist is etched, so as to form a trench on the epitaxial layer, as shown in fig. 6.
It should be noted that, in the drawings described in the present application, each hierarchical structure is only an example, and does not represent a true size ratio thereof. In addition, the number of the grooves is two in fig. 6, but in practical applications, the number of the grooves may be more, for example, 5 or 10, and is not limited herein.
Thereafter, as shown in fig. 7, the photoresist layer may be directly stripped, for example, a wet etching process or a dry photoresist removing process is used to remove the photoresist on the surface of the epitaxial layer, and a trench structure is formed on the epitaxial layer.
Referring to fig. 8, after the trench is formed, the trench may be oxidized to form a first oxide layer, wherein, when the oxidation process is performed, the entire surface layer of the epitaxial layer is actually oxidized, that is, the first oxide layer is formed on both the mesa surface of the epitaxial layer and the surface of the trench.
The first oxide layer formed by oxidation on the surface of the trench is made of silicon dioxide. In addition, in the oxidation process, a thin silicon dioxide layer (namely, a first oxidation layer) can be formed on the surface of the groove by utilizing a short-time thermal oxidation process, and the silicon dioxide layer can achieve the effect of improving the state of a silicon carbide/silicon dioxide interface and improve the performance of a device.
It should be noted that, during the oxidation process of the first oxide layer, the thickness of the sidewall may be larger than that of the bottom, but since the thickness of the first oxide layer is itself thinner, the influence on the uniformity of the entire trench oxide layer may be relatively small.
Then, referring to fig. 9, a second oxide layer is formed on the surface of the first oxide layer by depositing amorphous silicon and oxidizing. The second oxide layer is mainly used for improving the thickness uniformity problem. The second oxide layer is manufactured by adopting a deposition process, and the uniformity of the deposited second oxide layer is not influenced by the crystal orientation of the silicon carbide epitaxial layer, so that the uniformity of the second oxide layer can be improved.
And, the principle of oxidation of amorphous silicon is a-si + O 2 -SiO 2 Thus, the material of the second oxide layer is also silicon dioxide.
On the basis, the first oxide layer and the second oxide layer jointly form a trench oxide layer, the first oxide layer mainly plays a role in improving the interface state, and the second oxide layer is mainly used for improving the uniformity. Therefore, in order to improve the overall uniformity of the trench oxide layer, it is necessary to provide the second oxide layer with a relatively thick thickness and the first oxide layer with a relatively thin thickness.
As one realization mode, the thickness of the deposited amorphous silicon is 2 to 3 times of the thickness of the first oxide layer, so that the thickness of the formed second oxide layer is 2 to 3 times of the thickness of the first oxide layer.
Optionally, the thickness of the first oxide layer is set to be 100 to 150 angstroms, and the thickness of the second oxide layer is set to be 300 angstroms. Through this thickness setting, on the one hand, satisfied and utilized the effect that thicker second oxide layer improved the whole homogeneity of trench oxide layer, on the other hand, through setting up suitable first oxide layer thickness, neither can appear the condition that thickness is thicker, also can play the better effect of improving interface state simultaneously.
Here, it should be noted that, in the present application, after the first oxide layer is formed, the second oxide layer is formed by an amorphous silicon oxidation method, instead of forming the oxide layer by a polysilicon oxidation method in the prior art, an advantage of better uniformity effect can be achieved. The amorphous silicon material has relatively low deposition temperature, more stable deposition rate and more uniform deposition thickness, so that the final deposition effect of the second oxide layer is better.
Illustratively, amorphous silicon may be deposited in an environment of less than 550 ℃ by an LPCVD (Low Pressure Chemical Vapor Deposition) process and oxidized in an environment of 900 to 1200 ℃.
Meanwhile, it should be noted that when depositing the amorphous silicon, the same thickness of amorphous silicon is deposited on the mesa of the epitaxial layer, and on this basis, the first oxide layer and the second oxide layer on the mesa may be removed at one time after the amorphous silicon is oxidized, as shown in fig. 10.
Naturally, the above process is only one implementation, and in other implementations, other processes may be adopted to implement the fabrication of the first oxide layer and the second oxide layer in fig. 10, for example, referring to fig. 11, on the basis of fig. 9, the first oxide layer and the second oxide layer on the mesa of the epitaxial layer are not removed, but polysilicon deposition is directly performed on the basis of fig. 9, and then the first oxide layer and the second oxide layer are simultaneously removed during the polysilicon etching back.
After the first oxide layer and the second oxide layer are formed, referring to fig. 12, the method may further include:
and S110, depositing polycrystalline silicon on the basis of the groove.
And S112, etching back the polysilicon.
And S114, oxidizing the polysilicon on the surface of the groove to form a silicon dioxide layer on the surface of the polysilicon.
Referring to fig. 13, polysilicon is deposited along the trench, and in order to ensure that the polysilicon fills the entire trench, the polysilicon is relatively thick and is deposited on both the trench and the mesa of the epitaxial layer. Fig. 13 is an example, and is a hierarchical structure formed by removing the first oxide layer and the second oxide layer on the epitaxial layer mesa and then depositing polysilicon, but not limited thereto, and of course, polysilicon may be deposited in the hierarchical structure of fig. 11.
As shown in fig. 14, a polysilicon etch back may be performed after the polysilicon is deposited to level the height of the polysilicon in the trench with the mesa of the epitaxial layer.
Then, referring to fig. 15, the surface polysilicon is oxidized, and a silicon dioxide layer is formed on the surface of the polysilicon. By this implementation, it can be understood that, at the point a in the figure, the silicon dioxide layer is in direct contact with the second oxide layer, and then a sealed space is formed by the silicon dioxide layer, the second oxide layer and the first oxide layer, and the polysilicon layer is included therein, so that the overall reliability is stronger, and ions cannot enter the polysilicon layer from the a position and enter the first oxide layer or the second oxide layer from the a position, thereby improving the ion contamination resistance and the contamination resistance.
In addition, in practical applications, referring to fig. 16, due to the existence of the trench, when depositing the polysilicon, a recess is formed at a position where the polysilicon corresponds to the recess. On this basis, as shown in fig. 17, after the polysilicon is etched back, a recess is also formed on the polysilicon surface in the trench, and after the above process, an interlayer dielectric or the like may be continuously formed along the mesa surface of the epitaxial layer in order to complete the device fabrication. On the other hand, if the interlayer dielectric is directly formed on the mesa of the epitaxial layer, the interlayer dielectric is not flat due to the presence of the recess, and therefore cracks due to stress such as temperature change are likely to occur, and the reliability of the entire device is not high. And silicon dioxide formed on the surface of the polysilicon can fill the recess by oxidizing the surface of the polysilicon, so that the surface of the epitaxial layer is flatter. In addition, because the silicon carbide epitaxial layer material has the characteristics of high inertia, high stability and the like, the oxidation rate of the surface of the polycrystalline silicon is obviously higher than that of the silicon carbide epitaxial layer, and the influence on the silicon carbide epitaxial layer is relatively small.
Based on the foregoing implementation manner, please continue to refer to fig. 15, an embodiment of the present application further provides a semiconductor device fabricated by the trench oxide layer fabrication method, where the semiconductor device includes: a silicon carbide epitaxial layer; wherein, the silicon carbide epitaxial layer is provided with a groove; a first oxide layer on the surface of the trench; and a second oxide layer located on the surface of the first oxide layer; wherein the thickness of the second oxide layer is greater than that of the first oxide layer.
Optionally, the semiconductor device further comprises a polysilicon layer located in the trench and a silicon dioxide layer located on the surface of the polysilicon layer.
And, in one implementation, the thickness of the second oxide layer is 2 to 3 times of the thickness of the first oxide layer. For example, the thickness of the first oxide layer is 100 to 150 angstroms, and the thickness of the second oxide layer is 300 angstroms.
In summary, the present application provides a method for fabricating a trench oxide layer and a semiconductor device, which includes providing a silicon carbide epitaxial layer with a trench, oxidizing the silicon carbide epitaxial layer along a surface of the trench to form a first oxide layer, and depositing amorphous silicon along a surface of the first oxide layer; and finally, oxidizing the amorphous silicon, and forming a second oxide layer on the surface of the first oxide layer. Because this application is when making the trench oxide layer, earlier at the trench surface grow the first oxide layer that the one deck is thin, and then can improve the interface state of carborundum, on this basis, continue through deposit amorphous silicon and the processing mode of oxidation, can make the second oxide layer of formation more even, and then make the homogeneity of whole trench oxide layer promote.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. A method for manufacturing a trench oxide layer is characterized by comprising the following steps:
providing a silicon carbide epitaxial layer with a groove;
oxidizing along the surface of the groove to form a first oxidation layer;
depositing amorphous silicon along the surface of the first oxide layer; wherein the thickness of the amorphous silicon is greater than that of the first oxide layer;
and oxidizing the amorphous silicon, and forming a second oxide layer on the surface of the first oxide layer.
2. The method of claim 1, wherein after the step of oxidizing the amorphous silicon, the method further comprises:
depositing polysilicon based on the trench;
carrying out back etching on the polycrystalline silicon;
and oxidizing the polysilicon on the surface of the groove to form a silicon dioxide layer on the surface of the polysilicon.
3. The method of claim 1, wherein depositing amorphous silicon along the surface of the first oxide layer comprises:
and depositing amorphous silicon with the thickness of 2 to 3 times of the thickness of the first oxide layer.
4. The method of claim 3, wherein the step of oxidizing along the surface of the trench to form a first oxide layer comprises:
oxidizing the surface of the groove to form a first oxide layer with the thickness of 100 to 150 angstroms;
the step of depositing amorphous silicon along the surface of the first oxide layer comprises:
and depositing amorphous silicon with the thickness of 300 angstroms along the surface of the first oxide layer.
5. The method of claim 1, wherein depositing amorphous silicon along the surface of the first oxide layer comprises:
amorphous silicon is deposited using an LPCVD process.
6. The method of claim 1 wherein providing a silicon carbide epitaxial layer with a trench comprises:
spin-coating a photoresist along the surface of the epitaxial layer;
patterning the photoresist;
and etching a groove on the epitaxial layer based on the photoresist.
7. A semiconductor device manufactured by the method for manufacturing a trench oxide layer according to any one of claims 1 to 6, the semiconductor device comprising:
a silicon carbide epitaxial layer; the silicon carbide epitaxial layer is provided with a groove;
the first oxidation layer is positioned on the surface of the groove;
the second oxidation layer is positioned on the surface of the first oxidation layer; wherein the thickness of the second oxide layer is greater than the thickness of the first oxide layer.
8. The semiconductor device of claim 7, further comprising a polysilicon layer located within the trench and a silicon dioxide layer located on a surface of the polysilicon layer.
9. The semiconductor device according to claim 7, wherein the thickness of the second oxide layer is 2 to 3 times that of the first oxide layer.
10. The semiconductor device according to claim 9, wherein the first oxide layer has a thickness of 100 to 150 angstroms, and the second oxide layer has a thickness of 300 angstroms.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310181101.2A CN115863413A (en) | 2023-03-01 | 2023-03-01 | Method for manufacturing trench oxide layer and semiconductor device |
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| CN202310181101.2A CN115863413A (en) | 2023-03-01 | 2023-03-01 | Method for manufacturing trench oxide layer and semiconductor device |
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| CN202310181101.2A Pending CN115863413A (en) | 2023-03-01 | 2023-03-01 | Method for manufacturing trench oxide layer and semiconductor device |
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